diff options
author | Joshua Bakita <bakitajoshua@gmail.com> | 2023-10-29 13:07:40 -0400 |
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committer | Joshua Bakita <bakitajoshua@gmail.com> | 2023-10-29 13:10:52 -0400 |
commit | 2c5337a24f7f2d02989dfb733c55d6d8c7e90493 (patch) | |
tree | b9f1028cb443b03190b710c0d7ee640bf5958631 /include/nvgpu/pmu.h | |
parent | aa06f84f03cba7ad1aae5cd527355bb3d8c152a6 (diff) |
Update includes to L4T r32.7.4 and drop nvgpu/gk20a.h dependency
Also add instructions for updating `include/`. These files are now
only needed to build on Linux 4.9-based Tegra platforms.
Diffstat (limited to 'include/nvgpu/pmu.h')
-rw-r--r-- | include/nvgpu/pmu.h | 20 |
1 files changed, 19 insertions, 1 deletions
diff --git a/include/nvgpu/pmu.h b/include/nvgpu/pmu.h index 2b745c7..fb1b016 100644 --- a/include/nvgpu/pmu.h +++ b/include/nvgpu/pmu.h | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2017-2019, NVIDIA CORPORATION. All rights reserved. | 2 | * Copyright (c) 2017-2022, NVIDIA CORPORATION. All rights reserved. |
3 | * | 3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), | 5 | * copy of this software and associated documentation files (the "Software"), |
@@ -94,6 +94,23 @@ | |||
94 | #define PMU_STATE_STARTED 7U /* Fully unitialized */ | 94 | #define PMU_STATE_STARTED 7U /* Fully unitialized */ |
95 | #define PMU_STATE_EXIT 8U /* Exit PMU state machine */ | 95 | #define PMU_STATE_EXIT 8U /* Exit PMU state machine */ |
96 | 96 | ||
97 | /* state transition : | ||
98 | * OFF => [OFF_ON_PENDING optional] => ON_PENDING => ON => OFF | ||
99 | * ON => OFF is always synchronized | ||
100 | */ | ||
101 | /* elpg is off */ | ||
102 | #define PMU_ELPG_STAT_OFF 0U | ||
103 | /* elpg is on */ | ||
104 | #define PMU_ELPG_STAT_ON 1U | ||
105 | /* elpg is off, ALLOW cmd has been sent, wait for ack */ | ||
106 | #define PMU_ELPG_STAT_ON_PENDING 2U | ||
107 | /* elpg is on, DISALLOW cmd has been sent, wait for ack */ | ||
108 | #define PMU_ELPG_STAT_OFF_PENDING 3U | ||
109 | /* elpg is off, caller has requested on, but ALLOW | ||
110 | * cmd hasn't been sent due to ENABLE_ALLOW delay | ||
111 | */ | ||
112 | #define PMU_ELPG_STAT_OFF_ON_PENDING 4U | ||
113 | |||
97 | #define GK20A_PMU_UCODE_NB_MAX_OVERLAY 32U | 114 | #define GK20A_PMU_UCODE_NB_MAX_OVERLAY 32U |
98 | #define GK20A_PMU_UCODE_NB_MAX_DATE_LENGTH 64U | 115 | #define GK20A_PMU_UCODE_NB_MAX_DATE_LENGTH 64U |
99 | 116 | ||
@@ -351,6 +368,7 @@ struct nvgpu_pmu { | |||
351 | u32 stat_dmem_offset[PMU_PG_ELPG_ENGINE_ID_INVALID_ENGINE]; | 368 | u32 stat_dmem_offset[PMU_PG_ELPG_ENGINE_ID_INVALID_ENGINE]; |
352 | 369 | ||
353 | u32 elpg_stat; | 370 | u32 elpg_stat; |
371 | u32 disallow_state; | ||
354 | 372 | ||
355 | u32 mscg_stat; | 373 | u32 mscg_stat; |
356 | u32 mscg_transition_state; | 374 | u32 mscg_transition_state; |