Include nvgpu headers

These are needed to build on NVIDIA's Jetson boards for the time
being. Only a couple structs are required, so it should be fairly
easy to remove this dependency at some point in the future.

1 files changed, 527 insertions, 0 deletions

diff --git a/include/nvgpu/pmu.h b/include/nvgpu/pmu.h
new file mode 100644
index 0000000..2b745c7
--- /dev/null
+++ b/include/nvgpu/pmu.h
@@ -0,0 +1,527 @@
+/*
+ * Copyright (c) 2017-2019, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef NVGPU_PMU_H
+#define NVGPU_PMU_H
+
+#include <nvgpu/kmem.h>
+#include <nvgpu/nvgpu_mem.h>
+#include <nvgpu/allocator.h>
+#include <nvgpu/lock.h>
+#include <nvgpu/cond.h>
+#include <nvgpu/thread.h>
+#include <nvgpu/nvgpu_common.h>
+#include <nvgpu/flcnif_cmn.h>
+#include <nvgpu/pmuif/nvgpu_gpmu_cmdif.h>
+#include <nvgpu/falcon.h>
+
+#define nvgpu_pmu_dbg(g, fmt, args...) \
+        nvgpu_log(g, gpu_dbg_pmu, fmt, ##args)
+
+/* defined by pmu hw spec */
+#define GK20A_PMU_VA_SIZE               (512 * 1024 * 1024)
+#define GK20A_PMU_UCODE_SIZE_MAX        (256 * 1024)
+#define GK20A_PMU_SEQ_BUF_SIZE          4096
+
+#define GK20A_PMU_TRACE_BUFSIZE         0x4000    /* 4K */
+#define GK20A_PMU_DMEM_BLKSIZE2         8
+
+#define PMU_MODE_MISMATCH_STATUS_MAILBOX_R  6
+#define PMU_MODE_MISMATCH_STATUS_VAL        0xDEADDEAD
+
+/* Falcon Register index */
+#define PMU_FALCON_REG_R0               (0)
+#define PMU_FALCON_REG_R1               (1)
+#define PMU_FALCON_REG_R2               (2)
+#define PMU_FALCON_REG_R3               (3)
+#define PMU_FALCON_REG_R4               (4)
+#define PMU_FALCON_REG_R5               (5)
+#define PMU_FALCON_REG_R6               (6)
+#define PMU_FALCON_REG_R7               (7)
+#define PMU_FALCON_REG_R8               (8)
+#define PMU_FALCON_REG_R9               (9)
+#define PMU_FALCON_REG_R10              (10)
+#define PMU_FALCON_REG_R11              (11)
+#define PMU_FALCON_REG_R12              (12)
+#define PMU_FALCON_REG_R13              (13)
+#define PMU_FALCON_REG_R14              (14)
+#define PMU_FALCON_REG_R15              (15)
+#define PMU_FALCON_REG_IV0              (16)
+#define PMU_FALCON_REG_IV1              (17)
+#define PMU_FALCON_REG_UNDEFINED        (18)
+#define PMU_FALCON_REG_EV               (19)
+#define PMU_FALCON_REG_SP               (20)
+#define PMU_FALCON_REG_PC               (21)
+#define PMU_FALCON_REG_IMB              (22)
+#define PMU_FALCON_REG_DMB              (23)
+#define PMU_FALCON_REG_CSW              (24)
+#define PMU_FALCON_REG_CCR              (25)
+#define PMU_FALCON_REG_SEC              (26)
+#define PMU_FALCON_REG_CTX              (27)
+#define PMU_FALCON_REG_EXCI             (28)
+#define PMU_FALCON_REG_RSVD0    (29)
+#define PMU_FALCON_REG_RSVD1    (30)
+#define PMU_FALCON_REG_RSVD2    (31)
+#define PMU_FALCON_REG_SIZE             (32)
+
+/* Choices for pmu_state */
+#define PMU_STATE_OFF                   0U /* PMU is off */
+#define PMU_STATE_STARTING              1U /* PMU is on, but not booted */
+#define PMU_STATE_INIT_RECEIVED         2U /* PMU init message received */
+#define PMU_STATE_ELPG_BOOTING          3U /* PMU is booting */
+#define PMU_STATE_ELPG_BOOTED           4U /* ELPG is initialized */
+#define PMU_STATE_LOADING_PG_BUF        5U /* Loading PG buf */
+#define PMU_STATE_LOADING_ZBC           6U /* Loading ZBC buf */
+#define PMU_STATE_STARTED               7U /* Fully unitialized */
+#define PMU_STATE_EXIT                  8U /* Exit PMU state machine */
+
+#define GK20A_PMU_UCODE_NB_MAX_OVERLAY      32U
+#define GK20A_PMU_UCODE_NB_MAX_DATE_LENGTH  64U
+
+#define PMU_MAX_NUM_SEQUENCES           (256U)
+#define PMU_SEQ_BIT_SHIFT               (5U)
+#define PMU_SEQ_TBL_SIZE        \
+                (PMU_MAX_NUM_SEQUENCES >> PMU_SEQ_BIT_SHIFT)
+
+#define PMU_INVALID_SEQ_DESC            (~0)
+
+enum {
+        GK20A_PMU_DMAIDX_UCODE          = 0,
+        GK20A_PMU_DMAIDX_VIRT           = 1,
+        GK20A_PMU_DMAIDX_PHYS_VID       = 2,
+        GK20A_PMU_DMAIDX_PHYS_SYS_COH   = 3,
+        GK20A_PMU_DMAIDX_PHYS_SYS_NCOH  = 4,
+        GK20A_PMU_DMAIDX_RSVD           = 5,
+        GK20A_PMU_DMAIDX_PELPG          = 6,
+        GK20A_PMU_DMAIDX_END            = 7
+};
+
+enum {
+        PMU_SEQ_STATE_FREE = 0,
+        PMU_SEQ_STATE_PENDING,
+        PMU_SEQ_STATE_USED,
+        PMU_SEQ_STATE_CANCELLED
+};
+
+/*PG defines used by nvpgu-pmu*/
+#define PMU_PG_IDLE_THRESHOLD_SIM               1000
+#define PMU_PG_POST_POWERUP_IDLE_THRESHOLD_SIM  4000000
+/* TBD: QT or else ? */
+#define PMU_PG_IDLE_THRESHOLD                   15000
+#define PMU_PG_POST_POWERUP_IDLE_THRESHOLD      1000000
+
+#define PMU_PG_LPWR_FEATURE_RPPG 0x0
+#define PMU_PG_LPWR_FEATURE_MSCG 0x1
+
+#define PMU_MSCG_DISABLED 0U
+#define PMU_MSCG_ENABLED 1U
+
+/* Default Sampling Period of AELPG */
+#define APCTRL_SAMPLING_PERIOD_PG_DEFAULT_US                    (1000000)
+
+/* Default values of APCTRL parameters */
+#define APCTRL_MINIMUM_IDLE_FILTER_DEFAULT_US                   (100)
+#define APCTRL_MINIMUM_TARGET_SAVING_DEFAULT_US                 (10000)
+#define APCTRL_POWER_BREAKEVEN_DEFAULT_US                       (2000)
+#define APCTRL_CYCLES_PER_SAMPLE_MAX_DEFAULT                    (200)
+
+/* pmu load const defines */
+#define PMU_BUSY_CYCLES_NORM_MAX                (1000U)
+
+/* RPC */
+#define PMU_RPC_EXECUTE(_stat, _pmu, _unit, _func, _prpc, _size)\
+        do {                                                 \
+                memset(&((_prpc)->hdr), 0, sizeof((_prpc)->hdr));\
+                \
+                (_prpc)->hdr.unit_id   = PMU_UNIT_##_unit;       \
+                (_prpc)->hdr.function = NV_PMU_RPC_ID_##_unit##_##_func;\
+                (_prpc)->hdr.flags    = 0x0;    \
+                \
+                _stat = nvgpu_pmu_rpc_execute(_pmu, &((_prpc)->hdr),    \
+                        (sizeof(*(_prpc)) - sizeof((_prpc)->scratch)),\
+                        (_size), NULL, NULL, false);    \
+        } while (0)
+
+/* RPC blocking call to copy back data from PMU to  _prpc */
+#define PMU_RPC_EXECUTE_CPB(_stat, _pmu, _unit, _func, _prpc, _size)\
+        do {                                                 \
+                memset(&((_prpc)->hdr), 0, sizeof((_prpc)->hdr));\
+                \
+                (_prpc)->hdr.unit_id   = PMU_UNIT_##_unit;       \
+                (_prpc)->hdr.function = NV_PMU_RPC_ID_##_unit##_##_func;\
+                (_prpc)->hdr.flags    = 0x0;    \
+                \
+                _stat = nvgpu_pmu_rpc_execute(_pmu, &((_prpc)->hdr),    \
+                        (sizeof(*(_prpc)) - sizeof((_prpc)->scratch)),\
+                        (_size), NULL, NULL, true);     \
+        } while (0)
+
+/* RPC non-blocking with call_back handler option */
+#define PMU_RPC_EXECUTE_CB(_stat, _pmu, _unit, _func, _prpc, _size, _cb, _cbp)\
+        do {                                                 \
+                memset(&((_prpc)->hdr), 0, sizeof((_prpc)->hdr));\
+                \
+                (_prpc)->hdr.unit_id   = PMU_UNIT_##_unit;       \
+                (_prpc)->hdr.function = NV_PMU_RPC_ID_##_unit##_##_func;\
+                (_prpc)->hdr.flags    = 0x0;    \
+                \
+                _stat = nvgpu_pmu_rpc_execute(_pmu, &((_prpc)->hdr),    \
+                        (sizeof(*(_prpc)) - sizeof((_prpc)->scratch)),\
+                        (_size), _cb, _cbp, false);     \
+        } while (0)
+
+typedef void (*pmu_callback)(struct gk20a *, struct pmu_msg *, void *, u32,
+        u32);
+
+struct rpc_handler_payload {
+        void *rpc_buff;
+        bool is_mem_free_set;
+        bool complete;
+};
+
+struct pmu_rpc_desc {
+        void   *prpc;
+        u16 size_rpc;
+        u16 size_scratch;
+};
+
+struct pmu_payload {
+        struct {
+                void *buf;
+                u32 offset;
+                u32 size;
+                u32 fb_size;
+        } in, out;
+        struct pmu_rpc_desc rpc;
+};
+
+struct pmu_ucode_desc {
+        u32 descriptor_size;
+        u32 image_size;