diff options
| author | Joshua Bakita <bakitajoshua@gmail.com> | 2023-10-29 13:07:40 -0400 |
|---|---|---|
| committer | Joshua Bakita <bakitajoshua@gmail.com> | 2023-10-29 13:10:52 -0400 |
| commit | 2c5337a24f7f2d02989dfb733c55d6d8c7e90493 (patch) | |
| tree | b9f1028cb443b03190b710c0d7ee640bf5958631 /include/nvgpu/nvgpu_err.h | |
| parent | aa06f84f03cba7ad1aae5cd527355bb3d8c152a6 (diff) | |
Update includes to L4T r32.7.4 and drop nvgpu/gk20a.h dependency
Also add instructions for updating `include/`. These files are now
only needed to build on Linux 4.9-based Tegra platforms.
Diffstat (limited to 'include/nvgpu/nvgpu_err.h')
| -rw-r--r-- | include/nvgpu/nvgpu_err.h | 359 |
1 files changed, 359 insertions, 0 deletions
diff --git a/include/nvgpu/nvgpu_err.h b/include/nvgpu/nvgpu_err.h new file mode 100644 index 0000000..0595faf --- /dev/null +++ b/include/nvgpu/nvgpu_err.h | |||
| @@ -0,0 +1,359 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (c) 2021, NVIDIA CORPORATION. All rights reserved. | ||
| 3 | * | ||
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
| 5 | * copy of this software and associated documentation files (the "Software"), | ||
| 6 | * to deal in the Software without restriction, including without limitation | ||
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
| 8 | * and/or sell copies of the Software, and to permit persons to whom the | ||
| 9 | * Software is furnished to do so, subject to the following conditions: | ||
| 10 | * | ||
| 11 | * The above copyright notice and this permission notice shall be included in | ||
| 12 | * all copies or substantial portions of the Software. | ||
| 13 | * | ||
| 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
| 15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
| 16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
| 17 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
| 18 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
| 19 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
| 20 | * DEALINGS IN THE SOFTWARE. | ||
| 21 | */ | ||
| 22 | |||
| 23 | #ifndef NVGPU_NVGPU_ERR_H | ||
| 24 | #define NVGPU_NVGPU_ERR_H | ||
| 25 | |||
| 26 | /** | ||
| 27 | * @file | ||
| 28 | * | ||
| 29 | * Define indices for HW units and errors. Define structures used to carry error | ||
| 30 | * information. Declare prototype for APIs that are used to report GPU HW errors | ||
| 31 | * to the Safety_Services framework. | ||
| 32 | */ | ||
| 33 | |||
| 34 | #include <nvgpu/types.h> | ||
| 35 | #include <nvgpu/atomic.h> | ||
| 36 | |||
| 37 | struct gk20a; | ||
| 38 | |||
| 39 | /** | ||
| 40 | * @defgroup INDICES_FOR_GPU_HW_UNITS | ||
| 41 | * Macros used to assign unique index to GPU HW units. | ||
| 42 | * @{ | ||
| 43 | */ | ||
| 44 | #define NVGPU_ERR_MODULE_SM (0U) | ||
| 45 | #define NVGPU_ERR_MODULE_FECS (1U) | ||
| 46 | #define NVGPU_ERR_MODULE_PMU (2U) | ||
| 47 | /** | ||
| 48 | * @} | ||
| 49 | */ | ||
| 50 | |||
| 51 | /** | ||
| 52 | * @defgroup LIST_OF_ERRORS_REPORTED_FROM_SM | ||
| 53 | * Macros used to assign unique index to errors reported from the SM unit. | ||
| 54 | * @{ | ||
| 55 | */ | ||
| 56 | #define GPU_SM_L1_TAG_ECC_CORRECTED (0U) | ||
| 57 | #define GPU_SM_L1_TAG_ECC_UNCORRECTED (1U) | ||
| 58 | #define GPU_SM_CBU_ECC_UNCORRECTED (3U) | ||
| 59 | #define GPU_SM_LRF_ECC_UNCORRECTED (5U) | ||
| 60 | #define GPU_SM_L1_DATA_ECC_UNCORRECTED (7U) | ||
| 61 | #define GPU_SM_ICACHE_L0_DATA_ECC_UNCORRECTED (9U) | ||
| 62 | #define GPU_SM_ICACHE_L1_DATA_ECC_UNCORRECTED (11U) | ||
| 63 | #define GPU_SM_ICACHE_L0_PREDECODE_ECC_UNCORRECTED (13U) | ||
| 64 | #define GPU_SM_L1_TAG_MISS_FIFO_ECC_UNCORRECTED (15U) | ||
| 65 | #define GPU_SM_L1_TAG_S2R_PIXPRF_ECC_UNCORRECTED (17U) | ||
| 66 | #define GPU_SM_ICACHE_L1_PREDECODE_ECC_UNCORRECTED (20U) | ||
| 67 | /** | ||
| 68 | * @} | ||
| 69 | */ | ||
| 70 | |||
| 71 | /** | ||
| 72 | * @defgroup LIST_OF_ERRORS_REPORTED_FROM_FECS | ||
| 73 | * Macros used to assign unique index to errors reported from the FECS unit. | ||
| 74 | * @{ | ||
| 75 | */ | ||
| 76 | #define GPU_FECS_FALCON_IMEM_ECC_CORRECTED (0U) | ||
| 77 | #define GPU_FECS_FALCON_IMEM_ECC_UNCORRECTED (1U) | ||
| 78 | #define GPU_FECS_FALCON_DMEM_ECC_UNCORRECTED (3U) | ||
| 79 | /** | ||
| 80 | * @} | ||
| 81 | */ | ||
| 82 | |||
| 83 | /** | ||
| 84 | * @defgroup LIST_OF_ERRORS_REPORTED_FROM_GPCCS | ||
| 85 | * Macros used to assign unique index to errors reported from the GPCCS unit. | ||
| 86 | * @{ | ||
| 87 | */ | ||
| 88 | #define GPU_GPCCS_FALCON_IMEM_ECC_CORRECTED (0U) | ||
| 89 | #define GPU_GPCCS_FALCON_IMEM_ECC_UNCORRECTED (1U) | ||
| 90 | #define GPU_GPCCS_FALCON_DMEM_ECC_UNCORRECTED (3U) | ||
| 91 | /** | ||
| 92 | * @} | ||
| 93 | */ | ||
| 94 | |||
| 95 | /** | ||
| 96 | * @defgroup LIST_OF_ERRORS_REPORTED_FROM_MMU | ||
| 97 | * Macros used to assign unique index to errors reported from the MMU unit. | ||
| 98 | * @{ | ||
| 99 | */ | ||
| 100 | #define GPU_MMU_L1TLB_SA_DATA_ECC_UNCORRECTED (1U) | ||
| 101 | #define GPU_MMU_L1TLB_FA_DATA_ECC_UNCORRECTED (3U) | ||
| 102 | /** | ||
| 103 | * @} | ||
| 104 | */ | ||
| 105 | |||
| 106 | /** | ||
| 107 | * @defgroup LIST_OF_ERRORS_REPORTED_FROM_GCC | ||
| 108 | * Macros used to assign unique index to errors reported from the GCC unit. | ||
| 109 | * @{ | ||
| 110 | */ | ||
| 111 | #define GPU_GCC_L15_ECC_UNCORRECTED (1U) | ||
| 112 | /** | ||
| 113 | * @} | ||
| 114 | */ | ||
| 115 | |||
| 116 | |||
| 117 | /** | ||
| 118 | * @defgroup LIST_OF_ERRORS_REPORTED_FROM_PMU | ||
| 119 | * Macros used to assign unique index to errors reported from the PMU unit. | ||
| 120 | * @{ | ||
| 121 | */ | ||
| 122 | #define GPU_PMU_FALCON_IMEM_ECC_CORRECTED (0U) | ||
| 123 | #define GPU_PMU_FALCON_IMEM_ECC_UNCORRECTED (1U) | ||
| 124 | #define GPU_PMU_FALCON_DMEM_ECC_UNCORRECTED (3U) | ||
| 125 | /** | ||
| 126 | * @} | ||
| 127 | */ | ||
| 128 | |||
| 129 | /** | ||
| 130 | * @defgroup LIST_OF_ERRORS_REPORTED_FROM_LTC | ||
| 131 | * Macros used to assign unique index to errors reported from the LTC unit. | ||
| 132 | * @{ | ||
| 133 | */ | ||
| 134 | #define GPU_LTC_CACHE_DSTG_ECC_CORRECTED (0U) | ||
| 135 | #define GPU_LTC_CACHE_DSTG_ECC_UNCORRECTED (1U) | ||
| 136 | #define GPU_LTC_CACHE_TSTG_ECC_UNCORRECTED (3U) | ||
| 137 | #define GPU_LTC_CACHE_DSTG_BE_ECC_UNCORRECTED (7U) | ||
| 138 | /** | ||
| 139 | * @} | ||
| 140 | */ | ||
| 141 | |||
| 142 | /** | ||
| 143 | * @defgroup LIST_OF_ERRORS_REPORTED_FROM_HUBMMU | ||
| 144 | * Macros used to assign unique index to errors reported from the HUBMMU unit. | ||
| 145 | * @{ | ||
| 146 | */ | ||
| 147 | #define GPU_HUBMMU_L2TLB_SA_DATA_ECC_UNCORRECTED (1U) | ||
| 148 | #define GPU_HUBMMU_TLB_SA_DATA_ECC_UNCORRECTED (3U) | ||
| 149 | #define GPU_HUBMMU_PTE_DATA_ECC_UNCORRECTED (5U) | ||
| 150 | #define GPU_HUBMMU_PDE0_DATA_ECC_UNCORRECTED (7U) | ||
| 151 | #define GPU_HUBMMU_PAGE_FAULT_ERROR (8U) | ||
| 152 | |||
| 153 | |||
| 154 | #ifdef CONFIG_NVGPU_SUPPORT_LINUX_ECC_ERROR_REPORTING | ||
| 155 | /** | ||
| 156 | * @} | ||
| 157 | */ | ||
| 158 | |||
| 159 | /** | ||
| 160 | * nvgpu_err_desc structure holds fields which describe an error along with | ||
| 161 | * function callback which can be used to inject the error. | ||
| 162 | */ | ||
| 163 | struct nvgpu_err_desc { | ||
| 164 | /** String representation of error. */ | ||
| 165 | const char *name; | ||
| 166 | |||
| 167 | /** Flag to classify an error as critical or non-critical. */ | ||
| 168 | bool is_critical; | ||
| 169 | |||
| 170 | /** | ||
| 171 | * Error Threshold: once this threshold value is reached, then the | ||
| 172 | * corresponding error counter will be reset to 0 and the error will be | ||
| 173 | * propagated to Safety_Services. | ||
| 174 | */ | ||
| 175 | int err_threshold; | ||
| 176 | |||
| 177 | /** | ||
| 178 | * Total number of times an error has occurred (since its last reset). | ||
| 179 | */ | ||
| 180 | nvgpu_atomic_t err_count; | ||
| 181 | |||
| 182 | /** Error ID. */ | ||
| 183 | u8 error_id; | ||
| 184 | }; | ||
| 185 | |||
| 186 | /** | ||
| 187 | * gpu_err_header structure holds fields which are required to identify the | ||
| 188 | * version of header, sub-error type, sub-unit id, error address and time stamp. | ||
| 189 | */ | ||
| 190 | struct gpu_err_header { | ||
| 191 | /** Version of GPU error header. */ | ||
| 192 | struct { | ||
| 193 | /** Major version number. */ | ||
| 194 | u16 major; | ||
| 195 | /** Minor version number. */ | ||
| 196 | u16 minor; | ||
| 197 | } version; | ||
| 198 | |||
| 199 | /** Sub error type corresponding to the error that is being reported. */ | ||
| 200 | u32 sub_err_type; | ||
| 201 | |||
| 202 | /** ID of the sub-unit in a HW unit which encountered an error. */ | ||
| 203 | u64 sub_unit_id; | ||
| 204 | |||
| 205 | /** Location of the error. */ | ||
| 206 | u64 address; | ||
| 207 | |||
| 208 | /** Timestamp in nano seconds. */ | ||
| 209 | u64 timestamp_ns; | ||
| 210 | }; | ||
| 211 | |||
| 212 | struct gpu_ecc_error_info { | ||
| 213 | struct gpu_err_header header; | ||
| 214 | |||
| 215 | /** Number of ECC errors. */ | ||
| 216 | u64 err_cnt; | ||
| 217 | }; | ||
| 218 | |||
| 219 | /** | ||
| 220 | * nvgpu_err_hw_module structure holds fields which describe the h/w modules | ||
| 221 | * error reporting capabilities. | ||
| 222 | |||
