diff options
author | Joshua Bakita <bakitajoshua@gmail.com> | 2023-10-29 13:07:40 -0400 |
---|---|---|
committer | Joshua Bakita <bakitajoshua@gmail.com> | 2023-10-29 13:10:52 -0400 |
commit | 2c5337a24f7f2d02989dfb733c55d6d8c7e90493 (patch) | |
tree | b9f1028cb443b03190b710c0d7ee640bf5958631 /include/nvgpu/hw | |
parent | aa06f84f03cba7ad1aae5cd527355bb3d8c152a6 (diff) |
Update includes to L4T r32.7.4 and drop nvgpu/gk20a.h dependency
Also add instructions for updating `include/`. These files are now
only needed to build on Linux 4.9-based Tegra platforms.
Diffstat (limited to 'include/nvgpu/hw')
-rw-r--r-- | include/nvgpu/hw/gk20a/hw_gr_gk20a.h | 61 | ||||
-rw-r--r-- | include/nvgpu/hw/gm20b/hw_gr_gm20b.h | 14 | ||||
-rw-r--r-- | include/nvgpu/hw/gp106/hw_gr_gp106.h | 4 | ||||
-rw-r--r-- | include/nvgpu/hw/gp10b/hw_gr_gp10b.h | 4 | ||||
-rw-r--r-- | include/nvgpu/hw/gv100/hw_gr_gv100.h | 4 | ||||
-rw-r--r-- | include/nvgpu/hw/gv11b/hw_gr_gv11b.h | 4 |
6 files changed, 90 insertions, 1 deletions
diff --git a/include/nvgpu/hw/gk20a/hw_gr_gk20a.h b/include/nvgpu/hw/gk20a/hw_gr_gk20a.h index 826108f..376cc8f 100644 --- a/include/nvgpu/hw/gk20a/hw_gr_gk20a.h +++ b/include/nvgpu/hw/gk20a/hw_gr_gk20a.h | |||
@@ -1380,6 +1380,10 @@ static inline u32 gr_gpc0_gpccs_ctxsw_status_1_r(void) | |||
1380 | { | 1380 | { |
1381 | return 0x00502400U; | 1381 | return 0x00502400U; |
1382 | } | 1382 | } |
1383 | static inline u32 gr_gpc0_gpccs_ctxsw_mailbox__size_1_v(void) | ||
1384 | { | ||
1385 | return 0x00000010U; | ||
1386 | } | ||
1383 | static inline u32 gr_fecs_ctxsw_idlestate_r(void) | 1387 | static inline u32 gr_fecs_ctxsw_idlestate_r(void) |
1384 | { | 1388 | { |
1385 | return 0x00409420U; | 1389 | return 0x00409420U; |
@@ -3804,4 +3808,61 @@ static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_run_trigger_task_f(void) | |||
3804 | { | 3808 | { |
3805 | return 0x40000000U; | 3809 | return 0x40000000U; |
3806 | } | 3810 | } |
3811 | |||
3812 | static inline u32 gr_gpc0_gpccs_falcon_irqstat_r(void) | ||
3813 | { | ||
3814 | return 0x00502008U; | ||
3815 | } | ||
3816 | static inline u32 gr_gpc0_gpccs_falcon_irqmode_r(void) | ||
3817 | { | ||
3818 | return 0x0050200cU; | ||
3819 | } | ||
3820 | static inline u32 gr_gpc0_gpccs_falcon_irqmask_r(void) | ||
3821 | { | ||
3822 | return 0x00502018U; | ||
3823 | } | ||
3824 | static inline u32 gr_gpc0_gpccs_falcon_irqdest_r(void) | ||
3825 | { | ||
3826 | return 0x0050201cU; | ||
3827 | } | ||
3828 | static inline u32 gr_gpc0_gpccs_falcon_debug1_r(void) | ||
3829 | { | ||
3830 | return 0x00502090U; | ||
3831 | } | ||
3832 | static inline u32 gr_gpc0_gpccs_falcon_debuginfo_r(void) | ||
3833 | { | ||
3834 | return 0x00502094U; | ||
3835 | } | ||
3836 | static inline u32 gr_gpc0_gpccs_falcon_engctl_r(void) | ||
3837 | { | ||
3838 | return 0x005020a4U; | ||
3839 | } | ||
3840 | static inline u32 gr_gpc0_gpccs_falcon_curctx_r(void) | ||
3841 | { | ||
3842 | return 0x00502050U; | ||
3843 | } | ||
3844 | static inline u32 gr_gpc0_gpccs_falcon_nxtctx_r(void) | ||
3845 | { | ||
3846 | return 0x00502054U; | ||
3847 | } | ||
3848 | static inline u32 gr_gpc0_gpccs_ctxsw_mailbox_r(u32 i) | ||
3849 | { | ||
3850 | return 0x00502800U + i*4U; | ||
3851 | } | ||
3852 | static inline u32 gr_gpc0_gpccs_falcon_icd_cmd_r(void) | ||
3853 | { | ||
3854 | return 0x00502200U; | ||
3855 | } | ||
3856 | static inline u32 gr_gpc0_gpccs_falcon_icd_cmd_opc_rreg_f(void) | ||
3857 | { | ||
3858 | return 0x8U; | ||
3859 | } | ||
3860 | static inline u32 gr_gpc0_gpccs_falcon_icd_cmd_idx_f(u32 v) | ||
3861 | { | ||
3862 | return (v & 0x1fU) << 8U; | ||
3863 | } | ||
3864 | static inline u32 gr_gpc_gpccs_falcon_icd_rdata_r(void) | ||
3865 | { | ||
3866 | return 0x0050220cU; | ||
3867 | } | ||
3807 | #endif | 3868 | #endif |
diff --git a/include/nvgpu/hw/gm20b/hw_gr_gm20b.h b/include/nvgpu/hw/gm20b/hw_gr_gm20b.h index 5bbb3b9..79ad326 100644 --- a/include/nvgpu/hw/gm20b/hw_gr_gm20b.h +++ b/include/nvgpu/hw/gm20b/hw_gr_gm20b.h | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2014-2018, NVIDIA CORPORATION. All rights reserved. | 2 | * Copyright (c) 2014-2023, NVIDIA CORPORATION. All rights reserved. |
3 | * | 3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), | 5 | * copy of this software and associated documentation files (the "Software"), |
@@ -1396,6 +1396,10 @@ static inline u32 gr_gpc0_gpccs_ctxsw_status_1_r(void) | |||
1396 | { | 1396 | { |
1397 | return 0x00502400U; | 1397 | return 0x00502400U; |
1398 | } | 1398 | } |
1399 | static inline u32 gr_gpc0_gpccs_ctxsw_mailbox__size_1_v(void) | ||
1400 | { | ||
1401 | return 0x00000010U; | ||
1402 | } | ||
1399 | static inline u32 gr_fecs_ctxsw_idlestate_r(void) | 1403 | static inline u32 gr_fecs_ctxsw_idlestate_r(void) |
1400 | { | 1404 | { |
1401 | return 0x00409420U; | 1405 | return 0x00409420U; |
@@ -2344,6 +2348,14 @@ static inline u32 gr_gpcs_tpcs_tex_m_dbg2_su_rd_coalesce_en_m(void) | |||
2344 | { | 2348 | { |
2345 | return 0x1U << 4U; | 2349 | return 0x1U << 4U; |
2346 | } | 2350 | } |
2351 | static inline u32 gr_gpcs_tpcs_tex_m_dbg2_tex_rd_coalesce_en_f(u32 v) | ||
2352 | { | ||
2353 | return (v & 0x1U) << 5U; | ||
2354 | } | ||
2355 | static inline u32 gr_gpcs_tpcs_tex_m_dbg2_tex_rd_coalesce_en_m(void) | ||
2356 | { | ||
2357 | return 0x1U << 5U; | ||
2358 | } | ||
2347 | static inline u32 gr_gpccs_falcon_addr_r(void) | 2359 | static inline u32 gr_gpccs_falcon_addr_r(void) |
2348 | { | 2360 | { |
2349 | return 0x0041a0acU; | 2361 | return 0x0041a0acU; |
diff --git a/include/nvgpu/hw/gp106/hw_gr_gp106.h b/include/nvgpu/hw/gp106/hw_gr_gp106.h index 3ebed7e..ac82901 100644 --- a/include/nvgpu/hw/gp106/hw_gr_gp106.h +++ b/include/nvgpu/hw/gp106/hw_gr_gp106.h | |||
@@ -1508,6 +1508,10 @@ static inline u32 gr_gpc0_gpccs_ctxsw_status_1_r(void) | |||
1508 | { | 1508 | { |
1509 | return 0x00502400U; | 1509 | return 0x00502400U; |
1510 | } | 1510 | } |
1511 | static inline u32 gr_gpc0_gpccs_ctxsw_mailbox__size_1_v(void) | ||
1512 | { | ||
1513 | return 0x00000010U; | ||
1514 | } | ||
1511 | static inline u32 gr_fecs_ctxsw_idlestate_r(void) | 1515 | static inline u32 gr_fecs_ctxsw_idlestate_r(void) |
1512 | { | 1516 | { |
1513 | return 0x00409420U; | 1517 | return 0x00409420U; |
diff --git a/include/nvgpu/hw/gp10b/hw_gr_gp10b.h b/include/nvgpu/hw/gp10b/hw_gr_gp10b.h index f7bc4c2..89c6bba 100644 --- a/include/nvgpu/hw/gp10b/hw_gr_gp10b.h +++ b/include/nvgpu/hw/gp10b/hw_gr_gp10b.h | |||
@@ -1584,6 +1584,10 @@ static inline u32 gr_gpc0_gpccs_ctxsw_status_1_r(void) | |||
1584 | { | 1584 | { |
1585 | return 0x00502400U; | 1585 | return 0x00502400U; |
1586 | } | 1586 | } |
1587 | static inline u32 gr_gpc0_gpccs_ctxsw_mailbox__size_1_v(void) | ||
1588 | { | ||
1589 | return 0x00000010U; | ||
1590 | } | ||
1587 | static inline u32 gr_fecs_ctxsw_idlestate_r(void) | 1591 | static inline u32 gr_fecs_ctxsw_idlestate_r(void) |
1588 | { | 1592 | { |
1589 | return 0x00409420U; | 1593 | return 0x00409420U; |
diff --git a/include/nvgpu/hw/gv100/hw_gr_gv100.h b/include/nvgpu/hw/gv100/hw_gr_gv100.h index 0f83d6b..3955a63 100644 --- a/include/nvgpu/hw/gv100/hw_gr_gv100.h +++ b/include/nvgpu/hw/gv100/hw_gr_gv100.h | |||
@@ -1816,6 +1816,10 @@ static inline u32 gr_gpc0_gpccs_ctxsw_status_1_r(void) | |||
1816 | { | 1816 | { |
1817 | return 0x00502400U; | 1817 | return 0x00502400U; |
1818 | } | 1818 | } |
1819 | static inline u32 gr_gpc0_gpccs_ctxsw_mailbox__size_1_v(void) | ||
1820 | { | ||
1821 | return 0x00000010U; | ||
1822 | } | ||
1819 | static inline u32 gr_fecs_ctxsw_idlestate_r(void) | 1823 | static inline u32 gr_fecs_ctxsw_idlestate_r(void) |
1820 | { | 1824 | { |
1821 | return 0x00409420U; | 1825 | return 0x00409420U; |
diff --git a/include/nvgpu/hw/gv11b/hw_gr_gv11b.h b/include/nvgpu/hw/gv11b/hw_gr_gv11b.h index f7d8089..4a3da79 100644 --- a/include/nvgpu/hw/gv11b/hw_gr_gv11b.h +++ b/include/nvgpu/hw/gv11b/hw_gr_gv11b.h | |||
@@ -2420,6 +2420,10 @@ static inline u32 gr_gpc0_gpccs_ctxsw_status_1_r(void) | |||
2420 | { | 2420 | { |
2421 | return 0x00502400U; | 2421 | return 0x00502400U; |
2422 | } | 2422 | } |
2423 | static inline u32 gr_gpc0_gpccs_ctxsw_mailbox__size_1_v(void) | ||
2424 | { | ||
2425 | return 0x00000010U; | ||
2426 | } | ||
2423 | static inline u32 gr_fecs_ctxsw_idlestate_r(void) | 2427 | static inline u32 gr_fecs_ctxsw_idlestate_r(void) |
2424 | { | 2428 | { |
2425 | return 0x00409420U; | 2429 | return 0x00409420U; |