diff options
author | Joshua Bakita <bakitajoshua@gmail.com> | 2023-06-28 18:24:25 -0400 |
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committer | Joshua Bakita <bakitajoshua@gmail.com> | 2023-06-28 18:24:25 -0400 |
commit | 01e6fac4d61fdd7fff5433942ec93fc2ea1e4df1 (patch) | |
tree | 4ef34501728a087be24f4ba0af90f91486bf780b /include/nvgpu/enabled.h | |
parent | 306a03d18b305e4e573be3b2931978fa10679eb9 (diff) |
Include nvgpu headers
These are needed to build on NVIDIA's Jetson boards for the time
being. Only a couple structs are required, so it should be fairly
easy to remove this dependency at some point in the future.
Diffstat (limited to 'include/nvgpu/enabled.h')
-rw-r--r-- | include/nvgpu/enabled.h | 216 |
1 files changed, 216 insertions, 0 deletions
diff --git a/include/nvgpu/enabled.h b/include/nvgpu/enabled.h new file mode 100644 index 0000000..ef55dad --- /dev/null +++ b/include/nvgpu/enabled.h | |||
@@ -0,0 +1,216 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2017-2020, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
5 | * copy of this software and associated documentation files (the "Software"), | ||
6 | * to deal in the Software without restriction, including without limitation | ||
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
8 | * and/or sell copies of the Software, and to permit persons to whom the | ||
9 | * Software is furnished to do so, subject to the following conditions: | ||
10 | * | ||
11 | * The above copyright notice and this permission notice shall be included in | ||
12 | * all copies or substantial portions of the Software. | ||
13 | * | ||
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
17 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
18 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
19 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
20 | * DEALINGS IN THE SOFTWARE. | ||
21 | */ | ||
22 | |||
23 | #ifndef NVGPU_ENABLED_H | ||
24 | #define NVGPU_ENABLED_H | ||
25 | |||
26 | struct gk20a; | ||
27 | |||
28 | #include <nvgpu/types.h> | ||
29 | |||
30 | /* | ||
31 | * Available flags that describe what's enabled and what's not in the GPU. Each | ||
32 | * flag here is defined by it's offset in a bitmap. | ||
33 | */ | ||
34 | #define NVGPU_IS_FMODEL 1 | ||
35 | #define NVGPU_DRIVER_IS_DYING 2 | ||
36 | #define NVGPU_GR_USE_DMA_FOR_FW_BOOTSTRAP 3 | ||
37 | #define NVGPU_FECS_TRACE_VA 4 | ||
38 | #define NVGPU_CAN_RAILGATE 5 | ||
39 | #define NVGPU_KERNEL_IS_DYING 6 | ||
40 | #define NVGPU_FECS_TRACE_FEATURE_CONTROL 7 | ||
41 | |||
42 | /* | ||
43 | * ECC flags | ||
44 | */ | ||
45 | /* SM LRF ECC is enabled */ | ||
46 | #define NVGPU_ECC_ENABLED_SM_LRF 8 | ||
47 | /* SM SHM ECC is enabled */ | ||
48 | #define NVGPU_ECC_ENABLED_SM_SHM 9 | ||
49 | /* TEX ECC is enabled */ | ||
50 | #define NVGPU_ECC_ENABLED_TEX 10 | ||
51 | /* L2 ECC is enabled */ | ||
52 | #define NVGPU_ECC_ENABLED_LTC 11 | ||
53 | /* SM L1 DATA ECC is enabled */ | ||
54 | #define NVGPU_ECC_ENABLED_SM_L1_DATA 12 | ||
55 | /* SM L1 TAG ECC is enabled */ | ||
56 | #define NVGPU_ECC_ENABLED_SM_L1_TAG 13 | ||
57 | /* SM CBU ECC is enabled */ | ||
58 | #define NVGPU_ECC_ENABLED_SM_CBU 14 | ||
59 | /* SM ICAHE ECC is enabled */ | ||
60 | #define NVGPU_ECC_ENABLED_SM_ICACHE 15 | ||
61 | |||
62 | /* | ||
63 | * MM flags. | ||
64 | */ | ||
65 | #define NVGPU_MM_UNIFY_ADDRESS_SPACES 16 | ||
66 | /* false if vidmem aperture actually points to sysmem */ | ||
67 | #define NVGPU_MM_HONORS_APERTURE 17 | ||
68 | /* unified or split memory with separate vidmem? */ | ||
69 | #define NVGPU_MM_UNIFIED_MEMORY 18 | ||
70 | /* User-space managed address spaces support */ | ||
71 | #define NVGPU_SUPPORT_USERSPACE_MANAGED_AS 20 | ||
72 | /* IO coherence support is available */ | ||
73 | #define NVGPU_SUPPORT_IO_COHERENCE 21 | ||
74 | /* MAP_BUFFER_EX with partial mappings */ | ||
75 | #define NVGPU_SUPPORT_PARTIAL_MAPPINGS 22 | ||
76 | /* MAP_BUFFER_EX with sparse allocations */ | ||
77 | #define NVGPU_SUPPORT_SPARSE_ALLOCS 23 | ||
78 | /* Direct PTE kind control is supported (map_buffer_ex) */ | ||
79 | #define NVGPU_SUPPORT_MAP_DIRECT_KIND_CTRL 24 | ||
80 | /* Support batch mapping */ | ||
81 | #define NVGPU_SUPPORT_MAP_BUFFER_BATCH 25 | ||
82 | /* Use coherent aperture for sysmem. */ | ||
83 | #define NVGPU_USE_COHERENT_SYSMEM 26 | ||
84 | /* Use physical scatter tables instead of IOMMU */ | ||
85 | #define NVGPU_MM_USE_PHYSICAL_SG 27 | ||
86 | /* WAR for gm20b chips. */ | ||
87 | #define NVGPU_MM_FORCE_128K_PMU_VM 28 | ||
88 | |||
89 | /* | ||
90 | * Host flags | ||
91 | */ | ||
92 | #define NVGPU_HAS_SYNCPOINTS 30 | ||
93 | /* sync fence FDs are available in, e.g., submit_gpfifo */ | ||
94 | #define NVGPU_SUPPORT_SYNC_FENCE_FDS 31 | ||
95 | /* NVGPU_DBG_GPU_IOCTL_CYCLE_STATS is available */ | ||
96 | #define NVGPU_SUPPORT_CYCLE_STATS 32 | ||
97 | /* NVGPU_DBG_GPU_IOCTL_CYCLE_STATS_SNAPSHOT is available */ | ||
98 | #define NVGPU_SUPPORT_CYCLE_STATS_SNAPSHOT 33 | ||
99 | /* Both gpu driver and device support TSG */ | ||
100 | #define NVGPU_SUPPORT_TSG 34 | ||
101 | /* Fast deterministic submits with no job tracking are supported */ | ||
102 | #define NVGPU_SUPPORT_DETERMINISTIC_SUBMIT_NO_JOBTRACKING 35 | ||
103 | /* Deterministic submits are supported even with job tracking */ | ||
104 | #define NVGPU_SUPPORT_DETERMINISTIC_SUBMIT_FULL 36 | ||
105 | /* NVGPU_IOCTL_CHANNEL_RESCHEDULE_RUNLIST is available */ | ||
106 | #define NVGPU_SUPPORT_RESCHEDULE_RUNLIST 37 | ||
107 | |||
108 | /* NVGPU_GPU_IOCTL_GET_EVENT_FD is available */ | ||
109 | #define NVGPU_SUPPORT_DEVICE_EVENTS 38 | ||
110 | /* FECS context switch tracing is available */ | ||
111 | #define NVGPU_SUPPORT_FECS_CTXSW_TRACE 39 | ||
112 | |||
113 | /* NVGPU_GPU_IOCTL_SET_DETERMINISTIC_OPTS is available */ | ||
114 | #define NVGPU_SUPPORT_DETERMINISTIC_OPTS 40 | ||
115 | |||
116 | /* | ||
117 | * Security flags | ||
118 | */ | ||
119 | |||
120 | #define NVGPU_SEC_SECUREGPCCS 41 | ||
121 | #define NVGPU_SEC_PRIVSECURITY 42 | ||
122 | /* VPR is supported */ | ||
123 | #define NVGPU_SUPPORT_VPR 43 | ||
124 | |||
125 | /* | ||
126 | * Nvlink flags | ||
127 | */ | ||
128 | |||
129 | #define NVGPU_SUPPORT_NVLINK 45 | ||
130 | /* | ||
131 | * PMU flags. | ||
132 | */ | ||
133 | /* perfmon enabled or disabled for PMU */ | ||
134 | #define NVGPU_PMU_PERFMON 48 | ||
135 | #define NVGPU_PMU_PSTATE 49 | ||
136 | #define NVGPU_PMU_ZBC_SAVE 50 | ||
137 | #define NVGPU_PMU_FECS_BOOTSTRAP_DONE 51 | ||
138 | #define NVGPU_GPU_CAN_BLCG 52 | ||
139 | #define NVGPU_GPU_CAN_SLCG 53 | ||
140 | #define NVGPU_GPU_CAN_ELCG 54 | ||
141 | /* Clock control support */ | ||
142 | #define NVGPU_SUPPORT_CLOCK_CONTROLS 55 | ||
143 | /* NVGPU_GPU_IOCTL_GET_VOLTAGE is available */ | ||
144 | #define NVGPU_SUPPORT_GET_VOLTAGE 56 | ||
145 | /* NVGPU_GPU_IOCTL_GET_CURRENT is available */ | ||
146 | #define NVGPU_SUPPORT_GET_CURRENT 57 | ||
147 | /* NVGPU_GPU_IOCTL_GET_POWER is available */ | ||
148 | #define NVGPU_SUPPORT_GET_POWER 58 | ||
149 | /* NVGPU_GPU_IOCTL_GET_TEMPERATURE is available */ | ||
150 | #define NVGPU_SUPPORT_GET_TEMPERATURE 59 | ||
151 | /* NVGPU_GPU_IOCTL_SET_THERM_ALERT_LIMIT is available */ | ||
152 | #define NVGPU_SUPPORT_SET_THERM_ALERT_LIMIT 60 | ||
153 | |||
154 | /* whether to run PREOS binary on dGPUs */ | ||
155 | #define NVGPU_PMU_RUN_PREOS 61 | ||
156 | |||
157 | /* set if ASPM is enabled; only makes sense for PCI */ | ||
158 | #define NVGPU_SUPPORT_ASPM 62 | ||
159 | /* subcontexts are available */ | ||
160 | #define NVGPU_SUPPORT_TSG_SUBCONTEXTS 63 | ||
161 | /* Simultaneous Compute and Graphics (SCG) is available */ | ||
162 | #define NVGPU_SUPPORT_SCG 64 | ||
163 | |||
164 | /* GPU_VA address of a syncpoint is supported */ | ||
165 | #define NVGPU_SUPPORT_SYNCPOINT_ADDRESS 65 | ||
166 | /* Allocating per-channel syncpoint in user space is supported */ | ||
167 | #define NVGPU_SUPPORT_USER_SYNCPOINT 66 | ||
168 | |||
169 | /* USERMODE enable bit */ | ||
170 | #define NVGPU_SUPPORT_USERMODE_SUBMIT 67 | ||
171 | |||
172 | /* Multiple WPR support */ | ||
173 | #define NVGPU_SUPPORT_MULTIPLE_WPR 68 | ||
174 | |||
175 | /* SEC2 RTOS support*/ | ||
176 | #define NVGPU_SUPPORT_SEC2_RTOS 69 | ||
177 | |||
178 | /* NVGPU_GPU_IOCTL_GET_GPU_LOAD is available */ | ||
179 | #define NVGPU_SUPPORT_GET_GPU_LOAD 70 | ||
180 | |||
181 | /* PLATFORM_ATOMIC support */ | ||
182 | #define NVGPU_SUPPORT_PLATFORM_ATOMIC 71 | ||
183 | |||
184 | /* NVGPU_GPU_IOCTL_SET_MMU_DEBUG_MODE is available */ | ||
185 | #define NVGPU_SUPPORT_SET_CTX_MMU_DEBUG_MODE 72 | ||
186 | |||
187 | /* | ||
188 | * Must be greater than the largest bit offset in the above list. | ||
189 | */ | ||
190 | #define NVGPU_MAX_ENABLED_BITS 73U | ||
191 | |||
192 | /** | ||
193 | * nvgpu_is_enabled - Check if the passed flag is enabled. | ||
194 | * | ||
195 | * @g - The GPU. | ||
196 | * @flag - Which flag to check. | ||
197 | * | ||
198 | * Returns true if the passed @flag is true; false otherwise. | ||
199 | */ | ||
200 | bool nvgpu_is_enabled(struct gk20a *g, int flag); | ||
201 | |||
202 | /** | ||
203 | * __nvgpu_set_enabled - Set the state of a flag. | ||
204 | * | ||
205 | * @g - The GPU. | ||
206 | * @flag - Which flag to modify. | ||
207 | * @state - The state to set the flag to. | ||
208 | * | ||
209 | * Set the state of the passed @flag to @state. | ||
210 | */ | ||
211 | void __nvgpu_set_enabled(struct gk20a *g, int flag, bool state); | ||
212 | |||
213 | int nvgpu_init_enabled_flags(struct gk20a *g); | ||
214 | void nvgpu_free_enabled_flags(struct gk20a *g); | ||
215 | |||
216 | #endif /* NVGPU_ENABLED_H */ | ||