diff options
author | Joshua Bakita <bakitajoshua@gmail.com> | 2024-09-25 16:09:09 -0400 |
---|---|---|
committer | Joshua Bakita <bakitajoshua@gmail.com> | 2024-09-25 16:09:09 -0400 |
commit | f347fde22f1297e4f022600d201780d5ead78114 (patch) | |
tree | 76be305d6187003a1e0486ff6e91efb1062ae118 /include/nvgpu/bios.h | |
parent | 8340d234d78a7d0f46c11a584de538148b78b7cb (diff) |
Delete no-longer-needed nvgpu headersHEADmasterjbakita-wip
The dependency on these was removed in commit 8340d234.
Diffstat (limited to 'include/nvgpu/bios.h')
-rw-r--r-- | include/nvgpu/bios.h | 1123 |
1 files changed, 0 insertions, 1123 deletions
diff --git a/include/nvgpu/bios.h b/include/nvgpu/bios.h deleted file mode 100644 index 7d729b6..0000000 --- a/include/nvgpu/bios.h +++ /dev/null | |||
@@ -1,1123 +0,0 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2014-2018, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
5 | * copy of this software and associated documentation files (the "Software"), | ||
6 | * to deal in the Software without restriction, including without limitation | ||
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
8 | * and/or sell copies of the Software, and to permit persons to whom the | ||
9 | * Software is furnished to do so, subject to the following conditions: | ||
10 | * | ||
11 | * The above copyright notice and this permission notice shall be included in | ||
12 | * all copies or substantial portions of the Software. | ||
13 | * | ||
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
17 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
18 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
19 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
20 | * DEALINGS IN THE SOFTWARE. | ||
21 | */ | ||
22 | |||
23 | #ifndef NVGPU_BIOS_H | ||
24 | #define NVGPU_BIOS_H | ||
25 | |||
26 | #include <nvgpu/types.h> | ||
27 | |||
28 | struct gk20a; | ||
29 | |||
30 | #define PERF_PTRS_WIDTH 0x4 | ||
31 | #define PERF_PTRS_WIDTH_16 0x2 | ||
32 | |||
33 | enum { | ||
34 | CLOCKS_TABLE = 2, | ||
35 | CLOCK_PROGRAMMING_TABLE, | ||
36 | FLL_TABLE, | ||
37 | VIN_TABLE, | ||
38 | FREQUENCY_CONTROLLER_TABLE | ||
39 | }; | ||
40 | |||
41 | enum { | ||
42 | PERFORMANCE_TABLE = 0, | ||
43 | MEMORY_CLOCK_TABLE, | ||
44 | MEMORY_TWEAK_TABLE, | ||
45 | POWER_CONTROL_TABLE, | ||
46 | THERMAL_CONTROL_TABLE, | ||
47 | THERMAL_DEVICE_TABLE, | ||
48 | THERMAL_COOLERS_TABLE, | ||
49 | PERFORMANCE_SETTINGS_SCRIPT, | ||
50 | CONTINUOUS_VIRTUAL_BINNING_TABLE, | ||
51 | POWER_SENSORS_TABLE = 0xA, | ||
52 | POWER_CAPPING_TABLE = 0xB, | ||
53 | POWER_TOPOLOGY_TABLE = 0xF, | ||
54 | THERMAL_CHANNEL_TABLE = 0x12, | ||
55 | VOLTAGE_RAIL_TABLE = 26, | ||
56 | VOLTAGE_DEVICE_TABLE, | ||
57 | VOLTAGE_POLICY_TABLE, | ||
58 | LOWPOWER_TABLE, | ||
59 | LOWPOWER_GR_TABLE = 32, | ||
60 | LOWPOWER_MS_TABLE = 33, | ||
61 | }; | ||
62 | |||
63 | enum { | ||
64 | VP_FIELD_TABLE = 0, | ||
65 | VP_FIELD_REGISTER, | ||
66 | VP_TRANSLATION_TABLE, | ||
67 | }; | ||
68 | |||
69 | struct bit_token { | ||
70 | u8 token_id; | ||
71 | u8 data_version; | ||
72 | u16 data_size; | ||
73 | u16 data_ptr; | ||
74 | } __packed; | ||
75 | |||
76 | #define BIOS_GET_FIELD(value, name) ((value & name##_MASK) >> name##_SHIFT) | ||
77 | |||
78 | struct fll_descriptor_header { | ||
79 | u8 version; | ||
80 | u8 size; | ||
81 | } __packed; | ||
82 | |||
83 | #define FLL_DESCRIPTOR_HEADER_10_SIZE_4 4U | ||
84 | #define FLL_DESCRIPTOR_HEADER_10_SIZE_6 6U | ||
85 | |||
86 | struct fll_descriptor_header_10 { | ||
87 | u8 version; | ||
88 | u8 header_size; | ||
89 | u8 entry_size; | ||
90 | u8 entry_count; | ||
91 | u16 max_min_freq_mhz; | ||
92 | } __packed; | ||
93 | |||
94 | #define FLL_DESCRIPTOR_ENTRY_10_SIZE 15U | ||
95 | |||
96 | struct fll_descriptor_entry_10 { | ||
97 | u8 fll_device_type; | ||
98 | u8 clk_domain; | ||
99 | u8 fll_device_id; | ||
100 | u16 lut_params; | ||
101 | u8 vin_idx_logic; | ||
102 | u8 vin_idx_sram; | ||
103 | u16 fll_params; | ||
104 | u8 min_freq_vfe_idx; | ||
105 | u8 freq_ctrl_idx; | ||
106 | u16 ref_freq_mhz; | ||
107 | u16 ffr_cutoff_freq_mhz; | ||
108 | } __packed; | ||
109 | |||
110 | #define NV_FLL_DESC_FLL_PARAMS_MDIV_MASK 0x1F | ||
111 | #define NV_FLL_DESC_FLL_PARAMS_MDIV_SHIFT 0 | ||
112 | |||
113 | #define NV_FLL_DESC_FLL_PARAMS_SKIP_PLDIV_BELOW_DVCO_MIN_MASK 0x20 | ||
114 | #define NV_FLL_DESC_FLL_PARAMS_SKIP_PLDIV_BELOW_DVCO_MIN_SHIFT 5 | ||
115 | |||
116 | #define NV_FLL_DESC_LUT_PARAMS_VSELECT_MASK 0x3 | ||
117 | #define NV_FLL_DESC_LUT_PARAMS_VSELECT_SHIFT 0 | ||
118 | |||
119 | #define NV_FLL_DESC_LUT_PARAMS_HYSTERISIS_THRESHOLD_MASK 0x3C | ||
120 | #define NV_FLL_DESC_LUT_PARAMS_HYSTERISIS_THRESHOLD_SHIFT 2 | ||
121 | |||
122 | struct vin_descriptor_header_10 { | ||
123 | u8 version; | ||
124 | u8 header_sizee; | ||
125 | u8 entry_size; | ||
126 | u8 entry_count; | ||
127 | u8 flags0; | ||
128 | u32 vin_cal; | ||
129 | } __packed; | ||
130 | |||
131 | struct vin_descriptor_entry_10 { | ||
132 | u8 vin_device_type; | ||
133 | u8 volt_domain_vbios; | ||
134 | u8 vin_device_id; | ||
135 | } __packed; | ||
136 | |||
137 | #define NV_VIN_DESC_FLAGS0_VIN_CAL_REVISION_MASK 0x7 | ||
138 | #define NV_VIN_DESC_FLAGS0_VIN_CAL_REVISION_SHIFT 0 | ||
139 | |||
140 | #define NV_VIN_DESC_FLAGS0_VIN_CAL_TYPE_MASK 0xF0 | ||
141 | #define NV_VIN_DESC_FLAGS0_VIN_CAL_TYPE_SHIFT 4 | ||
142 | |||
143 | #define NV_VIN_DESC_FLAGS0_DISABLE_CONTROL_MASK 0x8 | ||
144 | #define NV_VIN_DESC_FLAGS0_DISABLE_CONTROL_SHIFT 3 | ||
145 | |||
146 | #define NV_VIN_DESC_VIN_CAL_SLOPE_FRACTION_MASK 0x1FF | ||
147 | #define NV_VIN_DESC_VIN_CAL_SLOPE_FRACTION_SHIFT 0 | ||
148 | |||
149 | #define NV_VIN_DESC_VIN_CAL_SLOPE_INTEGER_MASK 0x3C00 | ||
150 | #define NV_VIN_DESC_VIN_CAL_SLOPE_INTEGER_SHIFT 10 | ||
151 | |||
152 | #define NV_VIN_DESC_VIN_CAL_INTERCEPT_FRACTION_MASK 0x3C000 | ||
153 | #define NV_VIN_DESC_VIN_CAL_INTERCEPT_FRACTION_SHIFT 14 | ||
154 | |||
155 | #define NV_VIN_DESC_VIN_CAL_INTERCEPT_INTEGER_MASK 0xFFC0000 | ||
156 | #define NV_VIN_DESC_VIN_CAL_INTERCEPT_INTEGER_SHIFT 18 | ||
157 | |||
158 | #define NV_VIN_DESC_VIN_CAL_OFFSET_MASK 0x7F | ||
159 | #define NV_VIN_DESC_VIN_CAL_OFFSET_SHIFT 0 | ||
160 | |||
161 | #define NV_VIN_DESC_VIN_CAL_GAIN_MASK 0xF80 | ||
162 | #define NV_VIN_DESC_VIN_CAL_GAIN_SHIFT 7 | ||
163 | |||
164 | #define VBIOS_CLOCKS_TABLE_1X_HEADER_SIZE_07 0x07U | ||
165 | struct vbios_clocks_table_1x_header { | ||
166 | u8 version; | ||
167 | u8 header_size; | ||
168 | u8 entry_size; | ||
169 | u8 entry_count; | ||
170 | u8 clocks_hal; | ||
171 | u16 cntr_sampling_periodms; | ||
172 | } __packed; | ||
173 | |||
174 | #define VBIOS_CLOCKS_TABLE_35_HEADER_SIZE_09 0x09U | ||
175 | struct vbios_clocks_table_35_header { | ||
176 | u8 version; | ||
177 | u8 header_size; | ||
178 | u8 entry_size; | ||
179 | u8 entry_count; | ||
180 | u8 clocks_hal; | ||
181 | u16 cntr_sampling_periodms; | ||
182 | u16 reference_window; | ||
183 | } __packed; | ||
184 | |||
185 | #define VBIOS_CLOCKS_TABLE_1X_ENTRY_SIZE_09 0x09U | ||
186 | struct vbios_clocks_table_1x_entry { | ||
187 | u8 flags0; | ||
188 | u16 param0; | ||
189 | u32 param1; | ||
190 | u16 param2; | ||
191 | } __packed; | ||
192 | |||
193 | #define VBIOS_CLOCKS_TABLE_35_ENTRY_SIZE_11 0x0BU | ||
194 | struct vbios_clocks_table_35_entry { | ||
195 | u8 flags0; | ||
196 | u16 param0; | ||
197 | u32 param1; | ||
198 | u16 param2; | ||
199 | u16 param3; | ||
200 | } __packed; | ||
201 | |||
202 | #define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_FLAGS0_USAGE_MASK 0x1F | ||
203 | #define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_FLAGS0_USAGE_SHIFT 0 | ||
204 | #define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_FLAGS0_USAGE_FIXED 0x00 | ||
205 | #define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_FLAGS0_USAGE_MASTER 0x01 | ||
206 | #define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_FLAGS0_USAGE_SLAVE 0x02 | ||
207 | |||
208 | #define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM0_PROG_CLK_PROG_IDX_FIRST_MASK 0xFF | ||
209 | #define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM0_PROG_CLK_PROG_IDX_FIRST_SHIFT 0 | ||
210 | #define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM0_PROG_CLK_PROG_IDX_LAST_MASK 0xFF00 | ||
211 | #define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM0_PROG_CLK_PROG_IDX_LAST_SHIFT 0x08 | ||
212 | |||
213 | #define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM1_FIXED_FREQUENCY_MHZ_MASK 0xFFFF | ||
214 | #define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM1_FIXED_FREQUENCY_MHZ_SHIFT 0 | ||
215 | #define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM1_MASTER_FREQ_OC_DELTA_MIN_MHZ_MASK 0xFFFF | ||
216 | #define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM1_MASTER_FREQ_OC_DELTA_MIN_MHZ_SHIFT 0 | ||
217 | |||
218 | #define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM1_MASTER_FREQ_OC_DELTA_MAX_MHZ_MASK 0xFFFF0000 | ||
219 | #define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM1_MASTER_FREQ_OC_DELTA_MAX_MHZ_SHIFT 0 | ||
220 | |||
221 | #define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM1_SLAVE_MASTER_DOMAIN_MASK 0xF | ||
222 | #define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM1_SLAVE_MASTER_DOMAIN_SHIFT 0 | ||
223 | |||
224 | #define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM2_PROG_NOISE_UNAWARE_ORDERING_IDX_MASK 0xF | ||
225 | #define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM2_PROG_NOISE_UNAWARE_ORDERING_IDX_SHIFT 0 | ||
226 | |||
227 | #define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM2_PROG_NOISE_AWARE_ORDERING_IDX_MASK 0xF0 | ||
228 | #define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM2_PROG_NOISE_AWARE_ORDERING_IDX_SHIFT 4 | ||
229 | |||
230 | #define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM2_PROG_FORCE_NOISE_UNAWARE_ORDERING_MASK 0x100 | ||
231 | #define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM2_PROG_FORCE_NOISE_UNAWARE_ORDERING_SHIFT 8 | ||
232 | #define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM2_PROG_FORCE_NOISE_UNAWARE_ORDERING_FALSE 0x00 | ||
233 | #define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM2_PROG_FORCE_NOISE_UNAWARE_ORDERING_TRUE 0x01 | ||
234 | |||
235 | #define NV_VBIOS_CLOCKS_TABLE_35_ENTRY_PARAM2_PROG_PRE_VOLT_ORDERING_IDX_MASK 0xF | ||
236 | #define NV_VBIOS_CLOCKS_TABLE_35_ENTRY_PARAM2_PROG_PRE_VOLT_ORDERING_IDX_SHIFT 0 | ||
237 | |||
238 | #define NV_VBIOS_CLOCKS_TABLE_35_ENTRY_PARAM2_PROG_POST_VOLT_ORDERING_IDX_MASK 0xF0 | ||
239 | #define NV_VBIOS_CLOCKS_TABLE_35_ENTRY_PARAM2_PROG_POST_VOLT_ORDERING_IDX_SHIFT 4 | ||
240 | |||
241 | #define NV_VBIOS_CLOCKS_TABLE_35_ENTRY_PARAM3_CLK_MONITOR_THRESHOLD_MIN_MASK 0xFF | ||
242 | #define NV_VBIOS_CLOCKS_TABLE_35_ENTRY_PARAM3_CLK_MONITOR_THRESHOLD_MIN_SHIFT 0 | ||
243 | #define NV_VBIOS_CLOCKS_TABLE_35_ENTRY_PARAM3_CLK_MONITOR_THRESHOLD_MAX_MASK 0xFF00 | ||
244 | #define NV_VBIOS_CLOCKS_TABLE_35_ENTRY_PARAM3_CLK_MONITOR_THRESHOLD_MAX_SHIFT 0x08 | ||
245 | |||
246 | #define VBIOS_CLOCK_PROGRAMMING_TABLE_1X_HEADER_SIZE_08 0x08U | ||
247 | struct vbios_clock_programming_table_1x_header { | ||
248 | u8 version; | ||
249 | u8 header_size; | ||
250 | u8 entry_size; | ||
251 | u8 entry_count; | ||
252 | u8 slave_entry_size; | ||
253 | u8 slave_entry_count; | ||
254 | u8 vf_entry_size; | ||
255 | u8 vf_entry_count; | ||
256 | } __packed; | ||
257 | |||
258 | #define VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_SIZE_05 0x05U | ||
259 | #define VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_SIZE_0D 0x0DU | ||
260 | struct vbios_clock_programming_table_1x_entry { | ||
261 | u8 flags0; | ||
262 | u16 freq_max_mhz; | ||
263 | u8 param0; | ||
264 | u8 param1; | ||
265 | u32 rsvd; | ||
266 | u32 rsvd1; | ||
267 | } __packed; | ||
268 | |||
269 | #define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_FLAGS0_TYPE_MASK 0xF | ||
270 | #define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_FLAGS0_TYPE_SHIFT 0 | ||
271 | #define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_FLAGS0_TYPE_MASTER_RATIO 0x00 | ||
272 | #define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_FLAGS0_TYPE_MASTER_TABLE 0x01 | ||
273 | #define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_FLAGS0_TYPE_SLAVE 0x02 | ||
274 | |||
275 | #define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_FLAGS0_SOURCE_MASK 0x70 | ||
276 | #define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_FLAGS0_SOURCE_SHIFT 4 | ||
277 | #define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_FLAGS0_SOURCE_PLL 0x00 | ||
278 | #define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_FLAGS0_SOURCE_ONE_SOURCE 0x01 | ||
279 | #define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_FLAGS0_SOURCE_FLL 0x02 | ||
280 | |||
281 | #define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_FLAGS0_OVOC_ENABLED_MASK 0x80 | ||
282 | #define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_FLAGS0_OVOC_ENABLED_SHIFT 7 | ||
283 | #define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_FLAGS0_OVOC_ENABLED_FALSE 0x00 | ||
284 | #define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_FLAGS0_OVOC_ENABLED_TRUE 0x01 | ||
285 | |||
286 | #define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_PARAM0_PLL_PLL_INDEX_MASK 0xFF | ||
287 | #define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_PARAM0_PLL_PLL_INDEX_SHIFT 0 | ||
288 | |||
289 | #define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_PARAM1_PLL_FREQ_STEP_SIZE_MASK 0xFF | ||
290 | #define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_PARAM1_PLL_FREQ_STEP_SIZE_SHIFT 0 | ||
291 | |||
292 | #define VBIOS_CLOCK_PROGRAMMING_TABLE_1X_SLAVE_ENTRY_SIZE_03 0x03U | ||
293 | struct vbios_clock_programming_table_1x_slave_entry { | ||
294 | u8 clk_dom_idx; | ||
295 | u16 param0; | ||
296 | } __packed; | ||
297 | |||
298 | #define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_SLAVE_ENTRY_PARAM0_MASTER_RATIO_RATIO_MASK 0xFF | ||
299 | #define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_SLAVE_ENTRY_PARAM0_MASTER_RATIO_RATIO_SHIFT 0 | ||
300 | |||
301 | #define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_SLAVE_ENTRY_PARAM0_MASTER_TABLE_FREQ_MASK 0x3FFF | ||
302 | #define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_SLAVE_ENTRY_PARAM0_MASTER_TABLE_FREQ_SHIFT 0 | ||
303 | |||
304 | #define VBIOS_CLOCK_PROGRAMMING_TABLE_1X_VF_ENTRY_SIZE_02 0x02U | ||
305 | struct vbios_clock_programming_table_1x_vf_entry { | ||
306 | u8 vfe_idx; | ||
307 | u8 param0; | ||
308 | } __packed; | ||
309 | |||
310 | #define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_VF_ENTRY_PARAM0_FLL_GAIN_VFE_IDX_MASK 0xFF | ||
311 | #define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_VF_ENTRY_PARAM0_FLL_GAIN_VFE_IDX_SHIFT 0 | ||
312 | |||
313 | struct vbios_vfe_3x_header_struct { | ||
314 | u8 version; | ||
315 | u8 header_size; | ||
316 | u8 vfe_var_entry_size; | ||
317 | u8 vfe_var_entry_count; | ||
318 | u8 vfe_equ_entry_size; | ||
319 | u8 vfe_equ_entry_count; | ||
320 | u8 polling_periodms; | ||
321 | } __packed; | ||
322 | |||
323 | #define VBIOS_VFE_3X_VAR_ENTRY_SIZE_11 0x11U | ||
324 | #define VBIOS_VFE_3X_VAR_ENTRY_SIZE_19 0x19U | ||
325 | struct vbios_vfe_3x_var_entry_struct { | ||
326 | u8 type; | ||
327 | u32 out_range_min; | ||
328 | u32 out_range_max; | ||
329 | u32 param0; | ||
330 | u32 param1; | ||
331 | u32 param2; | ||
332 | u32 param3; | ||
333 | } __packed; | ||
334 | |||
335 | #define VBIOS_VFE_3X_VAR_ENTRY_TYPE_DISABLED 0x00U | ||
336 | #define VBIOS_VFE_3X_VAR_ENTRY_TYPE_SINGLE_FREQUENCY 0x01U | ||
337 | #define VBIOS_VFE_3X_VAR_ENTRY_TYPE_SINGLE_VOLTAGE 0x02U | ||
338 | #define VBIOS_VFE_3X_VAR_ENTRY_TYPE_SINGLE_SENSED_TEMP 0x03U | ||
339 | #define VBIOS_VFE_3X_VAR_ENTRY_TYPE_SINGLE_SENSED_FUSE 0x04U | ||
340 | #define VBIOS_VFE_3X_VAR_ENTRY_TYPE_DERIVED_PRODUCT 0x05U | ||
341 | #define VBIOS_VFE_3X_VAR_ENTRY_TYPE_DERIVED_SUM 0x06U | ||
342 | |||
343 | #define VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSTEMP_TH_CH_IDX_MASK 0xFF | ||
344 | #define VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSTEMP_TH_CH_IDX_SHIFT 0 | ||
345 | |||
346 | #define VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSTEMP_HYS_POS_MASK 0xFF00 | ||
347 | #define VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSTEMP_HYS_POS_SHIFT 8 | ||
348 | |||
349 | #define VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSTEMP_HYS_NEG_MASK 0xFF0000 | ||
350 | #define VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSTEMP_HYS_NEG_SHIFT 16 | ||
351 | |||
352 | #define VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSFUSE_VFIELD_ID_MASK 0xFF | ||
353 | #define VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSFUSE_VFIELD_ID_SHIFT 0 | ||
354 | |||
355 | #define VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSFUSE_VFIELD_ID_VER_MASK 0xFF00 | ||
356 | #define VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSFUSE_VFIELD_ID_VER_SHIFT 8 | ||
357 | |||
358 | #define VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSFUSE_EXPECTED_VER_MASK 0xFF0000 | ||
359 | #define VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSFUSE_EXPECTED_VER_SHIFT 16 | ||
360 | |||
361 | #define VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSFUSE_USE_DEFAULT_ON_VER_CHECK_FAIL_MASK 0x1000000 | ||
362 | #define VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSFUSE_USE_DEFAULT_ON_VER_CHECK_FAIL_SHIFT 24 | ||
363 | |||
364 | #define VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSFUSE_VALUE_SIGNED_INTEGER_MASK 0x2000000 | ||
365 | #define VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSFUSE_VALUE_SIGNED_INTEGER_SHIFT 25 | ||
366 | |||
367 | #define VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSFUSE_USE_DEFAULT_ON_VER_CHECK_FAIL_YES 0x00000001 | ||
368 | #define VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSFUSE_USE_DEFAULT_ON_VER_CHECK_FAIL_NO 0x00000000 | ||
369 | #define VBIOS_VFE_3X_VAR_ENTRY_PAR0_DPROD_VFE_VAR_IDX_0_MASK 0xFF | ||
370 | #define VBIOS_VFE_3X_VAR_ENTRY_PAR0_DPROD_VFE_VAR_IDX_0_SHIFT 0 | ||
371 | |||
372 | #define VBIOS_VFE_3X_VAR_ENTRY_PAR0_DPROD_VFE_VAR_IDX_1_MASK 0xFF00 | ||
373 | #define VBIOS_VFE_3X_VAR_ENTRY_PAR0_DPROD_VFE_VAR_IDX_1_SHIFT 8 | ||
374 | |||
375 | #define VBIOS_VFE_3X_VAR_ENTRY_PAR0_DSUM_VFE_VAR_IDX_0_MASK 0xFF | ||
376 | #define VBIOS_VFE_3X_VAR_ENTRY_PAR0_DSUM_VFE_VAR_IDX_0_SHIFT 0 | ||
377 | |||
378 | #define VBIOS_VFE_3X_VAR_ENTRY_PAR0_DSUM_VFE_VAR_IDX_1_MASK 0xFF00 | ||
379 | #define VBIOS_VFE_3X_VAR_ENTRY_PAR0_DSUM_VFE_VAR_IDX_1_SHIFT 8 | ||
380 | |||
381 | #define VBIOS_VFE_3X_VAR_ENTRY_PAR1_SSFUSE_DEFAULT_VAL_MASK 0xFFFFFFFF | ||
382 | #define VBIOS_VFE_3X_VAR_ENTRY_PAR1_SSFUSE_DEFAULT_VAL_SHIFT 0 | ||
383 | |||
384 | #define VBIOS_VFE_3X_VAR_ENTRY_PAR1_SSFUSE_HW_CORRECTION_SCALE_MASK 0xFFFFFFFF | ||
385 | #define VBIOS_VFE_3X_VAR_ENTRY_PAR1_SSFUSE_HW_CORRECTION_SCALE_SHIFT 0 | ||
386 | |||
387 | #define VBIOS_VFE_3X_VAR_ENTRY_PAR1_SSFUSE_HW_CORRECTION_OFFSET_MASK 0xFFFFFFFF | ||
388 | #define VBIOS_VFE_3X_VAR_ENTRY_PAR1_SSFUSE_HW_CORRECTION_OFFSET_SHIFT 0 | ||
389 | |||
390 | #define VBIOS_VFE_3X_EQU_ENTRY_SIZE_17 0x17U | ||
391 | #define VBIOS_VFE_3X_EQU_ENTRY_SIZE_18 0x18U | ||
392 | |||
393 | struct vbios_vfe_3x_equ_entry_struct { | ||
394 | u8 type; | ||
395 | u8 var_idx; | ||
396 | u8 equ_idx_next; | ||
397 | u32 out_range_min; | ||
398 | u32 out_range_max; | ||
399 | u32 param0; | ||
400 | u32 param1; | ||
401 | u32 param2; | ||
402 | u8 param3; | ||
403 | } __packed; | ||
404 | |||
405 | |||
406 | #define VBIOS_VFE_3X_EQU_ENTRY_TYPE_DISABLED 0x00U | ||
407 | #define VBIOS_VFE_3X_EQU_ENTRY_TYPE_QUADRATIC 0x01U | ||
408 | #define VBIOS_VFE_3X_EQU_ENTRY_TYPE_MINMAX 0x02U | ||
409 | #define VBIOS_VFE_3X_EQU_ENTRY_TYPE_COMPARE 0x03U | ||
410 | #define VBIOS_VFE_3X_EQU_ENTRY_TYPE_QUADRATIC_FXP 0x04U | ||
411 | #define VBIOS_VFE_3X_EQU_ENTRY_TYPE_MINMAX_FXP 0x05U | ||
412 | |||
413 | #define VBIOS_VFE_3X_EQU_ENTRY_IDX_INVALID 0xFFU | ||
414 | |||
415 | #define VBIOS_VFE_3X_EQU_ENTRY_PAR0_QUADRATIC_C0_MASK 0xFFFFFFFF | ||
416 | #define VBIOS_VFE_3X_EQU_ENTRY_PAR0_QUADRATIC_C0_SHIFT 0 | ||
417 | |||
418 | #define VBIOS_VFE_3X_EQU_ENTRY_PAR0_MINMAX_VFE_EQU_IDX_0_MASK 0xFF | ||
419 | #define VBIOS_VFE_3X_EQU_ENTRY_PAR0_MINMAX_VFE_EQU_IDX_0_SHIFT 0 | ||
420 | |||
421 | #define VBIOS_VFE_3X_EQU_ENTRY_PAR0_MINMAX_VFE_EQU_IDX_1_MASK 0xFF00 | ||
422 | #define VBIOS_VFE_3X_EQU_ENTRY_PAR0_MINMAX_VFE_EQU_IDX_1_SHIFT 8 | ||
423 | |||
424 | #define VBIOS_VFE_3X_EQU_ENTRY_PAR0_MINMAX_CRIT_MASK 0x10000 | ||
425 | #define VBIOS_VFE_3X_EQU_ENTRY_PAR0_MINMAX_CRIT_SHIFT 16 | ||
426 | #define VBIOS_VFE_3X_EQU_ENTRY_PAR0_MINMAX_CRIT_MIN 0x00000000 | ||
427 | #define VBIOS_VFE_3X_EQU_ENTRY_PAR0_MINMAX_CRIT_MAX 0x00000001 | ||
428 | |||
429 | #define VBIOS_VFE_3X_EQU_ENTRY_PAR0_COMPARE_CRIT_MASK 0xFFFFFFFF | ||
430 | #define VBIOS_VFE_3X_EQU_ENTRY_PAR0_COMPARE_CRIT_SHIFT 0 | ||
431 | |||
432 | #define VBIOS_VFE_3X_EQU_ENTRY_PAR1_QUADRATIC_C1_MASK 0xFFFFFFFF | ||
433 | #define VBIOS_VFE_3X_EQU_ENTRY_PAR1_QUADRATIC_C1_SHIFT 0 | ||
434 | |||
435 | #define VBIOS_VFE_3X_EQU_ENTRY_PAR1_COMPARE_VFE_EQU_IDX_TRUE_MASK 0xFF | ||
436 | #define VBIOS_VFE_3X_EQU_ENTRY_PAR1_COMPARE_VFE_EQU_IDX_TRUE_SHIFT 0 | ||
437 | |||
438 | #define VBIOS_VFE_3X_EQU_ENTRY_PAR1_COMPARE_VFE_EQU_IDX_FALSE_MASK 0xFF00 | ||
439 | #define VBIOS_VFE_3X_EQU_ENTRY_PAR1_COMPARE_VFE_EQU_IDX_FALSE_SHIFT 8 | ||
440 | |||
441 | #define VBIOS_VFE_3X_EQU_ENTRY_PAR1_COMPARE_FUNCTION_MASK 0x70000 | ||
442 | #define VBIOS_VFE_3X_EQU_ENTRY_PAR1_COMPARE_FUNCTION_SHIFT 16 | ||
443 | #define VBIOS_VFE_3X_EQU_ENTRY_PAR1_COMPARE_FUNCTION_EQUAL 0x00000000 | ||
444 | #define VBIOS_VFE_3X_EQU_ENTRY_PAR1_COMPARE_FUNCTION_GREATER_EQ 0x00000001 | ||
445 | #define VBIOS_VFE_3X_EQU_ENTRY_PAR1_COMPARE_FUNCTION_GREATER 0x00000002 | ||
446 | |||
447 | #define VBIOS_VFE_3X_EQU_ENTRY_PAR3_OUTPUT_TYPE_MASK 0xF | ||
448 | #define VBIOS_VFE_3X_EQU_ENTRY_PAR3_OUTPUT_TYPE_SHIFT 0 | ||
449 | #define VBIOS_VFE_3X_EQU_ENTRY_PAR3_OUTPUT_TYPE_UNITLESS 0x0 | ||
450 | #define VBIOS_VFE_3X_EQU_ENTRY_PAR3_OUTPUT_TYPE_FREQ_MHZ 0x1 | ||
451 | #define VBIOS_VFE_3X_EQU_ENTRY_PAR3_OUTPUT_TYPE_VOLT_UV 0x2 | ||
452 | #define VBIOS_VFE_3X_EQU_ENTRY_PAR3_OUTPUT_TYPE_VF_GAIN 0x3 | ||
453 | #define VBIOS_VFE_3X_EQU_ENTRY_PAR3_OUTPUT_TYPE_VOLT_DELTA_UV 0x4 | ||
454 | |||
455 | #define NV_VFIELD_DESC_SIZE_BYTE 0x00000000U | ||
456 | #define NV_VFIELD_DESC_SIZE_WORD 0x00000001U | ||
457 | #define NV_VFIELD_DESC_SIZE_DWORD 0x00000002U | ||
458 | #define VFIELD_SIZE(pvregentry) ((pvregentry->strap_reg_desc & 0x18U) >> 3U) | ||
459 | |||
460 | #define NV_PMU_BIOS_VFIELD_DESC_CODE_INVALID 0x00000000U | ||
461 | #define NV_PMU_BIOS_VFIELD_DESC_CODE_REG 0x00000001U | ||
462 | #define NV_PMU_BIOS_VFIELD_DESC_CODE_INDEX_REG 0x00000002U | ||
463 | |||
464 | #define NV_VFIELD_DESC_CODE_INVALID NV_PMU_BIOS_VFIELD_DESC_CODE_INVALID | ||
465 | #define NV_VFIELD_DESC_CODE_REG NV_PMU_BIOS_VFIELD_DESC_CODE_REG | ||
466 | #define NV_VFIELD_DESC_CODE_INDEX_REG NV_PMU_BIOS_VFIELD_DESC_CODE_INDEX_REG | ||
467 | |||
468 | #define VFIELD_CODE(pvregentry) ((pvregentry->strap_reg_desc & 0xE0U) >> 5U) | ||
469 | |||
470 | #define VFIELD_ID_STRAP_IDDQ 0x09U | ||
471 | #define VFIELD_ID_STRAP_IDDQ_1 0x0BU | ||
472 | |||
473 | #define VFIELD_REG_HEADER_SIZE 3U | ||
474 | struct vfield_reg_header { | ||
475 | u8 version; | ||
476 | u8 entry_size; | ||
477 | u8 count; | ||
478 | } __packed; | ||
479 | |||
480 | #define VBIOS_VFIELD_REG_TABLE_VERSION_1_0 0x10U | ||
481 | |||
482 | |||
483 | #define VFIELD_REG_ENTRY_SIZE 13U | ||
484 | struct vfield_reg_entry { | ||
485 | u8 strap_reg_desc; | ||
486 | u32 reg; | ||
487 | u32 reg_index; | ||
488 | u32 index; | ||
489 | } __packed; | ||
490 | |||
491 | #define VFIELD_HEADER_SIZE 3U | ||
492 | |||
493 | struct vfield_header { | ||
494 | u8 version; | ||
495 | u8 entry_size; | ||
496 | u8 count; | ||
497 | } __packed; | ||
498 | |||
499 | #define VBIOS_VFIELD_TABLE_VERSION_1_0 0x10U | ||
500 | |||
501 | #define VFIELD_BIT_START(ventry) (ventry.strap_desc & 0x1FU) | ||
502 | #define VFIELD_BIT_STOP(ventry) ((ventry.strap_desc & 0x3E0U) >> 5U) | ||
503 | #define VFIELD_BIT_REG(ventry) ((ventry.strap_desc & 0x3C00U) >> 10U) | ||
504 | |||
505 | #define VFIELD_ENTRY_SIZE 3U | ||
506 | |||
507 | struct vfield_entry { | ||
508 | u8 strap_id; | ||
509 | u16 strap_desc; | ||
510 | } __packed; | ||
511 | |||
512 | #define PERF_CLK_DOMAINS_IDX_MAX (32U) | ||
513 | #define PERF_CLK_DOMAINS_IDX_INVALID PERF_CLK_DOMAINS_IDX_MAX | ||
514 | |||
515 | #define VBIOS_PSTATE_TABLE_VERSION_5X 0x50U | ||
516 | #define VBIOS_PSTATE_HEADER_5X_SIZE_10 (10U) | ||
517 | |||
518 | struct vbios_pstate_header_5x { | ||
519 | u8 version; | ||
520 | u8 header_size; | ||
521 | u8 base_entry_size; | ||
522 | u8 base_entry_count; | ||
523 | u8 clock_entry_size; | ||
524 | u8 clock_entry_count; | ||
525 | u8 flags0; | ||
526 | u8 initial_pstate; | ||
527 | u8 cpi_support_level; | ||
528 | u8 cpi_features; | ||
529 | } __packed; | ||
530 | |||
531 | #define VBIOS_PSTATE_CLOCK_ENTRY_5X_SIZE_6 6U | ||
532 | |||
533 | #define VBIOS_PSTATE_BASE_ENTRY_5X_SIZE_2 0x2U | ||
534 | #define VBIOS_PSTATE_BASE_ENTRY_5X_SIZE_3 0x3U | ||
535 | |||
536 | struct vbios_pstate_entry_clock_5x { | ||
537 | u16 param0; | ||
538 | u32 param1; | ||
539 | } __packed; | ||
540 | |||
541 | struct vbios_pstate_entry_5x { | ||
542 | u8 pstate_level; | ||
543 | u8 flags0; | ||
544 | u8 lpwr_entry_idx; | ||
545 | struct vbios_pstate_entry_clock_5x clockEntry[PERF_CLK_DOMAINS_IDX_MAX]; | ||
546 | } __packed; | ||
547 | |||
548 | #define VBIOS_PSTATE_5X_CLOCK_PROG_PARAM0_NOM_FREQ_MHZ_SHIFT 0 | ||
549 | #define VBIOS_PSTATE_5X_CLOCK_PROG_PARAM0_NOM_FREQ_MHZ_MASK 0x00003FFF | ||
550 | |||
551 | #define VBIOS_PSTATE_5X_CLOCK_PROG_PARAM1_MIN_FREQ_MHZ_SHIFT 0 | ||
552 | #define VBIOS_PSTATE_5X_CLOCK_PROG_PARAM1_MIN_FREQ_MHZ_MASK 0x00003FFF | ||
553 | |||
554 | #define VBIOS_PSTATE_5X_CLOCK_PROG_PARAM1_MAX_FREQ_MHZ_SHIFT 14 | ||
555 | #define VBIOS_PSTATE_5X_CLOCK_PROG_PARAM1_MAX_FREQ_MHZ_MASK 0x0FFFC000 | ||
556 | |||
557 | #define VBIOS_PERFLEVEL_SKIP_ENTRY 0xFFU | ||
558 | |||
559 | #define VBIOS_MEMORY_CLOCK_HEADER_11_VERSION 0x11U | ||
560 | |||
561 | #define VBIOS_MEMORY_CLOCK_HEADER_11_0_SIZE 16U | ||
562 | #define VBIOS_MEMORY_CLOCK_HEADER_11_1_SIZE 21U | ||
563 | #define VBIOS_MEMORY_CLOCK_HEADER_11_2_SIZE 26U | ||
564 | |||
565 | struct vbios_memory_clock_header_1x { | ||
566 | u8 version; | ||
567 | u8 header_size; | ||
568 | u8 base_entry_size; | ||
569 | u8 strap_entry_size; | ||
570 | u8 strap_entry_count; | ||
571 | u8 entry_count; | ||
572 | u8 flags; | ||
573 | u8 fbvdd_settle_time; | ||
574 | u32 cfg_pwrd_val; | ||
575 | u16 fbvddq_high; | ||
576 | u16 fbvddq_low; | ||
577 | u32 script_list_ptr; | ||
578 | u8 script_list_count; | ||
579 | u32 cmd_script_list_ptr; | ||
580 | u8 cmd_script_list_count; | ||
581 | } __packed; | ||
582 | |||
583 | #define VBIOS_MEMORY_CLOCK_BASE_ENTRY_11_2_SIZE 20U | ||
584 | |||
585 | struct vbios_memory_clock_base_entry_11 { | ||
586 | u16 minimum; | ||
587 | u16 maximum; | ||
588 | u32 script_pointer; | ||
589 | u8 flags0; | ||
590 | u32 fbpa_config; | ||
591 | u32 fbpa_config1; | ||
592 | u8 flags1; | ||
593 | u8 ref_mpllssf_freq_delta; | ||
594 | u8 flags2; | ||
595 | } __packed; | ||
596 | |||
597 | /* Script Pointer Index */ | ||
598 | /* #define VBIOS_MEMORY_CLOCK_BASE_ENTRY_11_FLAGS1_SCRIPT_INDEX 3:2*/ | ||
599 | #define VBIOS_MEMORY_CLOCK_BASE_ENTRY_11_FLAGS1_SCRIPT_INDEX_MASK \ | ||
600 | ((u8)0xc) | ||
601 | #define VBIOS_MEMORY_CLOCK_BASE_ENTRY_11_FLAGS1_SCRIPT_INDEX_SHIFT 2 | ||
602 | /* #define VBIOS_MEMORY_CLOCK_BASE_ENTRY_12_FLAGS2_CMD_SCRIPT_INDEX 1:0*/ | ||
603 | #define VBIOS_MEMORY_CLOCK_BASE_ENTRY_12_FLAGS2_CMD_SCRIPT_INDEX_MASK \ | ||
604 | ((u8)0x3) | ||
605 | #define VBIOS_MEMORY_CLOCK_BASE_ENTRY_12_FLAGS2_CMD_SCRIPT_INDEX_SHIFT 0 | ||
606 | |||
607 | #define VBIOS_POWER_SENSORS_VERSION_2X 0x20U | ||
608 | #define VBIOS_POWER_SENSORS_2X_HEADER_SIZE_08 0x00000008U | ||
609 | |||
610 | struct pwr_sensors_2x_header { | ||
611 | u8 version; | ||
612 | u8 header_size; | ||
613 | u8 table_entry_size; | ||
614 | u8 num_table_entries; | ||
615 | u32 ba_script_pointer; | ||
616 | } __packed; | ||
617 | |||
618 | #define VBIOS_POWER_SENSORS_2X_ENTRY_SIZE_15 0x00000015U | ||
619 | |||
620 | struct pwr_sensors_2x_entry { | ||
621 | u8 flags0; | ||
622 | u32 class_param0; | ||
623 | u32 sensor_param0; | ||
624 | u32 sensor_param1; | ||
625 | u32 sensor_param2; | ||
626 | u32 sensor_param3; | ||
627 | } __packed; | ||
628 | |||
629 | #define NV_VBIOS_POWER_SENSORS_2X_ENTRY_FLAGS0_CLASS_MASK 0xF | ||
630 | #define NV_VBIOS_POWER_SENSORS_2X_ENTRY_FLAGS0_CLASS_SHIFT 0 | ||
631 | #define NV_VBIOS_POWER_SENSORS_2X_ENTRY_FLAGS0_CLASS_I2C 0x00000001U | ||
632 | |||
633 | #define NV_VBIOS_POWER_SENSORS_2X_ENTRY_CLASS_PARAM0_I2C_INDEX_MASK 0xFF | ||
634 | #define NV_VBIOS_POWER_SENSORS_2X_ENTRY_CLASS_PARAM0_I2C_INDEX_SHIFT 0 | ||
635 | #define NV_VBIOS_POWER_SENSORS_2X_ENTRY_CLASS_PARAM0_I2C_USE_FXP8_8_MASK 0x100 | ||
636 | #define NV_VBIOS_POWER_SENSORS_2X_ENTRY_CLASS_PARAM0_I2C_USE_FXP8_8_SHIFT 8 | ||
637 | |||
638 | #define NV_VBIOS_POWER_SENSORS_2X_ENTRY_SENSOR_PARAM0_INA3221_RSHUNT0_MOHM_MASK 0xFFFF | ||
639 | #define NV_VBIOS_POWER_SENSORS_2X_ENTRY_SENSOR_PARAM0_INA3221_RSHUNT0_MOHM_SHIFT 0 | ||
640 | #define NV_VBIOS_POWER_SENSORS_2X_ENTRY_SENSOR_PARAM0_INA3221_RSHUNT1_MOHM_MASK 0xFFFF0000 | ||
641 | #define NV_VBIOS_POWER_SENSORS_2X_ENTRY_SENSOR_PARAM0_INA3221_RSHUNT1_MOHM_SHIFT 16 | ||
642 | #define NV_VBIOS_POWER_SENSORS_2X_ENTRY_SENSOR_PARAM1_INA3221_RSHUNT2_MOHM_MASK 0xFFFF | ||
643 | #define NV_VBIOS_POWER_SENSORS_2X_ENTRY_SENSOR_PARAM1_INA3221_RSHUNT2_MOHM_SHIFT 0 | ||
644 | #define NV_VBIOS_POWER_SENSORS_2X_ENTRY_SENSOR_PARAM1_INA3221_CONFIGURATION_MASK 0xFFFF0000 | ||
645 | #define NV_VBIOS_POWER_SENSORS_2X_ENTRY_SENSOR_PARAM1_INA3221_CONFIGURATION_SHIFT 16 | ||
646 | |||
647 | #define NV_VBIOS_POWER_SENSORS_2X_ENTRY_SENSOR_PARAM2_INA3221_MASKENABLE_MASK 0xFFFF | ||
648 | #define NV_VBIOS_POWER_SENSORS_2X_ENTRY_SENSOR_PARAM2_INA3221_MASKENABLE_SHIFT 0 | ||
649 | #define NV_VBIOS_POWER_SENSORS_2X_ENTRY_SENSOR_PARAM2_INA3221_GPIOFUNCTION_MASK 0xFF0000 | ||
650 | #define NV_VBIOS_POWER_SENSORS_2X_ENTRY_SENSOR_PARAM2_INA3221_GPIOFUNCTION_SHIFT 16 | ||
651 | #define NV_VBIOS_POWER_SENSORS_2X_ENTRY_SENSOR_PARAM3_INA3221_CURR_CORRECT_M_MASK 0xFFFF | ||
652 | #define NV_VBIOS_POWER_SENSORS_2X_ENTRY_SENSOR_PARAM3_INA3221_CURR_CORRECT_M_SHIFT 0 | ||
653 | #define NV_VBIOS_POWER_SENSORS_2X_ENTRY_SENSOR_PARAM3_INA3221_CURR_CORRECT_B_MASK 0xFFFF0000 | ||
654 | #define NV_VBIOS_POWER_SENSORS_2X_ENTRY_SENSOR_PARAM3_INA3221_CURR_CORRECT_B_SHIFT 16 | ||
655 | |||
656 | #define VBIOS_POWER_TOPOLOGY_VERSION_2X 0x20U | ||
657 | #define VBIOS_POWER_TOPOLOGY_2X_HEADER_SIZE_06 0x00000006U | ||
658 | |||
659 | struct pwr_topology_2x_header { | ||
660 | u8 version; | ||
661 | u8 header_size; | ||
662 | u8 table_entry_size; | ||
663 | u8 num_table_entries; | ||
664 | u8 rel_entry_size; | ||
665 | u8 num_rel_entries; | ||
666 | } __packed; | ||
667 | |||
668 | #define VBIOS_POWER_TOPOLOGY_2X_ENTRY_SIZE_16 0x00000016U | ||
669 | |||
670 | struct pwr_topology_2x_entry { | ||
671 | u8 flags0; | ||
672 | u8 pwr_rail; | ||
673 | u32 param0; | ||
674 | u32 curr_corr_slope; | ||
675 | u32 curr_corr_offset; | ||
676 | u32 param1; | ||
677 | u32 param2; | ||
678 | } __packed; | ||
679 | |||
680 | #define NV_VBIOS_POWER_TOPOLOGY_2X_ENTRY_FLAGS0_CLASS_MASK 0xF | ||
681 | #define NV_VBIOS_POWER_TOPOLOGY_2X_ENTRY_FLAGS0_CLASS_SHIFT 0 | ||
682 | #define NV_VBIOS_POWER_TOPOLOGY_2X_ENTRY_FLAGS0_CLASS_SENSOR U8(0x00000001) | ||
683 | |||
684 | #define NV_VBIOS_POWER_TOPOLOGY_2X_ENTRY_PARAM1_SENSOR_INDEX_MASK 0xFF | ||
685 | #define NV_VBIOS_POWER_TOPOLOGY_2X_ENTRY_PARAM1_SENSOR_INDEX_SHIFT 0 | ||
686 | #define NV_VBIOS_POWER_TOPOLOGY_2X_ENTRY_PARAM1_SENSOR_PROVIDER_INDEX_MASK 0xFF00 | ||
687 | #define NV_VBIOS_POWER_TOPOLOGY_2X_ENTRY_PARAM1_SENSOR_PROVIDER_INDEX_SHIFT 8 | ||
688 | |||
689 | #define VBIOS_POWER_POLICY_VERSION_3X 0x30U | ||
690 | #define VBIOS_POWER_POLICY_3X_HEADER_SIZE_25 0x00000025U | ||
691 | |||
692 | struct pwr_policy_3x_header_struct { | ||
693 | u8 version; | ||
694 | u8 header_size; | ||
695 | u8 table_entry_size; | ||
696 | u8 num_table_entries; | ||
697 | u16 base_sample_period; | ||
698 | u16 min_client_sample_period; | ||
699 | u8 table_rel_entry_size; | ||
700 | u8 num_table_rel_entries; | ||
701 | u8 tgp_policy_idx; | ||
702 | u8 rtp_policy_idx; | ||
703 | u8 mxm_policy_idx; | ||
704 | u8 dnotifier_policy_idx; | ||
705 | u32 d2_limit; | ||
706 | u32 d3_limit; | ||
707 | u32 d4_limit; | ||
708 | u32 d5_limit; | ||
709 | u8 low_sampling_mult; | ||
710 | u8 pwr_tgt_policy_idx; | ||
711 | u8 pwr_tgt_floor_policy_idx; | ||
712 | u8 sm_bus_policy_idx; | ||
713 | u8 table_viol_entry_size; | ||
714 | u8 num_table_viol_entries; | ||
715 | } __packed; | ||
716 | |||
717 | #define VBIOS_POWER_POLICY_3X_ENTRY_SIZE_2E 0x0000002EU | ||
718 | |||
719 | struct pwr_policy_3x_entry_struct { | ||
720 | u8 flags0; | ||
721 | u8 ch_idx; | ||
722 | u32 limit_min; | ||
723 | u32 limit_rated; | ||
724 | u32 limit_max; | ||
725 | u32 param0; | ||
726 | u32 param1; | ||
727 | u32 param2; | ||
728 | u32 param3; | ||
729 | u32 limit_batt; | ||
730 | u8 flags1; | ||
731 | u8 past_length; | ||
732 | u8 next_length; | ||
733 | u16 ratio_min; | ||
734 | u16 ratio_max; | ||
735 | u8 sample_mult; | ||
736 | u32 filter_param; | ||
737 | } __packed; | ||
738 | |||
739 | #define NV_VBIOS_POWER_POLICY_3X_ENTRY_FLAGS0_CLASS_MASK 0xF | ||
740 | #define NV_VBIOS_POWER_POLICY_3X_ENTRY_FLAGS0_CLASS_SHIFT 0 | ||
741 | #define NV_VBIOS_POWER_POLICY_3X_ENTRY_FLAGS0_CLASS_HW_THRESHOLD 0x00000005U | ||
742 | #define NV_VBIOS_POWER_POLICY_3X_ENTRY_FLAGS0_LIMIT_UNIT_MASK 0x10 | ||
743 | #define NV_VBIOS_POWER_POLICY_3X_ENTRY_FLAGS0_LIMIT_UNIT_SHIFT 4 | ||
744 | |||
745 | #define NV_VBIOS_POWER_POLICY_3X_ENTRY_FLAGS1_FULL_DEFLECTION_LIMIT_MASK 0x1 | ||
746 | #define NV_VBIOS_POWER_POLICY_3X_ENTRY_FLAGS1_FULL_DEFLECTION_LIMIT_SHIFT 0 | ||
747 | #define NV_VBIOS_POWER_POLICY_3X_ENTRY_FLAGS1_INTEGRAL_CONTROL_MASK 0x2 | ||
748 | #define NV_VBIOS_POWER_POLICY_3X_ENTRY_FLAGS1_INTEGRAL_CONTROL_SHIFT 1 | ||
749 | #define NV_VBIOS_POWER_POLICY_3X_ENTRY_FLAGS1_FILTER_TYPE_MASK 0x3C | ||
750 | #define NV_VBIOS_POWER_POLICY_3X_ENTRY_FLAGS1_FILTER_TYPE_SHIFT 2 | ||
751 | |||
752 | #define NV_VBIOS_POWER_POLICY_3X_ENTRY_PARAM0_HW_THRESHOLD_THRES_IDX_MASK 0xFF | ||
753 | #define NV_VBIOS_POWER_POLICY_3X_ENTRY_PARAM0_HW_THRESHOLD_THRES_IDX_SHIFT 0 | ||
754 | #define NV_VBIOS_POWER_POLICY_3X_ENTRY_PARAM0_HW_THRESHOLD_LOW_THRESHOLD_IDX_MASK 0xFF00 | ||
755 | #define NV_VBIOS_POWER_POLICY_3X_ENTRY_PARAM0_HW_THRESHOLD_LOW_THRESHOLD_IDX_SHIFT 8 | ||
756 | #define NV_VBIOS_POWER_POLICY_3X_ENTRY_PARAM0_HW_THRESHOLD_LOW_THRESHOLD_USE_MASK 0x10000 | ||
757 | #define NV_VBIOS_POWER_POLICY_3X_ENTRY_PARAM0_HW_THRESHOLD_LOW_THRESHOLD_USE_SHIFT 16 | ||
758 | |||
759 | #define NV_VBIOS_POWER_POLICY_3X_ENTRY_PARAM1_HW_THRESHOLD_LOW_THRESHOLD_VAL_MASK 0xFFFF | ||
760 | #define NV_VBIOS_POWER_POLICY_3X_ENTRY_PARAM1_HW_THRESHOLD_LOW_THRESHOLD_VAL_SHIFT 0 | ||
761 | |||
762 | /* Voltage Rail Table */ | ||
763 | struct vbios_voltage_rail_table_1x_header { | ||
764 | u8 version; | ||
765 | u8 header_size; | ||
766 | u8 table_entry_size; | ||
767 | u8 num_table_entries; | ||
768 | u8 volt_domain_hal; | ||
769 | } __packed; | ||
770 | |||
771 | #define NV_VBIOS_VOLTAGE_RAIL_1X_ENTRY_SIZE_07 0X00000007U | ||
772 | #define NV_VBIOS_VOLTAGE_RAIL_1X_ENTRY_SIZE_08 0X00000008U | ||
773 | #define NV_VBIOS_VOLTAGE_RAIL_1X_ENTRY_SIZE_09 0X00000009U | ||
774 | #define NV_VBIOS_VOLTAGE_RAIL_1X_ENTRY_SIZE_0A 0X0000000AU | ||
775 | #define NV_VBIOS_VOLTAGE_RAIL_1X_ENTRY_SIZE_0B 0X0000000BU | ||
776 | #define NV_VBIOS_VOLTAGE_RAIL_1X_ENTRY_SIZE_0C 0X0000000CU | ||
777 | |||
778 | struct vbios_voltage_rail_table_1x_entry { | ||
779 | u32 boot_voltage_uv; | ||
780 | u8 rel_limit_vfe_equ_idx; | ||
781 | u8 alt_rel_limit_vfe_equidx; | ||
782 | u8 ov_limit_vfe_equ_idx; | ||
783 | u8 pwr_equ_idx; | ||
784 | u8 boot_volt_vfe_equ_idx; | ||
785 | u8 vmin_limit_vfe_equ_idx; | ||
786 | u8 volt_margin_limit_vfe_equ_idx; | ||
787 | u8 volt_scale_exp_pwr_equ_idx; | ||
788 | } __packed; | ||
789 | |||
790 | /* Voltage Device Table */ | ||
791 | struct vbios_voltage_device_table_1x_header { | ||
792 | u8 version; | ||
793 | u8 header_size; | ||
794 | u8 table_entry_size; | ||
795 | u8 num_table_entries; | ||
796 | } __packed; | ||
797 | |||
798 | struct vbios_voltage_device_table_1x_entry { | ||
799 | u8 type; | ||
800 | u8 volt_domain; | ||
801 | u16 settle_time_us; | ||
802 | u32 param0; | ||
803 | u32 param1; | ||
804 | u32 param2; | ||
805 | u32 param3; | ||
806 | u32 param4; | ||
807 | } __packed; | ||
808 | |||
809 | #define NV_VBIOS_VOLTAGE_DEVICE_1X_ENTRY_TYPE_INVALID 0x00U | ||
810 | #define NV_VBIOS_VOLTAGE_DEVICE_1X_ENTRY_TYPE_PSV 0x02U | ||
811 | |||
812 | #define NV_VBIOS_VDT_1X_ENTRY_PARAM0_PSV_INPUT_FREQUENCY_MASK \ | ||
813 | GENMASK(23, 0) | ||
814 | #define NV_VBIOS_VDT_1X_ENTRY_PARAM0_PSV_INPUT_FREQUENCY_SHIFT 0 | ||
815 | #define NV_VBIOS_VDT_1X_ENTRY_PARAM0_PSV_EXT_DEVICE_INDEX_MASK \ | ||
816 | GENMASK(31, 24) | ||
817 | #define NV_VBIOS_VDT_1X_ENTRY_PARAM0_PSV_EXT_DEVICE_INDEX_SHIFT 24 | ||
818 | |||
819 | #define NV_VBIOS_VDT_1X_ENTRY_PARAM1_PSV_VOLTAGE_MINIMUM_MASK \ | ||
820 | GENMASK(23, 0) | ||
821 | #define NV_VBIOS_VDT_1X_ENTRY_PARAM1_PSV_VOLTAGE_MINIMUM_SHIFT 0 | ||
822 | #define NV_VBIOS_VDT_1X_ENTRY_PARAM1_PSV_OPERATION_TYPE_MASK \ | ||
823 | GENMASK(31, 24) | ||
824 | #define NV_VBIOS_VDT_1X_ENTRY_PARAM1_PSV_OPERATION_TYPE_SHIFT 24 | ||
825 | #define NV_VBIOS_VDT_1X_ENTRY_PARAM1_PSV_OPERATION_TYPE_DEFAULT 0x00 | ||
826 | #define NV_VBIOS_VDT_1X_ENTRY_PARAM1_PSV_OPERATION_TYPE_LPWR_STEADY_STATE \ | ||
827 | 0x01 | ||
828 | #define NV_VBIOS_VDT_1X_ENTRY_PARAM1_PSV_OPERATION_TYPE_LPWR_SLEEP_STATE \ | ||
829 | 0x02 | ||
830 | #define NV_VBIOS_VDT_1X_ENTRY_PARAM2_PSV_VOLTAGE_MAXIMUM_MASK \ | ||
831 | GENMASK(23, 0) | ||
832 | #define NV_VBIOS_VDT_1X_ENTRY_PARAM2_PSV_VOLTAGE_MAXIMUM_SHIFT 0 | ||
833 | #define NV_VBIOS_VDT_1X_ENTRY_PARAM2_PSV_RSVD_MASK \ | ||
834 | GENMASK(31, 24) | ||
835 | #define NV_VBIOS_VDT_1X_ENTRY_PARAM2_PSV_RSVD_SHIFT 24 | ||
836 | |||
837 | #define NV_VBIOS_VDT_1X_ENTRY_PARAM3_PSV_VOLTAGE_BASE_MASK \ | ||
838 | GENMASK(23, 0) | ||
839 | #define NV_VBIOS_VDT_1X_ENTRY_PARAM3_PSV_VOLTAGE_BASE_SHIFT 0 | ||
840 | #define NV_VBIOS_VDT_1X_ENTRY_PARAM3_PSV_VOLTAGE_STEPS_MASK \ | ||
841 | GENMASK(31, 24) | ||
842 | #define NV_VBIOS_VDT_1X_ENTRY_PARAM3_PSV_VOLTAGE_STEPS_SHIFT 24 | ||
843 | |||
844 | #define NV_VBIOS_VDT_1X_ENTRY_PARAM4_PSV_OFFSET_SCALE_MASK \ | ||
845 | GENMASK(23, 0) | ||
846 | #define NV_VBIOS_VDT_1X_ENTRY_PARAM4_PSV_OFFSET_SCALE_SHIFT 0 | ||
847 | #define NV_VBIOS_VDT_1X_ENTRY_PARAM4_PSV_RSVD_MASK \ | ||
848 | GENMASK(31, 24) | ||
849 | #define NV_VBIOS_VDT_1X_ENTRY_PARAM4_PSV_RSVD_SHIFT 24 | ||
850 | |||
851 | /* Voltage Policy Table */ | ||
852 | struct vbios_voltage_policy_table_1x_header { | ||
853 | u8 version; | ||
854 | u8 header_size; | ||
855 | u8 table_entry_size; | ||
856 | u8 num_table_entries; | ||
857 | u8 perf_core_vf_seq_policy_idx; | ||
858 | } __packed; | ||
859 | |||
860 | struct vbios_voltage_policy_table_1x_entry { | ||
861 | u8 type; | ||
862 | u32 param0; | ||
863 | u32 param1; | ||
864 | u32 param2; | ||
865 | u32 param3; | ||
866 | } __packed; | ||
867 | |||
868 | #define NV_VBIOS_VOLTAGE_POLICY_1X_ENTRY_TYPE_INVALID 0x00U | ||
869 | #define NV_VBIOS_VOLTAGE_POLICY_1X_ENTRY_TYPE_SINGLE_RAIL 0x01U | ||
870 | #define NV_VBIOS_VOLTAGE_POLICY_1X_ENTRY_TYPE_SR_MULTI_STEP 0x02U | ||
871 | #define NV_VBIOS_VOLTAGE_POLICY_1X_ENTRY_TYPE_SR_SINGLE_STEP 0x03U | ||
872 | #define NV_VBIOS_VOLTAGE_POLICY_1X_ENTRY_TYPE_SINGLE_RAIL_MULTI_STEP 0x04U | ||
873 | |||
874 | #define NV_VBIOS_VPT_ENTRY_PARAM0_SINGLE_RAIL_VOLT_DOMAIN_MASK \ | ||
875 | GENMASK(7, 0) | ||
876 | #define NV_VBIOS_VPT_ENTRY_PARAM0_SINGLE_RAIL_VOLT_DOMAIN_SHIFT 0 | ||
877 | #define NV_VBIOS_VPT_ENTRY_PARAM0_RSVD_MASK GENMASK(8, 31) | ||
878 | #define NV_VBIOS_VPT_ENTRY_PARAM0_RSVD_SHIFT 8 | ||
879 | |||
880 | #define NV_VBIOS_VPT_ENTRY_PARAM0_SR_VD_MASTER_MASK \ | ||
881 | GENMASK(7, 0) | ||
882 | #define NV_VBIOS_VPT_ENTRY_PARAM0_SR_VD_MASTER_SHIFT 0 | ||
883 | #define NV_VBIOS_VPT_ENTRY_PARAM0_SR_VD_SLAVE_MASK \ | ||
884 | GENMASK(15, 8) | ||
885 | #define NV_VBIOS_VPT_ENTRY_PARAM0_SR_VD_SLAVE_SHIFT 8 | ||
886 | #define NV_VBIOS_VPT_ENTRY_PARAM0_SR_DELTA_SM_MIN_MASK \ | ||
887 | GENMASK(23, 16) | ||
888 | #define NV_VBIOS_VPT_ENTRY_PARAM0_SR_DELTA_SM_MIN_SHIFT 16 | ||
889 | #define NV_VBIOS_VPT_ENTRY_PARAM0_SR_DELTA_SM_MAX_MASK \ | ||
890 | GENMASK(31, 24) | ||
891 | #define NV_VBIOS_VPT_ENTRY_PARAM0_SR_DELTA_SM_MAX_SHIFT 24 | ||
892 | |||
893 | #define NV_VBIOS_VPT_ENTRY_PARAM1_SR_SETTLE_TIME_INTERMEDIATE_MASK \ | ||
894 | GENMASK(15, 0) | ||
895 | #define NV_VBIOS_VPT_ENTRY_PARAM1_SR_SETTLE_TIME_INTERMEDIATE_SHIFT 0 | ||
896 | #define NV_VBIOS_VPT_ENTRY_PARAM2_SR_RAMP_UP_STEP_SIZE_UV_MASK \ | ||
897 | GENMASK(31, 0) | ||
898 | #define NV_VBIOS_VPT_ENTRY_PARAM2_SR_RAMP_UP_STEP_SIZE_UV_SHIFT 0 | ||
899 | #define NV_VBIOS_VPT_ENTRY_PARAM3_SR_RAMP_DOWN_STEP_SIZE_UV_MASK \ | ||
900 | GENMASK(31, 0) | ||
901 | #define NV_VBIOS_VPT_ENTRY_PARAM3_SR_RAMP_DOWN_STEP_SIZE_UV_SHIFT 0 | ||
902 | |||
903 | /* Type-Specific Parameter DWORD 0 - Type = _SR_MULTI_STEP */ | ||
904 | #define NV_VBIOS_VPT_ENTRY_PARAM1_SR_SETTLE_TIME_INTERMEDIATE_MASK \ | ||
905 | GENMASK(15, 0) | ||
906 | #define NV_VBIOS_VPT_ENTRY_PARAM1_SR_SETTLE_TIME_INTERMEDIATE_SHIFT \ | ||
907 | 0 | ||
908 | |||
909 | #define VBIOS_THERM_DEVICE_VERSION_1X 0x10U | ||
910 | |||
911 | #define VBIOS_THERM_DEVICE_1X_HEADER_SIZE_04 0x00000004U | ||
912 | |||
913 | struct therm_device_1x_header { | ||
914 | u8 version; | ||
915 | u8 header_size; | ||
916 | u8 table_entry_size; | ||
917 | u8 num_table_entries; | ||
918 | } ; | ||
919 | |||
920 | struct therm_device_1x_entry { | ||
921 | u8 class_id; | ||
922 | u8 param0; | ||
923 | u8 flags; | ||
924 | } ; | ||
925 | |||
926 | #define NV_VBIOS_THERM_DEVICE_1X_ENTRY_CLASS_INVALID 0x00U | ||
927 | #define NV_VBIOS_THERM_DEVICE_1X_ENTRY_CLASS_GPU 0x01U | ||
928 | #define NV_VBIOS_THERM_DEVICE_1X_ENTRY_CLASS_GPU_GPC_TSOSC 0x02U | ||
929 | #define NV_VBIOS_THERM_DEVICE_1X_ENTRY_CLASS_GPU_GPC_SCI 0x03U | ||
930 | #define NV_VBIOS_THERM_DEVICE_1X_ENTRY_CLASS_HBM2_SITE 0x70U | ||
931 | #define NV_VBIOS_THERM_DEVICE_1X_ENTRY_CLASS_HBM2_COMBINED 0x71U | ||
932 | |||
933 | #define NV_VBIOS_THERM_DEVICE_1X_ENTRY_PARAM0_I2C_DEVICE_INDEX_MASK 0xFF | ||
934 | #define NV_VBIOS_THERM_DEVICE_1X_ENTRY_PARAM0_I2C_DEVICE_INDEX_SHIFT 0 | ||
935 | |||
936 | #define VBIOS_THERM_CHANNEL_VERSION_1X 0x10U | ||
937 | |||
938 | #define VBIOS_THERM_CHANNEL_1X_HEADER_SIZE_09 0x00000009U | ||
939 | |||
940 | struct therm_channel_1x_header { | ||
941 | u8 version; | ||
942 | u8 header_size; | ||
943 | u8 table_entry_size; | ||
944 | u8 num_table_entries; | ||
945 | u8 gpu_avg_pri_ch_idx; | ||
946 | u8 gpu_max_pri_ch_idx; | ||
947 | u8 board_pri_ch_idx; | ||
948 | u8 mem_pri_ch_idx; | ||
949 | u8 pwr_supply_pri_ch_idx; | ||
950 | } __packed; | ||
951 | |||
952 | struct therm_channel_1x_entry { | ||
953 | u8 class_id; | ||
954 | u8 param0; | ||
955 | u8 param1; | ||
956 | u8 param2; | ||
957 | u8 flags; | ||
958 | } __packed; | ||
959 | |||
960 | #define NV_VBIOS_THERM_CHANNEL_1X_ENTRY_CLASS_DEVICE 0x01U | ||
961 | |||
962 | #define NV_VBIOS_THERM_CHANNEL_1X_ENTRY_PARAM0_DEVICE_INDEX_MASK 0xFF | ||
963 | #define NV_VBIOS_THERM_CHANNEL_1X_ENTRY_PARAM0_DEVICE_INDEX_SHIFT 0 | ||
964 | |||
965 | #define NV_VBIOS_THERM_CHANNEL_1X_ENTRY_PARAM1_DEVICE_PROVIDER_INDEX_MASK 0xFF | ||
966 | #define NV_VBIOS_THERM_CHANNEL_1X_ENTRY_PARAM1_DEVICE_PROVIDER_INDEX_SHIFT 0 | ||
967 | |||
968 | /* Frequency Controller Table */ | ||
969 | struct vbios_fct_1x_header { | ||
970 | u8 version; | ||
971 | u8 header_size; | ||
972 | u8 entry_size; | ||
973 | u8 entry_count; | ||
974 | u16 sampling_period_ms; | ||
975 | } __packed; | ||
976 | |||
977 | struct vbios_fct_1x_entry { | ||
978 | u8 flags0; | ||
979 | u8 clk_domain_idx; | ||
980 | u16 param0; | ||
981 | u16 param1; | ||
982 | u32 param2; | ||
983 | u32 param3; | ||
984 | u32 param4; | ||
985 | u32 param5; | ||
986 | u32 param6; | ||
987 | u32 param7; | ||
988 | u32 param8; | ||
989 | } __packed; | ||
990 | |||
991 | #define NV_VBIOS_FCT_1X_ENTRY_FLAGS0_TYPE_MASK GENMASK(3, 0) | ||
992 | #define NV_VBIOS_FCT_1X_ENTRY_FLAGS0_TYPE_SHIFT 0 | ||
993 | #define NV_VBIOS_FCT_1X_ENTRY_FLAGS0_TYPE_DISABLED 0x0 | ||
994 | #define NV_VBIOS_FCT_1X_ENTRY_FLAGS0_TYPE_PI 0x1 | ||
995 | |||
996 | #define NV_VBIOS_FCT_1X_ENTRY_PARAM0_ID_MASK GENMASK(7, 0) | ||
997 | #define NV_VBIOS_FCT_1X_ENTRY_PARAM0_ID_SHIFT 0 | ||
998 | #define NV_VBIOS_FCT_1X_ENTRY_PARAM0_ID_SYS 0x00 | ||
999 | #define NV_VBIOS_FCT_1X_ENTRY_PARAM0_ID_LTC 0x01 | ||
1000 | #define NV_VBIOS_FCT_1X_ENTRY_PARAM0_ID_XBAR 0x02 | ||
1001 | #define NV_VBIOS_FCT_1X_ENTRY_PARAM0_ID_GPC0 0x03 | ||
1002 | #define NV_VBIOS_FCT_1X_ENTRY_PARAM0_ID_GPC1 0x04 | ||
1003 | #define NV_VBIOS_FCT_1X_ENTRY_PARAM0_ID_GPC2 0x05 | ||
1004 | #define NV_VBIOS_FCT_1X_ENTRY_PARAM0_ID_GPC3 0x06 | ||
1005 | #define NV_VBIOS_FCT_1X_ENTRY_PARAM0_ID_GPC4 0x07 | ||
1006 | #define NV_VBIOS_FCT_1X_ENTRY_PARAM0_ID_GPC5 0x08 | ||
1007 | #define NV_VBIOS_FCT_1X_ENTRY_PARAM0_ID_GPCS 0x09 | ||
1008 | |||
1009 | #define NV_VBIOS_FCT_1X_ENTRY_PARAM0_FREQ_MODE_MASK GENMASK(9, 8) | ||
1010 | #define NV_VBIOS_FCT_1X_ENTRY_PARAM0_FREQ_MODE_SHIFT 8 | ||
1011 | #define NV_VBIOS_FCT_1X_ENTRY_PARAM0_FREQ_MODE_BCAST 0x0 | ||
1012 | #define NV_VBIOS_FCT_1X_ENTRY_PARAM0_FREQ_MODE_MIN 0x1 | ||
1013 | #define NV_VBIOS_FCT_1X_ENTRY_PARAM0_FREQ_MODE_MAX 0x2 | ||
1014 | #define NV_VBIOS_FCT_1X_ENTRY_PARAM0_FREQ_MODE_AVG 0x3 | ||
1015 | |||
1016 | #define NV_VBIOS_FCT_1X_ENTRY_PARAM1_SLOWDOWN_PCT_MIN_MASK GENMASK(7, 0) | ||
1017 | #define NV_VBIOS_FCT_1X_ENTRY_PARAM1_SLOWDOWN_PCT_MIN_SHIFT 0 | ||
1018 | |||
1019 | #define NV_VBIOS_FCT_1X_ENTRY_PARAM1_POISON_MASK GENMASK(8, 8) | ||
1020 | #define NV_VBIOS_FCT_1X_ENTRY_PARAM1_POISON_SHIFT 8 | ||
1021 | #define NV_VBIOS_FCT_1X_ENTRY_PARAM1_POISON_NO 0x0 | ||
1022 | #define NV_VBIOS_FCT_1X_ENTRY_PARAM1_POISON_YES 0x1 | ||
1023 | |||
1024 | #define NV_VBIOS_FCT_1X_ENTRY_PARAM2_PROP_GAIN_MASK GENMASK(31, 0) | ||
1025 | #define NV_VBIOS_FCT_1X_ENTRY_PARAM2_PROP_GAIN_SHIFT 0 | ||
1026 | |||
1027 | #define NV_VBIOS_FCT_1X_ENTRY_PARAM3_INTEG_GAIN_MASK GENMASK(31, 0) | ||
1028 | #define NV_VBIOS_FCT_1X_ENTRY_PARAM3_INTEG_GAIN_SHIFT 0 | ||
1029 | |||
1030 | |||
1031 | #define NV_VBIOS_FCT_1X_ENTRY_PARAM4_INTEG_DECAY_MASK GENMASK(31, 0) | ||
1032 | #define NV_VBIOS_FCT_1X_ENTRY_PARAM4_INTEG_DECAY_SHIFT 0 | ||
1033 | |||
1034 | #define NV_VBIOS_FCT_1X_ENTRY_PARAM5_VOLT_DELTA_MIN_MASK GENMASK(31, 0) | ||
1035 | #define NV_VBIOS_FCT_1X_ENTRY_PARAM5_VOLT_DELTA_MIN_SHIFT 0 | ||
1036 | |||
1037 | |||
1038 | #define NV_VBIOS_FCT_1X_ENTRY_PARAM6_VOLT_DELTA_MAX_MASK GENMASK(31, 0) | ||
1039 | #define NV_VBIOS_FCT_1X_ENTRY_PARAM6_VOLT_DELTA_MAX_SHIFT 0 | ||
1040 | |||
1041 | #define NV_VBIOS_FCT_1X_ENTRY_PARAM7_FREQ_CAP_VF_MASK GENMASK(15, 0) | ||
1042 | #define NV_VBIOS_FCT_1X_ENTRY_PARAM7_FREQ_CAP_VF_SHIFT 0 | ||
1043 | #define NV_VBIOS_FCT_1X_ENTRY_PARAM7_FREQ_CAP_VMIN_MASK GENMASK(31, 16) | ||
1044 | #define NV_VBIOS_FCT_1X_ENTRY_PARAM7_FREQ_CAP_VMIN_SHIFT 16 | ||
1045 | |||
1046 | #define NV_VBIOS_FCT_1X_ENTRY_PARAM8_FREQ_HYST_POS_MASK GENMASK(15, 0) | ||
1047 | #define NV_VBIOS_FCT_1X_ENTRY_PARAM8_FREQ_HYST_POS_SHIFT 0 | ||
1048 | #define NV_VBIOS_FCT_1X_ENTRY_PARAM8_FREQ_HYST_NEG_MASK GENMASK(31, 16) | ||
1049 | #define NV_VBIOS_FCT_1X_ENTRY_PARAM8_FREQ_HYST_NEG_SHIFT 16 | ||
1050 | |||
1051 | /* LPWR Index Table */ | ||
1052 | struct nvgpu_bios_lpwr_idx_table_1x_header { | ||
1053 | u8 version; | ||
1054 | u8 header_size; | ||
1055 | u8 entry_size; | ||
1056 | u8 entry_count; | ||
1057 | u16 base_sampling_period; | ||
1058 | } __packed; | ||
1059 | |||
1060 | struct nvgpu_bios_lpwr_idx_table_1x_entry { | ||
1061 | u8 pcie_idx; | ||
1062 | u8 gr_idx; | ||
1063 | u8 ms_idx; | ||
1064 | u8 di_idx; | ||
1065 | u8 gc6_idx; | ||
1066 | } __packed; | ||
1067 | |||
1068 | /* LPWR MS Table*/ | ||
1069 | struct nvgpu_bios_lpwr_ms_table_1x_header { | ||
1070 | u8 version; | ||
1071 | u8 header_size; | ||
1072 | u8 entry_size; | ||
1073 | u8 entry_count; | ||
1074 | u8 default_entry_idx; | ||
1075 | u16 idle_threshold_us; | ||
1076 | } __packed; | ||
1077 | |||
1078 | struct nvgpu_bios_lpwr_ms_table_1x_entry { | ||
1079 | u32 feautre_mask; | ||
1080 | u16 dynamic_current_logic; | ||
1081 | u16 dynamic_current_sram; | ||
1082 | } __packed; | ||
1083 | |||
1084 | #define NV_VBIOS_LPWR_MS_FEATURE_MASK_MS_MASK GENMASK(0, 0) | ||
1085 | #define NV_VBIOS_LPWR_MS_FEATURE_MASK_MS_SHIFT 0 | ||
1086 | #define NV_VBIOS_LPWR_MS_FEATURE_MASK_MS_SWASR_MASK GENMASK(2, 2) | ||
1087 | #define NV_VBIOS_LPWR_MS_FEATURE_MASK_MS_SWASR_SHIFT 2 | ||
1088 | #define NV_VBIOS_LPWR_MS_FEATURE_MASK_MS_CLOCK_GATING_MASK \ | ||
1089 | GENMASK(3, 3) | ||
1090 | #define NV_VBIOS_LPWR_MS_FEATURE_MASK_MS_CLOCK_GATING_SHIFT 3 | ||
1091 | #define NV_VBIOS_LPWR_MS_FEATURE_MASK_MS_RPPG_MASK GENMASK(5, 5) | ||
1092 | #define NV_VBIOS_LPWR_MS_FEATURE_MASK_MS_RPPG_SHIFT 5 | ||
1093 | |||
1094 | /* LPWR GR Table */ | ||
1095 | struct nvgpu_bios_lpwr_gr_table_1x_header { | ||
1096 | u8 version; | ||
1097 | u8 header_size; | ||
1098 | u8 entry_size; | ||
1099 | u8 entry_count; | ||
1100 | u8 default_entry_idx; | ||
1101 | u16 idle_threshold_us; | ||
1102 | u8 adaptive_gr_multiplier; | ||
1103 | } __packed; | ||
1104 | |||
1105 | struct nvgpu_bios_lpwr_gr_table_1x_entry { | ||
1106 | u32 feautre_mask; | ||
1107 | } __packed; | ||
1108 | |||
1109 | #define NV_VBIOS_LPWR_GR_FEATURE_MASK_GR_MASK GENMASK(0, 0) | ||
1110 | #define NV_VBIOS_LPWR_GR_FEATURE_MASK_GR_SHIFT 0 | ||
1111 | |||
1112 | #define NV_VBIOS_LPWR_GR_FEATURE_MASK_GR_RPPG_MASK GENMASK(4, 4) | ||
1113 | #define NV_VBIOS_LPWR_GR_FEATURE_MASK_GR_RPPG_SHIFT 4 | ||
1114 | int nvgpu_bios_parse_rom(struct gk20a *g); | ||
1115 | u8 nvgpu_bios_read_u8(struct gk20a *g, u32 offset); | ||
1116 | s8 nvgpu_bios_read_s8(struct gk20a *g, u32 offset); | ||
1117 | u16 nvgpu_bios_read_u16(struct gk20a *g, u32 offset); | ||
1118 | u32 nvgpu_bios_read_u32(struct gk20a *g, u32 offset); | ||
1119 | void *nvgpu_bios_get_perf_table_ptrs(struct gk20a *g, | ||
1120 | struct bit_token *ptoken, u8 table_id); | ||
1121 | int nvgpu_bios_execute_script(struct gk20a *g, u32 offset); | ||
1122 | u32 nvgpu_bios_get_nvlink_config_data(struct gk20a *g); | ||
1123 | #endif | ||