diff options
author | Joshua Bakita <bakitajoshua@gmail.com> | 2023-06-28 18:24:25 -0400 |
---|---|---|
committer | Joshua Bakita <bakitajoshua@gmail.com> | 2023-06-28 18:24:25 -0400 |
commit | 01e6fac4d61fdd7fff5433942ec93fc2ea1e4df1 (patch) | |
tree | 4ef34501728a087be24f4ba0af90f91486bf780b /include/gk20a/hw_ltc_gk20a.h | |
parent | 306a03d18b305e4e573be3b2931978fa10679eb9 (diff) |
Include nvgpu headers
These are needed to build on NVIDIA's Jetson boards for the time
being. Only a couple structs are required, so it should be fairly
easy to remove this dependency at some point in the future.
Diffstat (limited to 'include/gk20a/hw_ltc_gk20a.h')
-rw-r--r-- | include/gk20a/hw_ltc_gk20a.h | 455 |
1 files changed, 455 insertions, 0 deletions
diff --git a/include/gk20a/hw_ltc_gk20a.h b/include/gk20a/hw_ltc_gk20a.h new file mode 100644 index 0000000..efe7f98 --- /dev/null +++ b/include/gk20a/hw_ltc_gk20a.h | |||
@@ -0,0 +1,455 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2012-2017, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
5 | * copy of this software and associated documentation files (the "Software"), | ||
6 | * to deal in the Software without restriction, including without limitation | ||
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
8 | * and/or sell copies of the Software, and to permit persons to whom the | ||
9 | * Software is furnished to do so, subject to the following conditions: | ||
10 | * | ||
11 | * The above copyright notice and this permission notice shall be included in | ||
12 | * all copies or substantial portions of the Software. | ||
13 | * | ||
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
17 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
18 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
19 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
20 | * DEALINGS IN THE SOFTWARE. | ||
21 | */ | ||
22 | /* | ||
23 | * Function naming determines intended use: | ||
24 | * | ||
25 | * <x>_r(void) : Returns the offset for register <x>. | ||
26 | * | ||
27 | * <x>_o(void) : Returns the offset for element <x>. | ||
28 | * | ||
29 | * <x>_w(void) : Returns the word offset for word (4 byte) element <x>. | ||
30 | * | ||
31 | * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits. | ||
32 | * | ||
33 | * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted | ||
34 | * and masked to place it at field <y> of register <x>. This value | ||
35 | * can be |'d with others to produce a full register value for | ||
36 | * register <x>. | ||
37 | * | ||
38 | * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This | ||
39 | * value can be ~'d and then &'d to clear the value of field <y> for | ||
40 | * register <x>. | ||
41 | * | ||
42 | * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted | ||
43 | * to place it at field <y> of register <x>. This value can be |'d | ||
44 | * with others to produce a full register value for <x>. | ||
45 | * | ||
46 | * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register | ||
47 | * <x> value 'r' after being shifted to place its LSB at bit 0. | ||
48 | * This value is suitable for direct comparison with other unshifted | ||
49 | * values appropriate for use in field <y> of register <x>. | ||
50 | * | ||
51 | * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for | ||
52 | * field <y> of register <x>. This value is suitable for direct | ||
53 | * comparison with unshifted values appropriate for use in field <y> | ||
54 | * of register <x>. | ||
55 | */ | ||
56 | #ifndef _hw_ltc_gk20a_h_ | ||
57 | #define _hw_ltc_gk20a_h_ | ||
58 | |||
59 | static inline u32 ltc_pltcg_base_v(void) | ||
60 | { | ||
61 | return 0x00140000U; | ||
62 | } | ||
63 | static inline u32 ltc_pltcg_extent_v(void) | ||
64 | { | ||
65 | return 0x0017ffffU; | ||
66 | } | ||
67 | static inline u32 ltc_ltcs_lts0_cbc_ctrl1_r(void) | ||
68 | { | ||
69 | return 0x001410c8U; | ||
70 | } | ||
71 | static inline u32 ltc_ltc0_lts0_dstg_cfg0_r(void) | ||
72 | { | ||
73 | return 0x00141200U; | ||
74 | } | ||
75 | static inline u32 ltc_ltcs_ltss_dstg_cfg0_r(void) | ||
76 | { | ||
77 | return 0x0017ea00U; | ||
78 | } | ||
79 | static inline u32 ltc_ltc0_lts0_tstg_cfg1_r(void) | ||
80 | { | ||
81 | return 0x00141104U; | ||
82 | } | ||
83 | static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_ways_v(u32 r) | ||
84 | { | ||
85 | return (r >> 0U) & 0xffffU; | ||
86 | } | ||
87 | static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_v(u32 r) | ||
88 | { | ||
89 | return (r >> 16U) & 0x3U; | ||
90 | } | ||
91 | static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_all_v(void) | ||
92 | { | ||
93 | return 0x00000000U; | ||
94 | } | ||
95 | static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_half_v(void) | ||
96 | { | ||
97 | return 0x00000001U; | ||
98 | } | ||
99 | static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_quarter_v(void) | ||
100 | { | ||
101 | return 0x00000002U; | ||
102 | } | ||
103 | static inline u32 ltc_ltcs_ltss_cbc_ctrl1_r(void) | ||
104 | { | ||
105 | return 0x0017e8c8U; | ||
106 | } | ||
107 | static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clean_active_f(void) | ||
108 | { | ||
109 | return 0x1U; | ||
110 | } | ||
111 | static inline u32 ltc_ltcs_ltss_cbc_ctrl1_invalidate_active_f(void) | ||
112 | { | ||
113 | return 0x2U; | ||
114 | } | ||
115 | static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clear_v(u32 r) | ||
116 | { | ||
117 | return (r >> 2U) & 0x1U; | ||
118 | } | ||
119 | static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clear_active_v(void) | ||
120 | { | ||
121 | return 0x00000001U; | ||
122 | } | ||
123 | static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clear_active_f(void) | ||
124 | { | ||
125 | return 0x4U; | ||
126 | } | ||
127 | static inline u32 ltc_ltc0_lts0_cbc_ctrl1_r(void) | ||
128 | { | ||
129 | return 0x001410c8U; | ||
130 | } | ||
131 | static inline u32 ltc_ltcs_ltss_cbc_ctrl2_r(void) | ||
132 | { | ||
133 | return 0x0017e8ccU; | ||
134 | } | ||
135 | static inline u32 ltc_ltcs_ltss_cbc_ctrl2_clear_lower_bound_f(u32 v) | ||
136 | { | ||
137 | return (v & 0x1ffffU) << 0U; | ||
138 | } | ||
139 | static inline u32 ltc_ltcs_ltss_cbc_ctrl3_r(void) | ||
140 | { | ||
141 | return 0x0017e8d0U; | ||
142 | } | ||
143 | static inline u32 ltc_ltcs_ltss_cbc_ctrl3_clear_upper_bound_f(u32 v) | ||
144 | { | ||
145 | return (v & 0x1ffffU) << 0U; | ||
146 | } | ||
147 | static inline u32 ltc_ltcs_ltss_cbc_ctrl3_clear_upper_bound_init_v(void) | ||
148 | { | ||
149 | return 0x0001ffffU; | ||
150 | } | ||
151 | static inline u32 ltc_ltcs_ltss_cbc_base_r(void) | ||
152 | { | ||
153 | return 0x0017e8d4U; | ||
154 | } | ||
155 | static inline u32 ltc_ltcs_ltss_cbc_base_alignment_shift_v(void) | ||
156 | { | ||
157 | return 0x0000000bU; | ||
158 | } | ||
159 | static inline u32 ltc_ltcs_ltss_cbc_base_address_v(u32 r) | ||
160 | { | ||
161 | return (r >> 0U) & 0x3ffffffU; | ||
162 | } | ||
163 | static inline u32 ltc_ltcs_ltss_cbc_param_r(void) | ||
164 | { | ||
165 | return 0x0017e8dcU; | ||
166 | } | ||
167 | static inline u32 ltc_ltcs_ltss_cbc_param_comptags_per_cache_line_v(u32 r) | ||
168 | { | ||
169 | return (r >> 0U) & 0xffffU; | ||
170 | } | ||
171 | static inline u32 ltc_ltcs_ltss_cbc_param_cache_line_size_v(u32 r) | ||
172 | { | ||
173 | return (r >> 24U) & 0xfU; | ||
174 | } | ||
175 | static inline u32 ltc_ltcs_ltss_cbc_param_slices_per_fbp_v(u32 r) | ||
176 | { | ||
177 | return (r >> 28U) & 0xfU; | ||
178 | } | ||
179 | static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_r(void) | ||
180 | { | ||
181 | return 0x0017e91cU; | ||
182 | } | ||
183 | static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_max_ways_evict_last_f(u32 v) | ||
184 | { | ||
185 | return (v & 0x1fU) << 16U; | ||
186 | } | ||
187 | static inline u32 ltc_ltcs_ltss_dstg_zbc_index_r(void) | ||
188 | { | ||
189 | return 0x0017ea44U; | ||
190 | } | ||
191 | static inline u32 ltc_ltcs_ltss_dstg_zbc_index_address_f(u32 v) | ||
192 | { | ||
193 | return (v & 0xfU) << 0U; | ||
194 | } | ||
195 | static inline u32 ltc_ltcs_ltss_dstg_zbc_color_clear_value_r(u32 i) | ||
196 | { | ||
197 | return 0x0017ea48U + i*4U; | ||
198 | } | ||
199 | static inline u32 ltc_ltcs_ltss_dstg_zbc_color_clear_value__size_1_v(void) | ||
200 | { | ||
201 | return 0x00000004U; | ||
202 | } | ||
203 | static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_r(void) | ||
204 | { | ||
205 | return 0x0017ea58U; | ||
206 | } | ||
207 | static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_s(void) | ||
208 | { | ||
209 | return 32U; | ||
210 | } | ||
211 | static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_f(u32 v) | ||
212 | { | ||
213 | return (v & 0xffffffffU) << 0U; | ||
214 | } | ||
215 | static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_m(void) | ||
216 | { | ||
217 | return 0xffffffffU << 0U; | ||
218 | } | ||
219 | static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_v(u32 r) | ||
220 | { | ||
221 | return (r >> 0U) & 0xffffffffU; | ||
222 | } | ||
223 | static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_2_r(void) | ||
224 | { | ||
225 | return 0x0017e924U; | ||
226 | } | ||
227 | static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_2_l2_bypass_mode_enabled_f(void) | ||
228 | { | ||
229 | return 0x10000000U; | ||
230 | } | ||
231 | static inline u32 ltc_ltcs_ltss_g_elpg_r(void) | ||
232 | { | ||
233 | return 0x0017e828U; | ||
234 | } | ||
235 | static inline u32 ltc_ltcs_ltss_g_elpg_flush_v(u32 r) | ||
236 | { | ||
237 | return (r >> 0U) & 0x1U; | ||
238 | } | ||
239 | static inline u32 ltc_ltcs_ltss_g_elpg_flush_pending_v(void) | ||
240 | { | ||
241 | return 0x00000001U; | ||
242 | } | ||
243 | static inline u32 ltc_ltcs_ltss_g_elpg_flush_pending_f(void) | ||
244 | { | ||
245 | return 0x1U; | ||
246 | } | ||
247 | static inline u32 ltc_ltc0_ltss_g_elpg_r(void) | ||
248 | { | ||
249 | return 0x00140828U; | ||
250 | } | ||
251 | static inline u32 ltc_ltc0_ltss_g_elpg_flush_v(u32 r) | ||
252 | { | ||
253 | return (r >> 0U) & 0x1U; | ||
254 | } | ||
255 | static inline u32 ltc_ltc0_ltss_g_elpg_flush_pending_v(void) | ||
256 | { | ||
257 | return 0x00000001U; | ||
258 | } | ||
259 | static inline u32 ltc_ltc0_ltss_g_elpg_flush_pending_f(void) | ||
260 | { | ||
261 | return 0x1U; | ||
262 | } | ||
263 | static inline u32 ltc_ltc0_ltss_intr_r(void) | ||
264 | { | ||
265 | return 0x00140820U; | ||
266 | } | ||
267 | static inline u32 ltc_ltcs_ltss_intr_r(void) | ||
268 | { | ||
269 | return 0x0017e820U; | ||
270 | } | ||
271 | static inline u32 ltc_ltcs_ltss_intr_en_evicted_cb_m(void) | ||
272 | { | ||
273 | return 0x1U << 20U; | ||
274 | } | ||
275 | static inline u32 ltc_ltcs_ltss_intr_en_illegal_compstat_m(void) | ||
276 | { | ||
277 | return 0x1U << 21U; | ||
278 | } | ||
279 | static inline u32 ltc_ltc0_lts0_intr_r(void) | ||
280 | { | ||
281 | return 0x00141020U; | ||
282 | } | ||
283 | static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_r(void) | ||
284 | { | ||
285 | return 0x0017e910U; | ||
286 | } | ||
287 | static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_v(u32 r) | ||
288 | { | ||
289 | return (r >> 0U) & 0x1U; | ||
290 | } | ||
291 | static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_pending_v(void) | ||
292 | { | ||
293 | return 0x00000001U; | ||
294 | } | ||
295 | static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_pending_f(void) | ||
296 | { | ||
297 | return 0x1U; | ||
298 | } | ||
299 | static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_max_cycles_between_invalidates_v(u32 r) | ||
300 | { | ||
301 | return (r >> 8U) & 0xfU; | ||
302 | } | ||
303 | static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_max_cycles_between_invalidates_3_v(void) | ||
304 | { | ||
305 | return 0x00000003U; | ||
306 | } | ||
307 | static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_max_cycles_between_invalidates_3_f(void) | ||
308 | { | ||
309 | return 0x300U; | ||
310 | } | ||
311 | static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_last_class_v(u32 r) | ||
312 | { | ||
313 | return (r >> 28U) & 0x1U; | ||
314 | } | ||
315 | static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_last_class_true_v(void) | ||
316 | { | ||
317 | return 0x00000001U; | ||
318 | } | ||
319 | static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_last_class_true_f(void) | ||
320 | { | ||
321 | return 0x10000000U; | ||
322 | } | ||
323 | static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_normal_class_v(u32 r) | ||
324 | { | ||
325 | return (r >> 29U) & 0x1U; | ||
326 | } | ||
327 | static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_normal_class_true_v(void) | ||
328 | { | ||
329 | return 0x00000001U; | ||
330 | } | ||
331 | static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_normal_class_true_f(void) | ||
332 | { | ||
333 | return 0x20000000U; | ||
334 | } | ||
335 | static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_first_class_v(u32 r) | ||
336 | { | ||
337 | return (r >> 30U) & 0x1U; | ||
338 | } | ||
339 | static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_first_class_true_v(void) | ||
340 | { | ||
341 | return 0x00000001U; | ||
342 | } | ||
343 | static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_first_class_true_f(void) | ||
344 | { | ||
345 | return 0x40000000U; | ||
346 | } | ||
347 | static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_r(void) | ||
348 | { | ||
349 | return 0x0017e914U; | ||
350 | } | ||
351 | static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_v(u32 r) | ||
352 | { | ||
353 | return (r >> 0U) & 0x1U; | ||
354 | } | ||
355 | static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_pending_v(void) | ||
356 | { | ||
357 | return 0x00000001U; | ||
358 | } | ||
359 | static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_pending_f(void) | ||
360 | { | ||
361 | return 0x1U; | ||
362 | } | ||
363 | static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_max_cycles_between_cleans_v(u32 r) | ||
364 | { | ||
365 | return (r >> 8U) & 0xfU; | ||
366 | } | ||
367 | static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_max_cycles_between_cleans_3_v(void) | ||
368 | { | ||
369 | return 0x00000003U; | ||
370 | } | ||
371 | static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_max_cycles_between_cleans_3_f(void) | ||
372 | { | ||
373 | return 0x300U; | ||
374 | } | ||
375 | static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_wait_for_fb_to_pull_v(u32 r) | ||
376 | { | ||
377 | return (r >> 16U) & 0x1U; | ||
378 | } | ||
379 | static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_wait_for_fb_to_pull_true_v(void) | ||
380 | { | ||
381 | return 0x00000001U; | ||
382 | } | ||
383 | static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_wait_for_fb_to_pull_true_f(void) | ||
384 | { | ||
385 | return 0x10000U; | ||
386 | } | ||
387 | static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_last_class_v(u32 r) | ||
388 | { | ||
389 | return (r >> 28U) & 0x1U; | ||
390 | } | ||
391 | static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_last_class_true_v(void) | ||
392 | { | ||
393 | return 0x00000001U; | ||
394 | } | ||
395 | static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_last_class_true_f(void) | ||
396 | { | ||
397 | return 0x10000000U; | ||
398 | } | ||
399 | static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_normal_class_v(u32 r) | ||
400 | { | ||
401 | return (r >> 29U) & 0x1U; | ||
402 | } | ||
403 | static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_normal_class_true_v(void) | ||
404 | { | ||
405 | return 0x00000001U; | ||
406 | } | ||
407 | static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_normal_class_true_f(void) | ||
408 | { | ||
409 | return 0x20000000U; | ||
410 | } | ||
411 | static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_first_class_v(u32 r) | ||
412 | { | ||
413 | return (r >> 30U) & 0x1U; | ||
414 | } | ||
415 | static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_first_class_true_v(void) | ||
416 | { | ||
417 | return 0x00000001U; | ||
418 | } | ||
419 | static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_first_class_true_f(void) | ||
420 | { | ||
421 | return 0x40000000U; | ||
422 | } | ||
423 | static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_r(void) | ||
424 | { | ||
425 | return 0x00140910U; | ||
426 | } | ||
427 | static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_invalidate_v(u32 r) | ||
428 | { | ||
429 | return (r >> 0U) & 0x1U; | ||
430 | } | ||
431 | static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_invalidate_pending_v(void) | ||
432 | { | ||
433 | return 0x00000001U; | ||
434 | } | ||
435 | static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_invalidate_pending_f(void) | ||
436 | { | ||
437 | return 0x1U; | ||
438 | } | ||
439 | static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_r(void) | ||
440 | { | ||
441 | return 0x00140914U; | ||
442 | } | ||
443 | static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_clean_v(u32 r) | ||
444 | { | ||
445 | return (r >> 0U) & 0x1U; | ||
446 | } | ||
447 | static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_clean_pending_v(void) | ||
448 | { | ||
449 | return 0x00000001U; | ||
450 | } | ||
451 | static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_clean_pending_f(void) | ||
452 | { | ||
453 | return 0x1U; | ||
454 | } | ||
455 | #endif | ||