Include nvgpu headers

These are needed to build on NVIDIA's Jetson boards for the time
being. Only a couple structs are required, so it should be fairly
easy to remove this dependency at some point in the future.

1 files changed, 8998 insertions, 0 deletions

diff --git a/include/gk20a/gr_gk20a.c b/include/gk20a/gr_gk20a.c
new file mode 100644
index 0000000..7bcf528
--- /dev/null
+++ b/include/gk20a/gr_gk20a.c
@@ -0,0 +1,8998 @@
+/*
+ * GK20A Graphics
+ *
+ * Copyright (c) 2011-2020, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include <nvgpu/dma.h>
+#include <nvgpu/kmem.h>
+#include <nvgpu/gmmu.h>
+#include <nvgpu/timers.h>
+#include <nvgpu/nvgpu_common.h>
+#include <nvgpu/log.h>
+#include <nvgpu/bsearch.h>
+#include <nvgpu/sort.h>
+#include <nvgpu/bug.h>
+#include <nvgpu/firmware.h>
+#include <nvgpu/enabled.h>
+#include <nvgpu/debug.h>
+#include <nvgpu/barrier.h>
+#include <nvgpu/mm.h>
+#include <nvgpu/ctxsw_trace.h>
+#include <nvgpu/error_notifier.h>
+#include <nvgpu/ecc.h>
+#include <nvgpu/io.h>
+#include <nvgpu/utils.h>
+#include <nvgpu/channel.h>
+#include <nvgpu/unit.h>
+#include <nvgpu/power_features/pg.h>
+#include <nvgpu/power_features/cg.h>
+
+#include "gk20a.h"
+#include "gr_gk20a.h"
+#include "gk20a/fecs_trace_gk20a.h"
+#include "gr_ctx_gk20a.h"
+#include "gr_pri_gk20a.h"
+#include "regops_gk20a.h"
+#include "dbg_gpu_gk20a.h"
+
+#include <nvgpu/hw/gk20a/hw_ccsr_gk20a.h>
+#include <nvgpu/hw/gk20a/hw_ctxsw_prog_gk20a.h>
+#include <nvgpu/hw/gk20a/hw_fifo_gk20a.h>
+#include <nvgpu/hw/gk20a/hw_gr_gk20a.h>
+#include <nvgpu/hw/gk20a/hw_gmmu_gk20a.h>
+#include <nvgpu/hw/gk20a/hw_mc_gk20a.h>
+#include <nvgpu/hw/gk20a/hw_ram_gk20a.h>
+#include <nvgpu/hw/gk20a/hw_pri_ringmaster_gk20a.h>
+#include <nvgpu/hw/gk20a/hw_top_gk20a.h>
+#include <nvgpu/hw/gk20a/hw_pbdma_gk20a.h>
+
+#define BLK_SIZE (256)
+#define NV_PERF_PMM_FBP_ROUTER_STRIDE 0x0200
+#define NV_PERF_PMMGPCROUTER_STRIDE     0x0200
+#define NV_PCFG_BASE            0x00088000
+#define NV_XBAR_MXBAR_PRI_GPC_GNIC_STRIDE       0x0020
+#define FE_PWR_MODE_TIMEOUT_MAX 2000
+#define FE_PWR_MODE_TIMEOUT_DEFAULT 10
+#define CTXSW_MEM_SCRUBBING_TIMEOUT_MAX 1000
+#define CTXSW_MEM_SCRUBBING_TIMEOUT_DEFAULT 10
+#define FECS_ARB_CMD_TIMEOUT_MAX 40
+#define FECS_ARB_CMD_TIMEOUT_DEFAULT 2
+
+static int gk20a_init_gr_bind_fecs_elpg(struct gk20a *g);
+
+static void gr_gk20a_free_channel_pm_ctx(struct gk20a *g,
+                                         struct vm_gk20a *vm,
+                                         struct nvgpu_gr_ctx *gr_ctx);
+
+/* channel patch ctx buffer */
+static int  gr_gk20a_alloc_channel_patch_ctx(struct gk20a *g,
+                                        struct channel_gk20a *c);
+static void gr_gk20a_free_channel_patch_ctx(struct gk20a *g,
+                                            struct vm_gk20a *vm,
+                                            struct nvgpu_gr_ctx *gr_ctx);
+
+/* golden ctx image */
+static int gr_gk20a_init_golden_ctx_image(struct gk20a *g,
+                                          struct channel_gk20a *c);
+
+int gr_gk20a_get_ctx_id(struct gk20a *g,
+                struct channel_gk20a *c,
+                u32 *ctx_id)
+{
+        struct tsg_gk20a *tsg;
+        struct nvgpu_gr_ctx *gr_ctx = NULL;
+        struct nvgpu_mem *mem = NULL;
+
+        tsg = tsg_gk20a_from_ch(c);
+        if (tsg == NULL) {
+                return -EINVAL;
+        }
+
+        gr_ctx = &tsg->gr_ctx;
+        mem = &gr_ctx->mem;
+
+        /* Channel gr_ctx buffer is gpu cacheable.
+           Flush and invalidate before cpu update. */
+        g->ops.mm.l2_flush(g, true);
+
+        *ctx_id = nvgpu_mem_rd(g, mem,
+                        ctxsw_prog_main_image_context_id_o());
+        nvgpu_log(g, gpu_dbg_fn | gpu_dbg_intr, "ctx_id: 0x%x", *ctx_id);
+
+        return 0;
+}
+
+void gk20a_fecs_dump_falcon_stats(struct gk20a *g)
+{
+        unsigned int i;
+
+        nvgpu_err(g, "gr_fecs_os_r : %d",
+                gk20a_readl(g, gr_fecs_os_r()));
+        nvgpu_err(g, "gr_fecs_cpuctl_r : 0x%x",
+                gk20a_readl(g, gr_fecs_cpuctl_r()));
+        nvgpu_err(g, "gr_fecs_idlestate_r : 0x%x",
+                gk20a_readl(g, gr_fecs_idlestate_r()));
+        nvgpu_err(g, "gr_fecs_mailbox0_r : 0x%x",
+                gk20a_readl(g, gr_fecs_mailbox0_r()));
+        nvgpu_err(g, "gr_fecs_mailbox1_r : 0x%x",
+                gk20a_readl(g, gr_fecs_mailbox1_r()));
+        nvgpu_err(g, "gr_fecs_irqstat_r : 0x%x",
+                gk20a_readl(g, gr_fecs_irqstat_r()));
+        nvgpu_err(g, "gr_fecs_irqmode_r : 0x%x",
+                gk20a_readl(g, gr_fecs_irqmode_r()));
+        nvgpu_err(g, "gr_fecs_irqmask_r : 0x%x",
+                gk20a_readl(g, gr_fecs_irqmask_r()));
+        nvgpu_err(g, "gr_fecs_irqdest_r : 0x%x",
+                gk20a_readl(g, gr_fecs_irqdest_r()));
+        nvgpu_err(g, "gr_fecs_debug1_r : 0x%x",
+                gk20a_readl(g, gr_fecs_debug1_r()));
+        nvgpu_err(g, "gr_fecs_debuginfo_r : 0x%x",
+                gk20a_readl(g, gr_fecs_debuginfo_r()));
+        nvgpu_err(g, "gr_fecs_ctxsw_status_1_r : 0x%x",
+                gk20a_readl(g, gr_fecs_ctxsw_status_1_r()));
+
+        for (i = 0; i < g->ops.gr.fecs_ctxsw_mailbox_size(); i++) {
+                nvgpu_err(g, "gr_fecs_ctxsw_mailbox_r(%d) : 0x%x",
+                        i, gk20a_readl(g, gr_fecs_ctxsw_mailbox_r(i)));
+        }
+
+        nvgpu_err(g, "gr_fecs_engctl_r : 0x%x",
+                gk20a_readl(g, gr_fecs_engctl_r()));
+        nvgpu_err(g, "gr_fecs_curctx_r : 0x%x",
+                gk20a_readl(g, gr_fecs_curctx_r()));
+        nvgpu_err(g, "gr_fecs_nxtctx_r : 0x%x",
+                gk20a_readl(g, gr_fecs_nxtctx_r()));
+
+        gk20a_writel(g, gr_fecs_icd_cmd_r(),
+                gr_fecs_icd_cmd_opc_rreg_f() |
+                gr_fecs_icd_cmd_idx_f(PMU_FALCON_REG_IMB));
+        nvgpu_err(g, "FECS_FALCON_REG_IMB : 0x%x",
+                gk20a_readl(g, gr_fecs_icd_rdata_r()));
+
+        gk20a_writel(g, gr_fecs_icd_cmd_r(),
+                gr_fecs_icd_cmd_opc_rreg_f() |
+                gr_fecs_icd_cmd_idx_f(PMU_FALCON_REG_DMB));
+        nvgpu_err(g, "FECS_FALCON_REG_DMB : 0x%x",
+                gk20a_readl(g, gr_fecs_icd_rdata_r()));
+
+        gk20a_writel(g, gr_fecs_icd_cmd_r(),
+                gr_fecs_icd_cmd_opc_rreg_f() |
+                gr_fecs_icd_cmd_idx_f(PMU_FALCON_REG_CSW));
+        nvgpu_err(g, "FECS_FALCON_REG_CSW : 0x%x",
+                gk20a_readl(g, gr_fecs_icd_rdata_r()));
+
+        gk20a_writel(g, gr_fecs_icd_cmd_r(),
+                gr_fecs_icd_cmd_opc_rreg_f() |
+                gr_fecs_icd_cmd_idx_f(PMU_FALCON_REG_CTX));
+        nvgpu_err(g, "FECS_FALCON_REG_CTX : 0x%x",
+                gk20a_readl(g, gr_fecs_icd_rdata_r()));
+
+        gk20a_writel(g, gr_fecs_icd_cmd_r(),
+                gr_fecs_icd_cmd_opc_rreg_f() |
+                gr_fecs_icd_cmd_idx_f(PMU_FALCON_REG_EXCI));
+        nvgpu_err(g, "FECS_FALCON_REG_EXCI : 0x%x",
+                gk20a_readl(g, gr_fecs_icd_rdata_r()));
+
+        for (i = 0; i < 4; i++) {
+                gk20a_writel(g, gr_fecs_icd_cmd_r(),
+                        gr_fecs_icd_cmd_opc_rreg_f() |
+                        gr_fecs_icd_cmd_idx_f(PMU_FALCON_REG_PC));
+                nvgpu_err(g, "FECS_FALCON_REG_PC : 0x%x",
+                        gk20a_readl(g, gr_fecs_icd_rdata_r()));
+
+                gk20a_writel(g, gr_fecs_icd_cmd_r(),
+                        gr_fecs_icd_cmd_opc_rreg_f() |
+                        gr_fecs_icd_cmd_idx_f(PMU_FALCON_REG_SP));
+                nvgpu_err(g, "FECS_FALCON_REG_SP : 0x%x",
+                        gk20a_readl(g, gr_fecs_icd_rdata_r()));
+        }
+}
+
+static void gr_gk20a_load_falcon_dmem(struct gk20a *g)
+{
+        u32 i, ucode_u32_size;
+        const u32 *ucode_u32_data;
+        u32 checksum;