diff options
author | Joshua Bakita <bakitajoshua@gmail.com> | 2023-06-28 18:24:25 -0400 |
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committer | Joshua Bakita <bakitajoshua@gmail.com> | 2023-06-28 18:24:25 -0400 |
commit | 01e6fac4d61fdd7fff5433942ec93fc2ea1e4df1 (patch) | |
tree | 4ef34501728a087be24f4ba0af90f91486bf780b /include/gk20a/gr_ctx_gk20a.h | |
parent | 306a03d18b305e4e573be3b2931978fa10679eb9 (diff) |
Include nvgpu headers
These are needed to build on NVIDIA's Jetson boards for the time
being. Only a couple structs are required, so it should be fairly
easy to remove this dependency at some point in the future.
Diffstat (limited to 'include/gk20a/gr_ctx_gk20a.h')
-rw-r--r-- | include/gk20a/gr_ctx_gk20a.h | 206 |
1 files changed, 206 insertions, 0 deletions
diff --git a/include/gk20a/gr_ctx_gk20a.h b/include/gk20a/gr_ctx_gk20a.h new file mode 100644 index 0000000..e75472c --- /dev/null +++ b/include/gk20a/gr_ctx_gk20a.h | |||
@@ -0,0 +1,206 @@ | |||
1 | /* | ||
2 | * GK20A Graphics Context | ||
3 | * | ||
4 | * Copyright (c) 2011-2018, NVIDIA CORPORATION. All rights reserved. | ||
5 | * | ||
6 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
7 | * copy of this software and associated documentation files (the "Software"), | ||
8 | * to deal in the Software without restriction, including without limitation | ||
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
10 | * and/or sell copies of the Software, and to permit persons to whom the | ||
11 | * Software is furnished to do so, subject to the following conditions: | ||
12 | * | ||
13 | * The above copyright notice and this permission notice shall be included in | ||
14 | * all copies or substantial portions of the Software. | ||
15 | * | ||
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
22 | * DEALINGS IN THE SOFTWARE. | ||
23 | */ | ||
24 | #ifndef NVGPU_GK20A_GR_CTX_GK20A_H | ||
25 | #define NVGPU_GK20A_GR_CTX_GK20A_H | ||
26 | |||
27 | #include <nvgpu/kmem.h> | ||
28 | |||
29 | struct gr_gk20a; | ||
30 | |||
31 | /* emulation netlists, match majorV with HW */ | ||
32 | #define GK20A_NETLIST_IMAGE_A "NETA_img.bin" | ||
33 | #define GK20A_NETLIST_IMAGE_B "NETB_img.bin" | ||
34 | #define GK20A_NETLIST_IMAGE_C "NETC_img.bin" | ||
35 | #define GK20A_NETLIST_IMAGE_D "NETD_img.bin" | ||
36 | |||
37 | /* | ||
38 | * Need to support multiple ARCH in same GPU family | ||
39 | * then need to provide path like ARCH/NETIMAGE to | ||
40 | * point to correct netimage within GPU family, | ||
41 | * Example, gm20x can support gm204 or gm206,so path | ||
42 | * for netimage is gm204/NETC_img.bin, and '/' char | ||
43 | * will inserted at null terminator char of "GAxxx" | ||
44 | * to get complete path like gm204/NETC_img.bin | ||
45 | */ | ||
46 | #define GPU_ARCH "GAxxx" | ||
47 | |||
48 | union __max_name { | ||
49 | #ifdef GK20A_NETLIST_IMAGE_A | ||
50 | char __name_a[sizeof(GK20A_NETLIST_IMAGE_A)]; | ||
51 | #endif | ||
52 | #ifdef GK20A_NETLIST_IMAGE_B | ||
53 | char __name_b[sizeof(GK20A_NETLIST_IMAGE_B)]; | ||
54 | #endif | ||
55 | #ifdef GK20A_NETLIST_IMAGE_C | ||
56 | char __name_c[sizeof(GK20A_NETLIST_IMAGE_C)]; | ||
57 | #endif | ||
58 | #ifdef GK20A_NETLIST_IMAGE_D | ||
59 | char __name_d[sizeof(GK20A_NETLIST_IMAGE_D)]; | ||
60 | #endif | ||
61 | }; | ||
62 | |||
63 | #define MAX_NETLIST_NAME (sizeof(GPU_ARCH) + sizeof(union __max_name)) | ||
64 | |||
65 | /* index for emulation netlists */ | ||
66 | #define NETLIST_FINAL -1 | ||
67 | #define NETLIST_SLOT_A 0 | ||
68 | #define NETLIST_SLOT_B 1 | ||
69 | #define NETLIST_SLOT_C 2 | ||
70 | #define NETLIST_SLOT_D 3 | ||
71 | #define MAX_NETLIST 4 | ||
72 | |||
73 | /* netlist regions */ | ||
74 | #define NETLIST_REGIONID_FECS_UCODE_DATA 0 | ||
75 | #define NETLIST_REGIONID_FECS_UCODE_INST 1 | ||
76 | #define NETLIST_REGIONID_GPCCS_UCODE_DATA 2 | ||
77 | #define NETLIST_REGIONID_GPCCS_UCODE_INST 3 | ||
78 | #define NETLIST_REGIONID_SW_BUNDLE_INIT 4 | ||
79 | #define NETLIST_REGIONID_SW_CTX_LOAD 5 | ||
80 | #define NETLIST_REGIONID_SW_NON_CTX_LOAD 6 | ||
81 | #define NETLIST_REGIONID_SW_METHOD_INIT 7 | ||
82 | #define NETLIST_REGIONID_CTXREG_SYS 8 | ||
83 | #define NETLIST_REGIONID_CTXREG_GPC 9 | ||
84 | #define NETLIST_REGIONID_CTXREG_TPC 10 | ||
85 | #define NETLIST_REGIONID_CTXREG_ZCULL_GPC 11 | ||
86 | #define NETLIST_REGIONID_CTXREG_PM_SYS 12 | ||
87 | #define NETLIST_REGIONID_CTXREG_PM_GPC 13 | ||
88 | #define NETLIST_REGIONID_CTXREG_PM_TPC 14 | ||
89 | #define NETLIST_REGIONID_MAJORV 15 | ||
90 | #define NETLIST_REGIONID_BUFFER_SIZE 16 | ||
91 | #define NETLIST_REGIONID_CTXSW_REG_BASE_INDEX 17 | ||
92 | #define NETLIST_REGIONID_NETLIST_NUM 18 | ||
93 | #define NETLIST_REGIONID_CTXREG_PPC 19 | ||
94 | #define NETLIST_REGIONID_CTXREG_PMPPC 20 | ||
95 | #define NETLIST_REGIONID_NVPERF_CTXREG_SYS 21 | ||
96 | #define NETLIST_REGIONID_NVPERF_FBP_CTXREGS 22 | ||
97 | #define NETLIST_REGIONID_NVPERF_CTXREG_GPC 23 | ||
98 | #define NETLIST_REGIONID_NVPERF_FBP_ROUTER 24 | ||
99 | #define NETLIST_REGIONID_NVPERF_GPC_ROUTER 25 | ||
100 | #define NETLIST_REGIONID_CTXREG_PMLTC 26 | ||
101 | #define NETLIST_REGIONID_CTXREG_PMFBPA 27 | ||
102 | #define NETLIST_REGIONID_SWVEIDBUNDLEINIT 28 | ||
103 | #define NETLIST_REGIONID_NVPERF_SYS_ROUTER 29 | ||
104 | #define NETLIST_REGIONID_NVPERF_PMA 30 | ||
105 | #define NETLIST_REGIONID_CTXREG_PMROP 31 | ||
106 | #define NETLIST_REGIONID_CTXREG_PMUCGPC 32 | ||
107 | #define NETLIST_REGIONID_CTXREG_ETPC 33 | ||
108 | #define NETLIST_REGIONID_SW_BUNDLE64_INIT 34 | ||
109 | #define NETLIST_REGIONID_NVPERF_PMCAU 35 | ||
110 | |||
111 | struct netlist_region { | ||
112 | u32 region_id; | ||
113 | u32 data_size; | ||
114 | u32 data_offset; | ||
115 | }; | ||
116 | |||
117 | struct netlist_image_header { | ||
118 | u32 version; | ||
119 | u32 regions; | ||
120 | }; | ||
121 | |||
122 | struct netlist_image { | ||
123 | struct netlist_image_header header; | ||
124 | struct netlist_region regions[1]; | ||
125 | }; | ||
126 | |||
127 | struct av_gk20a { | ||
128 | u32 addr; | ||
129 | u32 value; | ||
130 | }; | ||
131 | struct av64_gk20a { | ||
132 | u32 addr; | ||
133 | u32 value_lo; | ||
134 | u32 value_hi; | ||
135 | }; | ||
136 | struct aiv_gk20a { | ||
137 | u32 addr; | ||
138 | u32 index; | ||
139 | u32 value; | ||
140 | }; | ||
141 | struct aiv_list_gk20a { | ||
142 | struct aiv_gk20a *l; | ||
143 | u32 count; | ||
144 | }; | ||
145 | struct av_list_gk20a { | ||
146 | struct av_gk20a *l; | ||
147 | u32 count; | ||
148 | }; | ||
149 | struct av64_list_gk20a { | ||
150 | struct av64_gk20a *l; | ||
151 | u32 count; | ||
152 | }; | ||
153 | struct u32_list_gk20a { | ||
154 | u32 *l; | ||
155 | u32 count; | ||
156 | }; | ||
157 | |||
158 | struct ctxsw_buf_offset_map_entry { | ||
159 | u32 addr; /* Register address */ | ||
160 | u32 offset; /* Offset in ctxt switch buffer */ | ||
161 | }; | ||
162 | |||
163 | static inline | ||
164 | struct av_gk20a *alloc_av_list_gk20a(struct gk20a *g, struct av_list_gk20a *avl) | ||
165 | { | ||
166 | avl->l = nvgpu_kzalloc(g, avl->count * sizeof(*avl->l)); | ||
167 | return avl->l; | ||
168 | } | ||
169 | |||
170 | static inline | ||
171 | struct av64_gk20a *alloc_av64_list_gk20a(struct gk20a *g, struct av64_list_gk20a *avl) | ||
172 | { | ||
173 | avl->l = nvgpu_kzalloc(g, avl->count * sizeof(*avl->l)); | ||
174 | return avl->l; | ||
175 | } | ||
176 | |||
177 | static inline | ||
178 | struct aiv_gk20a *alloc_aiv_list_gk20a(struct gk20a *g, | ||
179 | struct aiv_list_gk20a *aivl) | ||
180 | { | ||
181 | aivl->l = nvgpu_kzalloc(g, aivl->count * sizeof(*aivl->l)); | ||
182 | return aivl->l; | ||
183 | } | ||
184 | |||
185 | static inline | ||
186 | u32 *alloc_u32_list_gk20a(struct gk20a *g, struct u32_list_gk20a *u32l) | ||
187 | { | ||
188 | u32l->l = nvgpu_kzalloc(g, u32l->count * sizeof(*u32l->l)); | ||
189 | return u32l->l; | ||
190 | } | ||
191 | |||
192 | struct gr_ucode_gk20a { | ||
193 | struct { | ||
194 | struct u32_list_gk20a inst; | ||
195 | struct u32_list_gk20a data; | ||
196 | } gpccs, fecs; | ||
197 | }; | ||
198 | |||
199 | /* main entry for grctx loading */ | ||
200 | int gr_gk20a_init_ctx_vars(struct gk20a *g, struct gr_gk20a *gr); | ||
201 | int gr_gk20a_init_ctx_vars_sim(struct gk20a *g, struct gr_gk20a *gr); | ||
202 | |||
203 | struct gpu_ops; | ||
204 | void gk20a_init_gr_ctx(struct gpu_ops *gops); | ||
205 | |||
206 | #endif /*NVGPU_GK20A_GR_CTX_GK20A_H*/ | ||