Include nvgpu headers

These are needed to build on NVIDIA's Jetson boards for the time
being. Only a couple structs are required, so it should be fairly
easy to remove this dependency at some point in the future.

1 files changed, 471 insertions, 0 deletions

diff --git a/include/gk20a/fifo_gk20a.h b/include/gk20a/fifo_gk20a.h
new file mode 100644
index 0000000..26365ca
--- /dev/null
+++ b/include/gk20a/fifo_gk20a.h
@@ -0,0 +1,471 @@
+/*
+ * GK20A graphics fifo (gr host)
+ *
+ * Copyright (c) 2011-2018, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+#ifndef FIFO_GK20A_H
+#define FIFO_GK20A_H
+
+#include <nvgpu/kref.h>
+
+struct gk20a_debug_output;
+struct mmu_fault_info;
+struct nvgpu_semaphore;
+struct channel_gk20a;
+struct tsg_gk20a;
+
+enum {
+        NVGPU_FIFO_RUNLIST_INTERLEAVE_LEVEL_LOW = 0,
+        NVGPU_FIFO_RUNLIST_INTERLEAVE_LEVEL_MEDIUM,
+        NVGPU_FIFO_RUNLIST_INTERLEAVE_LEVEL_HIGH,
+        NVGPU_FIFO_RUNLIST_INTERLEAVE_NUM_LEVELS,
+};
+
+#define MAX_RUNLIST_BUFFERS             2
+
+#define FIFO_INVAL_ENGINE_ID            ((u32)~0)
+#define FIFO_INVAL_CHANNEL_ID           ((u32)~0)
+#define FIFO_INVAL_TSG_ID               ((u32)~0)
+#define FIFO_INVAL_RUNLIST_ID           ((u32)~0)
+
+#define ID_TYPE_CHANNEL                 0
+#define ID_TYPE_TSG                     1
+#define ID_TYPE_UNKNOWN                 ((u32)~0)
+
+#define RC_YES                          1
+#define RC_NO                           0
+
+#define GRFIFO_TIMEOUT_CHECK_PERIOD_US 100000
+
+#define RC_TYPE_NO_RC                   0
+#define RC_TYPE_MMU_FAULT               1
+#define RC_TYPE_PBDMA_FAULT             2
+#define RC_TYPE_GR_FAULT                3
+#define RC_TYPE_PREEMPT_TIMEOUT         4
+#define RC_TYPE_CTXSW_TIMEOUT           5
+#define RC_TYPE_RUNLIST_UPDATE_TIMEOUT  6
+#define RC_TYPE_FORCE_RESET             7
+#define RC_TYPE_SCHED_ERR               8
+
+#define NVGPU_FIFO_DEFAULT_TIMESLICE_TIMEOUT    128UL
+#define NVGPU_FIFO_DEFAULT_TIMESLICE_SCALE      3UL
+
+/*
+ * Number of entries in the kickoff latency buffer, used to calculate
+ * the profiling and histogram. This number is calculated to be statistically
+ * significative on a histogram on a 5% step
+ */
+#ifdef CONFIG_DEBUG_FS
+#define FIFO_PROFILING_ENTRIES  16384
+#endif
+
+#define RUNLIST_DISABLED                0
+#define RUNLIST_ENABLED                 1
+
+/* generally corresponds to the "pbdma" engine */
+
+struct fifo_runlist_info_gk20a {
+        unsigned long *active_channels;
+        unsigned long *active_tsgs;
+        /* Each engine has its own SW and HW runlist buffer.*/
+        struct nvgpu_mem mem[MAX_RUNLIST_BUFFERS];
+        u32  cur_buffer;
+        u32  total_entries;
+        u32  pbdma_bitmask;      /* pbdmas supported for this runlist*/
+        u32  eng_bitmask;        /* engines using this runlist */
+        u32  reset_eng_bitmask;  /* engines to be reset during recovery */
+        u32  count;              /* cached runlist_hw_submit parameter */
+        bool stopped;
+        bool support_tsg;
+        /* protect ch/tsg/runlist preempt & runlist update */
+        struct nvgpu_mutex runlist_lock;
+};
+
+enum {
+        ENGINE_GR_GK20A        = 0U,
+        ENGINE_GRCE_GK20A      = 1U,
+        ENGINE_ASYNC_CE_GK20A  = 2U,
+        ENGINE_INVAL_GK20A     = 3U,
+};
+
+struct fifo_pbdma_exception_info_gk20a {
+        u32 status_r; /* raw register value from hardware */
+        u32 id, next_id;
+        u32 chan_status_v; /* raw value from hardware */
+        bool id_is_chid, next_id_is_chid;
+        bool chsw_in_progress;
+};
+
+struct fifo_engine_exception_info_gk20a {
+        u32 status_r; /* raw register value from hardware */
+        u32 id, next_id;
+        u32 ctx_status_v; /* raw value from hardware */
+        bool id_is_chid, next_id_is_chid;
+        bool faulted, idle, ctxsw_in_progress;
+};
+
+struct fifo_engine_info_gk20a {
+        u32 engine_id;
+        u32 runlist_id;
+        u32 intr_mask;
+        u32 reset_mask;
+        u32 pbdma_id;
+        u32 inst_id;
+        u32 pri_base;
+        u32 fault_id;
+        u32 engine_enum;
+        struct fifo_pbdma_exception_info_gk20a pbdma_exception_info;
+        struct fifo_engine_exception_info_gk20a engine_exception_info;
+};
+
+enum {
+        PROFILE_IOCTL_ENTRY = 0U,
+        PROFILE_ENTRY,
+        PROFILE_JOB_TRACKING,
+        PROFILE_APPEND,
+        PROFILE_END,
+        PROFILE_IOCTL_EXIT,
+        PROFILE_MAX
+};
+
+struct fifo_profile_gk20a {
+        u64 timestamp[PROFILE_MAX];
+};
+
+struct fifo_gk20a {
+        struct gk20a *g;
+        unsigned int num_channels;
+        unsigned int runlist_entry_size;
+        unsigned int num_runlist_entries;
+
+        unsigned int num_pbdma;
+        u32 *pbdma_map;
+
+        struct fifo_engine_info_gk20a *engine_info;
+        u32 max_engines;
+        u32 num_engines;
+        u32 *active_engines_list;
+
+        struct fifo_runlist_info_gk20a *runlist_info;
+        u32 max_runlists;
+#ifdef CONFIG_DEBUG_FS
+        struct {
+                struct fifo_profile_gk20a *data;
+                nvgpu_atomic_t get;
+                bool enabled;
+                u64 *sorted;
+                struct nvgpu_ref ref;
+                struct nvgpu_mutex lock;
+        } profile;
+#endif
+        struct nvgpu_mem userd;
+        u32 userd_entry_size;
+
+        unsigned int used_channels;
+        struct channel_gk20a *channel;
+        /* zero-kref'd channels here */
+        struct nvgpu_list_node free_chs;
+        struct nvgpu_mutex free_chs_mutex;
+        struct nvgpu_mutex engines_reset_mutex;
+
+        struct tsg_gk20a *tsg;
+        struct nvgpu_mutex tsg_inuse_mutex;
+
+        void (*remove_support)(struct fifo_gk20a *);
+        bool sw_ready;
+        struct {
+                /* share info between isrs and non-isr code */
+                struct {
+                        struct nvgpu_mutex mutex;
+                } isr;
+                struct {
+                        u32 device_fatal_0;
+                        u32 channel_fatal_0;
+                        u32 restartable_0;
+                } pbdma;
+                struct {
+
+                } engine;
+
+
+        } intr;
+
+        unsigned long deferred_fault_engines;
+        bool deferred_reset_pending;
+        struct nvgpu_mutex deferred_reset_mutex;
+
+        u32 max_subctx_count;
+        u32 channel_base;
+};
+
+struct ch_state {