diff options
author | Joshua Bakita <bakitajoshua@gmail.com> | 2023-06-28 18:24:25 -0400 |
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committer | Joshua Bakita <bakitajoshua@gmail.com> | 2023-06-28 18:24:25 -0400 |
commit | 01e6fac4d61fdd7fff5433942ec93fc2ea1e4df1 (patch) | |
tree | 4ef34501728a087be24f4ba0af90f91486bf780b /include/gk20a/clk_gk20a.h | |
parent | 306a03d18b305e4e573be3b2931978fa10679eb9 (diff) |
Include nvgpu headers
These are needed to build on NVIDIA's Jetson boards for the time
being. Only a couple structs are required, so it should be fairly
easy to remove this dependency at some point in the future.
Diffstat (limited to 'include/gk20a/clk_gk20a.h')
-rw-r--r-- | include/gk20a/clk_gk20a.h | 134 |
1 files changed, 134 insertions, 0 deletions
diff --git a/include/gk20a/clk_gk20a.h b/include/gk20a/clk_gk20a.h new file mode 100644 index 0000000..b8ec942 --- /dev/null +++ b/include/gk20a/clk_gk20a.h | |||
@@ -0,0 +1,134 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2011 - 2019, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
5 | * copy of this software and associated documentation files (the "Software"), | ||
6 | * to deal in the Software without restriction, including without limitation | ||
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
8 | * and/or sell copies of the Software, and to permit persons to whom the | ||
9 | * Software is furnished to do so, subject to the following conditions: | ||
10 | * | ||
11 | * The above copyright notice and this permission notice shall be included in | ||
12 | * all copies or substantial portions of the Software. | ||
13 | * | ||
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
17 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
18 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
19 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
20 | * DEALINGS IN THE SOFTWARE. | ||
21 | */ | ||
22 | #ifndef CLK_GK20A_H | ||
23 | #define CLK_GK20A_H | ||
24 | |||
25 | #include <nvgpu/lock.h> | ||
26 | |||
27 | #if defined(CONFIG_COMMON_CLK) | ||
28 | #include <linux/clk-provider.h> | ||
29 | #endif | ||
30 | |||
31 | #define GPUFREQ_TABLE_END ~(u32)1 | ||
32 | enum { | ||
33 | /* only one PLL for gk20a */ | ||
34 | GK20A_GPC_PLL = 0, | ||
35 | /* 2 PLL revisions for gm20b */ | ||
36 | GM20B_GPC_PLL_B1, | ||
37 | GM20B_GPC_PLL_C1, | ||
38 | }; | ||
39 | |||
40 | enum gpc_pll_mode { | ||
41 | GPC_PLL_MODE_F = 0, /* fixed frequency mode a.k.a legacy mode */ | ||
42 | GPC_PLL_MODE_DVFS, /* DVFS mode a.k.a NA mode */ | ||
43 | }; | ||
44 | |||
45 | struct na_dvfs { | ||
46 | u32 n_int; | ||
47 | u32 sdm_din; | ||
48 | int dfs_coeff; | ||
49 | int dfs_det_max; | ||
50 | int dfs_ext_cal; | ||
51 | int uv_cal; | ||
52 | int mv; | ||
53 | }; | ||
54 | |||
55 | struct pll { | ||
56 | u32 id; | ||
57 | u32 clk_in; /* KHz */ | ||
58 | u32 M; | ||
59 | u32 N; | ||
60 | u32 PL; | ||
61 | u32 freq; /* KHz */ | ||
62 | bool enabled; | ||
63 | enum gpc_pll_mode mode; | ||
64 | struct na_dvfs dvfs; | ||
65 | }; | ||
66 | |||
67 | struct pll_parms { | ||
68 | u32 min_freq, max_freq; /* KHz */ | ||
69 | u32 min_vco, max_vco; /* KHz */ | ||
70 | u32 min_u, max_u; /* KHz */ | ||
71 | u32 min_M, max_M; | ||
72 | u32 min_N, max_N; | ||
73 | u32 min_PL, max_PL; | ||
74 | /* NA mode parameters*/ | ||
75 | int coeff_slope, coeff_offs; /* coeff = slope * V + offs */ | ||
76 | int uvdet_slope, uvdet_offs; /* uV = slope * det + offs */ | ||
77 | u32 vco_ctrl; | ||
78 | /* | ||
79 | * Timing parameters in us. Lock timeout is applied to locking in fixed | ||
80 | * frequency mode and to dynamic ramp in any mode; does not affect lock | ||
81 | * latency, since lock/ramp done status bit is polled. NA mode lock and | ||
82 | * and IDDQ exit delays set the time of the respective opertaions with | ||
83 | * no status polling. | ||
84 | */ | ||
85 | u32 lock_timeout; | ||
86 | u32 na_lock_delay; | ||
87 | u32 iddq_exit_delay; | ||
88 | /* NA mode DFS control */ | ||
89 | u32 dfs_ctrl; | ||
90 | }; | ||
91 | |||
92 | struct namemap_cfg; | ||
93 | |||
94 | struct clk_gk20a { | ||
95 | struct gk20a *g; | ||
96 | #if defined(CONFIG_COMMON_CLK) | ||
97 | struct clk *tegra_clk; | ||
98 | struct clk *tegra_clk_parent; | ||
99 | struct clk_hw hw; | ||
100 | #endif | ||
101 | struct pll gpc_pll; | ||
102 | struct pll gpc_pll_last; | ||
103 | struct nvgpu_mutex clk_mutex; | ||
104 | struct namemap_cfg *clk_namemap; | ||
105 | u32 namemap_num; | ||
106 | u32 *namemap_xlat_table; | ||
107 | bool sw_ready; | ||
108 | bool clk_hw_on; | ||
109 | bool debugfs_set; | ||
110 | int pll_poweron_uv; | ||
111 | unsigned long dvfs_safe_max_freq; | ||
112 | }; | ||
113 | |||
114 | #if defined(CONFIG_COMMON_CLK) | ||
115 | #define to_clk_gk20a(_hw) container_of(_hw, struct clk_gk20a, hw) | ||
116 | #endif | ||
117 | |||
118 | struct gpu_ops; | ||
119 | |||
120 | #define KHZ 1000 | ||
121 | #define MHZ 1000000 | ||
122 | |||
123 | static inline unsigned long rate_gpc2clk_to_gpu(unsigned long rate) | ||
124 | { | ||
125 | /* convert the kHz gpc2clk frequency to Hz gpcpll frequency */ | ||
126 | return (rate * KHZ) / 2; | ||
127 | } | ||
128 | static inline unsigned long rate_gpu_to_gpc2clk(unsigned long rate) | ||
129 | { | ||
130 | /* convert the Hz gpcpll frequency to kHz gpc2clk frequency */ | ||
131 | return (rate * 2) / KHZ; | ||
132 | } | ||
133 | |||
134 | #endif /* CLK_GK20A_H */ | ||