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authorJoshua Bakita <bakitajoshua@gmail.com>2023-06-28 18:24:25 -0400
committerJoshua Bakita <bakitajoshua@gmail.com>2023-06-28 18:24:25 -0400
commit01e6fac4d61fdd7fff5433942ec93fc2ea1e4df1 (patch)
tree4ef34501728a087be24f4ba0af90f91486bf780b /include/clk
parent306a03d18b305e4e573be3b2931978fa10679eb9 (diff)
Include nvgpu headers
These are needed to build on NVIDIA's Jetson boards for the time being. Only a couple structs are required, so it should be fairly easy to remove this dependency at some point in the future.
Diffstat (limited to 'include/clk')
-rw-r--r--include/clk/clk.c942
-rw-r--r--include/clk/clk.h144
-rw-r--r--include/clk/clk_arb.c1087
-rw-r--r--include/clk/clk_domain.c1666
-rw-r--r--include/clk/clk_domain.h157
-rw-r--r--include/clk/clk_fll.c495
-rw-r--r--include/clk/clk_fll.h81
-rw-r--r--include/clk/clk_freq_controller.c462
-rw-r--r--include/clk/clk_freq_controller.h84
-rw-r--r--include/clk/clk_mclk.h60
-rw-r--r--include/clk/clk_prog.c1152
-rw-r--r--include/clk/clk_prog.h100
-rw-r--r--include/clk/clk_vf_point.c433
-rw-r--r--include/clk/clk_vf_point.h83
-rw-r--r--include/clk/clk_vin.c573
-rw-r--r--include/clk/clk_vin.h79
16 files changed, 7598 insertions, 0 deletions
diff --git a/include/clk/clk.c b/include/clk/clk.c
new file mode 100644
index 0000000..d8e30c4
--- /dev/null
+++ b/include/clk/clk.c
@@ -0,0 +1,942 @@
1/*
2 * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21 */
22
23#include <nvgpu/pmu.h>
24#include <nvgpu/pmuif/nvgpu_gpmu_cmdif.h>
25#include <nvgpu/gk20a.h>
26
27#include "clk.h"
28#include "ctrl/ctrlclk.h"
29#include "ctrl/ctrlvolt.h"
30#include "volt/volt.h"
31
32#define BOOT_GPC2CLK_MHZ 2581
33#define BOOT_MCLK_MHZ 3003
34
35struct clkrpc_pmucmdhandler_params {
36 struct nv_pmu_clk_rpc *prpccall;
37 u32 success;
38};
39
40static void clkrpc_pmucmdhandler(struct gk20a *g, struct pmu_msg *msg,
41 void *param, u32 handle, u32 status)
42{
43 struct clkrpc_pmucmdhandler_params *phandlerparams =
44 (struct clkrpc_pmucmdhandler_params *)param;
45
46 nvgpu_log_info(g, " ");
47
48 if (msg->msg.clk.msg_type != NV_PMU_CLK_MSG_ID_RPC) {
49 nvgpu_err(g, "unsupported msg for VFE LOAD RPC %x",
50 msg->msg.clk.msg_type);
51 return;
52 }
53
54 if (phandlerparams->prpccall->b_supported) {
55 phandlerparams->success = 1;
56 }
57}
58
59
60int clk_pmu_freq_effective_avg_load(struct gk20a *g, bool bload)
61{
62 struct pmu_cmd cmd;
63 struct pmu_payload payload;
64 u32 status;
65 u32 seqdesc;
66 struct nv_pmu_clk_rpc rpccall;
67 struct clkrpc_pmucmdhandler_params handler;
68 struct nv_pmu_clk_load *clkload;
69
70 memset(&payload, 0, sizeof(struct pmu_payload));
71 memset(&rpccall, 0, sizeof(struct nv_pmu_clk_rpc));
72 memset(&handler, 0, sizeof(struct clkrpc_pmucmdhandler_params));
73 memset(&cmd, 0, sizeof(struct pmu_cmd));
74
75 rpccall.function = NV_PMU_CLK_RPC_ID_LOAD;
76 clkload = &rpccall.params.clk_load;
77 clkload->feature = NV_NV_PMU_CLK_LOAD_FEATURE_FREQ_EFFECTIVE_AVG;
78 clkload->action_mask = bload ?
79 NV_NV_PMU_CLK_LOAD_ACTION_MASK_FREQ_EFFECTIVE_AVG_CALLBACK_YES :
80 NV_NV_PMU_CLK_LOAD_ACTION_MASK_FREQ_EFFECTIVE_AVG_CALLBACK_NO;
81
82 cmd.hdr.unit_id = PMU_UNIT_CLK;
83 cmd.hdr.size = (u32)sizeof(struct nv_pmu_clk_cmd) +
84 (u32)sizeof(struct pmu_hdr);
85
86 cmd.cmd.clk.cmd_type = NV_PMU_CLK_CMD_ID_RPC;
87
88 payload.in.buf = (u8 *)&rpccall;
89 payload.in.size = (u32)sizeof(struct nv_pmu_clk_rpc);
90 payload.in.fb_size = PMU_CMD_SUBMIT_PAYLOAD_PARAMS_FB_SIZE_UNUSED;
91 payload.in.offset = NV_PMU_CLK_CMD_RPC_ALLOC_OFFSET;
92
93 payload.out.buf = (u8 *)&rpccall;
94 payload.out.size = (u32)sizeof(struct nv_pmu_clk_rpc);
95 payload.out.fb_size = PMU_CMD_SUBMIT_PAYLOAD_PARAMS_FB_SIZE_UNUSED;
96 payload.out.offset = NV_PMU_CLK_MSG_RPC_ALLOC_OFFSET;
97
98 handler.prpccall = &rpccall;
99 handler.success = 0;
100
101 status = nvgpu_pmu_cmd_post(g, &cmd, NULL, &payload,
102 PMU_COMMAND_QUEUE_LPQ,
103 clkrpc_pmucmdhandler, (void *)&handler,
104 &seqdesc, ~0);
105 if (status) {
106 nvgpu_err(g, "unable to post clk RPC cmd %x",
107 cmd.cmd.clk.cmd_type);
108 goto done;
109 }
110
111 pmu_wait_message_cond(&g->pmu,
112 gk20a_get_gr_idle_timeout(g),
113 &handler.success, 1);
114 if (handler.success == 0) {
115 nvgpu_err(g, "rpc call to load Effective avg clk domain freq failed");
116 status = -EINVAL;
117 }
118
119done:
120 return status;
121}
122
123u32 clk_freq_effective_avg(struct gk20a *g, u32 clkDomainMask) {
124
125 struct pmu_cmd cmd;
126 struct pmu_payload payload;
127 u32 status;
128 u32 seqdesc;
129 struct nv_pmu_clk_rpc rpccall;
130 struct clkrpc_pmucmdhandler_params handler;
131 struct nv_pmu_clk_freq_effective_avg *clk_freq_effective_avg;
132
133 memset(&payload, 0, sizeof(struct pmu_payload));
134 memset(&rpccall, 0, sizeof(struct nv_pmu_clk_rpc));
135 memset(&handler, 0, sizeof(struct clkrpc_pmucmdhandler_params));
136 memset(&cmd, 0, sizeof(struct pmu_cmd));
137
138 rpccall.function = NV_PMU_CLK_RPC_ID_CLK_FREQ_EFF_AVG;
139 clk_freq_effective_avg = &rpccall.params.clk_freq_effective_avg;
140 clk_freq_effective_avg->clkDomainMask = clkDomainMask;
141
142 cmd.hdr.unit_id = PMU_UNIT_CLK;
143 cmd.hdr.size = (u32)sizeof(struct nv_pmu_clk_cmd) +
144 (u32)sizeof(struct pmu_hdr);
145
146 cmd.cmd.clk.cmd_type = NV_PMU_CLK_CMD_ID_RPC;
147
148 payload.in.buf = (u8 *)&rpccall;
149 payload.in.size = (u32)sizeof(struct nv_pmu_clk_rpc);
150 payload.in.fb_size = PMU_CMD_SUBMIT_PAYLOAD_PARAMS_FB_SIZE_UNUSED;
151 payload.in.offset = NV_PMU_CLK_CMD_RPC_ALLOC_OFFSET;
152
153 payload.out.buf = (u8 *)&rpccall;
154 payload.out.size = (u32)sizeof(struct nv_pmu_clk_rpc);
155 payload.out.fb_size = PMU_CMD_SUBMIT_PAYLOAD_PARAMS_FB_SIZE_UNUSED;
156 payload.out.offset = NV_PMU_CLK_MSG_RPC_ALLOC_OFFSET;
157
158 handler.prpccall = &rpccall;
159 handler.success = 0;
160
161 status = nvgpu_pmu_cmd_post(g, &cmd, NULL, &payload,
162 PMU_COMMAND_QUEUE_LPQ,
163 clkrpc_pmucmdhandler, (void *)&handler,
164 &seqdesc, ~0);
165 if (status) {
166 nvgpu_err(g, "unable to post clk RPC cmd %x",
167 cmd.cmd.clk.cmd_type);
168 goto done;
169 }
170
171 pmu_wait_message_cond(&g->pmu,
172 gk20a_get_gr_idle_timeout(g),
173 &handler.success, 1);
174 if (handler.success == 0) {
175 nvgpu_err(g, "rpc call to get clk frequency average failed");
176 status = -EINVAL;
177 goto done;
178 }
179
180 return rpccall.params.clk_freq_effective_avg.freqkHz[clkDomainMask];
181
182done:
183 return status;
184}
185
186int clk_pmu_freq_controller_load(struct gk20a *g, bool bload, u8 bit_idx)
187{
188 struct pmu_cmd cmd;
189 struct pmu_payload payload;
190 u32 status;
191 u32 seqdesc;
192 struct nv_pmu_clk_rpc rpccall;
193 struct clkrpc_pmucmdhandler_params handler;
194 struct nv_pmu_clk_load *clkload;
195 struct clk_freq_controllers *pclk_freq_controllers;
196 struct ctrl_boardobjgrp_mask_e32 *load_mask;
197 struct boardobjgrpmask_e32 isolate_cfc_mask;