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authorJoshua Bakita <bakitajoshua@gmail.com>2023-06-28 18:24:25 -0400
committerJoshua Bakita <bakitajoshua@gmail.com>2023-06-28 18:24:25 -0400
commit01e6fac4d61fdd7fff5433942ec93fc2ea1e4df1 (patch)
tree4ef34501728a087be24f4ba0af90f91486bf780b /include/clk/clk_vin.c
parent306a03d18b305e4e573be3b2931978fa10679eb9 (diff)
Include nvgpu headers
These are needed to build on NVIDIA's Jetson boards for the time being. Only a couple structs are required, so it should be fairly easy to remove this dependency at some point in the future.
Diffstat (limited to 'include/clk/clk_vin.c')
-rw-r--r--include/clk/clk_vin.c573
1 files changed, 573 insertions, 0 deletions
diff --git a/include/clk/clk_vin.c b/include/clk/clk_vin.c
new file mode 100644
index 0000000..e0a4a5b
--- /dev/null
+++ b/include/clk/clk_vin.c
@@ -0,0 +1,573 @@
1/*
2 * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21 */
22
23#include <nvgpu/bios.h>
24#include <nvgpu/pmuif/nvgpu_gpmu_cmdif.h>
25#include <nvgpu/io.h>
26#include <nvgpu/gk20a.h>
27
28#include "boardobj/boardobjgrp.h"
29#include "boardobj/boardobjgrp_e32.h"
30
31#include "ctrl/ctrlvolt.h"
32
33#include "gp106/bios_gp106.h"
34
35#include "clk.h"
36#include "clk_vin.h"
37
38static int devinit_get_vin_device_table(struct gk20a *g,
39 struct avfsvinobjs *pvinobjs);
40
41static int vin_device_construct_v10(struct gk20a *g,
42 struct boardobj **ppboardobj,
43 u16 size, void *pargs);
44static int vin_device_construct_v20(struct gk20a *g,
45 struct boardobj **ppboardobj,
46 u16 size, void *pargs);
47static int vin_device_construct_super(struct gk20a *g,
48 struct boardobj **ppboardobj,
49 u16 size, void *pargs);
50static struct vin_device *construct_vin_device(struct gk20a *g, void *pargs);
51
52static int vin_device_init_pmudata_v10(struct gk20a *g,
53 struct boardobj *board_obj_ptr,
54 struct nv_pmu_boardobj *ppmudata);
55static int vin_device_init_pmudata_v20(struct gk20a *g,
56 struct boardobj *board_obj_ptr,
57 struct nv_pmu_boardobj *ppmudata);
58static int vin_device_init_pmudata_super(struct gk20a *g,
59 struct boardobj *board_obj_ptr,
60 struct nv_pmu_boardobj *ppmudata);
61
62u32 clk_avfs_get_vin_cal_fuse_v10(struct gk20a *g,
63 struct avfsvinobjs *pvinobjs,
64 struct vin_device_v20 *pvindev)
65{
66 u32 status = 0;
67 u32 slope, intercept;
68 u8 i;
69
70 if (pvinobjs->calibration_rev_vbios == g->ops.fuse.read_vin_cal_fuse_rev(g)) {
71 BOARDOBJGRP_FOR_EACH(&(pvinobjs->super.super),
72 struct vin_device_v20 *, pvindev, i) {
73 slope = 0;
74 intercept = 0;
75 pvindev = (struct vin_device_v20 *)CLK_GET_VIN_DEVICE(pvinobjs, i);
76 status = g->ops.fuse.read_vin_cal_slope_intercept_fuse(g,
77 pvindev->super.id, &slope, &intercept);
78 if (status) {
79 nvgpu_err(g,
80 "err reading vin cal for id %x", pvindev->super.id);
81 return status;
82 }
83 pvindev->data.vin_cal.cal_v10.slope = slope;
84 pvindev->data.vin_cal.cal_v10.intercept = intercept;
85 }
86 }
87 return status;
88
89}
90
91u32 clk_avfs_get_vin_cal_fuse_v20(struct gk20a *g,
92 struct avfsvinobjs *pvinobjs,
93 struct vin_device_v20 *pvindev)
94{
95 u32 status = 0;
96 s8 gain, offset;
97 u8 i;
98
99 if (pvinobjs->calibration_rev_vbios == g->ops.fuse.read_vin_cal_fuse_rev(g)) {
100 BOARDOBJGRP_FOR_EACH(&(pvinobjs->super.super),
101 struct vin_device_v20 *, pvindev, i) {
102 gain = '\0';
103 offset = '\0';
104 pvindev = (struct vin_device_v20 *)CLK_GET_VIN_DEVICE(pvinobjs, i);
105 status = g->ops.fuse.read_vin_cal_gain_offset_fuse(g,
106 pvindev->super.id, &gain, &offset);
107 if (status) {
108 nvgpu_err(g,
109 "err reading vin cal for id %x", pvindev->super.id);
110 return status;
111 }
112 pvindev->data.vin_cal.cal_v20.gain = gain;
113 pvindev->data.vin_cal.cal_v20.offset = offset;
114 }
115 }
116 return status;
117
118}
119
120static int _clk_vin_devgrp_pmudatainit_super(struct gk20a *g,
121 struct boardobjgrp *pboardobjgrp,
122 struct nv_pmu_boardobjgrp_super *pboardobjgrppmu)
123{
124 struct nv_pmu_clk_clk_vin_device_boardobjgrp_set_header *pset =
125 (struct nv_pmu_clk_clk_vin_device_boardobjgrp_set_header *)
126 pboardobjgrppmu;
127 struct avfsvinobjs *pvin_obbj = (struct avfsvinobjs *)pboardobjgrp;
128 int status = 0;
129
130 nvgpu_log_info(g, " ");
131
132 status = boardobjgrp_pmudatainit_e32(g, pboardobjgrp, pboardobjgrppmu);
133
134 pset->b_vin_is_disable_allowed = pvin_obbj->vin_is_disable_allowed;
135
136 nvgpu_log_info(g, " Done");
137 return status;
138}
139
140static int _clk_vin_devgrp_pmudata_instget(struct gk20a *g,
141 struct nv_pmu_boardobjgrp *pmuboardobjgrp,
142 struct nv_pmu_boardobj **ppboardobjpmudata,
143 u8 idx)
144{
145 struct nv_pmu_clk_clk_vin_device_boardobj_grp_set *pgrp_set =
146 (struct nv_pmu_clk_clk_vin_device_boardobj_grp_set *)
147 pmuboardobjgrp;
148
149 nvgpu_log_info(g, " ");
150
151 /*check whether pmuboardobjgrp has a valid boardobj in index*/
152 if (((u32)BIT(idx) &
153 pgrp_set->hdr.data.super.obj_mask.super.data[0]) == 0) {
154 return -EINVAL;
155 }
156
157 *ppboardobjpmudata = (struct nv_pmu_boardobj *)
158 &pgrp_set->objects[idx].data.board_obj;
159 nvgpu_log_info(g, " Done");
160 return 0;
161}
162
163static int _clk_vin_devgrp_pmustatus_instget(struct gk20a *g,
164 void *pboardobjgrppmu,
165 struct nv_pmu_boardobj_query **ppboardobjpmustatus,
166 u8 idx)
167{
168 struct nv_pmu_clk_clk_vin_device_boardobj_grp_get_status *pgrp_get_status =
169 (struct nv_pmu_clk_clk_vin_device_boardobj_grp_get_status *)
170 pboardobjgrppmu;
171
172 /*check whether pmuboardobjgrp has a valid boardobj in index*/
173 if (((u32)BIT(idx) &
174 pgrp_get_status->hdr.data.super.obj_mask.super.data[0]) == 0) {
175 return -EINVAL;
176 }
177
178 *ppboardobjpmustatus = (struct nv_pmu_boardobj_query *)
179 &pgrp_get_status->objects[idx].data.board_obj;
180 return 0;
181}
182
183int clk_vin_sw_setup(struct gk20a *g)
184{
185 int status;
186 struct boardobjgrp *pboardobjgrp = NULL;
187 struct vin_device_v20 *pvindev = NULL;
188 struct avfsvinobjs *pvinobjs;
189
190 nvgpu_log_info(g, " ");
191
192 status = boardobjgrpconstruct_e32(g, &g->clk_pmu.avfs_vinobjs.super);
193 if (status) {
194 nvgpu_err(g,
195 "error creating boardobjgrp for clk vin, statu - 0x%x",
196 status);
197 goto done;
198 }
199
200 pboardobjgrp = &g->clk_pmu.avfs_vinobjs.super.super;
201 pvinobjs = &g->clk_pmu.avfs_vinobjs;
202
203 BOARDOBJGRP_PMU_CONSTRUCT(pboardobjgrp, CLK, VIN_DEVICE);
204
205 status = BOARDOBJGRP_PMU_CMD_GRP_SET_CONSTRUCT(g, pboardobjgrp,
206 clk, CLK, clk_vin_device, CLK_VIN_DEVICE);
207 if (status) {
208 nvgpu_err(g,
209 "error constructing PMU_BOARDOBJ_CMD_GRP_SET interface - 0x%x",
210 status);
211 goto done;
212 }
213
214 pboardobjgrp->pmudatainit = _clk_vin_devgrp_pmudatainit_super;
215 pboardobjgrp->pmudatainstget = _clk_vin_devgrp_pmudata_instget;