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authorJoshua Bakita <bakitajoshua@gmail.com>2023-06-28 18:24:25 -0400
committerJoshua Bakita <bakitajoshua@gmail.com>2023-06-28 18:24:25 -0400
commit01e6fac4d61fdd7fff5433942ec93fc2ea1e4df1 (patch)
tree4ef34501728a087be24f4ba0af90f91486bf780b /include/clk/clk_domain.c
parent306a03d18b305e4e573be3b2931978fa10679eb9 (diff)
Include nvgpu headers
These are needed to build on NVIDIA's Jetson boards for the time being. Only a couple structs are required, so it should be fairly easy to remove this dependency at some point in the future.
Diffstat (limited to 'include/clk/clk_domain.c')
-rw-r--r--include/clk/clk_domain.c1666
1 files changed, 1666 insertions, 0 deletions
diff --git a/include/clk/clk_domain.c b/include/clk/clk_domain.c
new file mode 100644
index 0000000..3b64f51
--- /dev/null
+++ b/include/clk/clk_domain.c
@@ -0,0 +1,1666 @@
1/*
2 * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21 */
22
23#include <nvgpu/bios.h>
24#include <nvgpu/gk20a.h>
25
26#include "clk.h"
27#include "clk_fll.h"
28#include "clk_domain.h"
29#include "boardobj/boardobjgrp.h"
30#include "boardobj/boardobjgrp_e32.h"
31#include "ctrl/ctrlclk.h"
32#include "ctrl/ctrlvolt.h"
33
34static struct clk_domain *construct_clk_domain(struct gk20a *g, void *pargs);
35
36static int devinit_get_clocks_table(struct gk20a *g,
37 struct clk_domains *pdomainobjs);
38
39static int clk_domain_pmudatainit_super(struct gk20a *g, struct boardobj
40 *board_obj_ptr, struct nv_pmu_boardobj *ppmudata);
41
42static struct vbios_clocks_table_1x_hal_clock_entry
43 vbiosclktbl1xhalentry_gp[] = {
44 { clkwhich_gpc2clk, true, 1, },
45 { clkwhich_xbar2clk, true, 1, },
46 { clkwhich_mclk, false, 1, },
47 { clkwhich_sys2clk, true, 1, },
48 { clkwhich_hub2clk, false, 1, },
49 { clkwhich_nvdclk, false, 1, },
50 { clkwhich_pwrclk, false, 1, },
51 { clkwhich_dispclk, false, 1, },
52 { clkwhich_pciegenclk, false, 1, }
53};
54/*
55 * Updated from RM devinit_clock.c
56 * GV100 is 0x03 and
57 * GP10x is 0x02 in clocks_hal.
58 */
59static struct vbios_clocks_table_1x_hal_clock_entry
60 vbiosclktbl1xhalentry_gv[] = {
61 { clkwhich_gpcclk, true, 2, },
62 { clkwhich_xbarclk, true, 1, },
63 { clkwhich_mclk, false, 1, },
64 { clkwhich_sysclk, true, 1, },
65 { clkwhich_hubclk, false, 1, },
66 { clkwhich_nvdclk, true, 1, },
67 { clkwhich_pwrclk, false, 1, },
68 { clkwhich_dispclk, false, 1, },
69 { clkwhich_pciegenclk, false, 1, },
70 { clkwhich_hostclk, true, 1, }
71};
72
73static u32 clktranslatehalmumsettoapinumset(u32 clkhaldomains)
74{
75 u32 clkapidomains = 0;
76
77 if (clkhaldomains & BIT(clkwhich_gpcclk)) {
78 clkapidomains |= CTRL_CLK_DOMAIN_GPCCLK;
79 }
80 if (clkhaldomains & BIT(clkwhich_xbarclk)) {
81 clkapidomains |= CTRL_CLK_DOMAIN_XBARCLK;
82 }
83 if (clkhaldomains & BIT(clkwhich_sysclk)) {
84 clkapidomains |= CTRL_CLK_DOMAIN_SYSCLK;
85 }
86 if (clkhaldomains & BIT(clkwhich_hubclk)) {
87 clkapidomains |= CTRL_CLK_DOMAIN_HUBCLK;
88 }
89 if (clkhaldomains & BIT(clkwhich_hostclk)) {
90 clkapidomains |= CTRL_CLK_DOMAIN_HOSTCLK;
91 }
92 if (clkhaldomains & BIT(clkwhich_gpc2clk)) {
93 clkapidomains |= CTRL_CLK_DOMAIN_GPC2CLK;
94 }
95 if (clkhaldomains & BIT(clkwhich_xbar2clk)) {
96 clkapidomains |= CTRL_CLK_DOMAIN_XBAR2CLK;
97 }
98 if (clkhaldomains & BIT(clkwhich_sys2clk)) {
99 clkapidomains |= CTRL_CLK_DOMAIN_SYS2CLK;
100 }
101 if (clkhaldomains & BIT(clkwhich_hub2clk)) {
102 clkapidomains |= CTRL_CLK_DOMAIN_HUB2CLK;
103 }
104 if (clkhaldomains & BIT(clkwhich_pwrclk)) {
105 clkapidomains |= CTRL_CLK_DOMAIN_PWRCLK;
106 }
107 if (clkhaldomains & BIT(clkwhich_pciegenclk)) {
108 clkapidomains |= CTRL_CLK_DOMAIN_PCIEGENCLK;
109 }
110 if (clkhaldomains & BIT(clkwhich_mclk)) {
111 clkapidomains |= CTRL_CLK_DOMAIN_MCLK;
112 }
113 if (clkhaldomains & BIT(clkwhich_nvdclk)) {
114 clkapidomains |= CTRL_CLK_DOMAIN_NVDCLK;
115 }
116 if (clkhaldomains & BIT(clkwhich_dispclk)) {
117 clkapidomains |= CTRL_CLK_DOMAIN_DISPCLK;
118 }
119
120 return clkapidomains;
121}
122
123static int _clk_domains_pmudatainit_3x(struct gk20a *g,
124 struct boardobjgrp *pboardobjgrp,
125 struct nv_pmu_boardobjgrp_super *pboardobjgrppmu)
126{
127 struct nv_pmu_clk_clk_domain_boardobjgrp_set_header *pset =
128 (struct nv_pmu_clk_clk_domain_boardobjgrp_set_header *)
129 pboardobjgrppmu;
130 struct clk_domains *pdomains = (struct clk_domains *)pboardobjgrp;
131 int status = 0;
132
133 status = boardobjgrp_pmudatainit_e32(g, pboardobjgrp, pboardobjgrppmu);
134 if (status) {
135 nvgpu_err(g,
136 "error updating pmu boardobjgrp for clk domain 0x%x",
137 status);
138 goto done;
139 }
140
141 pset->vbios_domains = pdomains->vbios_domains;
142 pset->cntr_sampling_periodms = pdomains->cntr_sampling_periodms;
143 pset->version = CLK_DOMAIN_BOARDOBJGRP_VERSION;
144 pset->b_override_o_v_o_c = false;
145 pset->b_debug_mode = false;
146 pset->b_enforce_vf_monotonicity = pdomains->b_enforce_vf_monotonicity;
147 pset->b_enforce_vf_smoothening = pdomains->b_enforce_vf_smoothening;
148 if (g->ops.clk.split_rail_support) {
149 pset->volt_rails_max = 2;
150 } else {
151 pset->volt_rails_max = 1;
152 }
153 status = boardobjgrpmask_export(
154 &pdomains->master_domains_mask.super,
155 pdomains->master_domains_mask.super.bitcount,
156 &pset->master_domains_mask.super);
157
158 memcpy(&pset->deltas, &pdomains->deltas,
159 (sizeof(struct ctrl_clk_clk_delta)));
160
161done:
162 return status;
163}
164
165static int _clk_domains_pmudata_instget(struct gk20a *g,
166 struct nv_pmu_boardobjgrp *pmuboardobjgrp,
167 struct nv_pmu_boardobj **ppboardobjpmudata,
168 u8 idx)
169{
170 struct nv_pmu_clk_clk_domain_boardobj_grp_set *pgrp_set =
171 (struct nv_pmu_clk_clk_domain_boardobj_grp_set *)
172 pmuboardobjgrp;
173
174 nvgpu_log_info(g, " ");
175
176 /*check whether pmuboardobjgrp has a valid boardobj in index*/
177 if (((u32)BIT(idx) &
178 pgrp_set->hdr.data.super.obj_mask.super.data[0]) == 0) {
179 return -EINVAL;
180 }
181
182 *ppboardobjpmudata = (struct nv_pmu_boardobj *)
183 &pgrp_set->objects[idx].data.board_obj;
184 nvgpu_log_info(g, " Done");
185 return 0;
186}
187
188int clk_domain_sw_setup(struct gk20a *g)
189{
190 int status;
191 struct boardobjgrp *pboardobjgrp = NULL;
192 struct clk_domains *pclkdomainobjs;
193 struct clk_domain *pdomain;
194 struct clk_domain_3x_master *pdomain_master;
195 struct clk_domain_3x_slave *pdomain_slave;
196 u8 i;
197
198 nvgpu_log_info(g, " ");
199
200 status = boardobjgrpconstruct_e32(g, &g->clk_pmu.clk_domainobjs.super);
201 if (status) {
202 nvgpu_err(g,
203 "error creating boardobjgrp for clk domain, status - 0x%x",
204 status);
205 goto done;
206 }
207
208 pboardobjgrp = &g->clk_pmu.clk_domainobjs.super.super;
209 pclkdomainobjs = &(g->clk_pmu.clk_domainobjs);
210
211 BOARDOBJGRP_PMU_CONSTRUCT(pboardobjgrp, CLK, CLK_DOMAIN);
212
213 status = BOARDOBJGRP_PMU_CMD_GRP_SET_CONSTRUCT(g, pboardobjgrp,
214 clk, CLK, clk_domain, CLK_DOMAIN);
215 if (status) {
<