/*
* Copyright (c) 2012-2018, NVIDIA Corporation.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
/*
* Function naming determines intended use:
*
* <x>_r(void) : Returns the offset for register <x>.
*
* <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
*
* <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
*
* <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
* and masked to place it at field <y> of register <x>. This value
* can be |'d with others to produce a full register value for
* register <x>.
*
* <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
* value can be ~'d and then &'d to clear the value of field <y> for
* register <x>.
*
* <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
* to place it at field <y> of register <x>. This value can be |'d
* with others to produce a full register value for <x>.
*
* <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
* <x> value 'r' after being shifted to place its LSB at bit 0.
* This value is suitable for direct comparison with other unshifted
* values appropriate for use in field <y> of register <x>.
*
* <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
* field <y> of register <x>. This value is suitable for direct
* comparison with unshifted values appropriate for use in field <y>
* of register <x>.
*/
#ifndef __hw_sim_pci_h__
#define __hw_sim_pci_h__
/*This file is autogenerated. Do not edit. */
static inline u32 sim_r(void)
{
return 0x0008f000U;
}
static inline u32 sim_send_ring_r(void)
{
return 0x00000000U;
}
static inline u32 sim_send_ring_target_s(void)
{
return 2U;
}
static inline u32 sim_send_ring_target_f(u32 v)
{
return (v & 0x3U) << 0U;
}
static inline u32 sim_send_ring_target_m(void)
{
return 0x3U << 0U;
}
static inline u32 sim_send_ring_target_v(u32 r)
{
return (r >> 0U) & 0x3U;
}
static inline u32 sim_send_ring_target_phys_init_v(void)
{
return 0x00000001U;
}
static inline u32 sim_send_ring_target_phys_init_f(void)
{
return 0x1U;
}
static inline u32 sim_send_ring_target_phys__init_v(void)
{
return 0x00000001U;
}
static inline u32 sim_send_ring_target_phys__init_f(void)
{
return 0x1U;
}
static inline u32 sim_send_ring_target_phys__prod_v(void)
{
return 0x00000001U;
}
static inline u32 sim_send_ring_target_phys__prod_f(void)
{
return 0x1U;
}
static inline u32 sim_send_ring_target_phys_nvm_v(void)
{
return 0x00000001U;
}
static inline u32 sim_send_ring_target_phys_nvm_f(void)
{
return 0x1U;
}
static inline u32 sim_send_ring_target_phys_pci_v(void)
{
return 0x00000002U;
}
static inline u32 sim_send_ring_target_phys_pci_f(void)
{
return 0x2U;
}
static inline u32 sim_send_ring_target_phys_pci_coherent_v(void)
{
return 0x00000003U;
}
static inline u32 sim_send_ring_target_phys_pci_coherent_f(void)
{
return 0x3U;
}
static inline u32 sim_send_ring_status_s(void)
{
return 1U;
}
static inline u32 sim_send_ring_status_f(u32 v)
{
return (v & 0x1U) << 3U;
}
static inline u32 sim_send_ring_status_m(void)
{
return 0x1U << 3U;
}
static inline u32 sim_send_ring_status_v(u32 r)
{
return (r >> 3U) & 0x1U;
}
static inline u32 sim_send_ring_status_init_v(void)
{
return 0x00000000U;
}
static inline u32 sim_send_ring_status_init_f(void)
{
return 0x0U;
}
static inline u32 sim_send_ring_status__init_v(void)
{
return 0x00000000U;
}
static inline u32 sim_send_ring_status__init_f(void)
{
return 0x0U;
}
static inline u32 sim_send_ring_status__prod_v(void)
{
return 0x00000000U;
}
static inline u32 sim_send_ring_status__prod_f(void)
{
return 0x0U;
}
static inline u32 sim_send_ring_status_invalid_v(void)
{
return 0x00000000U;
}
static inline u32 sim_send_ring_status_invalid_f(void)
{
return 0x0U;
}
static inline u32 sim_send_ring_status_valid_v(void)
{
return 0x00000001U;
}
static inline u32 sim_send_ring_status_valid_f(void)
{
return 0x8U;
}
static inline u32 sim_send_ring_size_s(void)
{
return 2U;
}
static inline u32 sim_send_ring_size_f(u32 v)
{
return (v & 0x3U) << 4U;
}
static inline u32 sim_send_ring_size_m(void)
{
return 0x3U << 4U;
}
static inline u32 sim_send_ring_size_v(u32 r)
{
return (r >> 4U) & 0x3U;
}
static inline u32 sim_send_ring_size_init_v(void)
{
return 0x00000000U;
}
static inline u32 sim_send_ring_size_init_f(void)
{
return 0x0U;
}
static inline u32 sim_send_ring_size__init_v(void)
{
return 0x00000000U;
}
static inline u32 sim_send_ring_size__init_f(void)
{
return 0x0U;
}
static inline u32 sim_send_ring_size__prod_v(void)
{
return 0x00000000U;
}
static inline u32 sim_send_ring_size__prod_f(void)
{
return 0x0U;
}
static inline u32 sim_send_ring_size_4kb_v(void)
{
return 0x00000000U;
}
static inline u32 sim_send_ring_size_4kb_f(void)
{
return 0x0U;
}
static inline u32 sim_send_ring_size_8kb_v(void)
{
return 0x00000001U;
}
static inline u32 sim_send_ring_size_8kb_f(void)
{
return 0x10U;
}
static inline u32 sim_send_ring_size_12kb_v(void)
{
return 0x00000002U;
}
static inline u32 sim_send_ring_size_12kb_f(void)
{
return 0x20U;
}
static inline u32 sim_send_ring_size_16kb_v(void)
{
return 0x00000003U;
}
static inline u32 sim_send_ring_size_16kb_f(void)
{
return 0x30U;
}
static inline u32 sim_send_ring_gp_in_ring_s(void)
{
return 1U;
}
static inline u32 sim_send_ring_gp_in_ring_f(u32 v)
{
return (v & 0x1) << 11U;
}
static inline u32 sim_send_ring_gp_in_ring_m(void)
{
return 0x1 << 11U;
}
static inline u32 sim_send_ring_gp_in_ring_v(u32 r)
{
return (r >> 11) & 0x1U;
}
static inline u32 sim_send_ring_gp_in_ring__init_v(void)
{
return 0x00000000U;
}
static inline u32 sim_send_ring_gp_in_ring__init_f(void)
{
return 0x0U;
}
static inline u32 sim_send_ring_gp_in_ring__prod_v(void)
{
return 0x00000000U;
}
static inline u32 sim_send_ring_gp_in_ring__prod_f(void)
{
return 0x0U;
}
static inline u32 sim_send_ring_gp_in_ring_no_v(void)
{
return 0x00000000U;
}
static inline u32 sim_send_ring_gp_in_ring_no_f(void)
{
return 0x0U;
}
static inline u32 sim_send_ring_gp_in_ring_yes_v(void)
{
return 0x00000001U;
}
static inline u32 sim_send_ring_gp_in_ring_yes_f(void)
{
return 0x800U;
}
static inline u32 sim_send_ring_addr_lo_s(void)
{
return 20U;
}
static inline u32 sim_send_ring_addr_lo_f(u32 v)
{
return (v & 0xfffffU) << 12U;
}
static inline u32 sim_send_ring_addr_lo_m(void)
{
return 0xfffffU << 12U;
}
static inline u32 sim_send_ring_addr_lo_v(u32 r)
{
return (r >> 12U) & 0xfffffU;
}
static inline u32 sim_send_ring_addr_lo__init_v(void)
{
return 0x00000000U;
}
static inline u32 sim_send_ring_addr_lo__init_f(void)
{
return 0x0U;
}
static inline u32 sim_send_ring_addr_lo__prod_v(void)
{
return 0x00000000U;
}
static inline u32 sim_send_ring_addr_lo__prod_f(void)
{
return 0x0U;
}
static inline u32 sim_send_ring_hi_r(void)
{
return 0x00000004U;
}
static inline u32 sim_send_ring_hi_addr_s(void)
{
return 20U;
}
static inline u32 sim_send_ring_hi_addr_f(u32 v)
{
return (v & 0xfffffU) << 0U;
}
static inline u32 sim_send_ring_hi_addr_m(void)
{
return 0xfffffU << 0U;
}
static inline u32 sim_send_ring_hi_addr_v(u32 r)
{
return (r >> 0U) & 0xfffffU;
}
static inline u32 sim_send_ring_hi_addr__init_v(void)
{
return 0x00000000U;
}
static inline u32 sim_send_ring_hi_addr__init_f(void)
{
return 0x0U;
}
static inline u32 sim_send_ring_hi_addr__prod_v(void)
{
return 0x00000000U;
}
static inline u32 sim_send_ring_hi_addr__prod_f(void)
{
return 0x0U;
}
static inline u32 sim_send_put_r(void)
{
return 0x00000008U;
}
static inline u32 sim_send_put_pointer_s(void)
{
return 29U;
}
static inline u32 sim_send_put_pointer_f(u32 v)
{
return (v & 0x1fffffffU) << 3U;
}
static inline u32 sim_send_put_pointer_m(void)
{
return 0x1fffffffU << 3U;
}
static inline u32 sim_send_put_pointer_v(u32 r)
{
return (r >> 3U) & 0x1fffffffU;
}
static inline u32 sim_send_get_r(void)
{
return 0x0000000cU;
}
static inline u32 sim_send_get_pointer_s(void)
{
return 29U;
}
static inline u32 sim_send_get_pointer_f(u32 v)
{
return (v & 0x1fffffffU) << 3U;
}
static inline u32 sim_send_get_pointer_m(void)
{
return 0x1fffffffU << 3U;
}
static inline u32 sim_send_get_pointer_v(u32 r)
{
return (r >> 3U) & 0x1fffffffU;
}
static inline u32 sim_recv_ring_r(void)
{
return 0x00000010U;
}
static inline u32 sim_recv_ring_target_s(void)
{
return 2U;
}
static inline u32 sim_recv_ring_target_f(u32 v)
{
return (v & 0x3U) << 0U;
}
static inline u32 sim_recv_ring_target_m(void)
{
return 0x3U << 0U;
}
static inline u32 sim_recv_ring_target_v(u32 r)
{
return (r >> 0) & 0x3U;
}
static inline u32 sim_recv_ring_target_phys_init_v(void)
{
return 0x00000001U;
}
static inline u32 sim_recv_ring_target_phys_init_f(void)
{
return 0x1U;
}
static inline u32 sim_recv_ring_target_phys__init_v(void)
{
return 0x00000001U;
}
static inline u32 sim_recv_ring_target_phys__init_f(void)
{
return 0x1U;
}
static inline u32 sim_recv_ring_target_phys__prod_v(void)
{
return 0x00000001U;
}
static inline u32 sim_recv_ring_target_phys__prod_f(void)
{
return 0x1U;
}
static inline u32 sim_recv_ring_target_phys_nvm_v(void)
{
return 0x00000001U;
}
static inline u32 sim_recv_ring_target_phys_nvm_f(void)
{
return 0x1U;
}
static inline u32 sim_recv_ring_target_phys_pci_v(void)
{
return 0x00000002U;
}
static inline u32 sim_recv_ring_target_phys_pci_f(void)
{
return 0x2U;
}
static inline u32 sim_recv_ring_target_phys_pci_coherent_v(void)
{
return 0x00000003U;
}
static inline u32 sim_recv_ring_target_phys_pci_coherent_f(void)
{
return 0x3U;
}
static inline u32 sim_recv_ring_status_s(void)
{
return 1U;
}
static inline u32 sim_recv_ring_status_f(u32 v)
{
return (v & 0x1U) << 3U;
}
static inline u32 sim_recv_ring_status_m(void)
{
return 0x1U << 3U;
}
static inline u32 sim_recv_ring_status_v(u32 r)
{
return (r >> 3U) & 0x1U;
}
static inline u32 sim_recv_ring_status_init_v(void)
{
return 0x00000000U;
}
static inline u32 sim_recv_ring_status_init_f(void)
{
return 0x0U;
}
static inline u32 sim_recv_ring_status__init_v(void)
{
return 0x00000000U;
}
static inline u32 sim_recv_ring_status__init_f(void)
{
return 0x0U;
}
static inline u32 sim_recv_ring_status__prod_v(void)
{
return 0x00000000U;
}
static inline u32 sim_recv_ring_status__prod_f(void)
{
return 0x0U;
}
static inline u32 sim_recv_ring_status_invalid_v(void)
{
return 0x00000000U;
}
static inline u32 sim_recv_ring_status_invalid_f(void)
{
return 0x0U;
}
static inline u32 sim_recv_ring_status_valid_v(void)
{
return 0x00000001U;
}
static inline u32 sim_recv_ring_status_valid_f(void)
{
return 0x8U;
}
static inline u32 sim_recv_ring_size_s(void)
{
return 2U;
}
static inline u32 sim_recv_ring_size_f(u32 v)
{
return (v & 0x3U) << 4U;
}
static inline u32 sim_recv_ring_size_m(void)
{
return 0x3U << 4U;
}
static inline u32 sim_recv_ring_size_v(u32 r)
{
return (r >> 4U) & 0x3U;
}
static inline u32 sim_recv_ring_size_init_v(void)
{
return 0x00000000U;
}
static inline u32 sim_recv_ring_size_init_f(void)
{
return 0x0U;
}
static inline u32 sim_recv_ring_size__init_v(void)
{
return 0x00000000U;
}
static inline u32 sim_recv_ring_size__init_f(void)
{
return 0x0U;
}
static inline u32 sim_recv_ring_size__prod_v(void)
{
return 0x00000000U;
}
static inline u32 sim_recv_ring_size__prod_f(void)
{
return 0x0U;
}
static inline u32 sim_recv_ring_size_4kb_v(void)
{
return 0x00000000U;
}
static inline u32 sim_recv_ring_size_4kb_f(void)
{
return 0x0U;
}
static inline u32 sim_recv_ring_size_8kb_v(void)
{
return 0x00000001U;
}
static inline u32 sim_recv_ring_size_8kb_f(void)
{
return 0x10U;
}
static inline u32 sim_recv_ring_size_12kb_v(void)
{
return 0x00000002U;
}
static inline u32 sim_recv_ring_size_12kb_f(void)
{
return 0x20U;
}
static inline u32 sim_recv_ring_size_16kb_v(void)
{
return 0x00000003U;
}
static inline u32 sim_recv_ring_size_16kb_f(void)
{
return 0x30U;
}
static inline u32 sim_recv_ring_gp_in_ring_s(void)
{
return 1U;
}
static inline u32 sim_recv_ring_gp_in_ring_f(u32 v)
{
return (v & 0x1U) << 11U;
}
static inline u32 sim_recv_ring_gp_in_ring_m(void)
{
return 0x1U << 11U;
}
static inline u32 sim_recv_ring_gp_in_ring_v(u32 r)
{
return (r >> 11U) & 0x1U;
}
static inline u32 sim_recv_ring_gp_in_ring__init_v(void)
{
return 0x00000000U;
}
static inline u32 sim_recv_ring_gp_in_ring__init_f(void)
{
return 0x0U;
}
static inline u32 sim_recv_ring_gp_in_ring__prod_v(void)
{
return 0x00000000U;
}
static inline u32 sim_recv_ring_gp_in_ring__prod_f(void)
{
return 0x0U;
}
static inline u32 sim_recv_ring_gp_in_ring_no_v(void)
{
return 0x00000000U;
}
static inline u32 sim_recv_ring_gp_in_ring_no_f(void)
{
return 0x0U;
}
static inline u32 sim_recv_ring_gp_in_ring_yes_v(void)
{
return 0x00000001U;
}
static inline u32 sim_recv_ring_gp_in_ring_yes_f(void)
{
return 0x800U;
}
static inline u32 sim_recv_ring_addr_lo_s(void)
{
return 20U;
}
static inline u32 sim_recv_ring_addr_lo_f(u32 v)
{
return (v & 0xfffffU) << 12U;
}
static inline u32 sim_recv_ring_addr_lo_m(void)
{
return 0xfffffU << 12U;
}
static inline u32 sim_recv_ring_addr_lo_v(u32 r)
{
return (r >> 12U) & 0xfffffU;
}
static inline u32 sim_recv_ring_addr_lo__init_v(void)
{
return 0x00000000U;
}
static inline u32 sim_recv_ring_addr_lo__init_f(void)
{
return 0x0U;
}
static inline u32 sim_recv_ring_addr_lo__prod_v(void)
{
return 0x00000000U;
}
static inline u32 sim_recv_ring_addr_lo__prod_f(void)
{
return 0x0U;
}
static inline u32 sim_recv_ring_hi_r(void)
{
return 0x00000014U;
}
static inline u32 sim_recv_ring_hi_addr_s(void)
{
return 20U;
}
static inline u32 sim_recv_ring_hi_addr_f(u32 v)
{
return (v & 0xfffffU) << 0U;
}
static inline u32 sim_recv_ring_hi_addr_m(void)
{
return 0xfffffU << 0U;
}
static inline u32 sim_recv_ring_hi_addr_v(u32 r)
{
return (r >> 0U) & 0xfffffU;
}
static inline u32 sim_recv_ring_hi_addr__init_v(void)
{
return 0x00000000U;
}
static inline u32 sim_recv_ring_hi_addr__init_f(void)
{
return 0x0U;
}
static inline u32 sim_recv_ring_hi_addr__prod_v(void)
{
return 0x00000000U;
}
static inline u32 sim_recv_ring_hi_addr__prod_f(void)
{
return 0x0U;
}
static inline u32 sim_recv_put_r(void)
{
return 0x00000018U;
}
static inline u32 sim_recv_put_pointer_s(void)
{
return 11U;
}
static inline u32 sim_recv_put_pointer_f(u32 v)
{
return (v & 0x7ffU) << 3U;
}
static inline u32 sim_recv_put_pointer_m(void)
{
return 0x7ffU << 3U;
}
static inline u32 sim_recv_put_pointer_v(u32 r)
{
return (r >> 3U) & 0x7ffU;
}
static inline u32 sim_recv_get_r(void)
{
return 0x0000001cU;
}
static inline u32 sim_recv_get_pointer_s(void)
{
return 11U;
}
static inline u32 sim_recv_get_pointer_f(u32 v)
{
return (v & 0x7ffU) << 3U;
}
static inline u32 sim_recv_get_pointer_m(void)
{
return 0x7ffU << 3U;
}
static inline u32 sim_recv_get_pointer_v(u32 r)
{
return (r >> 3U) & 0x7ffU;
}
static inline u32 sim_config_r(void)
{
return 0x00000020U;
}
static inline u32 sim_config_mode_s(void)
{
return 1U;
}
static inline u32 sim_config_mode_f(u32 v)
{
return (v & 0x1U) << 0U;
}
static inline u32 sim_config_mode_m(void)
{
return 0x1U << 0U;
}
static inline u32 sim_config_mode_v(u32 r)
{
return (r >> 0U) & 0x1U;
}
static inline u32 sim_config_mode_disabled_v(void)
{
return 0x00000000U;
}
static inline u32 sim_config_mode_disabled_f(void)
{
return 0x0U;
}
static inline u32 sim_config_mode_enabled_v(void)
{
return 0x00000001U;
}
static inline u32 sim_config_mode_enabled_f(void)
{
return 0x1U;
}
static inline u32 sim_config_channels_s(void)
{
return 7U;
}
static inline u32 sim_config_channels_f(u32 v)
{
return (v & 0x7fU) << 1U;
}
static inline u32 sim_config_channels_m(void)
{
return 0x7fU << 1U;
}
static inline u32 sim_config_channels_v(u32 r)
{
return (r >> 1U) & 0x7fU;
}
static inline u32 sim_config_channels_none_v(void)
{
return 0x00000000U;
}
static inline u32 sim_config_channels_none_f(void)
{
return 0x0U;
}
static inline u32 sim_config_cached_only_s(void)
{
return 1U;
}
static inline u32 sim_config_cached_only_f(u32 v)
{
return (v & 0x1U) << 8U;
}
static inline u32 sim_config_cached_only_m(void)
{
return 0x1U << 8U;
}
static inline u32 sim_config_cached_only_v(u32 r)
{
return (r >> 8U) & 0x1U;
}
static inline u32 sim_config_cached_only_disabled_v(void)
{
return 0x00000000U;
}
static inline u32 sim_config_cached_only_disabled_f(void)
{
return 0x0U;
}
static inline u32 sim_config_cached_only_enabled_v(void)
{
return 0x00000001U;
}
static inline u32 sim_config_cached_only_enabled_f(void)
{
return 0x100U;
}
static inline u32 sim_config_validity_s(void)
{
return 2U;
}
static inline u32 sim_config_validity_f(u32 v)
{
return (v & 0x3U) << 9U;
}
static inline u32 sim_config_validity_m(void)
{
return 0x3U << 9U;
}
static inline u32 sim_config_validity_v(u32 r)
{
return (r >> 9U) & 0x3U;
}
static inline u32 sim_config_validity__init_v(void)
{
return 0x00000001U;
}
static inline u32 sim_config_validity__init_f(void)
{
return 0x200U;
}
static inline u32 sim_config_validity_valid_v(void)
{
return 0x00000001U;
}
static inline u32 sim_config_validity_valid_f(void)
{
return 0x200U;
}
static inline u32 sim_config_simulation_s(void)
{
return 2U;
}
static inline u32 sim_config_simulation_f(u32 v)
{
return (v & 0x3U) << 12U;
}
static inline u32 sim_config_simulation_m(void)
{
return 0x3U << 12U;
}
static inline u32 sim_config_simulation_v(u32 r)
{
return (r >> 12U) & 0x3U;
}
static inline u32 sim_config_simulation_disabled_v(void)
{
return 0x00000000U;
}
static inline u32 sim_config_simulation_disabled_f(void)
{
return 0x0U;
}
static inline u32 sim_config_simulation_fmodel_v(void)
{
return 0x00000001U;
}
static inline u32 sim_config_simulation_fmodel_f(void)
{
return 0x1000U;
}
static inline u32 sim_config_simulation_rtlsim_v(void)
{
return 0x00000002U;
}
static inline u32 sim_config_simulation_rtlsim_f(void)
{
return 0x2000U;
}
static inline u32 sim_config_secondary_display_s(void)
{
return 1U;
}
static inline u32 sim_config_secondary_display_f(u32 v)
{
return (v & 0x1U) << 14U;
}
static inline u32 sim_config_secondary_display_m(void)
{
return 0x1U << 14U;
}
static inline u32 sim_config_secondary_display_v(u32 r)
{
return (r >> 14U) & 0x1U;
}
static inline u32 sim_config_secondary_display_disabled_v(void)
{
return 0x00000000U;
}
static inline u32 sim_config_secondary_display_disabled_f(void)
{
return 0x0U;
}
static inline u32 sim_config_secondary_display_enabled_v(void)
{
return 0x00000001U;
}
static inline u32 sim_config_secondary_display_enabled_f(void)
{
return 0x4000U;
}
static inline u32 sim_config_num_heads_s(void)
{
return 8U;
}
static inline u32 sim_config_num_heads_f(u32 v)
{
return (v & 0xffU) << 17U;
}
static inline u32 sim_config_num_heads_m(void)
{
return 0xffU << 17U;
}
static inline u32 sim_config_num_heads_v(u32 r)
{
return (r >> 17U) & 0xffU;
}
static inline u32 sim_event_ring_r(void)
{
return 0x00000030U;
}
static inline u32 sim_event_ring_target_s(void)
{
return 2U;
}
static inline u32 sim_event_ring_target_f(u32 v)
{
return (v & 0x3U) << 0U;
}
static inline u32 sim_event_ring_target_m(void)
{
return 0x3U << 0U;
}
static inline u32 sim_event_ring_target_v(u32 r)
{
return (r >> 0U) & 0x3U;
}
static inline u32 sim_event_ring_target_phys_init_v(void)
{
return 0x00000001U;
}
static inline u32 sim_event_ring_target_phys_init_f(void)
{
return 0x1U;
}
static inline u32 sim_event_ring_target_phys__init_v(void)
{
return 0x00000001U;
}
static inline u32 sim_event_ring_target_phys__init_f(void)
{
return 0x1U;
}
static inline u32 sim_event_ring_target_phys__prod_v(void)
{
return 0x00000001U;
}
static inline u32 sim_event_ring_target_phys__prod_f(void)
{
return 0x1U;
}
static inline u32 sim_event_ring_target_phys_nvm_v(void)
{
return 0x00000001U;
}
static inline u32 sim_event_ring_target_phys_nvm_f(void)
{
return 0x1U;
}
static inline u32 sim_event_ring_target_phys_pci_v(void)
{
return 0x00000002U;
}
static inline u32 sim_event_ring_target_phys_pci_f(void)
{
return 0x2U;
}
static inline u32 sim_event_ring_target_phys_pci_coherent_v(void)
{
return 0x00000003U;
}
static inline u32 sim_event_ring_target_phys_pci_coherent_f(void)
{
return 0x3U;
}
static inline u32 sim_event_ring_status_s(void)
{
return 1U;
}
static inline u32 sim_event_ring_status_f(u32 v)
{
return (v & 0x1U) << 3U;
}
static inline u32 sim_event_ring_status_m(void)
{
return 0x1U << 3U;
}
static inline u32 sim_event_ring_status_v(u32 r)
{
return (r >> 3U) & 0x1U;
}
static inline u32 sim_event_ring_status_init_v(void)
{
return 0x00000000U;
}
static inline u32 sim_event_ring_status_init_f(void)
{
return 0x0U;
}
static inline u32 sim_event_ring_status__init_v(void)
{
return 0x00000000U;
}
static inline u32 sim_event_ring_status__init_f(void)
{
return 0x0U;
}
static inline u32 sim_event_ring_status__prod_v(void)
{
return 0x00000000U;
}
static inline u32 sim_event_ring_status__prod_f(void)
{
return 0x0U;
}
static inline u32 sim_event_ring_status_invalid_v(void)
{
return 0x00000000U;
}
static inline u32 sim_event_ring_status_invalid_f(void)
{
return 0x0U;
}
static inline u32 sim_event_ring_status_valid_v(void)
{
return 0x00000001U;
}
static inline u32 sim_event_ring_status_valid_f(void)
{
return 0x8U;
}
static inline u32 sim_event_ring_size_s(void)
{
return 2U;
}
static inline u32 sim_event_ring_size_f(u32 v)
{
return (v & 0x3U) << 4U;
}
static inline u32 sim_event_ring_size_m(void)
{
return 0x3U << 4U;
}
static inline u32 sim_event_ring_size_v(u32 r)
{
return (r >> 4U) & 0x3U;
}
static inline u32 sim_event_ring_size_init_v(void)
{
return 0x00000000U;
}
static inline u32 sim_event_ring_size_init_f(void)
{
return 0x0U;
}
static inline u32 sim_event_ring_size__init_v(void)
{
return 0x00000000U;
}
static inline u32 sim_event_ring_size__init_f(void)
{
return 0x0U;
}
static inline u32 sim_event_ring_size__prod_v(void)
{
return 0x00000000U;
}
static inline u32 sim_event_ring_size__prod_f(void)
{
return 0x0U;
}
static inline u32 sim_event_ring_size_4kb_v(void)
{
return 0x00000000U;
}
static inline u32 sim_event_ring_size_4kb_f(void)
{
return 0x0U;
}
static inline u32 sim_event_ring_size_8kb_v(void)
{
return 0x00000001U;
}
static inline u32 sim_event_ring_size_8kb_f(void)
{
return 0x10U;
}
static inline u32 sim_event_ring_size_12kb_v(void)
{
return 0x00000002U;
}
static inline u32 sim_event_ring_size_12kb_f(void)
{
return 0x20U;
}
static inline u32 sim_event_ring_size_16kb_v(void)
{
return 0x00000003U;
}
static inline u32 sim_event_ring_size_16kb_f(void)
{
return 0x30U;
}
static inline u32 sim_event_ring_gp_in_ring_s(void)
{
return 1U;
}
static inline u32 sim_event_ring_gp_in_ring_f(u32 v)
{
return (v & 0x1U) << 11U;
}
static inline u32 sim_event_ring_gp_in_ring_m(void)
{
return 0x1U << 11U;
}
static inline u32 sim_event_ring_gp_in_ring_v(u32 r)
{
return (r >> 11U) & 0x1U;
}
static inline u32 sim_event_ring_gp_in_ring__init_v(void)
{
return 0x00000000U;
}
static inline u32 sim_event_ring_gp_in_ring__init_f(void)
{
return 0x0U;
}
static inline u32 sim_event_ring_gp_in_ring__prod_v(void)
{
return 0x00000000U;
}
static inline u32 sim_event_ring_gp_in_ring__prod_f(void)
{
return 0x0U;
}
static inline u32 sim_event_ring_gp_in_ring_no_v(void)
{
return 0x00000000U;
}
static inline u32 sim_event_ring_gp_in_ring_no_f(void)
{
return 0x0U;
}
static inline u32 sim_event_ring_gp_in_ring_yes_v(void)
{
return 0x00000001U;
}
static inline u32 sim_event_ring_gp_in_ring_yes_f(void)
{
return 0x800U;
}
static inline u32 sim_event_ring_addr_lo_s(void)
{
return 20U;
}
static inline u32 sim_event_ring_addr_lo_f(u32 v)
{
return (v & 0xfffffU) << 12U;
}
static inline u32 sim_event_ring_addr_lo_m(void)
{
return 0xfffffU << 12U;
}
static inline u32 sim_event_ring_addr_lo_v(u32 r)
{
return (r >> 12U) & 0xfffffU;
}
static inline u32 sim_event_ring_addr_lo__init_v(void)
{
return 0x00000000U;
}
static inline u32 sim_event_ring_addr_lo__init_f(void)
{
return 0x0U;
}
static inline u32 sim_event_ring_addr_lo__prod_v(void)
{
return 0x00000000U;
}
static inline u32 sim_event_ring_addr_lo__prod_f(void)
{
return 0x0U;
}
static inline u32 sim_event_ring_hi_v(void)
{
return 0x00000034U;
}
static inline u32 sim_event_ring_hi_addr_s(void)
{
return 20U;
}
static inline u32 sim_event_ring_hi_addr_f(u32 v)
{
return (v & 0xfffffU) << 0U;
}
static inline u32 sim_event_ring_hi_addr_m(void)
{
return 0xfffffU << 0U;
}
static inline u32 sim_event_ring_hi_addr_v(u32 r)
{
return (r >> 0U) & 0xfffffU;
}
static inline u32 sim_event_ring_hi_addr__init_v(void)
{
return 0x00000000U;
}
static inline u32 sim_event_ring_hi_addr__init_f(void)
{
return 0x0U;
}
static inline u32 sim_event_ring_hi_addr__prod_v(void)
{
return 0x00000000U;
}
static inline u32 sim_event_ring_hi_addr__prod_f(void)
{
return 0x0U;
}
static inline u32 sim_event_put_r(void)
{
return 0x00000038U;
}
static inline u32 sim_event_put_pointer_s(void)
{
return 30U;
}
static inline u32 sim_event_put_pointer_f(u32 v)
{
return (v & 0x3fffffffU) << 2U;
}
static inline u32 sim_event_put_pointer_m(void)
{
return 0x3fffffffU << 2U;
}
static inline u32 sim_event_put_pointer_v(u32 r)
{
return (r >> 2U) & 0x3fffffffU;
}
static inline u32 sim_event_get_r(void)
{
return 0x0000003cU;
}
static inline u32 sim_event_get_pointer_s(void)
{
return 30U;
}
static inline u32 sim_event_get_pointer_f(u32 v)
{
return (v & 0x3fffffffU) << 2U;
}
static inline u32 sim_event_get_pointer_m(void)
{
return 0x3fffffffU << 2U;
}
static inline u32 sim_event_get_pointer_v(u32 r)
{
return (r >> 2U) & 0x3fffffffU;
}
static inline u32 sim_status_r(void)
{
return 0x00000028U;
}
static inline u32 sim_status_send_put_s(void)
{
return 1U;
}
static inline u32 sim_status_send_put_f(u32 v)
{
return (v & 0x1U) << 0U;
}
static inline u32 sim_status_send_put_m(void)
{
return 0x1 << 0U;
}
static inline u32 sim_status_send_put_v(u32 r)
{
return (r >> 0U) & 0x1U;
}
static inline u32 sim_status_send_put__init_v(void)
{
return 0x00000000U;
}
static inline u32 sim_status_send_put__init_f(void)
{
return 0x0U;
}
static inline u32 sim_status_send_put_idle_v(void)
{
return 0x00000000U;
}
static inline u32 sim_status_send_put_idle_f(void)
{
return 0x0U;
}
static inline u32 sim_status_send_put_pending_v(void)
{
return 0x00000001U;
}
static inline u32 sim_status_send_put_pending_f(void)
{
return 0x1U;
}
static inline u32 sim_status_send_get_s(void)
{
return 1U;
}
static inline u32 sim_status_send_get_f(u32 v)
{
return (v & 0x1U) << 1U;
}
static inline u32 sim_status_send_get_m(void)
{
return 0x1U << 1U;
}
static inline u32 sim_status_send_get_v(u32 r)
{
return (r >> 1U) & 0x1U;
}
static inline u32 sim_status_send_get__init_v(void)
{
return 0x00000000U;
}
static inline u32 sim_status_send_get__init_f(void)
{
return 0x0U;
}
static inline u32 sim_status_send_get_idle_v(void)
{
return 0x00000000U;
}
static inline u32 sim_status_send_get_idle_f(void)
{
return 0x0U;
}
static inline u32 sim_status_send_get_pending_v(void)
{
return 0x00000001U;
}
static inline u32 sim_status_send_get_pending_f(void)
{
return 0x2U;
}
static inline u32 sim_status_send_get_clear_v(void)
{
return 0x00000001U;
}
static inline u32 sim_status_send_get_clear_f(void)
{
return 0x2U;
}
static inline u32 sim_status_recv_put_s(void)
{
return 1U;
}
static inline u32 sim_status_recv_put_f(u32 v)
{
return (v & 0x1U) << 2U;
}
static inline u32 sim_status_recv_put_m(void)
{
return 0x1U << 2U;
}
static inline u32 sim_status_recv_put_v(u32 r)
{
return (r >> 2U) & 0x1U;
}
static inline u32 sim_status_recv_put__init_v(void)
{
return 0x00000000U;
}
static inline u32 sim_status_recv_put__init_f(void)
{
return 0x0U;
}
static inline u32 sim_status_recv_put_idle_v(void)
{
return 0x00000000U;
}
static inline u32 sim_status_recv_put_idle_f(void)
{
return 0x0U;
}
static inline u32 sim_status_recv_put_pending_v(void)
{
return 0x00000001U;
}
static inline u32 sim_status_recv_put_pending_f(void)
{
return 0x4U;
}
static inline u32 sim_status_recv_put_clear_v(void)
{
return 0x00000001U;
}
static inline u32 sim_status_recv_put_clear_f(void)
{
return 0x4U;
}
static inline u32 sim_status_recv_get_s(void)
{
return 1U;
}
static inline u32 sim_status_recv_get_f(u32 v)
{
return (v & 0x1U) << 3U;
}
static inline u32 sim_status_recv_get_m(void)
{
return 0x1U << 3U;
}
static inline u32 sim_status_recv_get_v(u32 r)
{
return (r >> 3U) & 0x1U;
}
static inline u32 sim_status_recv_get__init_v(void)
{
return 0x00000000U;
}
static inline u32 sim_status_recv_get__init_f(void)
{
return 0x0U;
}
static inline u32 sim_status_recv_get_idle_v(void)
{
return 0x00000000U;
}
static inline u32 sim_status_recv_get_idle_f(void)
{
return 0x0U;
}
static inline u32 sim_status_recv_get_pending_v(void)
{
return 0x00000001U;
}
static inline u32 sim_status_recv_get_pending_f(void)
{
return 0x8U;
}
static inline u32 sim_status_event_put_s(void)
{
return 1U;
}
static inline u32 sim_status_event_put_f(u32 v)
{
return (v & 0x1U) << 4U;
}
static inline u32 sim_status_event_put_m(void)
{
return 0x1U << 4U;
}
static inline u32 sim_status_event_put_v(u32 r)
{
return (r >> 4U) & 0x1U;
}
static inline u32 sim_status_event_put__init_v(void)
{
return 0x00000000U;
}
static inline u32 sim_status_event_put__init_f(void)
{
return 0x0U;
}
static inline u32 sim_status_event_put_idle_v(void)
{
return 0x00000000U;
}
static inline u32 sim_status_event_put_idle_f(void)
{
return 0x0U;
}
static inline u32 sim_status_event_put_pending_v(void)
{
return 0x00000001U;
}
static inline u32 sim_status_event_put_pending_f(void)
{
return 0x10U;
}
static inline u32 sim_status_event_put_clear_v(void)
{
return 0x00000001U;
}
static inline u32 sim_status_event_put_clear_f(void)
{
return 0x10U;
}
static inline u32 sim_status_event_get_s(void)
{
return 1U;
}
static inline u32 sim_status_event_get_f(u32 v)
{
return (v & 0x1U) << 5U;
}
static inline u32 sim_status_event_get_m(void)
{
return 0x1U << 5U;
}
static inline u32 sim_status_event_get_v(u32 r)
{
return (r >> 5U) & 0x1U;
}
static inline u32 sim_status_event_get__init_v(void)
{
return 0x00000000U;
}
static inline u32 sim_status_event_get__init_f(void)
{
return 0x0U;
}
static inline u32 sim_status_event_get_idle_v(void)
{
return 0x00000000U;
}
static inline u32 sim_status_event_get_idle_f(void)
{
return 0x0U;
}
static inline u32 sim_status_event_get_pending_v(void)
{
return 0x00000001U;
}
static inline u32 sim_status_event_get_pending_f(void)
{
return 0x20U;
}
static inline u32 sim_control_r(void)
{
return 0x0000002cU;
}
static inline u32 sim_control_send_put_s(void)
{
return 1U;
}
static inline u32 sim_control_send_put_f(u32 v)
{
return (v & 0x1U) << 0U;
}
static inline u32 sim_control_send_put_m(void)
{
return 0x1U << 0U;
}
static inline u32 sim_control_send_put_v(u32 r)
{
return (r >> 0U) & 0x1U;
}
static inline u32 sim_control_send_put__init_v(void)
{
return 0x00000000U;
}
static inline u32 sim_control_send_put__init_f(void)
{
return 0x0U;
}
static inline u32 sim_control_send_put_disabled_v(void)
{
return 0x00000000U;
}
static inline u32 sim_control_send_put_disabled_f(void)
{
return 0x0U;
}
static inline u32 sim_control_send_put_enabled_v(void)
{
return 0x00000001U;
}
static inline u32 sim_control_send_put_enabled_f(void)
{
return 0x1U;
}
static inline u32 sim_control_send_get_s(void)
{
return 1U;
}
static inline u32 sim_control_send_get_f(u32 v)
{
return (v & 0x1U) << 1U;
}
static inline u32 sim_control_send_get_m(void)
{
return 0x1U << 1U;
}
static inline u32 sim_control_send_get_v(u32 r)
{
return (r >> 1U) & 0x1U;
}
static inline u32 sim_control_send_get__init_v(void)
{
return 0x00000000U;
}
static inline u32 sim_control_send_get__init_f(void)
{
return 0x0U;
}
static inline u32 sim_control_send_get_disabled_v(void)
{
return 0x00000000U;
}
static inline u32 sim_control_send_get_disabled_f(void)
{
return 0x0U;
}
static inline u32 sim_control_send_get_enabled_v(void)
{
return 0x00000001U;
}
static inline u32 sim_control_send_get_enabled_f(void)
{
return 0x2U;
}
static inline u32 sim_control_recv_put_s(void)
{
return 1U;
}
static inline u32 sim_control_recv_put_f(u32 v)
{
return (v & 0x1U) << 2U;
}
static inline u32 sim_control_recv_put_m(void)
{
return 0x1U << 2U;
}
static inline u32 sim_control_recv_put_v(u32 r)
{
return (r >> 2U) & 0x1U;
}
static inline u32 sim_control_recv_put__init_v(void)
{
return 0x00000000U;
}
static inline u32 sim_control_recv_put__init_f(void)
{
return 0x0U;
}
static inline u32 sim_control_recv_put_disabled_v(void)
{
return 0x00000000U;
}
static inline u32 sim_control_recv_put_disabled_f(void)
{
return 0x0U;
}
static inline u32 sim_control_recv_put_enabled_v(void)
{
return 0x00000001U;
}
static inline u32 sim_control_recv_put_enabled_f(void)
{
return 0x4U;
}
static inline u32 sim_control_recv_get_s(void)
{
return 1U;
}
static inline u32 sim_control_recv_get_f(u32 v)
{
return (v & 0x1U) << 3U;
}
static inline u32 sim_control_recv_get_m(void)
{
return 0x1U << 3U;
}
static inline u32 sim_control_recv_get_v(u32 r)
{
return (r >> 3U) & 0x1U;
}
static inline u32 sim_control_recv_get__init_v(void)
{
return 0x00000000U;
}
static inline u32 sim_control_recv_get__init_f(void)
{
return 0x0U;
}
static inline u32 sim_control_recv_get_disabled_v(void)
{
return 0x00000000U;
}
static inline u32 sim_control_recv_get_disabled_f(void)
{
return 0x0U;
}
static inline u32 sim_control_recv_get_enabled_v(void)
{
return 0x00000001U;
}
static inline u32 sim_control_recv_get_enabled_f(void)
{
return 0x8U;
}
static inline u32 sim_control_event_put_s(void)
{
return 1U;
}
static inline u32 sim_control_event_put_f(u32 v)
{
return (v & 0x1U) << 4U;
}
static inline u32 sim_control_event_put_m(void)
{
return 0x1U << 4U;
}
static inline u32 sim_control_event_put_v(u32 r)
{
return (r >> 4U) & 0x1U;
}
static inline u32 sim_control_event_put__init_v(void)
{
return 0x00000000U;
}
static inline u32 sim_control_event_put__init_f(void)
{
return 0x0U;
}
static inline u32 sim_control_event_put_disabled_v(void)
{
return 0x00000000U;
}
static inline u32 sim_control_event_put_disabled_f(void)
{
return 0x0U;
}
static inline u32 sim_control_event_put_enabled_v(void)
{
return 0x00000001U;
}
static inline u32 sim_control_event_put_enabled_f(void)
{
return 0x10U;
}
static inline u32 sim_control_event_get_s(void)
{
return 1U;
}
static inline u32 sim_control_event_get_f(u32 v)
{
return (v & 0x1U) << 5U;
}
static inline u32 sim_control_event_get_m(void)
{
return 0x1U << 5U;
}
static inline u32 sim_control_event_get_v(u32 r)
{
return (r >> 5U) & 0x1U;
}
static inline u32 sim_control_event_get__init_v(void)
{
return 0x00000000U;
}
static inline u32 sim_control_event_get__init_f(void)
{
return 0x0U;
}
static inline u32 sim_control_event_get_disabled_v(void)
{
return 0x00000000U;
}
static inline u32 sim_control_event_get_disabled_f(void)
{
return 0x0U;
}
static inline u32 sim_control_event_get_enabled_v(void)
{
return 0x00000001U;
}
static inline u32 sim_control_event_get_enabled_f(void)
{
return 0x20U;
}
static inline u32 sim_dma_r(void)
{
return 0x00000000U;
}
static inline u32 sim_dma_target_s(void)
{
return 2U;
}
static inline u32 sim_dma_target_f(u32 v)
{
return (v & 0x3U) << 0U;
}
static inline u32 sim_dma_target_m(void)
{
return 0x3U << 0U;
}
static inline u32 sim_dma_target_v(u32 r)
{
return (r >> 0U) & 0x3U;
}
static inline u32 sim_dma_target_phys_init_v(void)
{
return 0x00000001U;
}
static inline u32 sim_dma_target_phys_init_f(void)
{
return 0x1U;
}
static inline u32 sim_dma_target_phys__init_v(void)
{
return 0x00000001U;
}
static inline u32 sim_dma_target_phys__init_f(void)
{
return 0x1U;
}
static inline u32 sim_dma_target_phys__prod_v(void)
{
return 0x00000001U;
}
static inline u32 sim_dma_target_phys__prod_f(void)
{
return 0x1U;
}
static inline u32 sim_dma_target_phys_nvm_v(void)
{
return 0x00000001U;
}
static inline u32 sim_dma_target_phys_nvm_f(void)
{
return 0x1U;
}
static inline u32 sim_dma_target_phys_pci_v(void)
{
return 0x00000002U;
}
static inline u32 sim_dma_target_phys_pci_f(void)
{
return 0x2U;
}
static inline u32 sim_dma_target_phys_pci_coherent_v(void)
{
return 0x00000003U;
}
static inline u32 sim_dma_target_phys_pci_coherent_f(void)
{
return 0x3U;
}
static inline u32 sim_dma_status_s(void)
{
return 1U;
}
static inline u32 sim_dma_status_f(u32 v)
{
return (v & 0x1U) << 3U;
}
static inline u32 sim_dma_status_m(void)
{
return 0x1U << 3U;
}
static inline u32 sim_dma_status_v(u32 r)
{
return (r >> 3U) & 0x1U;
}
static inline u32 sim_dma_status_init_v(void)
{
return 0x00000000U;
}
static inline u32 sim_dma_status_init_f(void)
{
return 0x0U;
}
static inline u32 sim_dma_status__init_v(void)
{
return 0x00000000U;
}
static inline u32 sim_dma_status__init_f(void)
{
return 0x0U;
}
static inline u32 sim_dma_status__prod_v(void)
{
return 0x00000000U;
}
static inline u32 sim_dma_status__prod_f(void)
{
return 0x0U;
}
static inline u32 sim_dma_status_invalid_v(void)
{
return 0x00000000U;
}
static inline u32 sim_dma_status_invalid_f(void)
{
return 0x0U;
}
static inline u32 sim_dma_status_valid_v(void)
{
return 0x00000001U;
}
static inline u32 sim_dma_status_valid_f(void)
{
return 0x8U;
}
static inline u32 sim_dma_size_s(void)
{
return 2U;
}
static inline u32 sim_dma_size_f(u32 v)
{
return (v & 0x3U) << 4U;
}
static inline u32 sim_dma_size_m(void)
{
return 0x3U << 4U;
}
static inline u32 sim_dma_size_v(u32 r)
{
return (r >> 4U) & 0x3U;
}
static inline u32 sim_dma_size_init_v(void)
{
return 0x00000000U;
}
static inline u32 sim_dma_size_init_f(void)
{
return 0x0U;
}
static inline u32 sim_dma_size__init_v(void)
{
return 0x00000000U;
}
static inline u32 sim_dma_size__init_f(void)
{
return 0x0U;
}
static inline u32 sim_dma_size__prod_v(void)
{
return 0x00000000U;
}
static inline u32 sim_dma_size__prod_f(void)
{
return 0x0U;
}
static inline u32 sim_dma_size_4kb_v(void)
{
return 0x00000000U;
}
static inline u32 sim_dma_size_4kb_f(void)
{
return 0x0U;
}
static inline u32 sim_dma_size_8kb_v(void)
{
return 0x00000001U;
}
static inline u32 sim_dma_size_8kb_f(void)
{
return 0x10U;
}
static inline u32 sim_dma_size_12kb_v(void)
{
return 0x00000002U;
}
static inline u32 sim_dma_size_12kb_f(void)
{
return 0x20U;
}
static inline u32 sim_dma_size_16kb_v(void)
{
return 0x00000003U;
}
static inline u32 sim_dma_size_16kb_f(void)
{
return 0x30U;
}
static inline u32 sim_dma_addr_lo_s(void)
{
return 20U;
}
static inline u32 sim_dma_addr_lo_f(u32 v)
{
return (v & 0xfffffU) << 12U;
}
static inline u32 sim_dma_addr_lo_m(void)
{
return 0xfffffU << 12U;
}
static inline u32 sim_dma_addr_lo_v(u32 r)
{
return (r >> 12U) & 0xfffffU;
}
static inline u32 sim_dma_addr_lo__init_v(void)
{
return 0x00000000U;
}
static inline u32 sim_dma_addr_lo__init_f(void)
{
return 0x0U;
}
static inline u32 sim_dma_addr_lo__prod_v(void)
{
return 0x00000000U;
}
static inline u32 sim_dma_addr_lo__prod_f(void)
{
return 0x0U;
}
static inline u32 sim_dma_hi_r(void)
{
return 0x00000004U;
}
static inline u32 sim_dma_hi_addr_s(void)
{
return 20U;
}
static inline u32 sim_dma_hi_addr_f(u32 v)
{
return (v & 0xfffffU) << 0U;
}
static inline u32 sim_dma_hi_addr_m(void)
{
return 0xfffffU << 0U;
}
static inline u32 sim_dma_hi_addr_v(u32 r)
{
return (r >> 0U) & 0xfffffU;
}
static inline u32 sim_dma_hi_addr__init_v(void)
{
return 0x00000000U;
}
static inline u32 sim_dma_hi_addr__init_f(void)
{
return 0x0U;
}
static inline u32 sim_dma_hi_addr__prod_v(void)
{
return 0x00000000U;
}
static inline u32 sim_dma_hi_addr__prod_f(void)
{
return 0x0U;
}
static inline u32 sim_msg_header_version_r(void)
{
return 0x00000000U;
}
static inline u32 sim_msg_header_version_major_tot_v(void)
{
return 0x03000000U;
}
static inline u32 sim_msg_header_version_minor_tot_v(void)
{
return 0x00000000U;
}
static inline u32 sim_msg_signature_r(void)
{
return 0x00000004U;
}
static inline u32 sim_msg_signature_valid_v(void)
{
return 0x43505256U;
}
static inline u32 sim_msg_length_r(void)
{
return 0x00000008U;
}
static inline u32 sim_msg_function_r(void)
{
return 0x0000000cU;
}
static inline u32 sim_msg_function_sim_escape_read_v(void)
{
return 0x00000023U;
}
static inline u32 sim_msg_function_sim_escape_write_v(void)
{
return 0x00000024U;
}
static inline u32 sim_msg_result_r(void)
{
return 0x00000010U;
}
static inline u32 sim_msg_result_success_v(void)
{
return 0x00000000U;
}
static inline u32 sim_msg_result_rpc_pending_v(void)
{
return 0xFFFFFFFFU;
}
static inline u32 sim_msg_sequence_r(void)
{
return 0x00000018U;
}
static inline u32 sim_msg_spare_r(void)
{
return 0x0000001cU;
}
static inline u32 sim_msg_spare__init_v(void)
{
return 0x00000000U;
}
#endif /* __hw_sim_pci_h__ */
