all_pairs/source/dijkstra/input.h


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#ifndef INPUT_H
#define INPUT_H

#define NUM_NODES 100

extern unsigned char dijkstra_AdjMatrix[NUM_NODES][NUM_NODES];

#endif  /* INPUT_H */
/*
 * Copyright (c) 2014-2018, NVIDIA CORPORATION.  All rights reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 * DEALINGS IN THE SOFTWARE.
 */

#ifndef NVGPU_BIOS_H
#define NVGPU_BIOS_H

#include <nvgpu/types.h>

struct gk20a;

#define PERF_PTRS_WIDTH 0x4
#define PERF_PTRS_WIDTH_16 0x2

enum {
	CLOCKS_TABLE = 2,
	CLOCK_PROGRAMMING_TABLE,
	FLL_TABLE,
	VIN_TABLE,
	FREQUENCY_CONTROLLER_TABLE
};

enum {
	PERFORMANCE_TABLE = 0,
	MEMORY_CLOCK_TABLE,
	MEMORY_TWEAK_TABLE,
	POWER_CONTROL_TABLE,
	THERMAL_CONTROL_TABLE,
	THERMAL_DEVICE_TABLE,
	THERMAL_COOLERS_TABLE,
	PERFORMANCE_SETTINGS_SCRIPT,
	CONTINUOUS_VIRTUAL_BINNING_TABLE,
	POWER_SENSORS_TABLE = 0xA,
	POWER_CAPPING_TABLE = 0xB,
	POWER_TOPOLOGY_TABLE = 0xF,
	THERMAL_CHANNEL_TABLE = 0x12,
	VOLTAGE_RAIL_TABLE = 26,
	VOLTAGE_DEVICE_TABLE,
	VOLTAGE_POLICY_TABLE,
	LOWPOWER_TABLE,
	LOWPOWER_GR_TABLE = 32,
	LOWPOWER_MS_TABLE = 33,
};

enum {
	VP_FIELD_TABLE = 0,
	VP_FIELD_REGISTER,
	VP_TRANSLATION_TABLE,
};

struct bit_token {
	u8 token_id;
	u8 data_version;
	u16 data_size;
	u16 data_ptr;
} __packed;

#define BIOS_GET_FIELD(value, name) ((value & name##_MASK) >> name##_SHIFT)

struct fll_descriptor_header {
	u8 version;
	u8 size;
} __packed;

#define FLL_DESCRIPTOR_HEADER_10_SIZE_4     4U
#define FLL_DESCRIPTOR_HEADER_10_SIZE_6     6U

struct fll_descriptor_header_10 {
	u8 version;
	u8 header_size;
	u8 entry_size;
	u8 entry_count;
	u16 max_min_freq_mhz;
} __packed;

#define FLL_DESCRIPTOR_ENTRY_10_SIZE     15U

struct fll_descriptor_entry_10 {
	u8 fll_device_type;
	u8 clk_domain;
	u8 fll_device_id;
	u16 lut_params;
	u8 vin_idx_logic;
	u8 vin_idx_sram;
	u16 fll_params;
	u8 min_freq_vfe_idx;
	u8 freq_ctrl_idx;
	u16 ref_freq_mhz;
	u16 ffr_cutoff_freq_mhz;
} __packed;

#define NV_FLL_DESC_FLL_PARAMS_MDIV_MASK 0x1F
#define NV_FLL_DESC_FLL_PARAMS_MDIV_SHIFT 0

#define NV_FLL_DESC_FLL_PARAMS_SKIP_PLDIV_BELOW_DVCO_MIN_MASK 0x20
#define NV_FLL_DESC_FLL_PARAMS_SKIP_PLDIV_BELOW_DVCO_MIN_SHIFT 5

#define NV_FLL_DESC_LUT_PARAMS_VSELECT_MASK 0x3
#define NV_FLL_DESC_LUT_PARAMS_VSELECT_SHIFT 0

#define NV_FLL_DESC_LUT_PARAMS_HYSTERISIS_THRESHOLD_MASK 0x3C
#define NV_FLL_DESC_LUT_PARAMS_HYSTERISIS_THRESHOLD_SHIFT 2

struct vin_descriptor_header_10 {
	u8 version;
	u8 header_sizee;
	u8 entry_size;
	u8 entry_count;
	u8 flags0;
	u32 vin_cal;
} __packed;

struct vin_descriptor_entry_10 {
	u8 vin_device_type;
	u8 volt_domain_vbios;
	u8 vin_device_id;
} __packed;

#define NV_VIN_DESC_FLAGS0_VIN_CAL_REVISION_MASK 0x7
#define NV_VIN_DESC_FLAGS0_VIN_CAL_REVISION_SHIFT 0

#define NV_VIN_DESC_FLAGS0_VIN_CAL_TYPE_MASK 0xF0
#define NV_VIN_DESC_FLAGS0_VIN_CAL_TYPE_SHIFT 4

#define NV_VIN_DESC_FLAGS0_DISABLE_CONTROL_MASK 0x8
#define NV_VIN_DESC_FLAGS0_DISABLE_CONTROL_SHIFT 3

#define NV_VIN_DESC_VIN_CAL_SLOPE_FRACTION_MASK 0x1FF
#define NV_VIN_DESC_VIN_CAL_SLOPE_FRACTION_SHIFT 0

#define NV_VIN_DESC_VIN_CAL_SLOPE_INTEGER_MASK 0x3C00
#define NV_VIN_DESC_VIN_CAL_SLOPE_INTEGER_SHIFT  10

#define NV_VIN_DESC_VIN_CAL_INTERCEPT_FRACTION_MASK 0x3C000
#define NV_VIN_DESC_VIN_CAL_INTERCEPT_FRACTION_SHIFT 14

#define NV_VIN_DESC_VIN_CAL_INTERCEPT_INTEGER_MASK 0xFFC0000
#define NV_VIN_DESC_VIN_CAL_INTERCEPT_INTEGER_SHIFT 18

#define NV_VIN_DESC_VIN_CAL_OFFSET_MASK 0x7F
#define NV_VIN_DESC_VIN_CAL_OFFSET_SHIFT 0

#define NV_VIN_DESC_VIN_CAL_GAIN_MASK 0xF80
#define NV_VIN_DESC_VIN_CAL_GAIN_SHIFT 7

#define VBIOS_CLOCKS_TABLE_1X_HEADER_SIZE_07 0x07U
struct vbios_clocks_table_1x_header {
	u8 version;
	u8 header_size;
	u8 entry_size;
	u8 entry_count;
	u8 clocks_hal;
	u16 cntr_sampling_periodms;
} __packed;

#define VBIOS_CLOCKS_TABLE_35_HEADER_SIZE_09 0x09U
struct vbios_clocks_table_35_header {
	u8 version;
	u8 header_size;
	u8 entry_size;
	u8 entry_count;
	u8 clocks_hal;
	u16 cntr_sampling_periodms;
	u16 reference_window;
} __packed;

#define VBIOS_CLOCKS_TABLE_1X_ENTRY_SIZE_09                                0x09U
struct vbios_clocks_table_1x_entry {
	u8 flags0;
	u16 param0;
	u32 param1;
	u16 param2;
} __packed;

#define VBIOS_CLOCKS_TABLE_35_ENTRY_SIZE_11                                0x0BU
struct vbios_clocks_table_35_entry {
	u8 flags0;
	u16 param0;
	u32 param1;
	u16 param2;
	u16 param3;
} __packed;

#define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_FLAGS0_USAGE_MASK                    0x1F
#define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_FLAGS0_USAGE_SHIFT                   0
#define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_FLAGS0_USAGE_FIXED                   0x00
#define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_FLAGS0_USAGE_MASTER                  0x01
#define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_FLAGS0_USAGE_SLAVE                   0x02

#define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM0_PROG_CLK_PROG_IDX_FIRST_MASK  0xFF
#define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM0_PROG_CLK_PROG_IDX_FIRST_SHIFT  0
#define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM0_PROG_CLK_PROG_IDX_LAST_MASK  0xFF00
#define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM0_PROG_CLK_PROG_IDX_LAST_SHIFT 0x08

#define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM1_FIXED_FREQUENCY_MHZ_MASK        0xFFFF
#define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM1_FIXED_FREQUENCY_MHZ_SHIFT       0
#define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM1_MASTER_FREQ_OC_DELTA_MIN_MHZ_MASK 0xFFFF
#define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM1_MASTER_FREQ_OC_DELTA_MIN_MHZ_SHIFT 0

#define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM1_MASTER_FREQ_OC_DELTA_MAX_MHZ_MASK 0xFFFF0000
#define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM1_MASTER_FREQ_OC_DELTA_MAX_MHZ_SHIFT 0

#define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM1_SLAVE_MASTER_DOMAIN_MASK         0xF
#define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM1_SLAVE_MASTER_DOMAIN_SHIFT       0

#define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM2_PROG_NOISE_UNAWARE_ORDERING_IDX_MASK 0xF
#define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM2_PROG_NOISE_UNAWARE_ORDERING_IDX_SHIFT 0

#define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM2_PROG_NOISE_AWARE_ORDERING_IDX_MASK     0xF0
#define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM2_PROG_NOISE_AWARE_ORDERING_IDX_SHIFT   4

#define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM2_PROG_FORCE_NOISE_UNAWARE_ORDERING_MASK 0x100
#define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM2_PROG_FORCE_NOISE_UNAWARE_ORDERING_SHIFT 8
#define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM2_PROG_FORCE_NOISE_UNAWARE_ORDERING_FALSE   0x00
#define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM2_PROG_FORCE_NOISE_UNAWARE_ORDERING_TRUE    0x01

#define NV_VBIOS_CLOCKS_TABLE_35_ENTRY_PARAM2_PROG_PRE_VOLT_ORDERING_IDX_MASK 0xF
#define NV_VBIOS_CLOCKS_TABLE_35_ENTRY_PARAM2_PROG_PRE_VOLT_ORDERING_IDX_SHIFT 0

#define NV_VBIOS_CLOCKS_TABLE_35_ENTRY_PARAM2_PROG_POST_VOLT_ORDERING_IDX_MASK     0xF0
#define NV_VBIOS_CLOCKS_TABLE_35_ENTRY_PARAM2_PROG_POST_VOLT_ORDERING_IDX_SHIFT   4

#define NV_VBIOS_CLOCKS_TABLE_35_ENTRY_PARAM3_CLK_MONITOR_THRESHOLD_MIN_MASK  0xFF
#define NV_VBIOS_CLOCKS_TABLE_35_ENTRY_PARAM3_CLK_MONITOR_THRESHOLD_MIN_SHIFT  0
#define NV_VBIOS_CLOCKS_TABLE_35_ENTRY_PARAM3_CLK_MONITOR_THRESHOLD_MAX_MASK  0xFF00
#define NV_VBIOS_CLOCKS_TABLE_35_ENTRY_PARAM3_CLK_MONITOR_THRESHOLD_MAX_SHIFT 0x08

#define VBIOS_CLOCK_PROGRAMMING_TABLE_1X_HEADER_SIZE_08                    0x08U
struct vbios_clock_programming_table_1x_header {
	u8 version;
	u8 header_size;
	u8 entry_size;
	u8 entry_count;
	u8 slave_entry_size;
	u8 slave_entry_count;
	u8 vf_entry_size;
	u8 vf_entry_count;
} __packed;

#define VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_SIZE_05                     0x05U
#define VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_SIZE_0D                     0x0DU
struct vbios_clock_programming_table_1x_entry {
	u8 flags0;
	u16 freq_max_mhz;
	u8 param0;
	u8 param1;
	u32 rsvd;
	u32 rsvd1;
} __packed;

#define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_FLAGS0_TYPE_MASK          0xF
#define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_FLAGS0_TYPE_SHIFT         0
#define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_FLAGS0_TYPE_MASTER_RATIO   0x00
#define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_FLAGS0_TYPE_MASTER_TABLE   0x01
#define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_FLAGS0_TYPE_SLAVE          0x02

#define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_FLAGS0_SOURCE_MASK          0x70
#define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_FLAGS0_SOURCE_SHIFT         4
#define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_FLAGS0_SOURCE_PLL          0x00
#define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_FLAGS0_SOURCE_ONE_SOURCE   0x01
#define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_FLAGS0_SOURCE_FLL        0x02

#define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_FLAGS0_OVOC_ENABLED_MASK    0x80
#define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_FLAGS0_OVOC_ENABLED_SHIFT   7
#define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_FLAGS0_OVOC_ENABLED_FALSE  0x00
#define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_FLAGS0_OVOC_ENABLED_TRUE   0x01

#define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_PARAM0_PLL_PLL_INDEX_MASK   0xFF
#define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_PARAM0_PLL_PLL_INDEX_SHIFT  0

#define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_PARAM1_PLL_FREQ_STEP_SIZE_MASK   0xFF
#define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_PARAM1_PLL_FREQ_STEP_SIZE_SHIFT  0

#define VBIOS_CLOCK_PROGRAMMING_TABLE_1X_SLAVE_ENTRY_SIZE_03               0x03U
struct vbios_clock_programming_table_1x_slave_entry {
	u8 clk_dom_idx;
	u16 param0;
} __packed;

#define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_SLAVE_ENTRY_PARAM0_MASTER_RATIO_RATIO_MASK 0xFF
#define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_SLAVE_ENTRY_PARAM0_MASTER_RATIO_RATIO_SHIFT 0

#define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_SLAVE_ENTRY_PARAM0_MASTER_TABLE_FREQ_MASK  0x3FFF
#define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_SLAVE_ENTRY_PARAM0_MASTER_TABLE_FREQ_SHIFT  0

#define VBIOS_CLOCK_PROGRAMMING_TABLE_1X_VF_ENTRY_SIZE_02                  0x02U
struct vbios_clock_programming_table_1x_vf_entry {
	u8 vfe_idx;
	u8 param0;
} __packed;

#define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_VF_ENTRY_PARAM0_FLL_GAIN_VFE_IDX_MASK 0xFF
#define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_VF_ENTRY_PARAM0_FLL_GAIN_VFE_IDX_SHIFT 0

struct vbios_vfe_3x_header_struct {
	u8 version;
	u8 header_size;
	u8 vfe_var_entry_size;
	u8 vfe_var_entry_count;
	u8 vfe_equ_entry_size;
	u8 vfe_equ_entry_count;
	u8 polling_periodms;
} __packed;

#define VBIOS_VFE_3X_VAR_ENTRY_SIZE_11                                     0x11U
#define VBIOS_VFE_3X_VAR_ENTRY_SIZE_19