mc2-scripts-and-benchmarks.git - Benchmarks and execution scripts for testing spatial isolation and SMT interference in MC^2

	Commit message (Collapse)	Author	Age
*	Benchmarks: Print full result paths from runner scripts	Joshua Bakita	2021-03-12
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*	Benchmarks: Allow test CPU specification in top-level runner scripts	Joshua Bakita	2021-03-11
\| \| \| \|	This allows artifact evaluators to test on CPUs other than CPU 15
*	Benchmarks: Make sure we always build with the correct config	Joshua Bakita	2021-03-09
\| \| \| \| \|	The current implementation of this is terrible, but seems to work. This should probably be replaced with some compile-time defines.
*	Get all the SD-VBS tests running and add a helper script + typo fix	Joshua Bakita	2020-10-22
\| \| \| \| \| \| \|	- Add a run_all_sd-vbs.sh script - Fix a typo in run_all_tacle.sh - Fix an issue with reversed arguments for asynchronous task pairs in run_bench.sh
*	Add pair benchmarking and isolation specification into run_bench.sh	Joshua Bakita	2020-10-22
	This allows `run_bench.sh` to replace all previous general paired benchmarking scripts. See `run_everything.sh` for an example of how to use the new script. This also fixes two critical bugs present in the old scripts: 1. The cpus_list was incorrectly set for resctrl when running synchronous pair timing with L2+L3 isolation (i). Each write to that file replaces the previous contents, and it was previously written once for each core. This prevented the entire 1st core from using any L3 cache. 2. The competing task list was indexed improperly in the asynchronous pair timing script. This caused the competing task to always be identical to the task being profiled. These issues combine to imply that in the rejected RTSS'20 paper: - All Level-C SMT timing data is suspect - Level-A and -B SMT timing data with L2+L3 isolation (i) is wildly optimistic