/*
* Copyright (c) 2016-2018, NVIDIA CORPORATION.  All rights reserved.
*
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 * DEALINGS IN THE SOFTWARE.
*/

#ifndef NVGPU_PMUIF_GPMUIFPMGR_H
#define NVGPU_PMUIF_GPMUIFPMGR_H

#include "ctrl/ctrlpmgr.h"
#include "gpmuifboardobj.h"
#include <nvgpu/flcnif_cmn.h>

struct nv_pmu_pmgr_i2c_device_desc {
	struct nv_pmu_boardobj super;
	u8 dcb_index;
	u16 i2c_address;
	u32 i2c_flags;
	u8 i2c_port;
};

#define NV_PMU_PMGR_I2C_DEVICE_DESC_TABLE_MAX_DEVICES              (32U)

struct nv_pmu_pmgr_i2c_device_desc_table {
	u32 dev_mask;
	struct nv_pmu_pmgr_i2c_device_desc
	devices[NV_PMU_PMGR_I2C_DEVICE_DESC_TABLE_MAX_DEVICES];
};

struct nv_pmu_pmgr_pwr_device_desc {
	struct nv_pmu_boardobj super;
	u32 power_corr_factor;
};

#define NV_PMU_PMGR_PWR_DEVICE_INA3221_CH_NUM                      0x03U

struct nv_pmu_pmgr_pwr_device_desc_ina3221 {
	struct nv_pmu_pmgr_pwr_device_desc super;
	u8 i2c_dev_idx;
	struct ctrl_pmgr_pwr_device_info_rshunt
		r_shuntm_ohm[NV_PMU_PMGR_PWR_DEVICE_INA3221_CH_NUM];
	u16 configuration;
	u16 mask_enable;
	u32 event_mask;
	u16 curr_correct_m;
	s16 curr_correct_b;
};

union nv_pmu_pmgr_pwr_device_desc_union {
	struct nv_pmu_boardobj board_obj;
	struct nv_pmu_pmgr_pwr_device_desc pwr_dev;
	struct nv_pmu_pmgr_pwr_device_desc_ina3221 ina3221;
};

struct nv_pmu_pmgr_pwr_device_ba_info {