mc2-scripts-and-benchmarks.git - Benchmarks and execution scripts for testing spatial isolation and SMT interference in MC^2

path: root/all_pairs/source/anagram/anagram_compare.h

	Commit message (Expand)	Author	Age
*	Reorganize and commit all the modified TACLeBench code and run scripts	Joshua Bakita	2019-10-07

/* Copyright 2021 Joshua Bakita * SPDX-License-Identifier: MIT */ // TODO(jbakita): Don't depend on these. #include <nvgpu/gk20a.h> // For struct gk20a #include <os/linux/os_linux.h> // For struct nvgpu_os_linux /* Runlist Channel A timeslice group (TSG) is composed of channels. Each channel is a FIFO queue of GPU commands. These commands are typically queued from userspace. `INST_PTR` points to a GPU Instance Block which contains pointers to the GPU virtual address space for this context. All channels in a TSG point to the same GPU Instance Block. ENTRY_TYPE (T) : type of this entry: ENTRY_TYPE_CHAN CHID (ID) : identifier of the channel to run (overlays ENTRY_ID) RUNQUEUE_SELECTOR (Q) : selects which PBDMA should run this channel if more than one PBDMA is supported by the runlist INST_PTR_LO : lower 20 bits of the 4k-aligned instance block pointer INST_PTR_HI : upper 32 bit of instance block pointer INST_TARGET (TGI) : aperture of the instance block USERD_PTR_LO : upper 24 bits of the low 32 bits, of the 512-byte-aligned USERD pointer USERD_PTR_HI : upper 32 bits of USERD pointer USERD_TARGET (TGU) : aperture of the USERD data structure */ enum ENTRY_TYPE {ENTRY_TYPE_CHAN = 0, ENTRY_TYPE_TSG = 1}; enum INST_TARGET {TARGET_VID_MEM = 0, TARGET_SYS_MEM_COHERENT = 2, TARGET_SYS_MEM_NONCOHERENT = 3}; struct runlist_chan { // 0:63 enum ENTRY_TYPE entry_type:1; uint32_t runqueue_selector:1; uint32_t padding:2; enum INST_TARGET inst_target:2; uint32_t padding2:2; uint32_t userd_ptr_lo:24; uint32_t userd_ptr_hi:32; // 64:128 uint32_t chid:12; uint32_t inst_ptr_lo:20; uint32_t inst_ptr_hi:32; } __attribute__((packed)); /* Runlist TSG (TimeSlice Group) The runlist is composed of timeslice groups (TSG). Each TSG corresponds to a single virtual address space on the GPU and contains `TSG_LENGTH` channels. These channels and virtual address space are accessible to the GPU host unit for use until the timeslice expires or a TSG switch is forcibly initiated via a write to `NV_PFIFO_PREEMPT`. timeslice = (TSG_TIMESLICE_TIMEOUT << TSG_TIMESLICE_SCALE) * 1024 nanoseconds ENTRY_TYPE (T) : type of this entry: ENTRY_TYPE_TSG TSGID : identifier of the Timeslice group (overlays ENTRY_ID) TSG_LENGTH : number of channels that are part of this timeslice group TIMESLICE_SCALE : scale factor for the TSG's timeslice TIMESLICE_TIMEOUT : timeout amount for the TSG's timeslice */ struct entry_tsg { // 0:63 enum ENTRY_TYPE entry_type:1; uint64_t padding:15; uint32_t timeslice_scale:4; uint64_t padding2:4; uint32_t timeslice_timeout:8; uint32_t tsg_length:8; uint32_t padding3:24; // 64:128 uint32_t tsgid:12; uint64_t padding4:52; } __attribute__((packed)); enum PREEMPT_TYPE {PREEMPT_TYPE_CHANNEL = 0, PREEMPT_TYPE_TSG = 1}; /* Preempt ID/CHID : Id of TSG or channel to preempt */ #define NV_PFIFO_PREEMPT 0x00002634 struct pfifo_preempt { uint32_t id:12; uint32_t padding:8; bool is_pending:1; uint32_t padding2:3; enum PREEMPT_TYPE type:2; uint32_t padding3:6; } __attribute__((packed)); #define NV_PFIFO_RUNLIST_PREEMPT 0x00002638 struct runlist_preempt { bool runlist_0:1; bool runlist_1:1;