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authorleochanj105 <leochanj@live.unc.edu>2021-10-26 13:22:32 -0400
committerleochanj105 <leochanj@live.unc.edu>2021-10-26 13:22:32 -0400
commit14c854543b1a3cf344a371a5b45595657f95786b (patch)
tree70f752880522e5e44669af365754ac0f649dce81 /SD-VBS/preload-times/mser
parent5e2ccfae0532ddd89bcc04bf14aad451e9c79785 (diff)
add deadlines and costs
Diffstat (limited to 'SD-VBS/preload-times/mser')
-rw-r--r--SD-VBS/preload-times/mser/T_cif.txt9
-rw-r--r--SD-VBS/preload-times/mser/T_fullhd.txt9
-rw-r--r--SD-VBS/preload-times/mser/T_qcif.txt9
-rw-r--r--SD-VBS/preload-times/mser/T_sim.txt9
-rw-r--r--SD-VBS/preload-times/mser/T_sim_fast.txt9
-rw-r--r--SD-VBS/preload-times/mser/T_sqcif.txt9
-rw-r--r--SD-VBS/preload-times/mser/T_test.txt9
-rw-r--r--SD-VBS/preload-times/mser/T_vga.txt9
8 files changed, 0 insertions, 72 deletions
diff --git a/SD-VBS/preload-times/mser/T_cif.txt b/SD-VBS/preload-times/mser/T_cif.txt
deleted file mode 100644
index 56f14c8..0000000
--- a/SD-VBS/preload-times/mser/T_cif.txt
+++ /dev/null
@@ -1,9 +0,0 @@
1Cycles elapsed - 17564120
2
3Input size - (264x352)
4Cycles elapsed - 43634710
5
6
7real 0m0.023s
8user 0m0.023s
9sys 0m0.000s
diff --git a/SD-VBS/preload-times/mser/T_fullhd.txt b/SD-VBS/preload-times/mser/T_fullhd.txt
deleted file mode 100644
index 45db824..0000000
--- a/SD-VBS/preload-times/mser/T_fullhd.txt
+++ /dev/null
@@ -1,9 +0,0 @@
1Cycles elapsed - 226852710
2
3Input size - (1920x1080)
4Cycles elapsed - 11064831740
5
6
7real 0m0.431s
8user 0m0.403s
9sys 0m0.028s
diff --git a/SD-VBS/preload-times/mser/T_qcif.txt b/SD-VBS/preload-times/mser/T_qcif.txt
deleted file mode 100644
index 2571249..0000000
--- a/SD-VBS/preload-times/mser/T_qcif.txt
+++ /dev/null
@@ -1,9 +0,0 @@
1Cycles elapsed - 4424280
2
3Input size - (132x176)
4Cycles elapsed - 18051495
5
6
7real 0m0.008s
8user 0m0.008s
9sys 0m0.000s
diff --git a/SD-VBS/preload-times/mser/T_sim.txt b/SD-VBS/preload-times/mser/T_sim.txt
deleted file mode 100644
index dfdbf56..0000000
--- a/SD-VBS/preload-times/mser/T_sim.txt
+++ /dev/null
@@ -1,9 +0,0 @@
1Cycles elapsed - 1140055
2
3Input size - (66x88)
4Cycles elapsed - 4858315
5
6
7real 0m0.003s
8user 0m0.003s
9sys 0m0.000s
diff --git a/SD-VBS/preload-times/mser/T_sim_fast.txt b/SD-VBS/preload-times/mser/T_sim_fast.txt
deleted file mode 100644
index 16a45e7..0000000
--- a/SD-VBS/preload-times/mser/T_sim_fast.txt
+++ /dev/null
@@ -1,9 +0,0 @@
1Cycles elapsed - 373275
2
3Input size - (36x48)
4Cycles elapsed - 1712655
5
6
7real 0m0.001s
8user 0m0.001s
9sys 0m0.000s
diff --git a/SD-VBS/preload-times/mser/T_sqcif.txt b/SD-VBS/preload-times/mser/T_sqcif.txt
deleted file mode 100644
index f5d7315..0000000
--- a/SD-VBS/preload-times/mser/T_sqcif.txt
+++ /dev/null
@@ -1,9 +0,0 @@
1Cycles elapsed - 1416520
2
3Input size - (66x88)
4Cycles elapsed - 5828060
5
6
7real 0m0.003s
8user 0m0.003s
9sys 0m0.000s
diff --git a/SD-VBS/preload-times/mser/T_test.txt b/SD-VBS/preload-times/mser/T_test.txt
deleted file mode 100644
index 8df6d92..0000000
--- a/SD-VBS/preload-times/mser/T_test.txt
+++ /dev/null
@@ -1,9 +0,0 @@
1Cycles elapsed - 88690
2
3Input size - (12x16)
4Cycles elapsed - 217490
5
6
7real 0m0.001s
8user 0m0.001s
9sys 0m0.000s
diff --git a/SD-VBS/preload-times/mser/T_vga.txt b/SD-VBS/preload-times/mser/T_vga.txt
deleted file mode 100644
index 22c28d0..0000000
--- a/SD-VBS/preload-times/mser/T_vga.txt
+++ /dev/null
@@ -1,9 +0,0 @@
1Cycles elapsed - 54885530
2
3Input size - (480x640)
4Cycles elapsed - 101965395
5
6
7real 0m0.054s
8user 0m0.054s
9sys 0m0.000s