mc2-scripts-and-benchmarks.git - Benchmarks and execution scripts for testing spatial isolation and SMT interference in MC^2

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author	Joshua Bakita <jbakita@cs.unc.edu>	2020-10-22 00:24:34 -0400
committer	Joshua Bakita <jbakita@cs.unc.edu>	2020-10-22 00:25:05 -0400
commit	4f634d4cd3254dfc68b65e63be32708105032101 (patch)
tree	0ebd638a40ae68d788c883e9f38a857b1225463e /ABmod-light-7-Tacle-Tacle-DIS/1/l3alloc.csv
parent	3b0aa125061b362b23ecf66afe8319e3a268c874 (diff)

Fix Makefiles so that a custom CFLAGS doesn't break the build

Diffstat (limited to 'ABmod-light-7-Tacle-Tacle-DIS/1/l3alloc.csv')

0 files changed, 0 insertions, 0 deletions

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/* * GK20A Graphics Engine * * Copyright (c) 2011-2021, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * DEALINGS IN THE SOFTWARE. */ #ifndef GR_GK20A_H #define GR_GK20A_H #include <nvgpu/types.h> #include "gr_ctx_gk20a.h" #include "mm_gk20a.h" #include <nvgpu/power_features/pg.h> #include <nvgpu/comptags.h> #include <nvgpu/cond.h> #define GR_IDLE_CHECK_DEFAULT 10 /* usec */ #define GR_IDLE_CHECK_MAX 200 /* usec */ #define GR_FECS_POLL_INTERVAL 5 /* usec */ #define INVALID_SCREEN_TILE_ROW_OFFSET 0xFFFFFFFF #define INVALID_MAX_WAYS 0xFFFFFFFF #define GK20A_FECS_UCODE_IMAGE "fecs.bin" #define GK20A_GPCCS_UCODE_IMAGE "gpccs.bin" #define GK20A_GR_MAX_PES_PER_GPC 3 #define GK20A_TIMEOUT_FPGA 100000 /* 100 sec */ /* Flags to be passed to g->ops.gr.alloc_obj_ctx() */ #define NVGPU_OBJ_CTX_FLAGS_SUPPORT_GFXP (1 << 1) #define NVGPU_OBJ_CTX_FLAGS_SUPPORT_CILP (1 << 2) /* * allocate a minimum of 1 page (4KB) worth of patch space, this is 512 entries * of address and data pairs */ #define PATCH_CTX_SLOTS_REQUIRED_PER_ENTRY 2 #define PATCH_CTX_SLOTS_PER_PAGE \ (PAGE_SIZE/(PATCH_CTX_SLOTS_REQUIRED_PER_ENTRY * sizeof(u32))) #define PATCH_CTX_ENTRIES_FROM_SIZE(size) (size/sizeof(u32)) #define NVGPU_PREEMPTION_MODE_GRAPHICS_WFI (1 << 0) #define NVGPU_PREEMPTION_MODE_GRAPHICS_GFXP (1 << 1) #define NVGPU_PREEMPTION_MODE_COMPUTE_WFI (1 << 0) #define NVGPU_PREEMPTION_MODE_COMPUTE_CTA (1 << 1) #define NVGPU_PREEMPTION_MODE_COMPUTE_CILP (1 << 2) #define CTXSW_INTR0 BIT32(0) #define CTXSW_INTR1 BIT32(1) #define MAILBOX_VALUE_TIMESTAMP_BUFFER_FULL 0x26 struct tsg_gk20a; struct channel_gk20a; struct nvgpu_warpstate; enum ctxsw_addr_type; enum /* global_ctx_buffer */ { CIRCULAR = 0, PAGEPOOL = 1, ATTRIBUTE = 2, CIRCULAR_VPR = 3, PAGEPOOL_VPR = 4, ATTRIBUTE_VPR = 5, GOLDEN_CTX = 6, PRIV_ACCESS_MAP = 7, /* #8 is reserved */ FECS_TRACE_BUFFER = 9, NR_GLOBAL_CTX_BUF = 10 }; /* either ATTRIBUTE or ATTRIBUTE_VPR maps to ATTRIBUTE_VA */ enum /*global_ctx_buffer_va */ { CIRCULAR_VA = 0, PAGEPOOL_VA = 1, ATTRIBUTE_VA = 2, GOLDEN_CTX_VA = 3, PRIV_ACCESS_MAP_VA = 4, /* #5 is reserved */ FECS_TRACE_BUFFER_VA = 6, NR_GLOBAL_CTX_BUF_VA = 7 }; enum { WAIT_UCODE_LOOP, WAIT_UCODE_TIMEOUT, WAIT_UCODE_ERROR, WAIT_UCODE_OK }; enum { GR_IS_UCODE_OP_EQUAL, GR_IS_UCODE_OP_NOT_EQUAL, GR_IS_UCODE_OP_AND, GR_IS_UCODE_OP_LESSER, GR_IS_UCODE_OP_LESSER_EQUAL, GR_IS_UCODE_OP_SKIP }; enum { eUcodeHandshakeInitComplete = 1, eUcodeHandshakeMethodFinished }; enum { ELCG_MODE = (1 << 0), BLCG_MODE = (1 << 1), INVALID_MODE = (1 << 2) }; enum { NVGPU_EVENT_ID_BPT_INT = 0, NVGPU_EVENT_ID_BPT_PAUSE, NVGPU_EVENT_ID_BLOCKING_SYNC, NVGPU_EVENT_ID_CILP_PREEMPTION_STARTED, NVGPU_EVENT_ID_CILP_PREEMPTION_COMPLETE, NVGPU_EVENT_ID_GR_SEMAPHORE_WRITE_AWAKEN, NVGPU_EVENT_ID_MAX, }; #ifndef GR_GO_IDLE_BUNDLE #define GR_GO_IDLE_BUNDLE 0x0000e100 /* --V-B */ #endif struct gr_channel_map_tlb_entry { u32 curr_ctx; u32 chid; u32 tsgid; }; struct gr_zcull_gk20a { u32 aliquot_width; u32 aliquot_height; u32 aliquot_size; u32 total_aliquots; u32 width_align_pixels; u32 height_align_pixels; u32 pixel_squares_by_aliquots; }; struct gr_zcull_info { u32 width_align_pixels; u32 height_align_pixels; u32 pixel_squares_by_aliquots; u32 aliquot_total; u32 region_byte_multiplier; u32 region_header_size; u32 subregion_header_size; u32 subregion_width_align_pixels; u32 subregion_height_align_pixels; u32 subregion_count; }; #define GK20A_ZBC_COLOR_VALUE_SIZE 4 /* RGBA */ #define GK20A_STARTOF_ZBC_TABLE 1U /* index zero reserved to indicate "not ZBCd" */ #define GK20A_SIZEOF_ZBC_TABLE 16 /* match ltcs_ltss_dstg_zbc_index_address width (4) */ #define GK20A_ZBC_TABLE_SIZE (16 - 1) #define GK20A_ZBC_TYPE_INVALID 0 #define GK20A_ZBC_TYPE_COLOR 1 #define GK20A_ZBC_TYPE_DEPTH 2 #define T19X_ZBC 3 struct zbc_color_table { u32 color_ds[GK20A_ZBC_COLOR_VALUE_SIZE]; u32 color_l2[GK20A_ZBC_COLOR_VALUE_SIZE]; u32 format; u32 ref_cnt; }; struct zbc_depth_table { u32 depth; u32 format; u32 ref_cnt; }; struct zbc_s_table { u32 stencil; u32 format; u32 ref_cnt; }; struct zbc_entry { u32 color_ds[GK20A_ZBC_COLOR_VALUE_SIZE]; u32 color_l2[GK20A_ZBC_COLOR_VALUE_SIZE]; u32 depth; u32 type; /* color or depth */ u32 format; }; struct zbc_query_params { u32 color_ds[GK20A_ZBC_COLOR_VALUE_SIZE]; u32 color_l2[GK20A_ZBC_COLOR_VALUE_SIZE]; u32 depth; u32 ref_cnt; u32 format; u32 type; /* color or depth */ u32 index_size; /* [out] size, [in] index */ }; struct sm_info { u32 gpc_index; u32 tpc_index; u32 sm_index; u32 global_tpc_index; }; #if defined(CONFIG_GK20A_CYCLE_STATS) struct gk20a_cs_snapshot_client; struct gk20a_cs_snapshot; #endif struct gr_gk20a_isr_data { u32 addr; u32 data_lo; u32 data_hi; u32 curr_ctx; struct channel_gk20a *ch; u32 offset; u32 sub_chan; u32 class_num; }; struct gr_ctx_buffer_desc { void (*destroy)(struct gk20a *, struct gr_ctx_buffer_desc *); struct nvgpu_mem mem; void *priv; }; struct nvgpu_preemption_modes_rec { u32 graphics_preemption_mode_flags; /* supported preemption modes */ u32 compute_preemption_mode_flags; /* supported preemption modes */ u32 default_graphics_preempt_mode; /* default mode */ u32 default_compute_preempt_mode; /* default mode */ }; struct gr_gk20a { struct gk20a *g; struct { bool dynamic; u32 buffer_size; u32 buffer_total_size; bool golden_image_initialized; u32 golden_image_size; u32 *local_golden_image; u32 hwpm_ctxsw_buffer_offset_map_count; struct ctxsw_buf_offset_map_entry *hwpm_ctxsw_buffer_offset_map; u32 zcull_ctxsw_image_size; u32 pm_ctxsw_image_size; u32 buffer_header_size; u32 priv_access_map_size; u32 fecs_trace_buffer_size; struct gr_ucode_gk20a ucode; struct av_list_gk20a sw_bundle_init; struct av_list_gk20a sw_method_init; struct aiv_list_gk20a sw_ctx_load; struct av_list_gk20a sw_non_ctx_load; struct av_list_gk20a sw_veid_bundle_init; struct av64_list_gk20a sw_bundle64_init; struct { struct aiv_list_gk20a sys; struct aiv_list_gk20a gpc; struct aiv_list_gk20a tpc; struct aiv_list_gk20a zcull_gpc; struct aiv_list_gk20a ppc; struct aiv_list_gk20a pm_sys; struct aiv_list_gk20a pm_gpc; struct aiv_list_gk20a pm_tpc; struct aiv_list_gk20a pm_ppc; struct aiv_list_gk20a perf_sys; struct aiv_list_gk20a perf_gpc; struct aiv_list_gk20a fbp; struct aiv_list_gk20a fbp_router; struct aiv_list_gk20a gpc_router; struct aiv_list_gk20a pm_ltc; struct aiv_list_gk20a pm_fbpa; struct aiv_list_gk20a perf_sys_router;


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