/************************************************************************ * s2io.c: A Linux PCI-X Ethernet driver for Neterion 10GbE Server NIC * Copyright(c) 2002-2005 Neterion Inc. * This software may be used and distributed according to the terms of * the GNU General Public License (GPL), incorporated herein by reference. * Drivers based on or derived from this code fall under the GPL and must * retain the authorship, copyright and license notice. This file is not * a complete program and may only be used when the entire operating * system is licensed under the GPL. * See the file COPYING in this distribution for more information. * * Credits: * Jeff Garzik : For pointing out the improper error condition * check in the s2io_xmit routine and also some * issues in the Tx watch dog function. Also for * patiently answering all those innumerable * questions regaring the 2.6 porting issues. * Stephen Hemminger : Providing proper 2.6 porting mechanism for some * macros available only in 2.6 Kernel. * Francois Romieu : For pointing out all code part that were * deprecated and also styling related comments. * Grant Grundler : For helping me get rid of some Architecture * dependent code. * Christopher Hellwig : Some more 2.6 specific issues in the driver. * * The module loadable parameters that are supported by the driver and a brief * explaination of all the variables. * rx_ring_num : This can be used to program the number of receive rings used * in the driver. * rx_ring_sz: This defines the number of descriptors each ring can have. This * is also an array of size 8. * rx_ring_mode: This defines the operation mode of all 8 rings. The valid * values are 1, 2 and 3. * tx_fifo_num: This defines the number of Tx FIFOs thats used int the driver. * tx_fifo_len: This too is an array of 8. Each element defines the number of * Tx descriptors that can be associated with each corresponding FIFO. ************************************************************************/ #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include /* local include */ #include "s2io.h" #include "s2io-regs.h" #define DRV_VERSION "2.0.11.2" /* S2io Driver name & version. */ static char s2io_driver_name[] = "Neterion"; static char s2io_driver_version[] = DRV_VERSION; static int rxd_size[4] = {32,48,48,64}; static int rxd_count[4] = {127,85,85,63}; static inline int RXD_IS_UP2DT(RxD_t *rxdp) { int ret; ret = ((!(rxdp->Control_1 & RXD_OWN_XENA)) && (GET_RXD_MARKER(rxdp->Control_2) != THE_RXD_MARK)); return ret; } /* * Cards with following subsystem_id have a link state indication * problem, 600B, 600C, 600D, 640B, 640C and 640D. * macro below identifies these cards given the subsystem_id. */ #define CARDS_WITH_FAULTY_LINK_INDICATORS(dev_type, subid) \ (dev_type == XFRAME_I_DEVICE) ? \ ((((subid >= 0x600B) && (subid <= 0x600D)) || \ ((subid >= 0x640B) && (subid <= 0x640D))) ? 1 : 0) : 0 #define LINK_IS_UP(val64) (!(val64 & (ADAPTER_STATUS_RMAC_REMOTE_FAULT | \ ADAPTER_STATUS_RMAC_LOCAL_FAULT))) #define TASKLET_IN_USE test_and_set_bit(0, (&sp->tasklet_status)) #define PANIC 1 #define LOW 2 static inline int rx_buffer_level(nic_t * sp, int rxb_size, int ring) { int level = 0; mac_info_t *mac_control; mac_control = &sp->mac_control; if ((mac_control->rings[ring].pkt_cnt - rxb_size) > 16) { level = LOW; if (rxb_size <= rxd_count[sp->rxd_mode]) { level = PANIC; } } return level; } /* Ethtool related variables and Macros. */ static char s2io_gstrings[][ETH_GSTRING_LEN] = { "Register test\t(offline)", "Eeprom test\t(offline)", "Link test\t(online)", "RLDRAM test\t(offline)", "BIST Test\t(offline)" }; static char ethtool_stats_keys[][ETH_GSTRING_LEN] = { {"tmac_frms"}, {"tmac_data_octets"}, {"tmac_drop_frms"}, {"tmac_mcst_frms"}, {"tmac_bcst_frms"}, {"tmac_pause_ctrl_frms"}, {"tmac_any_err_frms"}, {"tmac_vld_ip_octets"}, {"tmac_vld_ip"}, {"tmac_drop_ip"}, {"tmac_icmp"}, {"tmac_rst_tcp"}, {"tmac_tcp"}, {"tmac_udp"}, {"rmac_vld_frms"}, {"rmac_data_octets"}, {"rmac_fcs_err_frms"}, {"rmac_drop_frms"}, {"rmac_vld_mcst_frms"}, {"rmac_vld_bcst_frms"}, {"rmac_in_rng_len_err_frms"}, {"rmac_long_frms"}, {"rmac_pause_ctrl_frms"}, {"rmac_discarded_frms"}, {"rmac_usized_frms"}, {"rmac_osized_frms"}, {"rmac_frag_frms"}, {"rmac_jabber_frms"}, {"rmac_ip"}, {"rmac_ip_octets"}, {"rmac_hdr_err_ip"}, {"rmac_drop_ip"}, {"rmac_icmp"}, {"rmac_tcp"}, {"rmac_udp"}, {"rmac_err_drp_udp"}, {"rmac_pause_cnt"}, {"rmac_accepted_ip"}, {"rmac_err_tcp"}, {"\n DRIVER STATISTICS"}, {"single_bit_ecc_errs"}, {"double_bit_ecc_errs"}, ("lro_aggregated_pkts"), ("lro_flush_both_count"), ("lro_out_of_sequence_pkts"), ("lro_flush_due_to_max_pkts"), ("lro_avg_aggr_pkts"), }; #define S2IO_STAT_LEN sizeof(ethtool_stats_keys)/ ETH_GSTRING_LEN #define S2IO_STAT_STRINGS_LEN S2IO_STAT_LEN * ETH_GSTRING_LEN #define S2IO_TEST_LEN sizeof(s2io_gstrings) / ETH_GSTRING_LEN #define S2IO_STRINGS_LEN S2IO_TEST_LEN * ETH_GSTRING_LEN #define S2IO_TIMER_CONF(timer, handle, arg, exp) \ init_timer(&timer); \ timer.function = handle; \ timer.data = (unsigned long) arg; \ mod_timer(&timer, (jiffies + exp)) \ /* Add the vlan */ static void s2io_vlan_rx_register(struct net_device *dev, struct vlan_group *grp) { nic_t *nic = dev->priv; unsigned long flags; spin_lock_irqsave(&nic->tx_lock, flags); nic->vlgrp = grp; spin_unlock_irqrestore(&nic->tx_lock, flags); } /* Unregister the vlan */ static void s2io_vlan_rx_kill_vid(struct net_device *dev, unsigned long vid) { nic_t *nic = dev->priv; unsigned long flags; spin_lock_irqsave(&nic->tx_lock, flags); if (nic->vlgrp) nic->vlgrp->vlan_devices[vid] = NULL; spin_unlock_irqrestore(&nic->tx_lock, flags); } /* * Constants to be programmed into the Xena's registers, to configure * the XAUI. */ #define SWITCH_SIGN 0xA5A5A5A5A5A5A5A5ULL #define END_SIGN 0x0 static const u64 herc_act_dtx_cfg[] = { /* Set address */ 0x8000051536750000ULL, 0x80000515367500E0ULL, /* Write data */ 0x8000051536750004ULL, 0x80000515367500E4ULL, /* Set address */ 0x80010515003F0000ULL, 0x80010515003F00E0ULL, /* Write data */ 0x80010515003F0004ULL, 0x80010515003F00E4ULL, /* Set address */ 0x801205150D440000ULL, 0x801205150D4400E0ULL, /* Write data */ 0x801205150D440004ULL, 0x801205150D4400E4ULL, /* Set address */ 0x80020515F2100000ULL, 0x80020515F21000E0ULL, /* Write data */ 0x80020515F2100004ULL, 0x80020515F21000E4ULL, /* Done */ END_SIGN }; static const u64 xena_mdio_cfg[] = { /* Reset PMA PLL */ 0xC001010000000000ULL, 0xC0010100000000E0ULL, 0xC0010100008000E4ULL, /* Remove Reset from PMA PLL */ 0xC001010000000000ULL, 0xC0010100000000E0ULL, 0xC0010100000000E4ULL, END_SIGN }; static const u64 xena_dtx_cfg[] = { 0x8000051500000000ULL, 0x80000515000000E0ULL, 0x80000515D93500E4ULL, 0x8001051500000000ULL, 0x80010515000000E0ULL, 0x80010515001E00E4ULL, 0x8002051500000000ULL, 0x80020515000000E0ULL, 0x80020515F21000E4ULL, /* Set PADLOOPBACKN */ 0x8002051500000000ULL, 0x80020515000000E0ULL, 0x80020515B20000E4ULL, 0x8003051500000000ULL, 0x80030515000000E0ULL, 0x80030515B20000E4ULL, 0x8004051500000000ULL, 0x80040515000000E0ULL, 0x80040515B20000E4ULL, 0x8005051500000000ULL, 0x80050515000000E0ULL, 0x80050515B20000E4ULL, SWITCH_SIGN, /* Remove PADLOOPBACKN */ 0x8002051500000000ULL, 0x80020515000000E0ULL, 0x80020515F20000E4ULL, 0x8003051500000000ULL, 0x80030515000000E0ULL, 0x80030515F20000E4ULL, 0x8004051500000000ULL, 0x80040515000000E0ULL, 0x80040515F20000E4ULL, 0x8005051500000000ULL, 0x80050515000000E0ULL, 0x80050515F20000E4ULL, END_SIGN }; /* * Constants for Fixing the MacAddress problem seen mostly on * Alpha machines. */ static const u64 fix_mac[] = { 0x0060000000000000ULL, 0x0060600000000000ULL, 0x0040600000000000ULL, 0x0000600000000000ULL, 0x0020600000000000ULL, 0x0060600000000000ULL, 0x0020600000000000ULL, 0x0060600000000000ULL, 0x0020600000000000ULL, 0x0060600000000000ULL, 0x0020600000000000ULL, 0x0060600000000000ULL, 0x0020600000000000ULL, 0x0060600000000000ULL, 0x0020600000000000ULL, 0x0060600000000000ULL, 0x0020600000000000ULL, 0x0060600000000000ULL, 0x0020600000000000ULL, 0x0060600000000000ULL, 0x0020600000000000ULL, 0x0060600000000000ULL, 0x0020600000000000ULL, 0x0060600000000000ULL, 0x0020600000000000ULL, 0x0000600000000000ULL, 0x0040600000000000ULL, 0x0060600000000000ULL, END_SIGN }; /* Module Loadable parameters. */ static unsigned int tx_fifo_num = 1; static unsigned int tx_fifo_len[MAX_TX_FIFOS] = {[0 ...(MAX_TX_FIFOS - 1)] = 0 }; static unsigned int rx_ring_num = 1; static unsigned int rx_ring_sz[MAX_RX_RINGS] = {[0 ...(MAX_RX_RINGS - 1)] = 0 }; static unsigned int rts_frm_len[MAX_RX_RINGS] = {[0 ...(MAX_RX_RINGS - 1)] = 0 }; static unsigned int rx_ring_mode = 1; static unsigned int use_continuous_tx_intrs = 1; static unsigned int rmac_pause_time = 65535; static unsigned int mc_pause_threshold_q0q3 = 187; static unsigned int mc_pause_threshold_q4q7 = 187; static unsigned int shared_splits; static unsigned int tmac_util_period = 5; static unsigned int rmac_util_period = 5; static unsigned int bimodal = 0; static unsigned int l3l4hdr_size = 128; #ifndef CONFIG_S2IO_NAPI static unsigned int indicate_max_pkts; #endif /* Frequency of Rx desc syncs expressed as power of 2 */ static unsigned int rxsync_frequency = 3; /* Interrupt type. Values can be 0(INTA), 1(MSI), 2(MSI_X) */ static unsigned int intr_type = 0; /* Large receive offload feature */ static unsigned int lro = 0; /* Max pkts to be aggregated by LRO at one time. If not specified, * aggregation happens until we hit max IP pkt size(64K) */ static unsigned int lro_max_pkts = 0xFFFF; /* * S2IO device table. * This table lists all the devices that this driver supports. */ static struct pci_device_id s2io_tbl[] __devinitdata = { {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_S2IO_WIN, PCI_ANY_ID, PCI_ANY_ID}, {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_S2IO_UNI, PCI_ANY_ID, PCI_ANY_ID}, {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_HERC_WIN, PCI_ANY_ID, PCI_ANY_ID}, {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_HERC_UNI, PCI_ANY_ID, PCI_ANY_ID}, {0,} }; MODULE_DEVICE_TABLE(pci, s2io_tbl); static struct pci_driver s2io_driver = { .name = "S2IO", .id_table = s2io_tbl, .probe = s2io_init_nic, .remove = __devexit_p(s2io_rem_nic), }; /* A simplifier macro used both by init and free shared_mem Fns(). */ #define TXD_MEM_PAGE_CNT(len, per_each) ((len+per_each - 1) / per_each) /** * init_shared_mem - Allocation and Initialization of Memory * @nic: Device private variable. * Description: The function allocates all the memory areas shared * between the NIC and the driver. This includes Tx descriptors, * Rx descriptors and the statistics block. */ static int init_shared_mem(struct s2io_nic *nic) { u32 size; void *tmp_v_addr, *tmp_v_addr_next; dma_addr_t tmp_p_addr, tmp_p_addr_next; RxD_block_t *pre_rxd_blk = NULL; int i, j, blk_cnt, rx_sz, tx_sz; int lst_size, lst_per_page; struct net_device *dev = nic->dev; unsigned long tmp; buffAdd_t *ba; mac_info_t *mac_control; struct config_param *config; mac_control = &nic->mac_control; config = &nic->config; /* Allocation and initialization of TXDLs in FIOFs */ size = 0; for (i = 0; i < config->tx_fifo_num; i++) { size += config->tx_cfg[i].fifo_len; } if (size > MAX_AVAILABLE_TXDS) { DBG_PRINT(ERR_DBG, "%s: Requested TxDs too high, ", __FUNCTION__); DBG_PRINT(ERR_DBG, "Requested: %d, max supported: 8192\n", size); return FAILURE; } lst_size = (sizeof(TxD_t) * config->max_txds); tx_sz = lst_size * size; lst_per_page = PAGE_SIZE / lst_size; for (i = 0; i < config->tx_fifo_num; i++) { int fifo_len = config->tx_cfg[i].fifo_len; int list_holder_size = fifo_len * sizeof(list_info_hold_t); mac_control->fifos[i].list_info = kmalloc(list_holder_size, GFP_KERNEL); if (!mac_control->fifos[i].list_info) { DBG_PRINT(ERR_DBG, "Malloc failed for list_info\n"); return -ENOMEM; } memset(mac_control->fifos[i].list_info, 0, list_holder_size); } for (i = 0; i < config->tx_fifo_num; i++) { int page_num = TXD_MEM_PAGE_CNT(config->tx_cfg[i].fifo_len, lst_per_page); mac_control->fifos[i].tx_curr_put_info.offset = 0; mac_control->fifos[i].tx_curr_put_info.fifo_len = config->tx_cfg[i].fifo_len - 1; mac_control->fifos[i].tx_curr_get_info.offset = 0; mac_control->fifos[i].tx_curr_get_info.fifo_len = config->tx_cfg[i].fifo_len - 1; mac_control->fifos[i].fifo_no = i; mac_control->fifos[i].nic = nic; mac_control->fifos[i].max_txds = MAX_SKB_FRAGS + 2; for (j = 0; j < page_num; j++) { int k = 0; dma_addr_t tmp_p; void *tmp_v; tmp_v = pci_alloc_consistent(nic->pdev, PAGE_SIZE, &tmp_p); if (!tmp_v) { DBG_PRINT(ERR_DBG, "pci_alloc_consistent "); DBG_PRINT(ERR_DBG, "failed for TxDL\n"); return -ENOMEM; } /* If we got a zero DMA address(can happen on * certain platforms like PPC), reallocate. * Store virtual address of page we don't want, * to be freed later. */ if (!tmp_p) { mac_control->zerodma_virt_addr = tmp_v; DBG_PRINT(INIT_DBG, "%s: Zero DMA address for TxDL. ", dev->name); DBG_PRINT(INIT_DBG, "Virtual address %p\n", tmp_v); tmp_v = pci_alloc_consistent(nic->pdev, PAGE_SIZE, &tmp_p); if (!tmp_v) { DBG_PRINT(ERR_DBG, "pci_alloc_consistent "); DBG_PRINT(ERR_DBG, "failed for TxDL\n"); return -ENOMEM; } } while (k < lst_per_page) { int l = (j * lst_per_page) + k; if (l == config->tx_cfg[i].fifo_len) break; mac_control->fifos[i].list_info[l].list_virt_addr = tmp_v + (k * lst_size); mac_control->fifos[i].list_info[l].list_phy_addr = tmp_p + (k * lst_size); k++; } } } nic->ufo_in_band_v = kmalloc((sizeof(u64) * size), GFP_KERNEL); if (!nic->ufo_in_band_v) return -ENOMEM; /* Allocation and initialization of RXDs in Rings */ size = 0; for (i = 0; i < config->rx_ring_num; i++) { if (config->rx_cfg[i].num_rxd % (rxd_count[nic->rxd_mode] + 1)) { DBG_PRINT(ERR_DBG, "%s: RxD count of ", dev->name); DBG_PRINT(ERR_DBG, "Ring%d is not a multiple of ", i); DBG_PRINT(ERR_DBG, "RxDs per Block"); return FAILURE; } size += config->rx_cfg[i].num_rxd; mac_control->rings[i].block_count = config->rx_cfg[i].num_rxd / (rxd_count[nic->rxd_mode] + 1 ); mac_control->rings[i].pkt_cnt = config->rx_cfg[i].num_rxd - mac_control->rings[i].block_count; } if (nic->rxd_mode == RXD_MODE_1) size = (size * (sizeof(RxD1_t))); else size = (size * (sizeof(RxD3_t))); rx_sz = size; for (i = 0; i < config->rx_ring_num; i++) { mac_control->rings[i].rx_curr_get_info.block_index = 0; mac_control->rings[i].rx_curr_get_info.offset = 0; mac_control->rings[i].rx_curr_get_info.ring_len = config->rx_cfg[i].num_rxd - 1; mac_control->rings[i].rx_curr_put_info.block_index = 0; mac_control->rings[i].rx_curr_put_info.offset = 0; mac_control->rings[i].rx_curr_put_info.ring_len = config->rx_cfg[i].num_rxd - 1; mac_control->rings[i].nic = nic; mac_control->rings[i].ring_no = i; blk_cnt = config->rx_cfg[i].num_rxd / (rxd_count[nic->rxd_mode] + 1); /* Allocating all the Rx blocks */ for (j = 0; j < blk_cnt; j++) { rx_block_info_t *rx_blocks; int l; rx_blocks = &mac_control->rings[i].rx_blocks[j]; size = SIZE_OF_BLOCK; //size is always page size tmp_v_addr = pci_alloc_consistent(nic->pdev, size, &tmp_p_addr); if (tmp_v_addr == NULL) { /* * In case of failure, free_shared_mem() * is called, which should free any * memory that was alloced till the * failure happened. */ rx_blocks->block_virt_addr = tmp_v_addr; return -ENOMEM; } memset(tmp_v_addr, 0, size); rx_blocks->block_virt_addr = tmp_v_addr; rx_blocks->block_dma_addr = tmp_p_addr; rx_blocks->rxds = kmalloc(sizeof(rxd_info_t)* rxd_count[nic->rxd_mode], GFP_KERNEL); for (l=0; lrxd_mode];l++) { rx_blocks->rxds[l].virt_addr = rx_blocks->block_virt_addr + (rxd_size[nic->rxd_mode] * l); rx_blocks->rxds[l].dma_addr = rx_blocks->block_dma_addr + (rxd_size[nic->rxd_mode] * l); } mac_control->rings[i].rx_blocks[j].block_virt_addr = tmp_v_addr; mac_control->rings[i].rx_blocks[j].block_dma_addr = tmp_p_addr; } /* Interlinking all Rx Blocks */ for (j = 0; j < blk_cnt; j++) { tmp_v_addr = mac_control->rings[i].rx_blocks[j].block_virt_addr; tmp_v_addr_next = mac_control->rings[i].rx_blocks[(j + 1) % blk_cnt].block_virt_addr; tmp_p_addr = mac_control->rings[i].rx_blocks[j].block_dma_addr; tmp_p_addr_next = mac_control->rings[i].rx_blocks[(j + 1) % blk_cnt].block_dma_addr; pre_rxd_blk = (RxD_block_t *) tmp_v_addr; pre_rxd_blk->reserved_2_pNext_RxD_block = (unsigned long) tmp_v_addr_next; pre_rxd_blk->pNext_RxD_Blk_physical = (u64) tmp_p_addr_next; } } if (nic->rxd_mode >= RXD_MODE_3A) { /* * Allocation of Storages for buffer addresses in 2BUFF mode * and the buffers as well. */ for (i = 0; i < config->rx_ring_num; i++) { blk_cnt = config->rx_cfg[i].num_rxd / (rxd_count[nic->rxd_mode]+ 1); mac_control->rings[i].ba = kmalloc((sizeof(buffAdd_t *) * blk_cnt), GFP_KERNEL); if (!mac_control->rings[i].ba) return -ENOMEM; for (j = 0; j < blk_cnt; j++) { int k = 0; mac_control->rings[i].ba[j] = kmalloc((sizeof(buffAdd_t) * (rxd_count[nic->rxd_mode] + 1)), GFP_KERNEL); if (!mac_control->rings[i].ba[j]) return -ENOMEM; while (k != rxd_count[nic->rxd_mode]) { ba = &mac_control->rings[i].ba[j][k]; ba->ba_0_org = (void *) kmalloc (BUF0_LEN + ALIGN_SIZE, GFP_KERNEL); if (!ba->ba_0_org) return -ENOMEM; tmp = (unsigned long)ba->ba_0_org; tmp += ALIGN_SIZE; tmp &= ~((unsigned long) ALIGN_SIZE); ba->ba_0 = (void *) tmp; ba->ba_1_org = (void *) kmalloc (BUF1_LEN + ALIGN_SIZE, GFP_KERNEL); if (!ba->ba_1_org) return -ENOMEM; tmp = (unsigned long) ba->ba_1_org; tmp += ALIGN_SIZE; tmp &= ~((unsigned long) ALIGN_SIZE); ba->ba_1 = (void *) tmp; k++; } } } } /* Allocation and initialization of Statistics block */ size = sizeof(StatInfo_t); mac_control->stats_mem = pci_alloc_consistent (nic->pdev, size, &mac_control->stats_mem_phy); if (!mac_control->stats_mem) { /* * In case of failure, free_shared_mem() is called, which * should free any memory that was alloced till the * failure happened. */ return -ENOMEM; } mac_control->stats_mem_sz = size; tmp_v_addr = mac_control->stats_mem; mac_control->stats_info = (StatInfo_t *) tmp_v_addr; memset(tmp_v_addr, 0, size); DBG_PRINT(INIT_DBG, "%s:Ring Mem PHY: 0x%llx\n", dev->name, (unsigned long long) tmp_p_addr); return SUCCESS; } /** * free_shared_mem - Free the allocated Memory * @nic: Device private variable. * Description: This function is to free all memory locations allocated by * the init_shared_mem() function and return it to the kernel. */ static void free_shared_mem(struct s2io_nic *nic) { int i, j, blk_cnt, size; void *tmp_v_addr; dma_addr_t tmp_p_addr; mac_info_t *mac_control; struct config_param *config; int lst_size, lst_per_page; struct net_device *dev = nic->dev; if (!nic) return; mac_control = &nic->mac_control; config = &nic->config; lst_size = (sizeof(TxD_t) * config->max_txds); lst_per_page = PAGE_SIZE / lst_size; for (i = 0; i < config->tx_fifo_num; i++) { int page_num = TXD_MEM_PAGE_CNT(config->tx_cfg[i].fifo_len, lst_per_page); for (j = 0; j < page_num; j++) { int mem_blks = (j * lst_per_page); if (!mac_control->fifos[i].list_info) return; if (!mac_control->fifos[i].list_info[mem_blks]. list_virt_addr) break; pci_free_consistent(nic->pdev, PAGE_SIZE, mac_control->fifos[i]. list_info[mem_blks]. list_virt_addr, mac_control->fifos[i]. list_info[mem_blks]. list_phy_addr); } /* If we got a zero DMA address during allocation, * free the page now */ if (mac_control->zerodma_virt_addr) { pci_free_consistent(nic->pdev, PAGE_SIZE, mac_control->zerodma_virt_addr, (dma_addr_t)0); DBG_PRINT(INIT_DBG, "%s: Freeing TxDL with zero DMA addr. ", dev->name); DBG_PRINT(INIT_DBG, "Virtual address %p\n", mac_control->zerodma_virt_addr); } kfree(mac_control->fifos[i].list_info); } size = SIZE_OF_BLOCK; for (i = 0; i < config->rx_ring_num; i++) { blk_cnt = mac_control->rings[i].block_count; for (j = 0; j < blk_cnt; j++) { tmp_v_addr = mac_control->rings[i].rx_blocks[j]. block_virt_addr; tmp_p_addr = mac_control->rings[i].rx_blocks[j]. block_dma_addr; if (tmp_v_addr == NULL) break; pci_free_consistent(nic->pdev, size, tmp_v_addr, tmp_p_addr); kfree(mac_control->rings[i].rx_blocks[j].rxds); } } if (nic->rxd_mode >= RXD_MODE_3A) { /* Freeing buffer storage addresses in 2BUFF mode. */ for (i = 0; i < config->rx_ring_num; i++) { blk_cnt = config->rx_cfg[i].num_rxd / (rxd_count[nic->rxd_mode] + 1); for (j = 0; j < blk_cnt; j++) { int k = 0; if (!mac_control->rings[i].ba[j]) continue; while (k != rxd_count[nic->rxd_mode]) { buffAdd_t *ba = &mac_control->rings[i].ba[j][k]; kfree(ba->ba_0_org); kfree(ba->ba_1_org); k++; } kfree(mac_control->rings[i].ba[j]); } kfree(mac_control->rings[i].ba); } } if (mac_control->stats_mem) { pci_free_consistent(nic->pdev, mac_control->stats_mem_sz, mac_control->stats_mem, mac_control->stats_mem_phy); } if (nic->ufo_in_band_v) kfree(nic->ufo_in_band_v); } /** * s2io_verify_pci_mode - */ static int s2io_verify_pci_mode(nic_t *nic) { XENA_dev_config_t __iomem *bar0 = nic->bar0; register u64 val64 = 0; int mode; val64 = readq(&bar0->pci_mode); mode = (u8)GET_PCI_MODE(val64); if ( val64 & PCI_MODE_UNKNOWN_MODE) return -1; /* Unknown PCI mode */ return mode; } /** * s2io_print_pci_mode - */ static int s2io_print_pci_mode(nic_t *nic) { XENA_dev_config_t __iomem *bar0 = nic->bar0; register u64 val64 = 0; int mode; struct config_param *config = &nic->config; val64 = readq(&bar0->pci_mode); mode = (u8)GET_PCI_MODE(val64); if ( val64 & PCI_MODE_UNKNOWN_MODE) return -1; /* Unknown PCI mode */ if (val64 & PCI_MODE_32_BITS) { DBG_PRINT(ERR_DBG, "%s: Device is on 32 bit ", nic->dev->name); } else { DBG_PRINT(ERR_DBG, "%s: Device is on 64 bit ", nic->dev->name); } switch(mode) { case PCI_MODE_PCI_33: DBG_PRINT(ERR_DBG, "33MHz PCI bus\n"); config->bus_speed = 33; break; case PCI_MODE_PCI_66: DBG_PRINT(ERR_DBG, "66MHz PCI bus\n"); config->bus_speed = 133; break; case PCI_MODE_PCIX_M1_66: DBG_PRINT(ERR_DBG, "66MHz PCIX(M1) bus\n"); config->bus_speed = 133; /* Herc doubles the clock rate */ break; case PCI_MODE_PCIX_M1_100: DBG_PRINT(ERR_DBG, "100MHz PCIX(M1) bus\n"); config->bus_speed = 200; break; case PCI_MODE_PCIX_M1_133: DBG_PRINT(ERR_DBG, "133MHz PCIX(M1) bus\n"); config->bus_speed = 266; break; case PCI_MODE_PCIX_M2_66: DBG_PRINT(ERR_DBG, "133MHz PCIX(M2) bus\n"); config->bus_speed = 133; break; case PCI_MODE_PCIX_M2_100: DBG_PRINT(ERR_DBG, "200MHz PCIX(M2) bus\n"); config->bus_speed = 200; break; case PCI_MODE_PCIX_M2_133: DBG_PRINT(ERR_DBG, "266MHz PCIX(M2) bus\n"); config->bus_speed = 266; break; default: return -1; /* Unsupported bus speed */ } return mode; } /** * init_nic - Initialization of hardware * @nic: device peivate variable * Description: The function sequentially configures every block * of the H/W from their reset values. * Return Value: SUCCESS on success and * '-1' on failure (endian settings incorrect). */ static int init_nic(struct s2io_nic *nic) { XENA_dev_config_t __iomem *bar0 = nic->bar0; struct net_device *dev = nic->dev; register u64 val64 = 0; void __iomem *add; u32 time; int i, j; mac_info_t *mac_control; struct config_param *config; int mdio_cnt = 0, dtx_cnt = 0; unsigned long long mem_share; int mem_size; mac_control = &nic->mac_control; config = &nic->config; /* to set the swapper controle on the card */ if(s2io_set_swapper(nic)) { DBG_PRINT(ERR_DBG,"ERROR: Setting Swapper failed\n"); return -1; } /* * Herc requires EOI to be removed from reset before XGXS, so.. */ if (nic->device_type & XFRAME_II_DEVICE) { val64 = 0xA500000000ULL; writeq(val64, &bar0->sw_reset); msleep(500); val64 = readq(&bar0->sw_reset); } /* Remove XGXS from reset state */ val64 = 0; writeq(val64, &bar0->sw_reset); msleep(500); val64 = readq(&bar0->sw_reset); /* Enable Receiving broadcasts */ add = &bar0->mac_cfg; val64 = readq(&bar0->mac_cfg); val64 |= MAC_RMAC_BCAST_ENABLE; writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key); writel((u32) val64, add); writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key); writel((u32) (val64 >> 32), (add + 4)); /* Read registers in all blocks */ val64 = readq(&bar0->mac_int_mask); val64 = readq(&bar0->mc_int_mask); val64 = readq(&bar0->xgxs_int_mask); /* Set MTU */ val64 = dev->mtu; writeq(vBIT(val64, 2, 14), &bar0->rmac_max_pyld_len); /* * Configuring the XAUI Interface of Xena. * *************************************** * To Configure the Xena's XAUI, one has to write a series * of 64 bit values into two registers in a particular * sequence. Hence a macro 'SWITCH_SIGN' has been defined * which will be defined in the array of configuration values * (xena_dtx_cfg & xena_mdio_cfg) at appropriate places * to switch writing from one regsiter to another. We continue * writing these values until we encounter the 'END_SIGN' macro. * For example, After making a series of 21 writes into * dtx_control register the 'SWITCH_SIGN' appears and hence we * start writing into mdio_control until we encounter END_SIGN. */ if (nic->device_type & XFRAME_II_DEVICE) { while (herc_act_dtx_cfg[dtx_cnt] != END_SIGN) { SPECIAL_REG_WRITE(herc_act_dtx_cfg[dtx_cnt], &bar0->dtx_control, UF); if (dtx_cnt & 0x1) msleep(1); /* Necessary!! */ dtx_cnt++; } } else { while (1) { dtx_cfg: while (xena_dtx_cfg[dtx_cnt] != END_SIGN) { if (xena_dtx_cfg[dtx_cnt] == SWITCH_SIGN) { dtx_cnt++; goto mdio_cfg; } SPECIAL_REG_WRITE(xena_dtx_cfg[dtx_cnt], &bar0->dtx_control, UF); val64 = readq(&bar0->dtx_control); dtx_cnt++; } mdio_cfg: while (xena_mdio_cfg[mdio_cnt] != END_SIGN) { if (xena_mdio_cfg[mdio_cnt] == SWITCH_SIGN) { mdio_cnt++; goto dtx_cfg; } SPECIAL_REG_WRITE(xena_mdio_cfg[mdio_cnt], &bar0->mdio_control, UF); val64 = readq(&bar0->mdio_control); mdio_cnt++; } if ((xena_dtx_cfg[dtx_cnt] == END_SIGN) && (xena_mdio_cfg[mdio_cnt] == END_SIGN)) { break; } else { goto dtx_cfg; } } } /* Tx DMA Initialization */ val64 = 0; writeq(val64, &bar0->tx_fifo_partition_0); writeq(val64, &bar0->tx_fifo_partition_1); writeq(val64, &bar0->tx_fifo_partition_2); writeq(val64, &bar0->tx_fifo_partition_3); for (i = 0, j = 0; i < config->tx_fifo_num; i++) { val64 |= vBIT(config->tx_cfg[i].fifo_len - 1, ((i * 32) + 19), 13) | vBIT(config->tx_cfg[i].fifo_priority, ((i * 32) + 5), 3); if (i == (config->tx_fifo_num - 1)) { if (i % 2 == 0) i++; } switch (i) { case 1: writeq(val64, &bar0->tx_fifo_partition_0); val64 = 0; break; case 3: writeq(val64, &bar0->tx_fifo_partition_1); val64 = 0; break; case 5: writeq(val64, &bar0->tx_fifo_partition_2); val64 = 0; break; case 7: writeq(val64, &bar0->tx_fifo_partition_3); break; } } /* Enable Tx FIFO partition 0. */ val64 = readq(&bar0->tx_fifo_partition_0); val64 |= BIT(0); /* To enable the FIFO partition. */ writeq(val64, &bar0->tx_fifo_partition_0); /* * Disable 4 PCCs for Xena1, 2 and 3 as per H/W bug * SXE-008 TRANSMIT DMA ARBITRATION ISSUE. */ if ((nic->device_type == XFRAME_I_DEVICE) && (get_xena_rev_id(nic->pdev) < 4)) writeq(PCC_ENABLE_FOUR, &bar0->pcc_enable); val64 = readq(&bar0->tx_fifo_partition_0); DBG_PRINT(INIT_DBG, "Fifo partition at: 0x%p is: 0x%llx\n", &bar0->tx_fifo_partition_0, (unsigned long long) val64); /* * Initialization of Tx_PA_CONFIG register to ignore packet * integrity checking. */ val64 = readq(&bar0->tx_pa_cfg); val64 |= TX_PA_CFG_IGNORE_FRM_ERR | TX_PA_CFG_IGNORE_SNAP_OUI | TX_PA_CFG_IGNORE_LLC_CTRL | TX_PA_CFG_IGNORE_L2_ERR; writeq(val64, &bar0->tx_pa_cfg); /* Rx DMA intialization. */ val64 = 0; for (i = 0; i < config->rx_ring_num; i++) { val64 |= vBIT(config->rx_cfg[i].ring_priority, (5 + (i * 8)), 3); } writeq(val64, &bar0->rx_queue_priority); /* * Allocating equal share of memory to all the * configured Rings. */ val64 = 0; if (nic->device_type & XFRAME_II_DEVICE) mem_size = 32; else mem_size = 64; for (i = 0; i < config->rx_ring_num; i++) { switch (i) { case 0: mem_share = (mem_size / config->rx_ring_num + mem_size % config->rx_ring_num); val64 |= RX_QUEUE_CFG_Q0_SZ(mem_share); continue; case 1: mem_share = (mem_size / config->rx_ring_num); val64 |= RX_QUEUE_CFG_Q1_SZ(mem_share); continue; case 2: mem_share = (mem_size / config->rx_ring_num); val64 |= RX_QUEUE_CFG_Q2_SZ(mem_share); continue; case 3: mem_share = (mem_size / config->rx_ring_num); val64 |= RX_QUEUE_CFG_Q3_SZ(mem_share); continue; case 4: mem_share = (mem_size / config->rx_ring_num); val64 |= RX_QUEUE_CFG_Q4_SZ(mem_share); continue; case 5: mem_share = (mem_size / config->rx_ring_num); val64 |= RX_QUEUE_CFG_Q5_SZ(mem_share); continue; case 6: mem_share = (mem_size / config->rx_ring_num); val64 |= RX_QUEUE_CFG_Q6_SZ(mem_share); continue; case 7: mem_share = (mem_size / config->rx_ring_num); val64 |= RX_QUEUE_CFG_Q7_SZ(mem_share); continue; } } writeq(val64, &bar0->rx_queue_cfg); /* * Filling Tx round robin registers * as per the number of FIFOs */ switch (config->tx_fifo_num) { case 1: val64 = 0x0000000000000000ULL; writeq(val64, &bar0->tx_w_round_robin_0); writeq(val64, &bar0->tx_w_round_robin_1); writeq(val64, &bar0->tx_w_round_robin_2); writeq(val64, &bar0->tx_w_round_robin_3); writeq(val64, &bar0->tx_w_round_robin_4); break; case 2: val64 = 0x0000010000010000ULL; writeq(val64, &bar0->tx_w_round_robin_0); val64 = 0x0100000100000100ULL; writeq(val64, &bar0->tx_w_round_robin_1); val64 = 0x0001000001000001ULL; writeq(val64, &bar0->tx_w_round_robin_2); val64 = 0x0000010000010000ULL; writeq(val64, &bar0->tx_w_round_robin_3); val64 = 0x0100000000000000ULL; writeq(val64, &bar0->tx_w_round_robin_4); break; case 3: val64 = 0x0001000102000001ULL; writeq(val64, &bar0->tx_w_round_robin_0); val64 = 0x0001020000010001ULL; writeq(val64, &bar0->tx_w_round_robin_1); val64 = 0x0200000100010200ULL; writeq(val64, &bar0->tx_w_round_robin_2); val64 = 0x0001000102000001ULL; writeq(val64, &bar0->tx_w_round_robin_3); val64 = 0x0001020000000000ULL; writeq(val64, &bar0->tx_w_round_robin_4); break; case 4: val64 = 0x0001020300010200ULL; writeq(val64, &bar0->tx_w_round_robin_0); val64 = 0x0100000102030001ULL; writeq(val64, &bar0->tx_w_round_robin_1); val64 = 0x0200010000010203ULL; writeq(val64, &bar0->tx_w_round_robin_2); val64 = 0x0001020001000001ULL; writeq(val64, &bar0->tx_w_round_robin_3); val64 = 0x0203000100000000ULL; writeq(val64, &bar0->tx_w_round_robin_4); break; case 5: val64 = 0x0001000203000102ULL; writeq(val64, &bar0->tx_w_round_robin_0); val64 = 0x0001020001030004ULL; writeq(val64, &bar0->tx_w_round_robin_1); val64 = 0x0001000203000102ULL; writeq(val64, &bar0->tx_w_round_robin_2); val64 = 0x0001020001030004ULL; writeq(val64, &bar0->tx_w_round_robin_3); val64 = 0x0001000000000000ULL; writeq(val64, &bar0->tx_w_round_robin_4); break; case 6: val64 = 0x0001020304000102ULL; writeq(val64, &bar0->tx_w_round_robin_0); val64 = 0x0304050001020001ULL; writeq(val64, &bar0->tx_w_round_robin_1); val64 = 0x0203000100000102ULL; writeq(val64, &bar0->tx_w_round_robin_2); val64 = 0x0304000102030405ULL; writeq(val64, &bar0->tx_w_round_robin_3); val64 = 0x0001000200000000ULL; writeq(val64, &bar0->tx_w_round_robin_4); break; case 7: val64 = 0x0001020001020300ULL; writeq(val64, &bar0->tx_w_round_robin_0); val64 = 0x0102030400010203ULL; writeq(val64, &bar0->tx_w_round_robin_1); val64 = 0x0405060001020001ULL; writeq(val64, &bar0->tx_w_round_robin_2); val64 = 0x0304050000010200ULL; writeq(val64, &bar0->tx_w_round_robin_3); val64 = 0x0102030000000000ULL; writeq(val64, &bar0->tx_w_round_robin_4); break; case 8: val64 = 0x0001020300040105ULL; writeq(val64, &bar0->tx_w_round_robin_0); val64 = 0x0200030106000204ULL; writeq(val64, &bar0->tx_w_round_robin_1); val64 = 0x0103000502010007ULL; writeq(val64, &bar0->tx_w_round_robin_2); val64 = 0x0304010002060500ULL; writeq(val64, &bar0->tx_w_round_robin_3); val64 = 0x0103020400000000ULL; writeq(val64, &bar0->tx_w_round_robin_4); break; } /* Filling the Rx round robin registers as per the * number of Rings and steering based on QoS. */ switch (config->rx_ring_num) { case 1: val64 = 0x8080808080808080ULL; writeq(val64, &bar0->rts_qos_steering); break; case 2: val64 = 0x0000010000010000ULL; writeq(val64, &bar0->rx_w_round_robin_0); val64 = 0x0100000100000100ULL; writeq(val64, &bar0->rx_w_round_robin_1); val64 = 0x0001000001000001ULL; writeq(val64, &bar0->rx_w_round_robin_2); val64 = 0x0000010000010000ULL; writeq(val64, &bar0->rx_w_round_robin_3); val64 = 0x0100000000000000ULL; writeq(val64, &bar0->rx_w_round_robin_4); val64 = 0x8080808040404040ULL; writeq(val64, &bar0->rts_qos_steering); break; case 3: val64 = 0x0001000102000001ULL; writeq(val64, &bar0->rx_w_round_robin_0); val64 = 0x0001020000010001ULL; writeq(val64, &bar0->rx_w_round_robin_1); val64 = 0x0200000100010200ULL; writeq(val64, &bar0->rx_w_round_robin_2); val64 = 0x0001000102000001ULL; writeq(val64, &bar0->rx_w_round_robin_3); val64 = 0x0001020000000000ULL; writeq(val64, &bar0->rx_w_round_robin_4); val64 = 0x8080804040402020ULL; writeq(val64, &bar0->rts_qos_steering); break; case 4: val64 = 0x0001020300010200ULL; writeq(val64, &bar0->rx_w_round_robin_0); val64 = 0x0100000102030001ULL; writeq(val64, &bar0->rx_w_round_robin_1); val64 = 0x0200010000010203ULL; writeq(val64, &bar0->rx_w_round_robin_2); val64 = 0x0001020001000001ULL; writeq(val64, &bar0->rx_w_round_robin_3); val64 = 0x0203000100000000ULL; writeq(val64, &bar0->rx_w_round_robin_4); val64 = 0x8080404020201010ULL; writeq(val64, &bar0->rts_qos_steering); break; case 5: val64 = 0x0001000203000102ULL; writeq(val64, &bar0->rx_w_round_robin_0); val64 = 0x0001020001030004ULL; writeq(val64, &bar0->rx_w_round_robin_1); val64 = 0x0001000203000102ULL; writeq(val64, &bar0->rx_w_round_robin_2); val64 = 0x0001020001030004ULL; writeq(val64, &bar0->rx_w_round_robin_3); val64 = 0x0001000000000000ULL; writeq(val64, &bar0->rx_w_round_robin_4); val64 = 0x8080404020201008ULL; writeq(val64, &bar0->rts_qos_steering); break; case 6: val64 = 0x0001020304000102ULL; writeq(val64, &bar0->rx_w_round_robin_0); val64 = 0x0304050001020001ULL; writeq(val64, &bar0->rx_w_round_robin_1); val64 = 0x0203000100000102ULL; writeq(val64, &bar0->rx_w_round_robin_2); val64 = 0x0304000102030405ULL; writeq(val64, &bar0->rx_w_round_robin_3); val64 = 0x0001000200000000ULL; writeq(val64, &bar0->rx_w_round_robin_4); val64 = 0x8080404020100804ULL; writeq(val64, &bar0->rts_qos_steering); break; case 7: val64 = 0x0001020001020300ULL; writeq(val64, &bar0->rx_w_round_robin_0); val64 = 0x0102030400010203ULL; writeq(val64, &bar0->rx_w_round_robin_1); val64 = 0x0405060001020001ULL; writeq(val64, &bar0->rx_w_round_robin_2); val64 = 0x0304050000010200ULL; writeq(val64, &bar0->rx_w_round_robin_3); val64 = 0x0102030000000000ULL; writeq(val64, &bar0->rx_w_round_robin_4); val64 = 0x8080402010080402ULL; writeq(val64, &bar0->rts_qos_steering); break; case 8: val64 = 0x0001020300040105ULL; writeq(val64, &bar0->rx_w_round_robin_0); val64 = 0x0200030106000204ULL; writeq(val64, &bar0->rx_w_round_robin_1); val64 = 0x0103000502010007ULL; writeq(val64, &bar0->rx_w_round_robin_2); val64 = 0x0304010002060500ULL; writeq(val64, &bar0->rx_w_round_robin_3); val64 = 0x0103020400000000ULL; writeq(val64, &bar0->rx_w_round_robin_4); val64 = 0x8040201008040201ULL; writeq(val64, &bar0->rts_qos_steering); break; } /* UDP Fix */ val64 = 0; for (i = 0; i < 8; i++) writeq(val64, &bar0->rts_frm_len_n[i]); /* Set the default rts frame length for the rings configured */ val64 = MAC_RTS_FRM_LEN_SET(dev->mtu+22); for (i = 0 ; i < config->rx_ring_num ; i++) writeq(val64, &bar0->rts_frm_len_n[i]); /* Set the frame length for the configured rings * desired by the user */ for (i = 0; i < config->rx_ring_num; i++) { /* If rts_frm_len[i] == 0 then it is assumed that user not * specified frame length steering. * If the user provides the frame length then program * the rts_frm_len register for those values or else * leave it as it is. */ if (rts_frm_len[i] != 0) { writeq(MAC_RTS_FRM_LEN_SET(rts_frm_len[i]), &bar0->rts_frm_len_n[i]); } } /* Program statistics memory */ writeq(mac_control->stats_mem_phy, &bar0->stat_addr); if (nic->device_type == XFRAME_II_DEVICE) { val64 = STAT_BC(0x320); writeq(val64, &bar0->stat_byte_cnt); } /* * Initializing the sampling rate for the device to calculate the * bandwidth utilization. */ val64 = MAC_TX_LINK_UTIL_VAL(tmac_util_period) | MAC_RX_LINK_UTIL_VAL(rmac_util_period); writeq(val64, &bar0->mac_link_util); /* * Initializing the Transmit and Receive Traffic Interrupt * Scheme. */ /* * TTI Initialization. Default Tx timer gets us about * 250 interrupts per sec. Continuous interrupts are enabled * by default. */ if (nic->device_type == XFRAME_II_DEVICE) { int count = (nic->config.bus_speed * 125)/2; val64 = TTI_DATA1_MEM_TX_TIMER_VAL(count); } else { val64 = TTI_DATA1_MEM_TX_TIMER_VAL(0x2078); } val64 |= TTI_DATA1_MEM_TX_URNG_A(0xA) | TTI_DATA1_MEM_TX_URNG_B(0x10) | TTI_DATA1_MEM_TX_URNG_C(0x30) | TTI_DATA1_MEM_TX_TIMER_AC_EN; if (use_continuous_tx_intrs) val64 |= TTI_DATA1_MEM_TX_TIMER_CI_EN; writeq(val64, &bar0->tti_data1_mem); val64 = TTI_DATA2_MEM_TX_UFC_A(0x10) | TTI_DATA2_MEM_TX_UFC_B(0x20) | TTI_DATA2_MEM_TX_UFC_C(0x70) | TTI_DATA2_MEM_TX_UFC_D(0x80); writeq(val64, &bar0->tti_data2_mem); val64 = TTI_CMD_MEM_WE | TTI_CMD_MEM_STROBE_NEW_CMD; writeq(val64, &bar0->tti_command_mem); /* * Once the operation completes, the Strobe bit of the command * register will be reset. We poll for this particular condition * We wait for a maximum of 500ms for the operation to complete, * if it's not complete by then we return error. */ time = 0; while (TRUE) { val64 = readq(&bar0->tti_command_mem); if (!(val64 & TTI_CMD_MEM_STROBE_NEW_CMD)) { break; } if (time > 10) { DBG_PRINT(ERR_DBG, "%s: TTI init Failed\n", dev->name); return -1; } msleep(50); time++; } if (nic->config.bimodal) { int k = 0; for (k = 0; k < config->rx_ring_num; k++) { val64 = TTI_CMD_MEM_WE | TTI_CMD_MEM_STROBE_NEW_CMD; val64 |= TTI_CMD_MEM_OFFSET(0x38+k); writeq(val64, &bar0->tti_command_mem); /* * Once the operation completes, the Strobe bit of the command * register will be reset. We poll for this particular condition * We wait for a maximum of 500ms for the operation to complete, * if it's not complete by then we return error. */ time = 0; while (TRUE) { val64 = readq(&bar0->tti_command_mem); if (!(val64 & TTI_CMD_MEM_STROBE_NEW_CMD)) { break; } if (time > 10) { DBG_PRINT(ERR_DBG, "%s: TTI init Failed\n", dev->name); return -1; } time++; msleep(50); } } } else { /* RTI Initialization */ if (nic->device_type == XFRAME_II_DEVICE) { /* * Programmed to generate Apprx 500 Intrs per * second */ int count = (nic->config.bus_speed * 125)/4; val64 = RTI_DATA1_MEM_RX_TIMER_VAL(count); } else { val64 = RTI_DATA1_MEM_RX_TIMER_VAL(0xFFF); } val64 |= RTI_DATA1_MEM_RX_URNG_A(0xA) | RTI_DATA1_MEM_RX_URNG_B(0x10) | RTI_DATA1_MEM_RX_URNG_C(0x30) | RTI_DATA1_MEM_RX_TIMER_AC_EN; writeq(val64, &bar0->rti_data1_mem); val64 = RTI_DATA2_MEM_RX_UFC_A(0x1) | RTI_DATA2_MEM_RX_UFC_B(0x2) ; if (nic->intr_type == MSI_X) val64 |= (RTI_DATA2_MEM_RX_UFC_C(0x20) | \ RTI_DATA2_MEM_RX_UFC_D(0x40)); else val64 |= (RTI_DATA2_MEM_RX_UFC_C(0x40) | \ RTI_DATA2_MEM_RX_UFC_D(0x80)); writeq(val64, &bar0->rti_data2_mem); for (i = 0; i < config->rx_ring_num; i++) { val64 = RTI_CMD_MEM_WE | RTI_CMD_MEM_STROBE_NEW_CMD | RTI_CMD_MEM_OFFSET(i); writeq(val64, &bar0->rti_command_mem); /* * Once the operation completes, the Strobe bit of the * command register will be reset. We poll for this * particular condition. We wait for a maximum of 500ms * for the operation to complete, if it's not complete * by then we return error. */ time = 0; while (TRUE) { val64 = readq(&bar0->rti_command_mem); if (!(val64 & RTI_CMD_MEM_STROBE_NEW_CMD)) { break; } if (time > 10) { DBG_PRINT(ERR_DBG, "%s: RTI init Failed\n", dev->name); return -1; } time++; msleep(50); } } } /* * Initializing proper values as Pause threshold into all * the 8 Queues on Rx side. */ writeq(0xffbbffbbffbbffbbULL, &bar0->mc_pause_thresh_q0q3); writeq(0xffbbffbbffbbffbbULL, &bar0->mc_pause_thresh_q4q7); /* Disable RMAC PAD STRIPPING */ add = &bar0->mac_cfg; val64 = readq(&bar0->mac_cfg); val64 &= ~(MAC_CFG_RMAC_STRIP_PAD); writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key); writel((u32) (val64), add); writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key); writel((u32) (val64 >> 32), (add + 4)); val64 = readq(&bar0->mac_cfg); /* Enable FCS stripping by adapter */ add = &bar0->mac_cfg; val64 = readq(&bar0->mac_cfg); val64 |= MAC_CFG_RMAC_STRIP_FCS; if (nic->device_type == XFRAME_II_DEVICE) writeq(val64, &bar0->mac_cfg); else { writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key); writel((u32) (val64), add); writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key); writel((u32) (val64 >> 32), (add + 4)); } /* * Set the time value to be inserted in the pause frame * generated by xena. */ val64 = readq(&bar0->rmac_pause_cfg); val64 &= ~(RMAC_PAUSE_HG_PTIME(0xffff)); val64 |= RMAC_PAUSE_HG_PTIME(nic->mac_control.rmac_pause_time); writeq(val64, &bar0->rmac_pause_cfg); /* * Set the Threshold Limit for Generating the pause frame * If the amount of data in any Queue exceeds ratio of * (mac_control.mc_pause_threshold_q0q3 or q4q7)/256 * pause frame is generated */ val64 = 0; for (i = 0; i < 4; i++) { val64 |= (((u64) 0xFF00 | nic->mac_control. mc_pause_threshold_q0q3) << (i * 2 * 8)); } writeq(val64, &bar0->mc_pause_thresh_q0q3); val64 = 0; for (i = 0; i < 4; i++) { val64 |= (((u64) 0xFF00 | nic->mac_control. mc_pause_threshold_q4q7) << (i * 2 * 8)); } writeq(val64, &bar0->mc_pause_thresh_q4q7); /* * TxDMA will stop Read request if the number of read split has * exceeded the limit pointed by shared_splits */ val64 = readq(&bar0->pic_control); val64 |= PIC_CNTL_SHARED_SPLITS(shared_splits); writeq(val64, &bar0->pic_control); /* * Programming the Herc to split every write transaction * that does not start on an ADB to reduce disconnects. */ if (nic->device_type == XFRAME_II_DEVICE) { val64 = WREQ_SPLIT_MASK_SET_MASK(255); writeq(val64, &bar0->wreq_split_mask); } /* Setting Link stability period to 64 ms */ if (nic->device_type == XFRAME_II_DEVICE) { val64 = MISC_LINK_STABILITY_PRD(3); writeq(val64, &bar0->misc_control); } return SUCCESS; } #define LINK_UP_DOWN_INTERRUPT 1 #define MAC_RMAC_ERR_TIMER 2 static int s2io_link_fault_indication(nic_t *nic) { if (nic->intr_type != INTA) return MAC_RMAC_ERR_TIMER; if (nic->device_type == XFRAME_II_DEVICE) return LINK_UP_DOWN_INTERRUPT; else return MAC_RMAC_ERR_TIMER; } /** * en_dis_able_nic_intrs - Enable or Disable the interrupts * @nic: device private variable, * @mask: A mask indicating which Intr block must be modified and, * @flag: A flag indicating whether to enable or disable the Intrs. * Description: This function will either disable or enable the interrupts * depending on the flag argument. The mask argument can be used to * enable/disable any Intr block. * Return Value: NONE. */ static void en_dis_able_nic_intrs(struct s2io_nic *nic, u16 mask, int flag) { XENA_dev_config_t __iomem *bar0 = nic->bar0; register u64 val64 = 0, temp64 = 0; /* Top level interrupt classification */ /* PIC Interrupts */ if ((mask & (TX_PIC_INTR | RX_PIC_INTR))) { /* Enable PIC Intrs in the general intr mask register */ val64 = TXPIC_INT_M | PIC_RX_INT_M; if (flag == ENABLE_INTRS) { temp64 = readq(&bar0->general_int_mask); temp64 &= ~((u64) val64); writeq(temp64, &bar0->general_int_mask); /* * If Hercules adapter enable GPIO otherwise * disabled all PCIX, Flash, MDIO, IIC and GPIO * interrupts for now. * TODO */ if (s2io_link_fault_indication(nic) == LINK_UP_DOWN_INTERRUPT ) { temp64 = readq(&bar0->pic_int_mask); temp64 &= ~((u64) PIC_INT_GPIO); writeq(temp64, &bar0->pic_int_mask); temp64 = readq(&bar0->gpio_int_mask); temp64 &= ~((u64) GPIO_INT_MASK_LINK_UP); writeq(temp64, &bar0->gpio_int_mask); } else { writeq(DISABLE_ALL_INTRS, &bar0->pic_int_mask); } /* * No MSI Support is available presently, so TTI and * RTI interrupts are also disabled. */ } else if (flag == DISABLE_INTRS) { /* * Disable PIC Intrs in the general * intr mask register */ writeq(DISABLE_ALL_INTRS, &bar0->pic_int_mask); temp64 = readq(&bar0->general_int_mask); val64 |= temp64; writeq(val64, &bar0->general_int_mask); } } /* DMA Interrupts */ /* Enabling/Disabling Tx DMA interrupts */ if (mask & TX_DMA_INTR) { /* Enable TxDMA Intrs in the general intr mask register */ val64 = TXDMA_INT_M; if (flag == ENABLE_INTRS) { temp64 = readq(&bar0->general_int_mask); temp64 &= ~((u64) val64); writeq(temp64, &bar0->general_int_mask); /* * Keep all interrupts other than PFC interrupt * and PCC interrupt disabled in DMA level. */ val64 = DISABLE_ALL_INTRS & ~(TXDMA_PFC_INT_M | TXDMA_PCC_INT_M); writeq(val64, &bar0->txdma_int_mask); /* * Enable only the MISC error 1 interrupt in PFC block */ val64 = DISABLE_ALL_INTRS & (~PFC_MISC_ERR_1); writeq(val64, &bar0->pfc_err_mask); /* * Enable only the FB_ECC error interrupt in PCC block */ val64 = DISABLE_ALL_INTRS & (~PCC_FB_ECC_ERR); writeq(val64, &bar0->pcc_err_mask); } else if (flag == DISABLE_INTRS) { /* * Disable TxDMA Intrs in the general intr mask * register */ writeq(DISABLE_ALL_INTRS, &bar0->txdma_int_mask); writeq(DISABLE_ALL_INTRS, &bar0->pfc_err_mask); temp64 = readq(&bar0->general_int_mask); val64 |= temp64; writeq(val64, &bar0->general_int_mask); } } /* Enabling/Disabling Rx DMA interrupts */ if (mask & RX_DMA_INTR) { /* Enable RxDMA Intrs in the general intr mask register */ val64 = RXDMA_INT_M; if (flag == ENABLE_INTRS) { temp64 = readq(&bar0->general_int_mask); temp64 &= ~((u64) val64); writeq(temp64, &bar0->general_int_mask); /* * All RxDMA block interrupts are disabled for now * TODO */ writeq(DISABLE_ALL_INTRS, &bar0->rxdma_int_mask); } else if (flag == DISABLE_INTRS) { /* * Disable RxDMA Intrs in the general intr mask * register */ writeq(DISABLE_ALL_INTRS, &bar0->rxdma_int_mask); temp64 = readq(&bar0->general_int_mask); val64 |= temp64; writeq(val64, &bar0->general_int_mask); } } /* MAC Interrupts */ /* Enabling/Disabling MAC interrupts */ if (mask & (TX_MAC_INTR | RX_MAC_INTR)) { val64 = TXMAC_INT_M | RXMAC_INT_M; if (flag == ENABLE_INTRS) { temp64 = readq(&bar0->general_int_mask); temp64 &= ~((u64) val64); writeq(temp64, &bar0->general_int_mask); /* * All MAC block error interrupts are disabled for now * TODO */ } else if (flag == DISABLE_INTRS) { /* * Disable MAC Intrs in the general intr mask register */ writeq(DISABLE_ALL_INTRS, &bar0->mac_int_mask); writeq(DISABLE_ALL_INTRS, &bar0->mac_rmac_err_mask); temp64 = readq(&bar0->general_int_mask); val64 |= temp64; writeq(val64, &bar0->general_int_mask); } } /* XGXS Interrupts */ if (mask & (TX_XGXS_INTR | RX_XGXS_INTR)) { val64 = TXXGXS_INT_M | RXXGXS_INT_M; if (flag == ENABLE_INTRS) { temp64 = readq(&bar0->general_int_mask); temp64 &= ~((u64) val64); writeq(temp64, &bar0->general_int_mask); /* * All XGXS block error interrupts are disabled for now * TODO */ writeq(DISABLE_ALL_INTRS, &bar0->xgxs_int_mask); } else if (flag == DISABLE_INTRS) { /* * Disable MC Intrs in the general intr mask register */ writeq(DISABLE_ALL_INTRS, &bar0->xgxs_int_mask); temp64 = readq(&bar0->general_int_mask); val64 |= temp64; writeq(val64, &bar0->general_int_mask); } } /* Memory Controller(MC) interrupts */ if (mask & MC_INTR) { val64 = MC_INT_M; if (flag == ENABLE_INTRS) { temp64 = readq(&bar0->general_int_mask); temp64 &= ~((u64) val64); writeq(temp64, &bar0->general_int_mask); /* * Enable all MC Intrs. */ writeq(0x0, &bar0->mc_int_mask); writeq(0x0, &bar0->mc_err_mask); } else if (flag == DISABLE_INTRS) { /* * Disable MC Intrs in the general intr mask register */ writeq(DISABLE_ALL_INTRS, &bar0->mc_int_mask); temp64 = readq(&bar0->general_int_mask); val64 |= temp64; writeq(val64, &bar0->general_int_mask); } } /* Tx traffic interrupts */ if (mask & TX_TRAFFIC_INTR) { val64 = TXTRAFFIC_INT_M; if (flag == ENABLE_INTRS) { temp64 = readq(&bar0->general_int_mask); temp64 &= ~((u64) val64); writeq(temp64, &bar0->general_int_mask); /* * Enable all the Tx side interrupts * writing 0 Enables all 64 TX interrupt levels */ writeq(0x0, &bar0->tx_traffic_mask); } else if (flag == DISABLE_INTRS) { /* * Disable Tx Traffic Intrs in the general intr mask * register. */ writeq(DISABLE_ALL_INTRS, &bar0->tx_traffic_mask); temp64 = readq(&bar0->general_int_mask); val64 |= temp64; writeq(val64, &bar0->general_int_mask); } } /* Rx traffic interrupts */ if (mask & RX_TRAFFIC_INTR) { val64 = RXTRAFFIC_INT_M; if (flag == ENABLE_INTRS) { temp64 = readq(&bar0->general_int_mask); temp64 &= ~((u64) val64); writeq(temp64, &bar0->general_int_mask); /* writing 0 Enables all 8 RX interrupt levels */ writeq(0x0, &bar0->rx_traffic_mask); } else if (flag == DISABLE_INTRS) { /* * Disable Rx Traffic Intrs in the general intr mask * register. */ writeq(DISABLE_ALL_INTRS, &bar0->rx_traffic_mask); temp64 = readq(&bar0->general_int_mask); val64 |= temp64; writeq(val64, &bar0->general_int_mask); } } } static int check_prc_pcc_state(u64 val64, int flag, int rev_id, int herc) { int ret = 0; if (flag == FALSE) { if ((!herc && (rev_id >= 4)) || herc) { if (!(val64 & ADAPTER_STATUS_RMAC_PCC_IDLE) && ((val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) == ADAPTER_STATUS_RC_PRC_QUIESCENT)) { ret = 1; } }else { if (!(val64 & ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE) && ((val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) == ADAPTER_STATUS_RC_PRC_QUIESCENT)) { ret = 1; } } } else { if ((!herc && (rev_id >= 4)) || herc) { if (((val64 & ADAPTER_STATUS_RMAC_PCC_IDLE) == ADAPTER_STATUS_RMAC_PCC_IDLE) && (!(val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) || ((val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) == ADAPTER_STATUS_RC_PRC_QUIESCENT))) { ret = 1; } } else { if (((val64 & ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE) == ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE) && (!(val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) || ((val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) == ADAPTER_STATUS_RC_PRC_QUIESCENT))) { ret = 1; } } } return ret; } /** * verify_xena_quiescence - Checks whether the H/W is ready * @val64 : Value read from adapter status register. * @flag : indicates if the adapter enable bit was ever written once * before. * Description: Returns whether the H/W is ready to go or not. Depending * on whether adapter enable bit was written or not the comparison * differs and the calling function passes the input argument flag to * indicate this. * Return: 1 If xena is quiescence * 0 If Xena is not quiescence */ static int verify_xena_quiescence(nic_t *sp, u64 val64, int flag) { int ret = 0, herc; u64 tmp64 = ~((u64) val64); int rev_id = get_xena_rev_id(sp->pdev); herc = (sp->device_type == XFRAME_II_DEVICE); if (! (tmp64 & (ADAPTER_STATUS_TDMA_READY | ADAPTER_STATUS_RDMA_READY | ADAPTER_STATUS_PFC_READY | ADAPTER_STATUS_TMAC_BUF_EMPTY | ADAPTER_STATUS_PIC_QUIESCENT | ADAPTER_STATUS_MC_DRAM_READY | ADAPTER_STATUS_MC_QUEUES_READY | ADAPTER_STATUS_M_PLL_LOCK | ADAPTER_STATUS_P_PLL_LOCK))) { ret = check_prc_pcc_state(val64, flag, rev_id, herc); } return ret; } /** * fix_mac_address - Fix for Mac addr problem on Alpha platforms * @sp: Pointer to device specifc structure * Description : * New procedure to clear mac address reading problems on Alpha platforms * */ static void fix_mac_address(nic_t * sp) { XENA_dev_config_t __iomem *bar0 = sp->bar0; u64 val64; int i = 0; while (fix_mac[i] != END_SIGN) { writeq(fix_mac[i++], &bar0->gpio_control); udelay(10); val64 = readq(&bar0->gpio_control); } } /** * start_nic - Turns the device on * @nic : device private variable. * Description: * This function actually turns the device on. Before this function is * called,all Registers are configured from their reset states * and shared memory is allocated but the NIC is still quiescent. On * calling this function, the device interrupts are cleared and the NIC is * literally switched on by writing into the adapter control register. * Return Value: * SUCCESS on success and -1 on failure. */ static int start_nic(struct s2io_nic *nic) { XENA_dev_config_t __iomem *bar0 = nic->bar0; struct net_device *dev = nic->dev; register u64 val64 = 0; u16 interruptible; u16 subid, i; mac_info_t *mac_control; struct config_param *config; mac_control = &nic->mac_control; config = &nic->config; /* PRC Initialization and configuration */ for (i = 0; i < config->rx_ring_num; i++) { writeq((u64) mac_control->rings[i].rx_blocks[0].block_dma_addr, &bar0->prc_rxd0_n[i]); val64 = readq(&bar0->prc_ctrl_n[i]); if (nic->config.bimodal) val64 |= PRC_CTRL_BIMODAL_INTERRUPT; if (nic->rxd_mode == RXD_MODE_1) val64 |= PRC_CTRL_RC_ENABLED; else val64 |= PRC_CTRL_RC_ENABLED | PRC_CTRL_RING_MODE_3; writeq(val64, &bar0->prc_ctrl_n[i]); } if (nic->rxd_mode == RXD_MODE_3B) { /* Enabling 2 buffer mode by writing into Rx_pa_cfg reg. */ val64 = readq(&bar0->rx_pa_cfg); val64 |= RX_PA_CFG_IGNORE_L2_ERR; writeq(val64, &bar0->rx_pa_cfg); } /* * Enabling MC-RLDRAM. After enabling the device, we timeout * for around 100ms, which is approximately the time required * for the device to be ready for operation. */ val64 = readq(&bar0->mc_rldram_mrs); val64 |= MC_RLDRAM_QUEUE_SIZE_ENABLE | MC_RLDRAM_MRS_ENABLE; SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF); val64 = readq(&bar0->mc_rldram_mrs); msleep(100); /* Delay by around 100 ms. */ /* Enabling ECC Protection. */ val64 = readq(&bar0->adapter_control); val64 &= ~ADAPTER_ECC_EN; writeq(val64, &bar0->adapter_control); /* * Clearing any possible Link state change interrupts that * could have popped up just before Enabling the card. */ val64 = readq(&bar0->mac_rmac_err_reg); if (val64) writeq(val64, &bar0->mac_rmac_err_reg); /* * Verify if the device is ready to be enabled, if so enable * it. */ val64 = readq(&bar0->adapter_status); if (!verify_xena_quiescence(nic, val64, nic->device_enabled_once)) { DBG_PRINT(ERR_DBG, "%s: device is not ready, ", dev->name); DBG_PRINT(ERR_DBG, "Adapter status reads: 0x%llx\n", (unsigned long long) val64); return FAILURE; } /* Enable select interrupts */ if (nic->intr_type != INTA) en_dis_able_nic_intrs(nic, ENA_ALL_INTRS, DISABLE_INTRS); else { interruptible = TX_TRAFFIC_INTR | RX_TRAFFIC_INTR; interruptible |= TX_PIC_INTR | RX_PIC_INTR; interruptible |= TX_MAC_INTR | RX_MAC_INTR; en_dis_able_nic_intrs(nic, interruptible, ENABLE_INTRS); } /* * With some switches, link might be already up at this point. * Because of this weird behavior, when we enable laser, * we may not get link. We need to handle this. We cannot * figure out which switch is misbehaving. So we are forced to * make a global change. */ /* Enabling Laser. */ val64 = readq(&bar0->adapter_control); val64 |= ADAPTER_EOI_TX_ON; writeq(val64, &bar0->adapter_control); /* SXE-002: Initialize link and activity LED */ subid = nic->pdev->subsystem_device; if (((subid & 0xFF) >= 0x07) && (nic->device_type == XFRAME_I_DEVICE)) { val64 = readq(&bar0->gpio_control); val64 |= 0x0000800000000000ULL; writeq(val64, &bar0->gpio_control); val64 = 0x0411040400000000ULL; writeq(val64, (void __iomem *)bar0 + 0x2700); } /* * Don't see link state interrupts on certain switches, so * directly scheduling a link state task from here. */ schedule_work(&nic->set_link_task); return SUCCESS; } /** * s2io_txdl_getskb - Get the skb from txdl, unmap and return skb */ static struct sk_buff *s2io_txdl_getskb(fifo_info_t *fifo_data, TxD_t *txdlp, int get_off) { nic_t *nic = fifo_data->nic; struct sk_buff *skb; TxD_t *txds; u16 j, frg_cnt; txds = txdlp; if (txds->Host_Control == (u64)(long)nic->ufo_in_band_v) { pci_unmap_single(nic->pdev, (dma_addr_t) txds->Buffer_Pointer, sizeof(u64), PCI_DMA_TODEVICE); txds++; } skb = (struct sk_buff *) ((unsigned long) txds->Host_Control); if (!skb) { memset(txdlp, 0, (sizeof(TxD_t) * fifo_data->max_txds)); return NULL; } pci_unmap_single(nic->pdev, (dma_addr_t) txds->Buffer_Pointer, skb->len - skb->data_len, PCI_DMA_TODEVICE); frg_cnt = skb_shinfo(skb)->nr_frags; if (frg_cnt) { txds++; for (j = 0; j < frg_cnt; j++, txds++) { skb_frag_t *frag = &skb_shinfo(skb)->frags[j]; if (!txds->Buffer_Pointer) break; pci_unmap_page(nic->pdev, (dma_addr_t) txds->Buffer_Pointer, frag->size, PCI_DMA_TODEVICE); } } txdlp->Host_Control = 0; return(skb); } /** * free_tx_buffers - Free all queued Tx buffers * @nic : device private variable. * Description: * Free all queued Tx buffers. * Return Value: void */ static void free_tx_buffers(struct s2io_nic *nic) { struct net_device *dev = nic->dev; struct sk_buff *skb; TxD_t *txdp; int i, j; mac_info_t *mac_control; struct config_param *config; int cnt = 0; mac_control = &nic->mac_control; config = &nic->config; for (i = 0; i < config->tx_fifo_num; i++) { for (j = 0; j < config->tx_cfg[i].fifo_len - 1; j++) { txdp = (TxD_t *) mac_control->fifos[i].list_info[j]. list_virt_addr; skb = s2io_txdl_getskb(&mac_control->fifos[i], txdp, j); if (skb) { dev_kfree_skb(skb); cnt++; } } DBG_PRINT(INTR_DBG, "%s:forcibly freeing %d skbs on FIFO%d\n", dev->name, cnt, i); mac_control->fifos[i].tx_curr_get_info.offset = 0; mac_control->fifos[i].tx_curr_put_info.offset = 0; } } /** * stop_nic - To stop the nic * @nic ; device private variable. * Description: * This function does exactly the opposite of what the start_nic() * function does. This function is called to stop the device. * Return Value: * void. */ static void stop_nic(struct s2io_nic *nic) { XENA_dev_config_t __iomem *bar0 = nic->bar0; register u64 val64 = 0; u16 interruptible, i; mac_info_t *mac_control; struct config_param *config; mac_control = &nic->mac_control; config = &nic->config; /* Disable all interrupts */ interruptible = TX_TRAFFIC_INTR | RX_TRAFFIC_INTR; interruptible |= TX_PIC_INTR | RX_PIC_INTR; interruptible |= TX_MAC_INTR | RX_MAC_INTR; en_dis_able_nic_intrs(nic, interruptible, DISABLE_INTRS); /* Disable PRCs */ for (i = 0; i < config->rx_ring_num; i++) { val64 = readq(&bar0->prc_ctrl_n[i]); val64 &= ~((u64) PRC_CTRL_RC_ENABLED); writeq(val64, &bar0->prc_ctrl_n[i]); } } static int fill_rxd_3buf(nic_t *nic, RxD_t *rxdp, struct sk_buff *skb) { struct net_device *dev = nic->dev; struct sk_buff *frag_list; void *tmp; /* Buffer-1 receives L3/L4 headers */ ((RxD3_t*)rxdp)->Buffer1_ptr = pci_map_single (nic->pdev, skb->data, l3l4hdr_size + 4, PCI_DMA_FROMDEVICE); /* skb_shinfo(skb)->frag_list will have L4 data payload */ skb_shinfo(skb)->frag_list = dev_alloc_skb(dev->mtu + ALIGN_SIZE); if (skb_shinfo(skb)->frag_list == NULL) { DBG_PRINT(ERR_DBG, "%s: dev_alloc_skb failed\n ", dev->name); return -ENOMEM ; } frag_list = skb_shinfo(skb)->frag_list; frag_list->next = NULL; tmp = (void *)ALIGN((long)frag_list->data, ALIGN_SIZE + 1); frag_list->data = tmp; frag_list->tail = tmp; /* Buffer-2 receives L4 data payload */ ((RxD3_t*)rxdp)->Buffer2_ptr = pci_map_single(nic->pdev, frag_list->data, dev->mtu, PCI_DMA_FROMDEVICE); rxdp->Control_2 |= SET_BUFFER1_SIZE_3(l3l4hdr_size + 4); rxdp->Control_2 |= SET_BUFFER2_SIZE_3(dev->mtu); return SUCCESS; } /** * fill_rx_buffers - Allocates the Rx side skbs * @nic: device private variable * @ring_no: ring number * Description: * The function allocates Rx side skbs and puts the physical * address of these buffers into the RxD buffer pointers, so that the NIC * can DMA the received frame into these locations. * The NIC supports 3 receive modes, viz * 1. single buffer, * 2. three buffer and * 3. Five buffer modes. * Each mode defines how many fragments the received frame will be split * up into by the NIC. The frame is split into L3 header, L4 Header, * L4 payload in three buffer mode and in 5 buffer mode, L4 payload itself * is split into 3 fragments. As of now only single buffer mode is * supported. * Return Value: * SUCCESS on success or an appropriate -ve value on failure. */ static int fill_rx_buffers(struct s2io_nic *nic, int ring_no) { struct net_device *dev = nic->dev; struct sk_buff *skb; RxD_t *rxdp; int off, off1, size, block_no, block_no1; u32 alloc_tab = 0; u32 alloc_cnt; mac_info_t *mac_control; struct config_param *config; u64 tmp; buffAdd_t *ba; #ifndef CONFIG_S2IO_NAPI unsigned long flags; #endif RxD_t *first_rxdp = NULL; mac_control = &nic->mac_control; config = &nic->config; alloc_cnt = mac_control->rings[ring_no].pkt_cnt - atomic_read(&nic->rx_bufs_left[ring_no]); while (alloc_tab < alloc_cnt) { block_no = mac_control->rings[ring_no].rx_curr_put_info. block_index; block_no1 = mac_control->rings[ring_no].rx_curr_get_info.