From 3e6cb2d38a9c9758170813497a860c64543643d5 Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Tue, 21 Feb 2006 18:32:14 +0000 Subject: [MIPS] Use "=R" constraint to avoid compiler errors in cmpxchg(). Signed-off-by: Ralf Baechle --- include/asm-mips/system.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'include') diff --git a/include/asm-mips/system.h b/include/asm-mips/system.h index e8e5d41433..ddae9bae31 100644 --- a/include/asm-mips/system.h +++ b/include/asm-mips/system.h @@ -322,7 +322,7 @@ static inline unsigned long __cmpxchg_u32(volatile int * m, unsigned long old, #endif "2: \n" " .set pop \n" - : "=&r" (retval), "=m" (*m) + : "=&r" (retval), "=R" (*m) : "R" (*m), "Jr" (old), "Jr" (new) : "memory"); } else if (cpu_has_llsc) { @@ -342,7 +342,7 @@ static inline unsigned long __cmpxchg_u32(volatile int * m, unsigned long old, #endif "2: \n" " .set pop \n" - : "=&r" (retval), "=m" (*m) + : "=&r" (retval), "=R" (*m) : "R" (*m), "Jr" (old), "Jr" (new) : "memory"); } else { @@ -379,7 +379,7 @@ static inline unsigned long __cmpxchg_u64(volatile int * m, unsigned long old, #endif "2: \n" " .set pop \n" - : "=&r" (retval), "=m" (*m) + : "=&r" (retval), "=R" (*m) : "R" (*m), "Jr" (old), "Jr" (new) : "memory"); } else if (cpu_has_llsc) { @@ -397,7 +397,7 @@ static inline unsigned long __cmpxchg_u64(volatile int * m, unsigned long old, #endif "2: \n" " .set pop \n" - : "=&r" (retval), "=m" (*m) + : "=&r" (retval), "=R" (*m) : "R" (*m), "Jr" (old), "Jr" (new) : "memory"); } else { -- cgit v1.2.2 From 9b6695a8adfe0916e81ddd810a5b9db3eb8b0e46 Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Thu, 23 Feb 2006 12:23:27 +0000 Subject: [MIPS] SMP: Fix initialization order bug. A recent change requires cpu_possible_map to be initialized before smp_sched_init() but most MIPS platforms were initializing their processors in the prom_prepare_cpus callback of smp_prepare_cpus. The simple fix of calling prom_prepare_cpus from one of the earlier SMP initialization hooks doesn't work well either since IPIs may require init_IRQ() to have completed, so bit the bullet and split prom_prepare_cpus into two initialization functions, plat_smp_setup which is called early from setup_arch and plat_prepare_cpus called where prom_prepare_cpus used to be called. Signed-off-by: Ralf Baechle --- include/asm-mips/smp.h | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/include/asm-mips/smp.h b/include/asm-mips/smp.h index 5618f1e12f..75c6fe7c21 100644 --- a/include/asm-mips/smp.h +++ b/include/asm-mips/smp.h @@ -58,7 +58,9 @@ static inline int num_booting_cpus(void) return cpus_weight(cpu_callout_map); } -/* These are defined by the board-specific code. */ +/* + * These are defined by the board-specific code. + */ /* * Cause the function described by call_data to be executed on the passed @@ -79,7 +81,12 @@ extern void prom_boot_secondary(int cpu, struct task_struct *idle); extern void prom_init_secondary(void); /* - * Detect available CPUs, populate phys_cpu_present_map before smp_init + * Populate cpu_possible_map before smp_init, called from setup_arch. + */ +extern void plat_smp_setup(void); + +/* + * Called after init_IRQ but before __cpu_up. */ extern void prom_prepare_cpus(unsigned int max_cpus); -- cgit v1.2.2 From 92f22c183cd669c8575767fede8fe43bb4f7bce9 Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Thu, 23 Feb 2006 14:10:53 +0000 Subject: [MIPS] Fix atomic*_sub_if_positive return value. Reported and initial fix by Thomas Koeller , rewritten by me. Signed-off-by: Ralf Baechle --- include/asm-mips/atomic.h | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'include') diff --git a/include/asm-mips/atomic.h b/include/asm-mips/atomic.h index 654b97d3e1..2c8b853376 100644 --- a/include/asm-mips/atomic.h +++ b/include/asm-mips/atomic.h @@ -250,7 +250,10 @@ static __inline__ int atomic_sub_if_positive(int i, atomic_t * v) " subu %0, %1, %3 \n" " bltz %0, 1f \n" " sc %0, %2 \n" + " .set noreorder \n" " beqzl %0, 1b \n" + " subu %0, %1, %3 \n" + " .set reorder \n" " sync \n" "1: \n" " .set mips0 \n" @@ -266,7 +269,10 @@ static __inline__ int atomic_sub_if_positive(int i, atomic_t * v) " subu %0, %1, %3 \n" " bltz %0, 1f \n" " sc %0, %2 \n" + " .set noreorder \n" " beqz %0, 1b \n" + " subu %0, %1, %3 \n" + " .set reorder \n" " sync \n" "1: \n" " .set mips0 \n" @@ -598,7 +604,10 @@ static __inline__ long atomic64_sub_if_positive(long i, atomic64_t * v) " dsubu %0, %1, %3 \n" " bltz %0, 1f \n" " scd %0, %2 \n" + " .set noreorder \n" " beqzl %0, 1b \n" + " dsubu %0, %1, %3 \n" + " .set reorder \n" " sync \n" "1: \n" " .set mips0 \n" @@ -614,7 +623,10 @@ static __inline__ long atomic64_sub_if_positive(long i, atomic64_t * v) " dsubu %0, %1, %3 \n" " bltz %0, 1f \n" " scd %0, %2 \n" + " .set noreorder \n" " beqz %0, 1b \n" + " dsubu %0, %1, %3 \n" + " .set reorder \n" " sync \n" "1: \n" " .set mips0 \n" -- cgit v1.2.2