diff options
author | Masato Noguchi <Masato.Noguchi@jp.sony.com> | 2006-10-24 12:31:14 -0400 |
---|---|---|
committer | Paul Mackerras <paulus@samba.org> | 2006-10-25 00:20:20 -0400 |
commit | 24f43b33f74c8e8c8aabc40b728eaf9137802942 (patch) | |
tree | 013c3b7eabc49ef8706f6e989ee88aa9ec5ef04d /arch/powerpc | |
parent | 5414c6be57dd02e089c3eba1f5134f441733d013 (diff) |
[POWERPC] spufs: wrap mfc sdr access
SPRN_SDR1 and the SPE's MFC SDR are hypervisor resources and
are not accessible from a logical partition. This change adds an
access wrapper.
When running on bare H/W, the spufs needs to only set the SPE's MFC SDR
to the value of the PPE's SPRN_SDR1 once at SPE initialization, so this
change renames mfc_sdr_set() to mfc_sdr_setup() and moves the
access of SPRN_SDR1 into the mmio wrapper. It also removes the now
unneeded member mfc_sdr_RW from struct spu_priv1_collapsed.
Signed-off-by: Masato Noguchi <Masato.Noguchi@jp.sony.com>
Signed-off-by: Geoff Levand <geoffrey.levand@am.sony.com>
Signed-off-by: Arnd Bergmann <arnd.bergmann@de.ibm.com>
--
Signed-off-by: Paul Mackerras <paulus@samba.org>
Diffstat (limited to 'arch/powerpc')
-rw-r--r-- | arch/powerpc/platforms/cell/spu_base.c | 2 | ||||
-rw-r--r-- | arch/powerpc/platforms/cell/spu_priv1_mmio.c | 6 | ||||
-rw-r--r-- | arch/powerpc/platforms/cell/spufs/switch.c | 3 |
3 files changed, 4 insertions, 7 deletions
diff --git a/arch/powerpc/platforms/cell/spu_base.c b/arch/powerpc/platforms/cell/spu_base.c index d0fb959e3e..d41ad1d6c0 100644 --- a/arch/powerpc/platforms/cell/spu_base.c +++ b/arch/powerpc/platforms/cell/spu_base.c | |||
@@ -805,7 +805,7 @@ static int __init create_spu(struct device_node *spe) | |||
805 | if (ret) | 805 | if (ret) |
806 | goto out_unmap; | 806 | goto out_unmap; |
807 | spin_lock_init(&spu->register_lock); | 807 | spin_lock_init(&spu->register_lock); |
808 | spu_mfc_sdr_set(spu, mfspr(SPRN_SDR1)); | 808 | spu_mfc_sdr_setup(spu); |
809 | spu_mfc_sr1_set(spu, 0x33); | 809 | spu_mfc_sr1_set(spu, 0x33); |
810 | mutex_lock(&spu_mutex); | 810 | mutex_lock(&spu_mutex); |
811 | 811 | ||
diff --git a/arch/powerpc/platforms/cell/spu_priv1_mmio.c b/arch/powerpc/platforms/cell/spu_priv1_mmio.c index 71b69f0a1a..90011f9aab 100644 --- a/arch/powerpc/platforms/cell/spu_priv1_mmio.c +++ b/arch/powerpc/platforms/cell/spu_priv1_mmio.c | |||
@@ -84,9 +84,9 @@ static void mfc_dsisr_set(struct spu *spu, u64 dsisr) | |||
84 | out_be64(&spu->priv1->mfc_dsisr_RW, dsisr); | 84 | out_be64(&spu->priv1->mfc_dsisr_RW, dsisr); |
85 | } | 85 | } |
86 | 86 | ||
87 | static void mfc_sdr_set(struct spu *spu, u64 sdr) | 87 | static void mfc_sdr_setup(struct spu *spu) |
88 | { | 88 | { |
89 | out_be64(&spu->priv1->mfc_sdr_RW, sdr); | 89 | out_be64(&spu->priv1->mfc_sdr_RW, mfspr(SPRN_SDR1)); |
90 | } | 90 | } |
91 | 91 | ||
92 | static void mfc_sr1_set(struct spu *spu, u64 sr1) | 92 | static void mfc_sr1_set(struct spu *spu, u64 sr1) |
@@ -146,7 +146,7 @@ const struct spu_priv1_ops spu_priv1_mmio_ops = | |||
146 | .mfc_dar_get = mfc_dar_get, | 146 | .mfc_dar_get = mfc_dar_get, |
147 | .mfc_dsisr_get = mfc_dsisr_get, | 147 | .mfc_dsisr_get = mfc_dsisr_get, |
148 | .mfc_dsisr_set = mfc_dsisr_set, | 148 | .mfc_dsisr_set = mfc_dsisr_set, |
149 | .mfc_sdr_set = mfc_sdr_set, | 149 | .mfc_sdr_setup = mfc_sdr_setup, |
150 | .mfc_sr1_set = mfc_sr1_set, | 150 | .mfc_sr1_set = mfc_sr1_set, |
151 | .mfc_sr1_get = mfc_sr1_get, | 151 | .mfc_sr1_get = mfc_sr1_get, |
152 | .mfc_tclass_id_set = mfc_tclass_id_set, | 152 | .mfc_tclass_id_set = mfc_tclass_id_set, |
diff --git a/arch/powerpc/platforms/cell/spufs/switch.c b/arch/powerpc/platforms/cell/spufs/switch.c index 0f782ca662..b85347ff6b 100644 --- a/arch/powerpc/platforms/cell/spufs/switch.c +++ b/arch/powerpc/platforms/cell/spufs/switch.c | |||
@@ -2165,9 +2165,6 @@ static void init_priv1(struct spu_state *csa) | |||
2165 | MFC_STATE1_PROBLEM_STATE_MASK | | 2165 | MFC_STATE1_PROBLEM_STATE_MASK | |
2166 | MFC_STATE1_RELOCATE_MASK | MFC_STATE1_BUS_TLBIE_MASK; | 2166 | MFC_STATE1_RELOCATE_MASK | MFC_STATE1_BUS_TLBIE_MASK; |
2167 | 2167 | ||
2168 | /* Set storage description. */ | ||
2169 | csa->priv1.mfc_sdr_RW = mfspr(SPRN_SDR1); | ||
2170 | |||
2171 | /* Enable OS-specific set of interrupts. */ | 2168 | /* Enable OS-specific set of interrupts. */ |
2172 | csa->priv1.int_mask_class0_RW = CLASS0_ENABLE_DMA_ALIGNMENT_INTR | | 2169 | csa->priv1.int_mask_class0_RW = CLASS0_ENABLE_DMA_ALIGNMENT_INTR | |
2173 | CLASS0_ENABLE_INVALID_DMA_COMMAND_INTR | | 2170 | CLASS0_ENABLE_INVALID_DMA_COMMAND_INTR | |