litmus2008.git/arch/ia64/sn, branch master

[IA64] Update Altix nofault code

2008-01-03T21:22:54+00:00

Montecito and Montvale behaves slightly differently than previous
Itanium processors, resulting in the MCA due to a failed PIO read
to sometimes surfacing outside the nofault code.  This code is
based on discussions with Intel CPU architects and verified at
customer sites.

Signed-off-by: Russ Anderson 
Signed-off-by: Tony Luck

[IA64] Fix Altix BTE error return status

2007-12-19T19:19:19+00:00

The Altix shub2 BTE error detail bits are in a different location
than on shub1.  The current code does not take this into account
resulting in all shub2 BTE failures mapping to "unknown".

This patch reads the error detail bits from the proper location,
so the correct BTE failure reason is returned for both shub1
and shub2.

Signed-off-by: Russ Anderson 
Signed-off-by: Tony Luck

[IA64] Two trivial spelling fixes

2007-12-19T01:02:21+00:00

s/addres/address/
s/performanc/performance/

Signed-off-by: Joe Perches 
Signed-off-by: Tony Luck

[IA64] Add missing "space" to concatenated strings

2007-12-08T00:12:17+00:00

Signed-off-by: Joe Perches 
Signed-off-by: Tony Luck

[IA64] SGI Altix : fix bug in sn_io_late_init()

2007-12-08T00:11:37+00:00

When initializing pci_controller->node to point to the closest node we need
to take into consideration that a PIC PCI Bridge ASIC can be connected to a
headless/memless node just like the TIOCP and TIOCE Bridge ASICs

Signed-off-by: Mike Habeck 
Signed-off-by: Tony Luck

[IA64] XPC heartbeat timer function must run on CPU 0

2007-11-09T20:59:14+00:00

Currently, XPC's heartbeat timer function runs on whatever CPU modprobe/insmod
ran on when XPC was started. To avoid the heartbeat from being delayed for
long periods the timer function must run on CPU 0.

N.B. Altix doesn't currently allow cpu0 to be taken offline, so this is
safe for now.  This code must be revised when offline of cpu0 is enabled.

Signed-off-by: Dean Nelson 
Signed-off-by: Tony Luck

[IA64] Disable/re-enable CPE interrupts on Altix

2007-11-06T23:40:31+00:00

When the CPE handler encounters too many CPEs (such as a solid single
bit memory error), it sets up a polling timer and disables the CPE
interrupt (to avoid excessive overhead logging the stream of single
bit errors).  disable_irq_nosync() calls chip->disable() to provide
a chipset specifiec interface for disabling the interrupt.  This patch
adds the Altix specific support to disable and re-enable the CPE interrupt.

Signed-off-by: Russ Anderson (rja@sgi.com)
Signed-off-by: Tony Luck

[IA64] arch/ia64/sn/kernel/mca.c: undo lock when sn_oemdata can't be extended

2007-10-29T21:32:30+00:00

Clean up locking state in failure path.

Signed-off-by: Roel Kluin <12o3l@tiscali.nl>
Cc: Jes Sorensen 
Cc: "Luck, Tony" 
Signed-off-by: Andrew Morton 
Signed-off-by: Tony Luck

Update arch/ to use sg helpers

2007-10-22T19:19:59+00:00

Signed-off-by: Jens Axboe

Add missing newlines to some uses of dev_ messages

2007-10-18T21:37:28+00:00

Found these while looking at printk uses.

Add missing newlines to dev_ uses
Add missing KERN_ prefixes to multiline dev_s
Fixed a wierd->weird spelling typo
Added a newline to a printk

Signed-off-by: Joe Perches 
Cc: "Luck, Tony" 
Cc: Jens Axboe 
Cc: Mark M. Hoffman 
Cc: Roland Dreier 
Cc: Tilman Schmidt 
Cc: David Woodhouse 
Cc: Jeff Garzik 
Cc: Stephen Hemminger 
Cc: Greg KH 
Cc: Jeremy Fitzhardinge 
Cc: Geert Uytterhoeven 
Cc: Alessandro Zummo 
Cc: David Brownell 
Cc: James Smart 
Cc: Andrew Vasquez 
Cc: "Antonino A. Daplas" 
Cc: Evgeniy Polyakov 
Cc: Russell King 
Cc: Jaroslav Kysela 
Cc: Takashi Iwai 
Signed-off-by: Andrew Morton 
Signed-off-by: Linus Torvalds