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# ALSA PCI drivers

menuconfig SND_PCI
	bool "PCI sound devices"
	depends on PCI
	default y
	help
	  Support for sound devices connected via the PCI bus.

if SND_PCI

config SND_AD1889
	tristate "Analog Devices AD1889"
	select SND_AC97_CODEC
	help
	  Say Y here to include support for the integrated AC97 sound
	  device found in particular on the Hewlett-Packard [BCJ]-xxx0
	  class PA-RISC workstations, using the AD1819 codec.

	  To compile this as a module, choose M here: the module
	  will be called snd-ad1889.

config SND_ALS300
	tristate "Avance Logic ALS300/ALS300+"
	select SND_PCM
	select SND_AC97_CODEC
	select SND_OPL3_LIB
	help
	  Say 'Y' or 'M' to include support for Avance Logic ALS300/ALS300+

	  To compile this driver as a module, choose M here: the module
	  will be called snd-als300

config SND_ALS4000
	tristate "Avance Logic ALS4000"
	depends on ISA_DMA_API
	select SND_OPL3_LIB
	select SND_MPU401_UART
	select SND_PCM
	select SND_SB_COMMON
	help
	  Say Y here to include support for soundcards based on Avance Logic
	  ALS4000 chips.

	  To compile this driver as a module, choose M here: the module
	  will be called snd-als4000.

config SND_ALI5451
	tristate "ALi M5451 PCI Audio Controller"
	select SND_MPU401_UART
	select SND_AC97_CODEC
	help
	  Say Y here to include support for the integrated AC97 sound
	  device on motherboards using the ALi M5451 Audio Controller
	  (M1535/M1535D/M1535+/M1535D+ south bridges).  Newer chipsets
	  use the "Intel/SiS/nVidia/AMD/ALi AC97 Controller" driver.

	  To compile this driver as a module, choose M here: the module
	  will be called snd-ali5451.

config SND_ATIIXP
	tristate "ATI IXP AC97 Controller"
	select SND_AC97_CODEC
	help
	  Say Y here to include support for the integrated AC97 sound
	  device on motherboards with ATI chipsets (ATI IXP 150/200/250/
	  300/400).

	  To compile this driver as a module, choose M here: the module
	  will be called snd-atiixp.

config SND_ATIIXP_MODEM
	tristate "ATI IXP Modem"
	select SND_AC97_CODEC
	help
	  Say Y here to include support for the integrated MC97 modem on
	  motherboards with ATI chipsets (ATI IXP 150/200/250).

	  To compile this driver as a module, choose M here: the module
	  will be called snd-atiixp-modem.

config SND_AU8810
	tristate "Aureal Advantage"
	select SND_MPU401_UART
	select SND_AC97_CODEC
	help
	  Say Y here to include support for Aureal Advantage soundcards.

	  Supported features: Hardware Mixer, SRC, EQ and SPDIF output.
	  3D support code is in place, but not yet useable. For more info,
	  email the ALSA developer list, or <mjander@users.sourceforge.net>.

	  To compile this driver as a module, choose M here: the module
	  will be called snd-au8810.

config SND_AU8820
	tristate "Aureal Vortex"
	select SND_MPU401_UART
	select SND_AC97_CODEC
	help
	  Say Y here to include support for Aureal Vortex soundcards.

	  Supported features: Hardware Mixer and SRC. For more info, email
	  the ALSA developer list, or <mjander@users.sourceforge.net>.

	  To compile this driver as a module, choose M here: the module
	  will be called snd-au8820.

config SND_AU8830
	tristate "Aureal Vortex 2"
	select SND_MPU401_UART
	select SND_AC97_CODEC
	help
	  Say Y here to include support for Aureal Vortex 2 soundcards.

	  Supported features: Hardware Mixer, SRC, EQ and SPDIF output.
	  3D support code is in place, but not yet useable. For more info,
	  email the ALSA developer list, or <mjander@users.sourceforge.net>.

	  To compile this driver as a module, choose M here: the module
	  will be called snd-au8830.

config SND_AW2
	tristate "Emagic Audiowerk 2"
	help
	  Say Y here to include support for Emagic Audiowerk 2 soundcards.

	  Supported features: Analog and SPDIF output. Analog or SPDIF input.
	  Note: Switch between analog and digital input does not always work.
	  It can produce continuous noise. The workaround is to switch again
	  (and again) between digital and analog input until it works.

	  To compile this driver as a module, choose M here: the module
	  will be called snd-aw2.


config SND_AZT3328
	tristate "Aztech AZF3328 / PCI168"
	select SND_OPL3_LIB
	select SND_MPU401_UART
	select SND_PCM
	select SND_RAWMIDI
	help
	  Say Y here to include support for Aztech AZF3328 (PCI168)
	  soundcards.

	  To compile this driver as a module, choose M here: the module
	  will be called snd-azt3328.

config SND_BT87X
	tristate "Bt87x Audio Capture"
	select SND_PCM
	help
	  If you want to record audio from TV cards based on
	  Brooktree Bt878/Bt879 chips, say Y here and read
	  <file:Documentation/sound/alsa/Bt87x.txt>.

	  To compile this driver as a module, choose M here: the module
	  will be called snd-bt87x.

config SND_BT87X_OVERCLOCK
	bool "Bt87x Audio overclocking"
	depends on SND_BT87X
	help
	  Say Y here if 448000 Hz isn't enough for you and you want to
	  record from the analog input with up to 1792000 Hz.

	  Higher sample rates won't hurt your hardware, but audio
	  quality may suffer.

config SND_CA0106
	tristate "SB Audigy LS / Live 24bit"
	select SND_AC97_CODEC
	select SND_RAWMIDI
	select SND_VMASTER
	help
	  Say Y here to include support for the Sound Blaster Audigy LS
	  and Live 24bit.

	  To compile this driver as a module, choose M here: the module
	  will be called snd-ca0106.

config SND_CMIPCI
	tristate "C-Media 8338, 8738, 8768, 8770"
	select SND_OPL3_LIB
	select SND_MPU401_UART
	select SND_PCM
	help
	  If you want to use soundcards based on C-Media CMI8338, CMI8738,
	  CMI8768 or CMI8770 chips, say Y here and read
	  <file:Documentation/sound/alsa/CMIPCI.txt>.

	  To compile this driver as a module, choose M here: the module
	  will be called snd-cmipci.

config SND_OXYGEN_LIB
        tristate
	select SND_PCM
	select SND_MPU401_UART

config SND_OXYGEN
	tristate "C-Media 8788 (Oxygen)"
	select SND_OXYGEN_LIB
	help
	  Say Y here to include support for sound cards based on the
	  C-Media CMI8788 (Oxygen HD Audio) chip:
	   * Asound A-8788
	   * AuzenTech X-Meridian
	   * Bgears b-Enspirer
	   * Club3D Theatron DTS
	   * HT-Omega Claro (plus)
	   * HT-Omega Claro halo (XT)
	   * Razer Barracuda AC-1
	   * Sondigo Inferno

	  To compile this driver as a module, choose M here: the module
	  will be called snd-oxygen.

config SND_CS4281
	tristate "Cirrus Logic (Sound Fusion) CS4281"
	select SND_OPL3_LIB
	select SND_RAWMIDI
	select SND_AC97_CODEC
	help
	  Say Y here to include support for Cirrus Logic CS4281 chips.

	  To compile this driver as a module, choose M here: the module
	  will be called snd-cs4281.

config SND_CS46XX
	tristate "Cirrus Logic (Sound Fusion) CS4280/CS461x/CS462x/CS463x"
	select SND_RAWMIDI
	select SND_AC97_CODEC
	help
	  Say Y here to include support for Cirrus Logic CS4610/CS4612/
	  CS4614/CS4615/CS4622/CS4624/CS4630/CS4280 chips.

	  To compile this driver as a module, choose M here: the module
	  will be called snd-cs46xx.

config SND_CS46XX_NEW_DSP
	bool "Cirrus Logic (Sound Fusion) New DSP support"
	depends on SND_CS46XX
	default y
	help
	  Say Y here to use a new DSP image for SPDIF and dual codecs.

	  This works better than the old code, so say Y.

config SND_CS5530
	tristate "CS5530 Audio"
	depends on ISA_DMA_API
	select SND_SB16_DSP
	help
	  Say Y here to include support for audio on Cyrix/NatSemi CS5530 chips.

	  To compile this driver as a module, choose M here: the module
	  will be called snd-cs5530.

config SND_CS5535AUDIO
	tristate "CS5535/CS5536 Audio"
	select SND_PCM
	select SND_AC97_CODEC
	help
	  Say Y here to include support for audio on CS5535 chips. It is
	  referred to as NS CS5535 IO or AMD CS5535 IO companion in
	  various literature. This driver also supports the CS5536 audio
	  device. However, for both chips, on certain boards, you may
	  need to use ac97_quirk=hp_only if your board has physically
	  mapped headphone out to master output. If that works for you,
	  send lspci -vvv output to the mailing list so that your board
	  can be identified in the quirks list.

	  To compile this driver as a module, choose M here: the module
	  will be called snd-cs5535audio.

config SND_CTXFI
	tristate "Creative Sound Blaster X-Fi"
	select SND_PCM
	help
	  If you want to use soundcards based on Creative Sound Blastr X-Fi
	  boards with 20k1 or 20k2 chips, say Y here.

	  To compile this driver as a module, choose M here: the module
	  will be called snd-ctxfi.

config SND_DARLA20
	tristate "(Echoaudio) Darla20"
	select FW_LOADER
	select SND_PCM
	help
	  Say 'Y' or 'M' to include support for Echoaudio Darla.

	  To compile this driver as a module, choose M here: the module
	  will be called snd-darla20

config SND_GINA20
	tristate "(Echoaudio) Gina20"
	select FW_LOADER
	select SND_PCM
	help
	  Say 'Y' or 'M' to include support for Echoaudio Gina.

	  To compile this driver as a module, choose M here: the module
	  will be called snd-gina20

config SND_LAYLA20
	tristate "(Echoaudio) Layla20"
	select FW_LOADER
	select SND_RAWMIDI
	select SND_PCM
	help
	  Say 'Y' or 'M' to include support for Echoaudio Layla.

	  To compile this driver as a module, choose M here: the module
	  will be called snd-layla20

config SND_DARLA24
	tristate "(Echoaudio) Darla24"
	select FW_LOADER
	select SND_PCM
	help
	  Say 'Y' or 'M' to include support for Echoaudio Darla24.

	  To compile this driver as a module, choose M here: the module
	  will be called snd-darla24

config SND_GINA24
	tristate "(Echoaudio) Gina24"
	select FW_LOADER
	select SND_PCM
	help
	  Say 'Y' or 'M' to include support for Echoaudio Gina24.

	  To compile this driver as a module, choose M here: the module
	  will be called snd-gina24

config SND_LAYLA24
	tristate "(Echoaudio) Layla24"
	select FW_LOADER
	select SND_RAWMIDI
	select SND_PCM
	help
	  Say 'Y' or 'M' to include support for Echoaudio Layla24.

	  To compile this driver as a module, choose M here: the module
	  will be called snd-layla24

config SND_MONA
	tristate "(Echoaudio) Mona"
	select FW_LOADER
	select SND_RAWMIDI
	select SND_PCM
	help
	  Say 'Y' or 'M' to include support for Echoaudio Mona.

	  To compile this driver as a module, choose M here: the module
	  will be called snd-mona

config SND_MIA
	tristate "(Echoaudio) Mia"
	select FW_LOADER
	select SND_RAWMIDI
	select SND_PCM
	help
	  Say 'Y' or 'M' to include support for Echoaudio Mia and Mia-midi.

	  To compile this driver as a module, choose M here: the module
	  will be called snd-mia

config SND_ECHO3G
	tristate "(Echoaudio) 3G cards"
	select FW_LOADER
	select SND_RAWMIDI
	select SND_PCM
	help
	  Say 'Y' or 'M' to include support for Echoaudio Gina3G and Layla3G.

	  To compile this driver as a module, choose M here: the module
	  will be called snd-echo3g

config SND_INDIGO
	tristate "(Echoaudio) Indigo"
	select FW_LOADER
	select SND_PCM
	help
	  Say 'Y' or 'M' to include support for Echoaudio Indigo.

	  To compile this driver as a module, choose M here: the module
	  will be called snd-indigo

config SND_INDIGOIO
	tristate "(Echoaudio) Indigo IO"
	select FW_LOADER
	select SND_PCM
	help
	  Say 'Y' or 'M' to include support for Echoaudio Indigo IO.

	  To compile this driver as a module, choose M here: the module
	  will be called snd-indigoio

config SND_INDIGODJ
	tristate "(Echoaudio) Indigo DJ"
	select FW_LOADER
	select SND_PCM
	help
	  Say 'Y' or 'M' to include support for Echoaudio Indigo DJ.

	  To compile this driver as a module, choose M here: the module
	  will be called snd-indigodj

config SND_INDIGOIOX
	tristate "(Echoaudio) Indigo IOx"
	select FW_LOADER
	select SND_PCM
	help
	  Say 'Y' or 'M' to include support for Echoaudio Indigo IOx.

	  To compile this driver as a module, choose M here: the module
	  will be called snd-indigoiox

config SND_INDIGODJX
	tristate "(Echoaudio) Indigo DJx"
	select FW_LOADER
	select SND_PCM
	help
	  Say 'Y' or 'M' to include support for Echoaudio Indigo DJx.

	  To compile this driver as a module, choose M here: the module
	  will be called snd-indigodjx

config SND_EMU10K1
	tristate "Emu10k1 (SB Live!, Audigy, E-mu APS)"
	select FW_LOADER
	select SND_HWDEP
	select SND_RAWMIDI
	select SND_AC97_CODEC
	help
	  Say Y to include support for Sound Blaster PCI 512, Live!,
	  Audigy and E-mu APS (partially supported) soundcards.

	  The confusing multitude of mixer controls is documented in
	  <file:Documentation/sound/alsa/SB-Live-mixer.txt> and
	  <file:Documentation/sound/alsa/Audigy-mixer.txt>.

	  To compile this driver as a module, choose M here: the module
	  will be called snd-emu10k1.

config SND_EMU10K1X
	tristate "Emu10k1X (Dell OEM Version)"
	select SND_AC97_CODEC
	select SND_RAWMIDI
	help
	  Say Y here to include support for the Dell OEM version of the
	  Sound Blaster Live!.

	  To compile this driver as a module, choose M here: the module
	  will be called snd-emu10k1x.

config SND_ENS1370
	tristate "(Creative) Ensoniq AudioPCI 1370"
	select SND_RAWMIDI
	select SND_PCM
	help
	  Say Y here to include support for Ensoniq AudioPCI ES1370 chips.

	  To compile this driver as a module, choose M here: the module
	  will be called snd-ens1370.

config SND_ENS1371
	tristate "(Creative) Ensoniq AudioPCI 1371/1373"
	select SND_RAWMIDI
	select SND_AC97_CODEC
	help
	  Say Y here to include support for Ensoniq AudioPCI ES1371 chips and
	  Sound Blaster PCI 64 or 128 soundcards.

	  To compile this driver as a module, choose M here: the module
	  will be called snd-ens1371.

config SND_ES1938
	tristate "ESS ES1938/1946/1969 (Solo-1)"
	select SND_OPL3_LIB
	select SND_MPU401_UART
	select SND_AC97_CODEC
	help
	  Say Y here to include support for soundcards based on ESS Solo-1
	  (ES1938, ES1946, ES1969) chips.

	  To compile this driver as a module, choose M here: the module
	  will be called snd-es1938.

config SND_ES1968
	tristate "ESS ES1968/1978 (Maestro-1/2/2E)"
	select SND_MPU401_UART
	select SND_AC97_CODEC
	help
	  Say Y here to include support for soundcards based on ESS Maestro
	  1/2/2E chips.

	  To compile this driver as a module, choose M here: the module
	  will be called snd-es1968.

config SND_FM801
	tristate "ForteMedia FM801"
	select SND_OPL3_LIB
	select SND_MPU401_UART
	select SND_AC97_CODEC
	help
	  Say Y here to include support for soundcards based on the ForteMedia
	  FM801 chip.

	  To compile this driver as a module, choose M here: the module
	  will be called snd-fm801.

config SND_FM801_TEA575X_BOOL
	bool "ForteMedia FM801 + TEA5757 tuner"
	depends on SND_FM801
	depends on VIDEO_V4L2=y || VIDEO_V4L2=SND_FM801
	help
	  Say Y here to include support for soundcards based on the ForteMedia
	  FM801 chip with a TEA5757 tuner connected to GPIO1-3 pins (Media
	  Forte SF256-PCS-02) into the snd-fm801 driver.

config SND_FM801_TEA575X
	tristate
	depends on SND_FM801_TEA575X_BOOL
	default SND_FM801

source "sound/pci/hda/Kconfig"

config SND_HDSP
	tristate "RME Hammerfall DSP Audio"
	select SND_HWDEP
	select SND_RAWMIDI
	select SND_PCM
	help
	  Say Y here to include support for RME Hammerfall DSP Audio
	  soundcards.

	  To compile this driver as a module, choose M here: the module
	  will be called snd-hdsp.

comment "Don't forget to add built-in firmwares for HDSP driver"
	depends on SND_HDSP=y

config SND_HDSPM
	tristate "RME Hammerfall DSP MADI"
	select SND_HWDEP
	select SND_RAWMIDI
	select SND_PCM
	help
	  Say Y here to include support for RME Hammerfall DSP MADI
	  soundcards.

	  To compile this driver as a module, choose M here: the module
	  will be called snd-hdspm.

config SND_HIFIER
	tristate "TempoTec HiFier Fantasia"
	select SND_OXYGEN_LIB
	help
	  Say Y here to include support for the MediaTek/TempoTec HiFier
	  Fantasia sound card.

	  To compile this driver as a module, choose M here: the module
	  will be called snd-hifier.

config SND_ICE1712
	tristate "ICEnsemble ICE1712 (Envy24)"
	select SND_MPU401_UART
	select SND_AC97_CODEC
	select BITREVERSE
	help
	  Say Y here to include support for soundcards based on the
	  ICE1712 (Envy24) chip.

	  Currently supported hardware is: M-Audio Delta 1010(LT),
	  DiO 2496, 66, 44, 410, Audiophile 24/96; Digigram VX442;
	  TerraTec EWX 24/96, EWS 88MT/D, DMX 6Fire, Phase 88;
	  Hoontech SoundTrack DSP 24/Value/Media7.1; Event EZ8;
	  Lionstracs Mediastation, Terrasoniq TS 88.

	  To compile this driver as a module, choose M here: the module
	  will be called snd-ice1712.

config SND_ICE1724
	tristate "ICE/VT1724/1720 (Envy24HT/PT)"
	select SND_RAWMIDI
	select SND_AC97_CODEC
	select SND_VMASTER
	help
	  Say Y here to include support for soundcards based on
	  ICE/VT1724/1720 (Envy24HT/PT) chips.

	  Currently supported hardware is: AMP AUDIO2000; M-Audio
	  Revolution 5.1, 7.1, Audiophile 192; TerraTec Aureon 5.1 Sky,
	  7.1 Space/Universe, Phase 22/28; Onkyo SE-90PCI, SE-200PCI;
	  AudioTrak Prodigy 192, 7.1 (HIFI/LT/XT), HD2; Hercules
	  Fortissimo IV; ESI Juli@; Pontis MS300; EGO-SYS WaveTerminal
	  192M; Albatron K8X800 Pro II; Chaintech ZNF3-150/250, 9CJS,
	  AV-710; Shuttle SN25P.

	  To compile this driver as a module, choose M here: the module
	  will be called snd-ice1724.

config SND_INTEL8X0
	tristate "Intel/SiS/nVidia/AMD/ALi AC97 Controller"
	select SND_AC97_CODEC
	help
	  Say Y here to include support for the integrated AC97 sound
	  device on motherboards with Intel/SiS/nVidia/AMD chipsets, or
	  ALi chipsets using the M5455 Audio Controller.  (There is a
	  separate driver for ALi M5451 Audio Controllers.)

	  To compile this driver as a module, choose M here: the module
	  will be called snd-intel8x0.

config SND_INTEL8X0M
	tristate "Intel/SiS/nVidia/AMD MC97 Modem"
	select SND_AC97_CODEC
	help
	  Say Y here to include support for the integrated MC97 modem on
	  motherboards with Intel/SiS/nVidia/AMD chipsets.

	  To compile this driver as a module, choose M here: the module
	  will be called snd-intel8x0m.

config SND_KORG1212
	tristate "Korg 1212 IO"
	select SND_PCM
	help
	  Say Y here to include support for Korg 1212IO soundcards.

	  To compile this driver as a module, choose M here: the module
	  will be called snd-korg1212.

config SND_LX6464ES
	tristate "Digigram LX6464ES"
	select SND_PCM
	help
	  Say Y here to include support for Digigram LX6464ES boards.

	  To compile this driver as a module, choose M here: the module
	  will be called snd-lx6464es.


config SND_MAESTRO3
	tristate "ESS Allegro/Maestro3"
	select SND_AC97_CODEC
	help
	  Say Y here to include support for soundcards based on ESS Maestro 3
	  (Allegro) chips.

	  To compile this driver as a module, choose M here: the module
	  will be called snd-maestro3.

config SND_MIXART
	tristate "Digigram miXart"
	select SND_HWDEP
	select SND_PCM
	help
	  If you want to use Digigram miXart soundcards, say Y here and
	  read <file:Documentation/sound/alsa/MIXART.txt>.

	  To compile this driver as a module, choose M here: the module
	  will be called snd-mixart.

config SND_NM256
	tristate "NeoMagic NM256AV/ZX"
	select SND_AC97_CODEC
	help
	  Say Y here to include support for NeoMagic NM256AV/ZX chips.

	  To compile this driver as a module, choose M here: the module
	  will be called snd-nm256.

config SND_PCXHR
	tristate "Digigram PCXHR"
	select SND_PCM
	select SND_HWDEP
	help
	  Say Y here to include support for Digigram PCXHR boards.

	  To compile this driver as a module, choose M here: the module
	  will be called snd-pcxhr.

config SND_RIPTIDE
	tristate "Conexant Riptide"
	select FW_LOADER
	select SND_OPL3_LIB
	select SND_MPU401_UART
	select SND_AC97_CODEC
	help
	  Say 'Y' or 'M' to include support for Conexant Riptide chip.

	  To compile this driver as a module, choose M here: the module
	  will be called snd-riptide

config SND_RME32
	tristate "RME Digi32, 32/8, 32 PRO"
	select SND_PCM
	help
	  Say Y to include support for RME Digi32, Digi32 PRO and
	  Digi32/8 (Sek'd Prodif32, Prodif96 and Prodif Gold) audio
	  devices.

	  To compile this driver as a module, choose M here: the module
	  will be called snd-rme32.

config SND_RME96
	tristate "RME Digi96, 96/8, 96/8 PRO"
	select SND_PCM
	help
	  Say Y here to include support for RME Digi96, Digi96/8 and
	  Digi96/8 PRO/PAD/PST soundcards.

	  To compile this driver as a module, choose M here: the module
	  will be called snd-rme96.

config SND_RME9652
	tristate "RME Digi9652 (Hammerfall)"
	select SND_PCM
	help
	  Say Y here to include support for RME Hammerfall (RME
	  Digi9652/Digi9636) soundcards.

	  To compile this driver as a module, choose M here: the module
	  will be called snd-rme9652.

config SND_SIS7019
	tristate "SiS 7019 Audio Accelerator"
	depends on X86 && !X86_64
	select SND_AC97_CODEC
	help
	  Say Y here to include support for the SiS 7019 Audio Accelerator.

	  To compile this driver as a module, choose M here: the module
	  will be called snd-sis7019.

config SND_SONICVIBES
	tristate "S3 SonicVibes"
	select SND_OPL3_LIB
	select SND_MPU401_UART
	select SND_AC97_CODEC
	help
	  Say Y here to include support for soundcards based on the S3
	  SonicVibes chip.

	  To compile this driver as a module, choose M here: the module
	  will be called snd-sonicvibes.

config SND_TRIDENT
	tristate "Trident 4D-Wave DX/NX; SiS 7018"
	select SND_MPU401_UART
	select SND_AC97_CODEC
	help
	  Say Y here to include support for soundcards based on Trident
	  4D-Wave DX/NX or SiS 7018 chips.

	  To compile this driver as a module, choose M here: the module
	  will be called snd-trident.

config SND_VIA82XX
	tristate "VIA 82C686A/B, 8233/8235 AC97 Controller"
	select SND_MPU401_UART
	select SND_AC97_CODEC
	help
	  Say Y here to include support for the integrated AC97 sound
	  device on motherboards with VIA chipsets.

	  To compile this driver as a module, choose M here: the module
	  will be called snd-via82xx.

config SND_VIA82XX_MODEM
	tristate "VIA 82C686A/B, 8233 based Modems"
	select SND_AC97_CODEC
	help
	  Say Y here to include support for the integrated MC97 modem on
	  motherboards with VIA chipsets.

	  To compile this driver as a module, choose M here: the module
	  will be called snd-via82xx-modem.

config SND_VIRTUOSO
	tristate "Asus Virtuoso 100/200 (Xonar)"
	select SND_OXYGEN_LIB
	help
	  Say Y here to include support for sound cards based on the
	  Asus AV100/AV200 chips, i.e., Xonar D1, DX, D2, D2X,
	  Essence ST (Deluxe), and Essence STX.
	  Support for the HDAV1.3 (Deluxe) is very experimental.

	  To compile this driver as a module, choose M here: the module
	  will be called snd-virtuoso.

config SND_VX222
	tristate "Digigram VX222"
	select SND_VX_LIB
	help
	  Say Y here to include support for Digigram VX222 soundcards.

	  To compile this driver as a module, choose M here: the module
	  will be called snd-vx222.

config SND_YMFPCI
	tristate "Yamaha YMF724/740/744/754"
	select SND_OPL3_LIB
	select SND_MPU401_UART
	select SND_AC97_CODEC
	help
	  Say Y here to include support for Yamaha PCI audio chips -
	  YMF724, YMF724F, YMF740, YMF740C, YMF744, YMF754.

	  To compile this driver as a module, choose M here: the module
	  will be called snd-ymfpci.

endif	# SND_PCI
lass="hl opt">(*commit_global_cb_manager)(struct gk20a *g, struct channel_gk20a *ch, bool patch); void (*commit_global_pagepool)(struct gk20a *g, struct channel_ctx_gk20a *ch_ctx, u64 addr, u32 size, bool patch); void (*init_gpc_mmu)(struct gk20a *g); int (*handle_sw_method)(struct gk20a *g, u32 addr, u32 class_num, u32 offset, u32 data); void (*set_alpha_circular_buffer_size)(struct gk20a *g, u32 data); void (*set_circular_buffer_size)(struct gk20a *g, u32 data); void (*enable_hww_exceptions)(struct gk20a *g); bool (*is_valid_class)(struct gk20a *g, u32 class_num); void (*get_sm_dsm_perf_regs)(struct gk20a *g, u32 *num_sm_dsm_perf_regs, u32 **sm_dsm_perf_regs, u32 *perf_register_stride); void (*get_sm_dsm_perf_ctrl_regs)(struct gk20a *g, u32 *num_sm_dsm_perf_regs, u32 **sm_dsm_perf_regs, u32 *perf_register_stride); void (*set_hww_esr_report_mask)(struct gk20a *g); int (*setup_alpha_beta_tables)(struct gk20a *g, struct gr_gk20a *gr); int (*falcon_load_ucode)(struct gk20a *g, u64 addr_base, struct gk20a_ctxsw_ucode_segments *segments, u32 reg_offset); int (*load_ctxsw_ucode)(struct gk20a *g); u32 (*get_gpc_tpc_mask)(struct gk20a *g, u32 gpc_index); void (*set_gpc_tpc_mask)(struct gk20a *g, u32 gpc_index); void (*free_channel_ctx)(struct channel_gk20a *c); int (*alloc_obj_ctx)(struct channel_gk20a *c, struct nvgpu_alloc_obj_ctx_args *args); int (*free_obj_ctx)(struct channel_gk20a *c, struct nvgpu_free_obj_ctx_args *args); int (*bind_ctxsw_zcull)(struct gk20a *g, struct gr_gk20a *gr, struct channel_gk20a *c, u64 zcull_va, u32 mode); int (*get_zcull_info)(struct gk20a *g, struct gr_gk20a *gr, struct gr_zcull_info *zcull_params); bool (*is_tpc_addr)(struct gk20a *g, u32 addr); u32 (*get_tpc_num)(struct gk20a *g, u32 addr); bool (*is_ltcs_ltss_addr)(struct gk20a *g, u32 addr); bool (*is_ltcn_ltss_addr)(struct gk20a *g, u32 addr); bool (*get_lts_in_ltc_shared_base)(void); void (*split_lts_broadcast_addr)(struct gk20a *g, u32 addr, u32 *priv_addr_table, u32 *priv_addr_table_index); void (*split_ltc_broadcast_addr)(struct gk20a *g, u32 addr, u32 *priv_addr_table, u32 *priv_addr_table_index); void (*detect_sm_arch)(struct gk20a *g); int (*add_zbc_color)(struct gk20a *g, struct gr_gk20a *gr, struct zbc_entry *color_val, u32 index); int (*add_zbc_depth)(struct gk20a *g, struct gr_gk20a *gr, struct zbc_entry *depth_val, u32 index); int (*zbc_set_table)(struct gk20a *g, struct gr_gk20a *gr, struct zbc_entry *zbc_val); int (*zbc_query_table)(struct gk20a *g, struct gr_gk20a *gr, struct zbc_query_params *query_params); void (*pmu_save_zbc)(struct gk20a *g, u32 entries); int (*add_zbc)(struct gk20a *g, struct gr_gk20a *gr, struct zbc_entry *zbc_val); u32 (*pagepool_default_size)(struct gk20a *g); int (*init_ctx_state)(struct gk20a *g); int (*alloc_gr_ctx)(struct gk20a *g, struct gr_ctx_desc **__gr_ctx, struct vm_gk20a *vm, u32 class, u32 padding); void (*free_gr_ctx)(struct gk20a *g, struct vm_gk20a *vm, struct gr_ctx_desc *gr_ctx); void (*update_ctxsw_preemption_mode)(struct gk20a *g, struct channel_ctx_gk20a *ch_ctx, struct mem_desc *mem); int (*update_smpc_ctxsw_mode)(struct gk20a *g, struct channel_gk20a *c, bool enable); int (*update_hwpm_ctxsw_mode)(struct gk20a *g, struct channel_gk20a *c, bool enable); int (*dump_gr_regs)(struct gk20a *g, struct gk20a_debug_output *o); int (*update_pc_sampling)(struct channel_gk20a *ch, bool enable); u32 (*get_max_fbps_count)(struct gk20a *g); u32 (*get_fbp_en_mask)(struct gk20a *g); u32 (*get_max_ltc_per_fbp)(struct gk20a *g); u32 (*get_max_lts_per_ltc)(struct gk20a *g); u32* (*get_rop_l2_en_mask)(struct gk20a *g); void (*init_sm_dsm_reg_info)(void); int (*wait_empty)(struct gk20a *g, unsigned long end_jiffies, u32 expect_delay); void (*init_cyclestats)(struct gk20a *g); void (*enable_cde_in_fecs)(struct gk20a *g, struct mem_desc *mem); int (*set_sm_debug_mode)(struct gk20a *g, struct channel_gk20a *ch, u64 sms, bool enable); void (*bpt_reg_info)(struct gk20a *g, struct warpstate *w_state); void (*get_access_map)(struct gk20a *g, u32 **whitelist, int *num_entries); int (*handle_fecs_error)(struct gk20a *g, struct channel_gk20a *ch, struct gr_gk20a_isr_data *isr_data); int (*pre_process_sm_exception)(struct gk20a *g, u32 gpc, u32 tpc, u32 global_esr, u32 warp_esr, bool sm_debugger_attached, struct channel_gk20a *fault_ch, bool *early_exit, bool *ignore_debugger); u32 (*mask_hww_warp_esr)(u32 hww_warp_esr); int (*handle_sm_exception)(struct gk20a *g, u32 gpc, u32 tpc, bool *post_event, struct channel_gk20a *fault_ch, u32 *hww_global_esr); int (*handle_tex_exception)(struct gk20a *g, u32 gpc, u32 tpc, bool *post_event); void (*create_gr_sysfs)(struct device *dev); u32 (*get_lrf_tex_ltc_dram_override)(struct gk20a *g); int (*record_sm_error_state)(struct gk20a *g, u32 gpc, u32 tpc); int (*update_sm_error_state)(struct gk20a *g, struct channel_gk20a *ch, u32 sm_id, struct nvgpu_dbg_gpu_sm_error_state_record * sm_error_state); int (*clear_sm_error_state)(struct gk20a *g, struct channel_gk20a *ch, u32 sm_id); int (*suspend_contexts)(struct gk20a *g, struct dbg_session_gk20a *dbg_s, int *ctx_resident_ch_fd); int (*set_preemption_mode)(struct channel_gk20a *ch, u32 graphics_preempt_mode, u32 compute_preempt_mode); int (*get_preemption_mode_flags)(struct gk20a *g, struct nvgpu_preemption_modes_rec *preemption_modes_rec); int (*set_ctxsw_preemption_mode)(struct gk20a *g, struct gr_ctx_desc *gr_ctx, struct vm_gk20a *vm, u32 class, u32 graphics_preempt_mode, u32 compute_preempt_mode); int (*fuse_override)(struct gk20a *g); int (*load_smid_config)(struct gk20a *g); void (*program_sm_id_numbering)(struct gk20a *g, u32 gpc, u32 tpc, u32 smid); void (*program_active_tpc_counts)(struct gk20a *g, u32 gpc); } gr; const char *name; struct { void (*init_fs_state)(struct gk20a *g); void (*reset)(struct gk20a *g); void (*init_uncompressed_kind_map)(struct gk20a *g); void (*init_kind_attr)(struct gk20a *g); void (*set_mmu_page_size)(struct gk20a *g); bool (*set_use_full_comp_tag_line)(struct gk20a *g); int (*compression_page_size)(struct gk20a *g); int (*compressible_page_size)(struct gk20a *g); void (*dump_vpr_wpr_info)(struct gk20a *g); } fb; struct { void (*slcg_bus_load_gating_prod)(struct gk20a *g, bool prod); void (*slcg_ce2_load_gating_prod)(struct gk20a *g, bool prod); void (*slcg_chiplet_load_gating_prod)(struct gk20a *g, bool prod); void (*slcg_ctxsw_firmware_load_gating_prod)(struct gk20a *g, bool prod); void (*slcg_fb_load_gating_prod)(struct gk20a *g, bool prod); void (*slcg_fifo_load_gating_prod)(struct gk20a *g, bool prod); void (*slcg_gr_load_gating_prod)(struct gk20a *g, bool prod); void (*slcg_ltc_load_gating_prod)(struct gk20a *g, bool prod); void (*slcg_perf_load_gating_prod)(struct gk20a *g, bool prod); void (*slcg_priring_load_gating_prod)(struct gk20a *g, bool prod); void (*slcg_pmu_load_gating_prod)(struct gk20a *g, bool prod); void (*slcg_therm_load_gating_prod)(struct gk20a *g, bool prod); void (*slcg_xbar_load_gating_prod)(struct gk20a *g, bool prod); void (*blcg_bus_load_gating_prod)(struct gk20a *g, bool prod); void (*blcg_ce_load_gating_prod)(struct gk20a *g, bool prod); void (*blcg_ctxsw_firmware_load_gating_prod)(struct gk20a *g, bool prod); void (*blcg_fb_load_gating_prod)(struct gk20a *g, bool prod); void (*blcg_fifo_load_gating_prod)(struct gk20a *g, bool prod); void (*blcg_gr_load_gating_prod)(struct gk20a *g, bool prod); void (*blcg_ltc_load_gating_prod)(struct gk20a *g, bool prod); void (*blcg_pwr_csb_load_gating_prod)(struct gk20a *g, bool prod); void (*blcg_pmu_load_gating_prod)(struct gk20a *g, bool prod); void (*blcg_xbar_load_gating_prod)(struct gk20a *g, bool prod); void (*pg_gr_load_gating_prod)(struct gk20a *g, bool prod); } clock_gating; struct { void (*bind_channel)(struct channel_gk20a *ch_gk20a); void (*unbind_channel)(struct channel_gk20a *ch_gk20a); void (*disable_channel)(struct channel_gk20a *ch); void (*enable_channel)(struct channel_gk20a *ch); int (*alloc_inst)(struct gk20a *g, struct channel_gk20a *ch); void (*free_inst)(struct gk20a *g, struct channel_gk20a *ch); int (*setup_ramfc)(struct channel_gk20a *c, u64 gpfifo_base, u32 gpfifo_entries, u32 flags); int (*resetup_ramfc)(struct channel_gk20a *c); int (*preempt_channel)(struct gk20a *g, u32 hw_chid); int (*preempt_tsg)(struct gk20a *g, u32 tsgid); int (*update_runlist)(struct gk20a *g, u32 runlist_id, u32 hw_chid, bool add, bool wait_for_finish); void (*trigger_mmu_fault)(struct gk20a *g, unsigned long engine_ids); void (*apply_pb_timeout)(struct gk20a *g); int (*wait_engine_idle)(struct gk20a *g); u32 (*get_num_fifos)(struct gk20a *g); u32 (*get_pbdma_signature)(struct gk20a *g); int (*channel_set_priority)(struct channel_gk20a *ch, u32 priority); int (*set_runlist_interleave)(struct gk20a *g, u32 id, bool is_tsg, u32 runlist_id, u32 new_level); int (*channel_set_timeslice)(struct channel_gk20a *ch, u32 timeslice); int (*tsg_set_timeslice)(struct tsg_gk20a *tsg, u32 timeslice); int (*force_reset_ch)(struct channel_gk20a *ch, u32 err_code, bool verbose); int (*engine_enum_from_type)(struct gk20a *g, u32 engine_type, u32 *inst_id); void (*device_info_data_parse)(struct gk20a *g, u32 table_entry, u32 *inst_id, u32 *pri_base, u32 *fault_id); int (*tsg_bind_channel)(struct tsg_gk20a *tsg, struct channel_gk20a *ch); int (*tsg_unbind_channel)(struct channel_gk20a *ch); u32 (*eng_runlist_base_size)(void); int (*init_engine_info)(struct fifo_gk20a *f); u32 (*runlist_entry_size)(void); void (*get_tsg_runlist_entry)(struct tsg_gk20a *tsg, u32 *runlist); void (*get_ch_runlist_entry)(struct channel_gk20a *ch, u32 *runlist); } fifo; struct pmu_v { /*used for change of enum zbc update cmd id from ver 0 to ver1*/ u32 cmd_id_zbc_table_update; u32 (*get_pmu_cmdline_args_size)(struct pmu_gk20a *pmu); void (*set_pmu_cmdline_args_cpu_freq)(struct pmu_gk20a *pmu, u32 freq); void (*set_pmu_cmdline_args_trace_size)(struct pmu_gk20a *pmu, u32 size); void (*set_pmu_cmdline_args_trace_dma_base)( struct pmu_gk20a *pmu); void (*set_pmu_cmdline_args_trace_dma_idx)( struct pmu_gk20a *pmu, u32 idx); void * (*get_pmu_cmdline_args_ptr)(struct pmu_gk20a *pmu); u32 (*get_pmu_allocation_struct_size)(struct pmu_gk20a *pmu); void (*set_pmu_allocation_ptr)(struct pmu_gk20a *pmu, void **pmu_alloc_ptr, void *assign_ptr); void (*pmu_allocation_set_dmem_size)(struct pmu_gk20a *pmu, void *pmu_alloc_ptr, u16 size); u16 (*pmu_allocation_get_dmem_size)(struct pmu_gk20a *pmu, void *pmu_alloc_ptr); u32 (*pmu_allocation_get_dmem_offset)(struct pmu_gk20a *pmu, void *pmu_alloc_ptr); u32 * (*pmu_allocation_get_dmem_offset_addr)( struct pmu_gk20a *pmu, void *pmu_alloc_ptr); void (*pmu_allocation_set_dmem_offset)(struct pmu_gk20a *pmu, void *pmu_alloc_ptr, u32 offset); void * (*pmu_allocation_get_fb_addr)( struct pmu_gk20a *pmu, void *pmu_alloc_ptr); void (*get_pmu_init_msg_pmu_queue_params)( struct pmu_queue *queue, u32 id, void *pmu_init_msg); void *(*get_pmu_msg_pmu_init_msg_ptr)( struct pmu_init_msg *init); u16 (*get_pmu_init_msg_pmu_sw_mg_off)( union pmu_init_msg_pmu *init_msg); u16 (*get_pmu_init_msg_pmu_sw_mg_size)( union pmu_init_msg_pmu *init_msg); u32 (*get_pmu_perfmon_cmd_start_size)(void); int (*get_perfmon_cmd_start_offsetofvar)( enum pmu_perfmon_cmd_start_fields field); void (*perfmon_start_set_cmd_type)(struct pmu_perfmon_cmd *pc, u8 value); void (*perfmon_start_set_group_id)(struct pmu_perfmon_cmd *pc, u8 value); void (*perfmon_start_set_state_id)(struct pmu_perfmon_cmd *pc, u8 value); void (*perfmon_start_set_flags)(struct pmu_perfmon_cmd *pc, u8 value); u8 (*perfmon_start_get_flags)(struct pmu_perfmon_cmd *pc); u32 (*get_pmu_perfmon_cmd_init_size)(void); int (*get_perfmon_cmd_init_offsetofvar)( enum pmu_perfmon_cmd_start_fields field); void (*perfmon_cmd_init_set_sample_buffer)( struct pmu_perfmon_cmd *pc, u16 value); void (*perfmon_cmd_init_set_dec_cnt)( struct pmu_perfmon_cmd *pc, u8 value); void (*perfmon_cmd_init_set_base_cnt_id)( struct pmu_perfmon_cmd *pc, u8 value); void (*perfmon_cmd_init_set_samp_period_us)( struct pmu_perfmon_cmd *pc, u32 value); void (*perfmon_cmd_init_set_num_cnt)(struct pmu_perfmon_cmd *pc, u8 value); void (*perfmon_cmd_init_set_mov_avg)(struct pmu_perfmon_cmd *pc, u8 value); void *(*get_pmu_seq_in_a_ptr)( struct pmu_sequence *seq); void *(*get_pmu_seq_out_a_ptr)( struct pmu_sequence *seq); void (*set_pmu_cmdline_args_secure_mode)(struct pmu_gk20a *pmu, u32 val); u32 (*get_perfmon_cntr_sz)(struct pmu_gk20a *pmu); void * (*get_perfmon_cntr_ptr)(struct pmu_gk20a *pmu); void (*set_perfmon_cntr_ut)(struct pmu_gk20a *pmu, u16 ut); void (*set_perfmon_cntr_lt)(struct pmu_gk20a *pmu, u16 lt); void (*set_perfmon_cntr_valid)(struct pmu_gk20a *pmu, u8 val); void (*set_perfmon_cntr_index)(struct pmu_gk20a *pmu, u8 val); void (*set_perfmon_cntr_group_id)(struct pmu_gk20a *pmu, u8 gid); u8 (*pg_cmd_eng_buf_load_size)(struct pmu_pg_cmd *pg); void (*pg_cmd_eng_buf_load_set_cmd_type)(struct pmu_pg_cmd *pg, u8 value); void (*pg_cmd_eng_buf_load_set_engine_id)(struct pmu_pg_cmd *pg, u8 value); void (*pg_cmd_eng_buf_load_set_buf_idx)(struct pmu_pg_cmd *pg, u8 value); void (*pg_cmd_eng_buf_load_set_pad)(struct pmu_pg_cmd *pg, u8 value); void (*pg_cmd_eng_buf_load_set_buf_size)(struct pmu_pg_cmd *pg, u16 value); void (*pg_cmd_eng_buf_load_set_dma_base)(struct pmu_pg_cmd *pg, u32 value); void (*pg_cmd_eng_buf_load_set_dma_offset)(struct pmu_pg_cmd *pg, u8 value); void (*pg_cmd_eng_buf_load_set_dma_idx)(struct pmu_pg_cmd *pg, u8 value); } pmu_ver; struct { int (*get_netlist_name)(struct gk20a *g, int index, char *name); bool (*is_fw_defined)(void); bool use_dma_for_fw_bootstrap; } gr_ctx; struct { int (*init)(struct gk20a *g); int (*max_entries)(struct gk20a *, struct nvgpu_ctxsw_trace_filter *); int (*flush)(struct gk20a *g); int (*poll)(struct gk20a *g); int (*enable)(struct gk20a *g); int (*disable)(struct gk20a *g); bool (*is_enabled)(struct gk20a *g); int (*reset)(struct gk20a *g); int (*bind_channel)(struct gk20a *, struct channel_gk20a *); int (*unbind_channel)(struct gk20a *, struct channel_gk20a *); int (*deinit)(struct gk20a *g); int (*alloc_user_buffer)(struct gk20a *g, void **buf, size_t *size); int (*free_user_buffer)(struct gk20a *g); int (*mmap_user_buffer)(struct gk20a *g, struct vm_area_struct *vma); int (*set_filter)(struct gk20a *g, struct nvgpu_ctxsw_trace_filter *filter); } fecs_trace; struct { bool (*support_sparse)(struct gk20a *g); bool (*is_debug_mode_enabled)(struct gk20a *g); void (*set_debug_mode)(struct gk20a *g, bool enable); u64 (*gmmu_map)(struct vm_gk20a *vm, u64 map_offset, struct sg_table *sgt, u64 buffer_offset, u64 size, int pgsz_idx, u8 kind_v, u32 ctag_offset, u32 flags, int rw_flag, bool clear_ctags, bool sparse, bool priv, struct vm_gk20a_mapping_batch *batch, enum gk20a_aperture aperture); void (*gmmu_unmap)(struct vm_gk20a *vm, u64 vaddr, u64 size, int pgsz_idx, bool va_allocated, int rw_flag, bool sparse, struct vm_gk20a_mapping_batch *batch); void (*vm_remove)(struct vm_gk20a *vm); int (*vm_alloc_share)(struct gk20a_as_share *as_share, u32 big_page_size, u32 flags); int (*vm_bind_channel)(struct gk20a_as_share *as_share, struct channel_gk20a *ch); int (*fb_flush)(struct gk20a *g); void (*l2_invalidate)(struct gk20a *g); void (*l2_flush)(struct gk20a *g, bool invalidate); void (*cbc_clean)(struct gk20a *g); void (*tlb_invalidate)(struct vm_gk20a *vm); void (*set_big_page_size)(struct gk20a *g, struct mem_desc *mem, int size); u32 (*get_big_page_sizes)(void); u32 (*get_physical_addr_bits)(struct gk20a *g); int (*init_mm_setup_hw)(struct gk20a *g); int (*init_bar2_vm)(struct gk20a *g); int (*init_bar2_mm_hw_setup)(struct gk20a *g); void (*remove_bar2_vm)(struct gk20a *g); const struct gk20a_mmu_level * (*get_mmu_levels)(struct gk20a *g, u32 big_page_size); void (*init_pdb)(struct gk20a *g, struct mem_desc *inst_block, struct vm_gk20a *vm); u64 (*get_iova_addr)(struct gk20a *g, struct scatterlist *sgl, u32 flags); int (*bar1_bind)(struct gk20a *g, struct mem_desc *bar1_inst); size_t (*get_vidmem_size)(struct gk20a *g); } mm; struct { int (*init_therm_setup_hw)(struct gk20a *g); int (*update_therm_gate_ctrl)(struct gk20a *g); } therm; struct { int (*prepare_ucode)(struct gk20a *g); int (*pmu_setup_hw_and_bootstrap)(struct gk20a *g); int (*pmu_nsbootstrap)(struct pmu_gk20a *pmu); int (*pmu_setup_elpg)(struct gk20a *g); int (*init_wpr_region)(struct gk20a *g); int (*load_lsfalcon_ucode)(struct gk20a *g, u32 falconidmask); void (*write_dmatrfbase)(struct gk20a *g, u32 addr); void (*pmu_elpg_statistics)(struct gk20a *g, u32 *ingating_time, u32 *ungating_time, u32 *gating_cnt); int (*pmu_pg_grinit_param)(struct gk20a *g, u8 grfeaturemask); int (*send_lrf_tex_ltc_dram_overide_en_dis_cmd) (struct gk20a *g, u32 mask); void (*dump_secure_fuses)(struct gk20a *g); int (*reset)(struct gk20a *g); int (*falcon_wait_for_halt)(struct gk20a *g, unsigned int timeout); int (*falcon_clear_halt_interrupt_status)(struct gk20a *g, unsigned int timeout); int (*init_falcon_setup_hw)(struct gk20a *g, void *desc, u32 bl_sz); bool (*is_lazy_bootstrap)(u32 falcon_id); bool (*is_priv_load)(u32 falcon_id); void (*get_wpr)(struct gk20a *g, struct wpr_carveout_info *inf); int (*alloc_blob_space)(struct gk20a *g, size_t size, struct mem_desc *mem); int (*pmu_populate_loader_cfg)(struct gk20a *g, void *lsfm, u32 *p_bl_gen_desc_size); int (*flcn_populate_bl_dmem_desc)(struct gk20a *g, void *lsfm, u32 *p_bl_gen_desc_size, u32 falconid); int (*mclk_init)(struct gk20a *g); u32 lspmuwprinitdone; u32 lsfloadedfalconid; bool fecsbootstrapdone; } pmu; struct { void (*disable_slowboot)(struct gk20a *g); int (*init_clk_support)(struct gk20a *g); int (*suspend_clk_support)(struct gk20a *g); } clk; bool privsecurity; bool securegpccs; struct { const struct regop_offset_range* ( *get_global_whitelist_ranges)(void); int (*get_global_whitelist_ranges_count)(void); const struct regop_offset_range* ( *get_context_whitelist_ranges)(void); int (*get_context_whitelist_ranges_count)(void); const u32* (*get_runcontrol_whitelist)(void); int (*get_runcontrol_whitelist_count)(void); const struct regop_offset_range* ( *get_runcontrol_whitelist_ranges)(void); int (*get_runcontrol_whitelist_ranges_count)(void); const u32* (*get_qctl_whitelist)(void); int (*get_qctl_whitelist_count)(void); const struct regop_offset_range* ( *get_qctl_whitelist_ranges)(void); int (*get_qctl_whitelist_ranges_count)(void); int (*apply_smpc_war)(struct dbg_session_gk20a *dbg_s); } regops; struct { void (*intr_enable)(struct gk20a *g); void (*intr_unit_config)(struct gk20a *g, bool enable, bool is_stalling, u32 unit); irqreturn_t (*isr_stall)(struct gk20a *g); irqreturn_t (*isr_nonstall)(struct gk20a *g); irqreturn_t (*isr_thread_stall)(struct gk20a *g); irqreturn_t (*isr_thread_nonstall)(struct gk20a *g); u32 intr_mask_restore[4]; } mc; struct { void (*show_dump)(struct gk20a *g, struct gk20a_debug_output *o); } debug; struct { int (*exec_reg_ops)(struct dbg_session_gk20a *dbg_s, struct nvgpu_dbg_gpu_reg_op *ops, u64 num_ops); int (*dbg_set_powergate)(struct dbg_session_gk20a *dbg_s, u32 mode); } dbg_session_ops; struct { void (*get_program_numbers)(struct gk20a *g, u32 block_height_log2, int *hprog, int *vprog); bool (*need_scatter_buffer)(struct gk20a *g); int (*populate_scatter_buffer)(struct gk20a *g, struct sg_table *sgt, size_t surface_size, void *scatter_buffer_ptr, size_t scatter_buffer_size); } cde; int (*get_litter_value)(struct gk20a *g, enum nvgpu_litter_value value); int (*chip_init_gpu_characteristics)(struct gk20a *g); int (*read_ptimer)(struct gk20a *g, u64 *value); struct { int (*init)(struct gk20a *g); void *(*get_perf_table_ptrs)(struct gk20a *g, struct bit_token *ptoken, u8 table_id); } bios; #if defined(CONFIG_GK20A_CYCLE_STATS) struct { int (*enable_snapshot)(struct channel_gk20a *ch, struct gk20a_cs_snapshot_client *client); void (*disable_snapshot)(struct gr_gk20a *gr); int (*check_data_available)(struct channel_gk20a *ch, u32 *pending, bool *hw_overflow); void (*set_handled_snapshots)(struct gk20a *g, u32 num); u32 (*allocate_perfmon_ids)(struct gk20a_cs_snapshot *data, u32 count); u32 (*release_perfmon_ids)(struct gk20a_cs_snapshot *data, u32 start, u32 count); int (*detach_snapshot)(struct channel_gk20a *ch, struct gk20a_cs_snapshot_client *client); } css; #endif }; struct nvgpu_bios_ucode { u8 *bootloader; u32 bootloader_phys_base; u32 bootloader_size; u8 *ucode; u32 phys_base; u32 size; u8 *dmem; u32 dmem_phys_base; u32 dmem_size; u32 code_entry_point; }; struct nvgpu_bios { u8 *data; struct nvgpu_bios_ucode devinit; struct nvgpu_bios_ucode preos; u8 *devinit_tables; u32 devinit_tables_size; u8 *bootscripts; u32 bootscripts_size; u32 devinit_tables_phys_base; u32 devinit_script_phys_base; struct bit_token *perf_token; struct bit_token *clock_token; u32 expansion_rom_offset; }; struct gk20a { struct device *dev; struct platform_device *host1x_dev; struct resource *reg_mem; void __iomem *regs; void __iomem *regs_saved; struct resource *bar1_mem; void __iomem *bar1; void __iomem *bar1_saved; bool power_on; bool suspended; struct rw_semaphore busy_lock; struct clk_gk20a clk; struct fifo_gk20a fifo; struct gr_gk20a gr; struct sim_gk20a sim; struct mm_gk20a mm; struct pmu_gk20a pmu; struct acr_desc acr; struct cooling_device_gk20a gk20a_cdev; #ifdef CONFIG_DEBUG_FS struct railgate_stats pstats; #endif /* Save pmu fw here so that it lives cross suspend/resume. pmu suspend destroys all pmu sw/hw states. Loading pmu fw in resume crashes when the resume is from sys_exit. */ const struct firmware *pmu_fw; u32 gr_idle_timeout_default; #if LINUX_VERSION_CODE < KERNEL_VERSION(4,4,0) u32 timeouts_enabled; #else bool timeouts_enabled; #endif struct mutex ch_wdt_lock; struct mutex poweroff_lock; /* Channel priorities */ u32 timeslice_low_priority_us; u32 timeslice_medium_priority_us; u32 timeslice_high_priority_us; #if LINUX_VERSION_CODE < KERNEL_VERSION(4,4,0) u32 runlist_interleave; #else bool runlist_interleave; #endif bool slcg_enabled; bool blcg_enabled; bool elcg_enabled; bool elpg_enabled; bool aelpg_enabled; bool forced_idle; bool forced_reset; bool allow_all; u32 emc3d_ratio; #ifdef CONFIG_DEBUG_FS spinlock_t debugfs_lock; struct dentry *debugfs_ltc_enabled; struct dentry *debugfs_timeouts_enabled; struct dentry *debugfs_gr_idle_timeout_default; struct dentry *debugfs_bypass_smmu; struct dentry *debugfs_disable_bigpage; struct dentry *debugfs_gr_default_attrib_cb_size; struct dentry *debugfs_timeslice_low_priority_us; struct dentry *debugfs_timeslice_medium_priority_us; struct dentry *debugfs_timeslice_high_priority_us; struct dentry *debugfs_runlist_interleave; #endif struct gk20a_ctxsw_ucode_info ctxsw_ucode_info; /* * A group of semaphore pools. One for each channel. */ struct gk20a_semaphore_sea *sema_sea; /* held while manipulating # of debug/profiler sessions present */ /* also prevents debug sessions from attaching until released */ struct mutex dbg_sessions_lock; int dbg_powergating_disabled_refcount; /*refcount for pg disable */ int dbg_timeout_disabled_refcount; /*refcount for timeout disable */ /* * When set subsequent VMAs will separate fixed and non-fixed * allocations. This avoids conflicts with fixed and non-fixed allocs * for some tests. The value in separate_fixed_allocs is used to * determine the split boundary. */ u64 separate_fixed_allocs; void (*remove_support)(struct device *); u64 pg_ingating_time_us; u64 pg_ungating_time_us; u32 pg_gating_cnt; spinlock_t mc_enable_lock; struct nvgpu_gpu_characteristics gpu_characteristics; struct { struct cdev cdev; struct device *node; } channel; struct gk20a_as as; struct { struct cdev cdev; struct device *node; } ctrl; struct { struct cdev cdev; struct device *node; } dbg; struct { struct cdev cdev; struct device *node; } prof; struct { struct cdev cdev; struct device *node; } tsg; struct { struct cdev cdev; struct device *node; } ctxsw; struct { struct cdev cdev; struct device *node; } sched; struct mutex client_lock; int client_refcount; /* open channels and ctrl nodes */ dev_t cdev_region; struct gpu_ops ops; int irq_stall; /* can be same as irq_nonstall in case of PCI */ int irq_nonstall; u32 max_ltc_count; u32 ltc_count; atomic_t hw_irq_stall_count; atomic_t hw_irq_nonstall_count; atomic_t sw_irq_stall_last_handled; wait_queue_head_t sw_irq_stall_last_handled_wq; atomic_t sw_irq_nonstall_last_handled; wait_queue_head_t sw_irq_nonstall_last_handled_wq; struct devfreq *devfreq; u32 devfreq_max_freq; u32 devfreq_min_freq; struct gk20a_scale_profile *scale_profile; struct gk20a_ctxsw_trace *ctxsw_trace; struct gk20a_fecs_trace *fecs_trace; struct gk20a_sched_ctrl sched_ctrl; struct device_dma_parameters dma_parms; struct gk20a_cde_app cde_app; bool mmu_debug_ctrl; u32 tpc_fs_mask_user; struct nvgpu_bios bios; struct debugfs_blob_wrapper bios_blob; struct gk20a_ce_app ce_app; /* PCI device identifier */ u16 pci_vendor_id, pci_device_id; u16 pci_subsystem_vendor_id, pci_subsystem_device_id; u16 pci_class; u8 pci_revision; }; static inline unsigned long gk20a_get_gr_idle_timeout(struct gk20a *g) { return g->timeouts_enabled ? g->gr_idle_timeout_default : MAX_SCHEDULE_TIMEOUT; } static inline struct gk20a *get_gk20a(struct device *dev) { return gk20a_get_platform(dev)->g; } enum BAR0_DEBUG_OPERATION { BARO_ZERO_NOP = 0, OP_END = 'DONE', BAR0_READ32 = '0R32', BAR0_WRITE32 = '0W32', }; struct share_buffer_head { enum BAR0_DEBUG_OPERATION operation; /* size of the operation item */ u32 size; u32 completed; u32 failed; u64 context; u64 completion_callback; }; struct gk20a_cyclestate_buffer_elem { struct share_buffer_head head; /* in */ u64 p_data; u64 p_done; u32 offset_bar0; u16 first_bit; u16 last_bit; /* out */ /* keep 64 bits to be consistent */ u64 data; }; /* debug accessories */ #ifdef CONFIG_DEBUG_FS /* debug info, default is compiled-in but effectively disabled (0 mask) */ #define GK20A_DEBUG /*e.g: echo 1 > /d/gk20a.0/dbg_mask */ #define GK20A_DEFAULT_DBG_MASK 0 #else /* manually enable and turn it on the mask */ /*#define NVGPU_DEBUG*/ #define GK20A_DEFAULT_DBG_MASK (dbg_info) #endif enum gk20a_dbg_categories { gpu_dbg_info = BIT(0), /* lightly verbose info */ gpu_dbg_fn = BIT(2), /* fn name tracing */ gpu_dbg_reg = BIT(3), /* register accesses, very verbose */ gpu_dbg_pte = BIT(4), /* gmmu ptes */ gpu_dbg_intr = BIT(5), /* interrupts */ gpu_dbg_pmu = BIT(6), /* gk20a pmu */ gpu_dbg_clk = BIT(7), /* gk20a clk */ gpu_dbg_map = BIT(8), /* mem mappings */ gpu_dbg_gpu_dbg = BIT(9), /* gpu debugger/profiler */ gpu_dbg_cde = BIT(10), /* cde info messages */ gpu_dbg_cde_ctx = BIT(11), /* cde context usage messages */ gpu_dbg_ctxsw = BIT(12), /* ctxsw tracing */ gpu_dbg_sched = BIT(13), /* sched control tracing */ gpu_dbg_map_v = BIT(14), /* verbose mem mappings */ gpu_dbg_sema = BIT(15), /* semaphore debugging */ gpu_dbg_sema_v = BIT(16), /* verbose semaphore debugging */ gpu_dbg_mem = BIT(31), /* memory accesses, very verbose */ }; #if defined(GK20A_DEBUG) extern u32 gk20a_dbg_mask; extern u32 gk20a_dbg_ftrace; #define gk20a_dbg(dbg_mask, format, arg...) \ do { \ if (unlikely((dbg_mask) & gk20a_dbg_mask)) { \ if (gk20a_dbg_ftrace) \ trace_printk(format "\n", ##arg); \ else \ pr_info("gk20a %s: " format "\n", \ __func__, ##arg); \ } \ } while (0) #else /* GK20A_DEBUG */ #define gk20a_dbg(dbg_mask, format, arg...) \ do { \ if (0) \ pr_info("gk20a %s: " format "\n", __func__, ##arg);\ } while (0) #endif #define gk20a_err(d, fmt, arg...) \ dev_err(d, "%s: " fmt "\n", __func__, ##arg) #define gk20a_warn(d, fmt, arg...) \ dev_warn(d, "%s: " fmt "\n", __func__, ##arg) #define gk20a_dbg_fn(fmt, arg...) \ gk20a_dbg(gpu_dbg_fn, fmt, ##arg) #define gk20a_dbg_info(fmt, arg...) \ gk20a_dbg(gpu_dbg_info, fmt, ##arg) void gk20a_init_clk_ops(struct gpu_ops *gops); /* register accessors */ int gk20a_lockout_registers(struct gk20a *g); int gk20a_restore_registers(struct gk20a *g); static inline void gk20a_writel(struct gk20a *g, u32 r, u32 v) { gk20a_dbg(gpu_dbg_reg, " r=0x%x v=0x%x", r, v); writel_relaxed(v, g->regs + r); wmb(); } static inline u32 gk20a_readl(struct gk20a *g, u32 r) { u32 v = readl(g->regs + r); gk20a_dbg(gpu_dbg_reg, " r=0x%x v=0x%x", r, v); return v; } static inline void gk20a_writel_check(struct gk20a *g, u32 r, u32 v) { gk20a_dbg(gpu_dbg_reg, " r=0x%x v=0x%x", r, v); wmb(); do { writel_relaxed(v, g->regs + r); } while (readl(g->regs + r) != v); } static inline void gk20a_bar1_writel(struct gk20a *g, u32 b, u32 v) { gk20a_dbg(gpu_dbg_reg, " b=0x%x v=0x%x", b, v); wmb(); writel_relaxed(v, g->bar1 + b); } static inline u32 gk20a_bar1_readl(struct gk20a *g, u32 b) { u32 v = readl(g->bar1 + b); gk20a_dbg(gpu_dbg_reg, " b=0x%x v=0x%x", b, v); return v; } /* convenience */ static inline struct device *dev_from_gk20a(struct gk20a *g) { return g->dev; } static inline struct gk20a *gk20a_from_dev(struct device *dev) { return ((struct gk20a_platform *)dev_get_drvdata(dev))->g; } static inline struct gk20a *gk20a_from_as(struct gk20a_as *as) { return container_of(as, struct gk20a, as); } static inline struct gk20a *gk20a_from_pmu(struct pmu_gk20a *pmu) { return container_of(pmu, struct gk20a, pmu); } static inline u32 u64_hi32(u64 n) { return (u32)((n >> 32) & ~(u32)0); } static inline u32 u64_lo32(u64 n) { return (u32)(n & ~(u32)0); } static inline u32 set_field(u32 val, u32 mask, u32 field) { return ((val & ~mask) | field); } /* invalidate channel lookup tlb */ static inline void gk20a_gr_flush_channel_tlb(struct gr_gk20a *gr) { spin_lock(&gr->ch_tlb_lock); memset(gr->chid_tlb, 0, sizeof(struct gr_channel_map_tlb_entry) * GR_CHANNEL_MAP_TLB_SIZE); spin_unlock(&gr->ch_tlb_lock); } /* classes that the device supports */ /* TBD: get these from an open-sourced SDK? */ enum { KEPLER_C = 0xA297, FERMI_TWOD_A = 0x902D, KEPLER_COMPUTE_A = 0xA0C0, KEPLER_INLINE_TO_MEMORY_A = 0xA040, KEPLER_DMA_COPY_A = 0xA0B5, KEPLER_CHANNEL_GPFIFO_C = 0xA26F, }; static inline bool gk20a_gpu_is_virtual(struct device *dev) { struct gk20a_platform *platform = dev_get_drvdata(dev); return platform->virtual_dev; } static inline int support_gk20a_pmu(struct device *dev) { if (IS_ENABLED(CONFIG_GK20A_PMU)) { /* gPMU is not supported for vgpu */ return !gk20a_gpu_is_virtual(dev); } return 0; } void gk20a_create_sysfs(struct device *dev); void gk20a_remove_sysfs(struct device *dev); #define GK20A_BAR0_IORESOURCE_MEM 0 #define GK20A_BAR1_IORESOURCE_MEM 1 #define GK20A_SIM_IORESOURCE_MEM 2 void gk20a_busy_noresume(struct device *dev); int __must_check gk20a_busy(struct device *dev); void gk20a_idle(struct device *dev); void gk20a_disable(struct gk20a *g, u32 units); void gk20a_enable(struct gk20a *g, u32 units); void gk20a_reset(struct gk20a *g, u32 units); int gk20a_do_idle(void); int gk20a_do_unidle(void); int __gk20a_do_idle(struct device *dev, bool force_reset); int __gk20a_do_unidle(struct device *dev); const struct firmware * gk20a_request_firmware(struct gk20a *g, const char *fw_name); #define NVGPU_GPU_ARCHITECTURE_SHIFT 4 /* constructs unique and compact GPUID from nvgpu_gpu_characteristics * arch/impl fields */ #define GK20A_GPUID(arch, impl) ((u32) ((arch) | (impl))) #define GK20A_GPUID_GK20A \ GK20A_GPUID(NVGPU_GPU_ARCH_GK100, NVGPU_GPU_IMPL_GK20A) #define GK20A_GPUID_GM20B \ GK20A_GPUID(NVGPU_GPU_ARCH_GM200, NVGPU_GPU_IMPL_GM20B) #define GK20A_GPUID_GM204 \ GK20A_GPUID(NVGPU_GPU_ARCH_GM200, NVGPU_GPU_IMPL_GM204) #define GK20A_GPUID_GM206 \ GK20A_GPUID(NVGPU_GPU_ARCH_GM200, NVGPU_GPU_IMPL_GM206) int gk20a_init_gpu_characteristics(struct gk20a *g); void gk20a_pbus_isr(struct gk20a *g); int gk20a_user_init(struct device *dev, const char *interface_name, struct class *class); void gk20a_user_deinit(struct device *dev, struct class *class); static inline u32 ptimer_scalingfactor10x(u32 ptimer_src_freq) { return (u32)(((u64)(PTIMER_REF_FREQ_HZ * 10)) / ptimer_src_freq); } static inline u32 scale_ptimer(u32 timeout , u32 scale10x) { if (((timeout*10) % scale10x) >= (scale10x/2)) return ((timeout * 10) / scale10x) + 1; else return (timeout * 10) / scale10x; } int gk20a_read_ptimer(struct gk20a *g, u64 *value); extern struct class nvgpu_class; #define INTERFACE_NAME "nvhost%s-gpu" int gk20a_pm_init(struct device *dev); int gk20a_pm_finalize_poweron(struct device *dev); void gk20a_remove_support(struct device *dev); static inline struct tsg_gk20a *tsg_gk20a_from_ch(struct channel_gk20a *ch) { struct tsg_gk20a *tsg = NULL; if (gk20a_is_channel_marked_as_tsg(ch)) { struct gk20a *g = ch->g; struct fifo_gk20a *f = &g->fifo; tsg = &f->tsg[ch->tsgid]; } return tsg; } static inline void gk20a_channel_trace_sched_param( void (*trace)(int chid, int tsgid, pid_t pid, u32 timeslice, u32 timeout, const char *interleave, const char *graphics_preempt_mode, const char *compute_preempt_mode), struct channel_gk20a *ch) { (trace)(ch->hw_chid, ch->tsgid, ch->pid, gk20a_is_channel_marked_as_tsg(ch) ? tsg_gk20a_from_ch(ch)->timeslice_us : ch->timeslice_us, ch->timeout_ms_max, gk20a_fifo_interleave_level_name(ch->interleave_level), gr_gk20a_graphics_preempt_mode_name(ch->ch_ctx.gr_ctx ? ch->ch_ctx.gr_ctx->graphics_preempt_mode : 0), gr_gk20a_compute_preempt_mode_name(ch->ch_ctx.gr_ctx ? ch->ch_ctx.gr_ctx->compute_preempt_mode : 0)); } #ifdef CONFIG_DEBUG_FS int gk20a_railgating_debugfs_init(struct device *dev); #endif int gk20a_secure_page_alloc(struct device *dev); #endif /* GK20A_H */