/* * Copyright (C) Freescale Semicondutor, Inc. 2006. All rights reserved. * * Author: Shlomi Gridish * * Description: * Internal header file for UCC Gigabit Ethernet unit routines. * * Changelog: * Jun 28, 2006 Li Yang * - Rearrange code and style fixes * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License as published by the * Free Software Foundation; either version 2 of the License, or (at your * option) any later version. */ #ifndef __UCC_GETH_H__ #define __UCC_GETH_H__ #include #include #include #include #include #include #include #include "ucc_geth_mii.h" #define DRV_DESC "QE UCC Gigabit Ethernet Controller" #define DRV_NAME "ucc_geth" #define DRV_VERSION "1.1" #define NUM_TX_QUEUES 8 #define NUM_RX_QUEUES 8 #define NUM_BDS_IN_PREFETCHED_BDS 4 #define TX_IP_OFFSET_ENTRY_MAX 8 #define NUM_OF_PADDRS 4 #define ENET_INIT_PARAM_MAX_ENTRIES_RX 9 #define ENET_INIT_PARAM_MAX_ENTRIES_TX 8 struct ucc_geth { struct ucc_fast uccf; u8 res0[0x100 - sizeof(struct ucc_fast)]; u32 maccfg1; /* mac configuration reg. 1 */ u32 maccfg2; /* mac configuration reg. 2 */ u32 ipgifg; /* interframe gap reg. */ u32 hafdup; /* half-duplex reg. */ u8 res1[0x10]; u8 miimng[0x18]; /* MII management structure moved to _mii.h */ u32 ifctl; /* interface control reg */ u32 ifstat; /* interface statux reg */ u32 macstnaddr1; /* mac station address part 1 reg */ u32 macstnaddr2; /* mac station address part 2 reg */ u8 res2[0x8]; u32 uempr; /* UCC Ethernet Mac parameter reg */ u32 utbipar; /* UCC tbi address reg */ u16 uescr; /* UCC Ethernet statistics control reg */ u8 res3[0x180 - 0x15A]; u32 tx64; /* Total number of frames (including bad frames) transmitted that were exactly of the minimal length (64 for un tagged, 68 for tagged, or with length exactly equal to the parameter MINLength */ u32 tx127; /* Total number of frames (including bad frames) transmitted that were between MINLength (Including FCS length==4) and 127 octets */ u32 tx255; /* Total number of frames (including bad frames) transmitted that were between 128 (Including FCS length==4) and 255 octets */ u32 rx64; /* Total number of frames received including bad frames that were exactly of the mninimal length (64 bytes) */ u32 rx127; /* Total number of frames (including bad frames) received that were between MINLength (Including FCS length==4) and 127 octets */ u32 rx255; /* Total number of frames (including bad frames) received that were between 128 (Including FCS length==4) and 255 octets */ u32 txok; /* Total number of octets residing in frames that where involved in succesfull transmission */ u16 txcf; /* Total number of PAUSE control frames transmitted by this MAC */ u8 res4[0x2]; u32 tmca; /* Total number of frames that were transmitted succesfully with the group address bit set that are not broadcast frames */ u32 tbca; /* Total number of frames transmitted succesfully that had destination address field equal to the broadcast address */ u32 rxfok; /* Total number of frames received OK */ u32 rxbok; /* Total number of octets received OK */ u32 rbyt; /* Total number of octets received including octets in bad frames. Must be implemented in HW because it includes octets in frames that never even reach the UCC */ u32 rmca; /* Total number of frames that were received succesfully with the group address bit set that are not broadcast frames */ u32 rbca; /* Total number of frames received succesfully that had destination address equal to the broadcast address */ u32 scar; /* Statistics carry register */ u32 scam; /* Statistics caryy mask register */ u8 res5[0x200 - 0x1c4]; } __attribute__ ((packed)); /* UCC GETH TEMODR Register */ #define TEMODER_TX_RMON_STATISTICS_ENABLE 0x0100 /* enable Tx statistics */ #define TEMODER_SCHEDULER_ENABLE 0x2000 /* enable scheduler */ #define TEMODER_IP_CHECKSUM_GENERATE 0x0400 /* generate IPv4 checksums */ #define TEMODER_PERFORMANCE_OPTIMIZATION_MODE1 0x0200 /* enable performance optimization enhancement (mode1) */ #define TEMODER_RMON_STATISTICS 0x0100 /* enable tx statistics */ #define TEMODER_NUM_OF_QUEUES_SHIFT (15-15) /* Number of queues << shift */ /* UCC GETH TEMODR Register */ #define REMODER_RX_RMON_STATISTICS_ENABLE 0x00001000 /* enable Rx statistics */ #define REMODER_RX_EXTENDED_FEATURES 0x80000000 /* enable extended features */ #define REMODER_VLAN_OPERATION_TAGGED_SHIFT (31-9 ) /* vlan operation tagged << shift */ #define REMODER_VLAN_OPERATION_NON_TAGGED_SHIFT (31-10) /* vlan operation non tagged << shift */ #define REMODER_RX_QOS_MODE_SHIFT (31-15) /* rx QoS mode << shift */ #define REMODER_RMON_STATISTICS 0x00001000 /* enable rx statistics */ #define REMODER_RX_EXTENDED_FILTERING 0x00000800 /* extended filtering vs. mpc82xx-like filtering */ #define REMODER_NUM_OF_QUEUES_SHIFT (31-23) /* Number of queues << shift */ #define REMODER_DYNAMIC_MAX_FRAME_LENGTH 0x00000008 /* enable dynamic max frame length */ #define REMODER_DYNAMIC_MIN_FRAME_LENGTH 0x00000004 /* enable dynamic min frame length */ #define REMODER_IP_CHECKSUM_CHECK 0x00000002 /* check IPv4 checksums */ #define REMODER_IP_ADDRESS_ALIGNMENT 0x00000001 /* align ip address to 4-byte boundary */ /* UCC GETH Event Register */ #define UCCE_MPD 0x80000000 /* Magic packet detection */ #define UCCE_SCAR 0x40000000 #define UCCE_GRA 0x20000000 /* Tx graceful stop complete */ #define UCCE_CBPR 0x10000000 #define UCCE_BSY 0x08000000 #define UCCE_RXC 0x04000000 #define UCCE_TXC 0x02000000 #define UCCE_TXE 0x01000000 #define UCCE_TXB7 0x00800000 #define UCCE_TXB6 0x00400000 #define UCCE_TXB5 0x00200000 #define UCCE_TXB4 0x00100000 #define UCCE_TXB3 0x00080000 #define UCCE_TXB2 0x00040000 #define UCCE_TXB1 0x00020000 #define UCCE_TXB0 0x00010000 #define UCCE_RXB7 0x00008000 #define UCCE_RXB6 0x00004000 #define UCCE_RXB5 0x00002000 #define UCCE_RXB4 0x00001000 #define UCCE_RXB3 0x00000800 #define UCCE_RXB2 0x00000400 #define UCCE_RXB1 0x00000200 #define UCCE_RXB0 0x00000100 #define UCCE_RXF7 0x00000080 #define UCCE_RXF6 0x00000040 #define UCCE_RXF5 0x00000020 #define UCCE_RXF4 0x00000010 #define UCCE_RXF3 0x00000008 #define UCCE_RXF2 0x00000004 #define UCCE_RXF1 0x00000002 #define UCCE_RXF0 0x00000001 #define UCCE_RXBF_SINGLE_MASK (UCCE_RXF0) #define UCCE_TXBF_SINGLE_MASK (UCCE_TXB0) #define UCCE_TXB (UCCE_TXB7 | UCCE_TXB6 | UCCE_TXB5 | UCCE_TXB4 |\ UCCE_TXB3 | UCCE_TXB2 | UCCE_TXB1 | UCCE_TXB0) #define UCCE_RXB (UCCE_RXB7 | UCCE_RXB6 | UCCE_RXB5 | UCCE_RXB4 |\ UCCE_RXB3 | UCCE_RXB2 | UCCE_RXB1 | UCCE_RXB0) #define UCCE_RXF (UCCE_RXF7 | UCCE_RXF6 | UCCE_RXF5 | UCCE_RXF4 |\ UCCE_RXF3 | UCCE_RXF2 | UCCE_RXF1 | UCCE_RXF0) #define UCCE_OTHER (UCCE_SCAR | UCCE_GRA | UCCE_CBPR | UCCE_BSY |\ UCCE_RXC | UCCE_TXC | UCCE_TXE) #define UCCE_RX_EVENTS (UCCE_RXF | UCCE_BSY) #define UCCE_TX_EVENTS (UCCE_TXB | UCCE_TXE) /* UCC GETH UPSMR (Protocol Specific Mode Register) */ #define UPSMR_ECM 0x04000000 /* Enable CAM Miss or Enable Filtering Miss */ #define UPSMR_HSE 0x02000000 /* Hardware Statistics Enable */ #define UPSMR_PRO 0x00400000 /* Promiscuous*/ #define UPSMR_CAP 0x00200000 /* CAM polarity */ #define UPSMR_RSH 0x00100000 /* Receive Short Frames */ #define UPSMR_RPM 0x00080000 /* Reduced Pin Mode interfaces */ #define UPSMR_R10M 0x00040000 /* RGMII/RMII 10 Mode */ #define UPSMR_RLPB 0x00020000 /* RMII Loopback Mode */ #define UPSMR_TBIM 0x00010000 /* Ten-bit Interface Mode */ #define UPSMR_RMM 0x00001000 /* RMII/RGMII Mode */ #define UPSMR_CAM 0x00000400 /* CAM Address Matching */ #define UPSMR_BRO 0x00000200 /* Broadcast Address */ #define UPSMR_RES1 0x00002000 /* Reserved feild - must be 1 */ /* UCC GETH MACCFG1 (MAC Configuration 1 Register) */ #define MACCFG1_FLOW_RX 0x00000020 /* Flow Control Rx */ #define MACCFG1_FLOW_TX 0x00000010 /* Flow Control Tx */ #define MACCFG1_ENABLE_SYNCHED_RX 0x00000008 /* Rx Enable synchronized to Rx stream */ #define MACCFG1_ENABLE_RX 0x00000004 /* Enable Rx */ #define MACCFG1_ENABLE_SYNCHED_TX 0x00000002 /* Tx Enable synchronized to Tx stream */ #define MACCFG1_ENABLE_TX 0x00000001 /* Enable Tx */ /* UCC GETH MACCFG2 (MAC Configuration 2 Register) */ #define MACCFG2_PREL_SHIFT (31 - 19) /* Preamble Length << shift */ #define MACCFG2_PREL_MASK 0x0000f000 /* Preamble Length mask */ #define MACCFG2_SRP 0x00000080 /* Soft Receive Preamble */ #define MACCFG2_STP 0x00000040 /* Soft Transmit Preamble */ #define MACCFG2_RESERVED_1 0x00000020 /* Reserved - must be set to 1 */ #define MACCFG2_LC 0x00000010 /* Length Check */ #define MACCFG2_MPE 0x00000008 /* Magic packet detect */ #define MACCFG2_FDX 0x00000001 /* Full Duplex */ #define MACCFG2_FDX_MASK 0x00000001 /* Full Duplex mask */ #define MACCFG2_PAD_CRC 0x00000004 #define MACCFG2_CRC_EN 0x00000002 #define MACCFG2_PAD_AND_CRC_MODE_NONE 0x00000000 /* Neither Padding short frames nor CRC */ #define MACCFG2_PAD_AND_CRC_MODE_CRC_ONLY 0x00000002 /* Append CRC only */ #define MACCFG2_PAD_AND_CRC_MODE_PAD_AND_CRC 0x00000004 #define MACCFG2_INTERFACE_MODE_NIBBLE 0x00000100 /* nibble mode (MII/RMII/RGMII 10/100bps) */ #define MACCFG2_INTERFACE_MODE_BYTE 0x00000200 /* byte mode (GMII/TBI/RTB/RGMII 1000bps ) */ #define MACCFG2_INTERFACE_MODE_MASK 0x00000300 /* mask covering all relevant bits */ /* UCC GETH IPGIFG (Inter-frame Gap / Inter-Frame Gap Register) */ #define IPGIFG_NON_BACK_TO_BACK_IFG_PART1_SHIFT (31 - 7) /* Non back-to-back inter frame gap part 1. << shift */ #define IPGIFG_NON_BACK_TO_BACK_IFG_PART2_SHIFT (31 - 15) /* Non back-to-back inter frame gap part 2. << shift */ #define IPGIFG_MINIMUM_IFG_ENFORCEMENT_SHIFT (31 - 23) /* Mimimum IFG Enforcement << shift */ #define IPGIFG_BACK_TO_BACK_IFG_SHIFT (31 - 31) /* back-to-back inter frame gap << shift */ #define IPGIFG_NON_BACK_TO_BACK_IFG_PART1_MAX 127 /* Non back-to-back inter frame gap part 1. max val */ #define IPGIFG_NON_BACK_TO_BACK_IFG_PART2_MAX 127 /* Non back-to-back inter frame gap part 2. max val */ #define IPGIFG_MINIMUM_IFG_ENFORCEMENT_MAX 255 /* Mimimum IFG Enforcement max val */ #define IPGIFG_BACK_TO_BACK_IFG_MAX 127 /* back-to-back inter frame gap max val */ #define IPGIFG_NBTB_CS_IPG_MASK 0x7F000000 #define IPGIFG_NBTB_IPG_MASK 0x007F0000 #define IPGIFG_MIN_IFG_MASK 0x0000FF00 #define IPGIFG_BTB_IPG_MASK 0x0000007F /* UCC GETH HAFDUP (Half Duplex Register) */ #define HALFDUP_ALT_BEB_TRUNCATION_SHIFT (31 - 11) /* Alternate Binary Exponential Backoff Truncation << shift */ #define HALFDUP_ALT_BEB_TRUNCATION_MAX 0xf /* Alternate Binary Exponential Backoff Truncation max val */ #define HALFDUP_ALT_BEB 0x00080000 /* Alternate Binary Exponential Backoff */ #define HALFDUP_BACK_PRESSURE_NO_BACKOFF 0x00040000 /* Back pressure no backoff */ #define HALFDUP_NO_BACKOFF 0x00020000 /* No Backoff */ #define HALFDUP_EXCESSIVE_DEFER 0x00010000 /* Excessive Defer */ #define HALFDUP_MAX_RETRANSMISSION_SHIFT (31 - 19) /* Maximum Retransmission << shift */ #define HALFDUP_MAX_RETRANSMISSION_MAX 0xf /* Maximum Retransmission max val */ #define HALFDUP_COLLISION_WINDOW_SHIFT (31 - 31) /* Collision Window << shift */ #define HALFDUP_COLLISION_WINDOW_MAX 0x3f /* Collision Window max val */ #define HALFDUP_ALT_BEB_TR_MASK 0x00F00000 #define HALFDUP_RETRANS_MASK 0x0000F000 #define HALFDUP_COL_WINDOW_MASK 0x0000003F /* UCC GETH UCCS (Ethernet Status Register) */ #define UCCS_BPR 0x02 /* Back pressure (in half duplex mode) */ #define UCCS_PAU 0x02 /* Pause state (in full duplex mode) */ #define UCCS_MPD 0x01 /* Magic Packet Detected */ /* UCC GETH IFSTAT (Interface Status Register) */ #define IFSTAT_EXCESS_DEFER 0x00000200 /* Excessive transmission defer */ /* UCC GETH MACSTNADDR1 (Station Address Part 1 Register) */ #define MACSTNADDR1_OCTET_6_SHIFT (31 - 7) /* Station address 6th octet << shift */ #define MACSTNADDR1_OCTET_5_SHIFT (31 - 15) /* Station address 5th octet << shift */ #define MACSTNADDR1_OCTET_4_SHIFT (31 - 23) /* Station address 4th octet << shift */ #define MACSTNADDR1_OCTET_3_SHIFT (31 - 31) /* Station address 3rd octet << shift */ /* UCC GETH MACSTNADDR2 (Station Address Part 2 Register) */ #define MACSTNADDR2_OCTET_2_SHIFT (31 - 7) /* Station address 2nd octet << shift */ #define MACSTNADDR2_OCTET_1_SHIFT (31 - 15) /* Station address 1st octet << shift */ /* UCC GETH UEMPR (Ethernet Mac Parameter Register) */ #define UEMPR_PAUSE_TIME_VALUE_SHIFT (31 - 15) /* Pause time value << shift */ #define UEMPR_EXTENDED_PAUSE_TIME_VALUE_SHIFT (31 - 31) /* Extended pause time value << shift */ /* UCC GETH UTBIPAR (Ten Bit Interface Physical Address Register) */ #define UTBIPAR_PHY_ADDRESS_SHIFT (31 - 31) /* Phy address << shift */ #define UTBIPAR_PHY_ADDRESS_MASK 0x0000001f /* Phy address mask */ /* UCC GETH UESCR (Ethernet Statistics Control Register) */ #define UESCR_AUTOZ 0x8000 /* Automatically zero addressed statistical counter values */ #define UESCR_CLRCNT 0x4000 /* Clear all statistics counters */ #define UESCR_MAXCOV_SHIFT (15 - 7) /* Max Coalescing Value << shift */ #define UESCR_SCOV_SHIFT (15 - 15) /* Status Coalescing Value << shift */ /* UCC GETH UDSR (Data Synchronization Register) */ #define UDSR_MAGIC 0x067E struct ucc_geth_thread_data_tx { u8 res0[104]; } __attribute__ ((packed)); struct ucc_geth_thread_data_rx { u8 res0[40]; } __attribute__ ((packed)); /* Send Queue Queue-Descriptor */ struct ucc_geth_send_queue_qd { u32 bd_ring_base; /* pointer to BD ring base address */ u8 res0[0x8]; u32 last_bd_completed_address;/* initialize to last entry in BD ring */ u8 res1[0x30]; } __attribute__ ((packed)); struct ucc_geth_send_queue_mem_region { struct ucc_geth_send_queue_qd sqqd[NUM_TX_QUEUES]; } __attribute__ ((packed)); struct ucc_geth_thread_tx_pram { u8 res0[64]; } __attribute__ ((packed)); struct ucc_geth_thread_rx_pram { u8 res0[128]; } __attribute__ ((packed)); #define THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING 64 #define THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_8 64 #define THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_16 96 struct ucc_geth_scheduler { u16 cpucount0; /* CPU packet counter */ u16 cpucount1; /* CPU packet counter */ u16 cecount0; /* QE packet counter */ u16 cecount1; /* QE packet counter */ u16 cpucount2; /* CPU packet counter */ u16 cpucount3; /* CPU packet counter */ u16 cecount2; /* QE packet counter */ u16 cecount3; /* QE packet counter */ u16 cpucount4; /* CPU packet counter */ u16 cpucount5; /* CPU packet counter */ u16 cecount4; /* QE packet counter */ u16 cecount5; /* QE packet counter */ u16 cpucount6; /* CPU packet counter */ u16 cpucount7; /* CPU packet counter */ u16 cecount6; /* QE packet counter */ u16 cecount7; /* QE packet counter */ u32 weightstatus[NUM_TX_QUEUES]; /* accumulated weight factor */ u32 rtsrshadow; /* temporary variable handled by QE */ u32 time; /* temporary variable handled by QE */ u32 ttl; /* temporary variable handled by QE */ u32 mblinterval; /* max burst length interval */ u16 nortsrbytetime; /* normalized value of byte time in tsr units */ u8 fracsiz; /* radix 2 log value of denom. of NorTSRByteTime */ u8 res0[1]; u8 strictpriorityq; /* Strict Priority Mask register */ u8 txasap; /* Transmit ASAP register */ u8 extrabw; /* Extra BandWidth register */ u8 oldwfqmas/* * net/tipc/net.c: TIPC network routing code * * Copyright (c) 1995-2006, Ericsson AB * Copyright (c) 2005, Wind River Systems * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 3. Neither the names of the copyright holders nor the names of its * contributors may be used to endorse or promote products derived from * this software without specific prior written permission. * * Alternatively, this software may be distributed under the terms of the * GNU General Public License ("GPL") version 2 as published by the Free * Software Foundation. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ #include "core.h" #include "bearer.h" #include "net.h" #include "zone.h" #include "addr.h" #include "name_table.h" #include "name_distr.h" #include "subscr.h" #include "link.h" #include "msg.h" #include "port.h" #include "bcast.h" #include "discover.h" #include "config.h" /* * The TIPC locking policy is designed to ensure a very fine locking * granularity, permitting complete parallel access to individual * port and node/link instances. The code consists of three major * locking domains, each protected with their own disjunct set of locks. * * 1: The routing hierarchy. * Comprises the structures 'zone', 'cluster', 'node', 'link' * and 'bearer'. The whole hierarchy is protected by a big * read/write lock, tipc_net_lock, to enssure that nothing is added * or removed while code is accessing any of these structures. * This layer must not be called from the two others while they * hold any of their own locks. * Neither must it itself do any upcalls to the other two before * it has released tipc_net_lock and other protective locks. * * Within the tipc_net_lock domain there are two sub-domains;'node' and * 'bearer', where local write operations are permitted, * provided that those are protected by individual spin_locks * per instance. Code holding tipc_net_lock(read) and a node spin_lock * is permitted to poke around in both the node itself and its * subordinate links. I.e, it can update link counters and queues, * change link state, send protocol messages, and alter the * "active_links" array in the node; but it can _not_ remove a link * or a node from the overall structure. * Correspondingly, individual bearers may change status within a * tipc_net_lock(read), protected by an individual spin_lock ber bearer * instance, but it needs tipc_net_lock(write) to remove/add any bearers. * * * 2: The transport level of the protocol. * This consists of the structures port, (and its user level * representations, such as user_port and tipc_sock), reference and * tipc_user (port.c, reg.c, socket.c). * * This layer has four different locks: * - The tipc_port spin_lock. This is protecting each port instance * from parallel data access and removal. Since we can not place * this lock in the port itself, it has been placed in the * corresponding reference table entry, which has the same life * cycle as the module. This entry is difficult to access from * outside the TIPC core, however, so a pointer to the lock has * been added in the port instance, -to be used for unlocking * only. * - A read/write lock to protect the reference table itself (teg.c). * (Nobody is using read-only access to this, so it can just as * well be changed to a spin_lock) * - A spin lock to protect the registry of kernel/driver users (reg.c) * - A global spin_lock (tipc_port_lock), which only task is to ensure * consistency where more than one port is involved in an operation, * i.e., whe a port is part of a linked list of ports. * There are two such lists; 'port_list', which is used for management, * and 'wait_list', which is used to queue ports during congestion. * * 3: The name table (name_table.c, name_distr.c, subscription.c) * - There is one big read/write-lock (tipc_nametbl_lock) protecting the * overall name table structure. Nothing must be added/removed to * this structure without holding write access to it. * - There is one local spin_lock per sub_sequence, which can be seen * as a sub-domain to the tipc_nametbl_lock domain. It is used only * for translation operations, and is needed because a translation * steps the root of the 'publication' linked list between each lookup. * This is always used within the scope of a tipc_nametbl_lock(read). * - A local spin_lock protecting the queue of subscriber events. */ DEFINE_RWLOCK(tipc_net_lock); struct network tipc_net = { NULL }; struct tipc_node *tipc_net_select_remote_node(u32 addr, u32 ref) { return tipc_zone_select_remote_node(tipc_net.zones[tipc_zone(addr)], addr, ref); } u32 tipc_net_select_router(u32 addr, u32 ref) { return tipc_zone_select_router(tipc_net.zones[tipc_zone(addr)], addr, ref); } #if 0 u32 tipc_net_next_node(u32 a) { if (tipc_net.zones[tipc_zone(a)]) return tipc_zone_next_node(a); return 0; } #endif void tipc_net_remove_as_router(u32 router) { u32 z_num; for (z_num = 1; z_num <= tipc_max_zones; z_num++) { if (!tipc_net.zones[z_num]) continue; tipc_zone_remove_as_router(tipc_net.zones[z_num], router); } } void tipc_net_send_external_routes(u32 dest) { u32 z_num; for (z_num = 1; z_num <= tipc_max_zones; z_num++) { if (tipc_net.zones[z_num]) tipc_zone_send_external_routes(tipc_net.zones[z_num], dest); } } static int net_init(void) { memset(&tipc_net, 0, sizeof(tipc_net)); tipc_net.zones = kcalloc(tipc_max_zones + 1, sizeof(struct _zone *), GFP_ATOMIC); if (!tipc_net.zones) { return -ENOMEM; } return 0; } static void net_stop(void) { u32 z_num; if (!tipc_net.zones) return; for (z_num = 1; z_num <= tipc_max_zones; z_num++) { tipc_zone_delete(tipc_net.zones[z_num]); } kfree(tipc_net.zones); tipc_net.zones = NULL; } static void net_route_named_msg(struct sk_buff *buf) { struct tipc_msg *msg = buf_msg(buf); u32 dnode; u32 dport; if (!msg_named(msg)) { msg_dbg(msg, "tipc_net->drop_nam:"); buf_discard(buf); return; } dnode = addr_domain(msg_lookup_scope(msg)); dport = tipc_nametbl_translate(msg_nametype(msg), msg_nameinst(msg), &dnode); dbg("tipc_net->lookup<%u,%u>-><%u,%x>\n", msg_nametype(msg), msg_nameinst(msg), dport, dnode); if (dport) { msg_set_destnode(msg, dnode); msg_set_destport(msg, dport); tipc_net_route_msg(buf); return; } msg_dbg(msg, "tipc_net->rej:NO NAME: "); tipc_reject_msg(buf, TIPC_ERR_NO_NAME); } void tipc_net_route_msg(struct sk_buff *buf) { struct tipc_msg *msg; u32 dnode; if (!buf) return; msg = buf_msg(buf); msg_incr_reroute_cnt(msg); if (msg_reroute_cnt(msg) > 6) { if (msg_errcode(msg)) { msg_dbg(msg, "NET>DISC>:"); buf_discard(buf); } else { msg_dbg(msg, "NET>REJ>:"); tipc_reject_msg(buf, msg_destport(msg) ? TIPC_ERR_NO_PORT : TIPC_ERR_NO_NAME); } return; } msg_dbg(msg, "tipc_net->rout: "); /* Handle message for this node */ dnode = msg_short(msg) ? tipc_own_addr : msg_destnode(msg); if (in_scope(dnode, tipc_own_addr)) { if (msg_isdata(msg)) { if (msg_mcast(msg)) tipc_port_recv_mcast(buf, NULL); else if (msg_destport(msg)) tipc_port_recv_msg(buf); else net_route_named_msg(buf); return; } switch (msg_user(msg)) { case ROUTE_DISTRIBUTOR: tipc_cltr_recv_routing_table(buf); break; case NAME_DISTRIBUTOR: tipc_named_recv(buf); break; case CONN_MANAGER: tipc_port_recv_proto_msg(buf); break; default: msg_dbg(msg,"DROP/NET/<REC<"); buf_discard(buf); } return; } /* Handle message for another node */ msg_dbg(msg, "NET>SEND>: "); tipc_link_send(buf, dnode, msg_link_selector(msg)); } int tipc_net_start(u32 addr) { char addr_string[16]; int res; if (tipc_mode != TIPC_NODE_MODE) return -ENOPROTOOPT; tipc_subscr_stop(); tipc_cfg_stop(); tipc_own_addr = addr; tipc_mode = TIPC_NET_MODE; tipc_named_reinit(); tipc_port_reinit(); if ((res = tipc_bearer_init()) || (res = net_init()) || (res = tipc_cltr_init()) ||