lib/locking-selftest-mutex.h


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#undef LOCK
#define LOCK		ML

#undef UNLOCK
#define UNLOCK		MU

#undef RLOCK
#undef WLOCK

#undef INIT
#define INIT		MI
/*
 * zs.h: Definitions for the DECstation Z85C30 serial driver.
 *
 * Adapted from drivers/sbus/char/sunserial.h by Paul Mackerras.
 * Adapted from drivers/macintosh/macserial.h by Harald Koerfgen.
 *
 * Copyright (C) 1996 Paul Mackerras (Paul.Mackerras@cs.anu.edu.au)
 * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
 * Copyright (C) 2004, 2005, 2007  Maciej W. Rozycki
 */
#ifndef _SERIAL_ZS_H
#define _SERIAL_ZS_H

#ifdef __KERNEL__

#define ZS_NUM_REGS 16

/*
 * This is our internal structure for each serial port's state.
 */
struct zs_port {
	struct zs_scc	*scc;			/* Containing SCC.  */
	struct uart_port port;			/* Underlying UART.  */

	int		clk_mode;		/* May be 1, 16, 32, or 64.  */

	unsigned int	tty_break;		/* Set on BREAK condition.  */
	int		tx_stopped;		/* Output is suspended.  */

	unsigned int	mctrl;			/* State of modem lines.  */
	u8		brk;			/* BREAK state from RR0.  */

	u8		regs[ZS_NUM_REGS];	/* Channel write registers.  */
};

/*
 * Per-SCC state for locking and the interrupt handler.
 */
struct zs_scc {
	struct zs_port	zport[2];
	spinlock_t	zlock;
	atomic_t	irq_guard;
	int		initialised;
};

#endif /* __KERNEL__ */

/*
 * Conversion routines to/from brg time constants from/to bits per second.
 */
#define ZS_BRG_TO_BPS(brg, freq) ((freq) / 2 / ((brg) + 2))
#define ZS_BPS_TO_BRG(bps, freq) ((((freq) + (bps)) / (2 * (bps))) - 2)

/*
 * The Zilog register set.
 */

/* Write Register 0 (Command) */
#define R0		0	/* Register selects */
#define R1		1
#define R2		2
#define R3		3
#define R4		4
#define R5		5
#define R6		6
#define R7		7
#define R8		8
#define R9		9
#define R10		10
#define R11		11
#define R12		12
#define R13		13
#define R14		14
#define R15		15

#define NULLCODE	0	/* Null Code */
#define POINT_HIGH	0x8	/* Select upper half of registers */
#define RES_EXT_INT	0x10	/* Reset Ext. Status Interrupts */
#define SEND_ABORT	0x18	/* HDLC Abort */
#define RES_RxINT_FC	0x20	/* Reset RxINT on First Character */
#define RES_Tx_P	0x28	/* Reset TxINT Pending */
#define ERR_RES		0x30	/* Error Reset */
#define RES_H_IUS	0x38	/* Reset highest IUS */

#define RES_Rx_CRC	0x40	/* Reset Rx CRC Checker */
#define RES_Tx_CRC	0x80	/* Reset Tx CRC Checker */
#define RES_EOM_L	0xC0	/* Reset EOM latch */

/* Write Register 1 (Tx/Rx/Ext Int Enable and WAIT/DMA Commands) */
#define EXT_INT_ENAB	0x1	/* Ext Int Enable */
#define TxINT_ENAB	0x2	/* Tx Int Enable */
#define PAR_SPEC	0x4	/* Parity is special condition */

#define RxINT_DISAB	0	/* Rx Int Disable */
#define RxINT_FCERR	0x8	/* Rx Int on First Character Only or Error */
#define RxINT_ALL	0x10	/* Int on all Rx Characters or error */
#define RxINT_ERR	0x18	/* Int on error only */
#define RxINT_MASK	0x18

#define WT_RDY_RT	0x20	/* Wait/Ready on R/T */
#define WT_FN_RDYFN	0x40	/* Wait/FN/Ready FN */
#define WT_RDY_ENAB	0x80	/* Wait/Ready Enable */

/* Write Register 2 (Interrupt Vector) */

/* Write Register 3 (Receive Parameters and Control) */
#define RxENABLE	0x1	/* Rx Enable */
#define SYNC_L_INH	0x2	/* Sync Character Load Inhibit */
#define ADD_SM		0x4	/* Address Search Mode (SDLC) */
#define RxCRC_ENAB	0x8	/* Rx CRC Enable */
#define ENT_HM		0x10	/* Enter Hunt Mode */
#define AUTO_ENAB	0x20	/* Auto Enables */
#define Rx5		0x0	/* Rx 5 Bits/Character */
#define Rx7		0x40	/* Rx 7 Bits/Character */
#define Rx6		0x80	/* Rx 6 Bits/Character */
#define Rx8		0xc0	/* Rx 8 Bits/Character */
#define RxNBITS_MASK	0xc0

/* Write Register 4 (Transmit/Receive Miscellaneous Parameters and Modes) */
#define PAR_ENA		0x1	/* Parity Enable */
#define PAR_EVEN	0x2	/* Parity Even/Odd* */

#define SYNC_ENAB	0	/* Sync Modes Enable */
#define SB1		0x4	/* 1 stop bit/char */
#define SB15		0x8	/* 1.5 stop bits/char */
#define SB2		0xc	/* 2 stop bits/char */
#define SB_MASK		0xc

#define MONSYNC		0	/* 8 Bit Sync character */
#define BISYNC		0x10	/* 16 bit sync character */
#define SDLC		0x20	/* SDLC Mode (01111110 Sync Flag) */
#define EXTSYNC		0x30	/* External Sync Mode */

#define X1CLK		0x0	/* x1 clock mode */
#define X16CLK		0x40	/* x16 clock mode */
#define X32CLK		0x80	/* x32 clock mode */
#define X64CLK		0xc0	/* x64 clock mode */
#define XCLK_MASK	0xc0

/* Write Register 5 (Transmit Parameters and Controls) */
#define TxCRC_ENAB	0x1	/* Tx CRC Enable */
#define RTS		0x2	/* RTS */
#define SDLC_CRC	0x4	/* SDLC/CRC-16 */
#define TxENAB		0x8	/* Tx Enable */
#define SND_BRK		0x10	/* Send Break */
#define Tx5		0x0	/* Tx 5 bits (or less)/character */
#define Tx7		0x20	/* Tx 7 bits/character */
#define Tx6		0x40	/* Tx 6 bits/character */
#define Tx8		0x60	/* Tx 8 bits/character */
#define TxNBITS_MASK	0x60
#define DTR		0x80	/* DTR */

/* Write Register 6 (Sync bits 0-7/SDLC Address Field) */

/* Write Register 7 (Sync bits 8-15/SDLC 01111110) */

/* Write Register 8 (Transmit Buffer) */

/* Write Register 9 (Master Interrupt Control) */
#define VIS		1	/* Vector Includes Status */