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#include <linux/spinlock.h>

struct cpustate_t {
	spinlock_t lock;
	int excl;
        int open_count;
	unsigned char cached_val;
	int inited;
	unsigned long *set_addr;
	unsigned long *clr_addr;
};


#define HDPU_CPUSTATE_NAME "hdpu cpustate"
#define HDPU_NEXUS_NAME "hdpu nexus"

#define CPUSTATE_KERNEL_MAJOR  0x10

#define CPUSTATE_KERNEL_INIT_DRV   0 /* CPU State Driver Initialized */
#define CPUSTATE_KERNEL_INIT_PCI   1 /* 64360 PCI Busses Init */
#define CPUSTATE_KERNEL_INIT_REG   2 /* 64360 Bridge Init */
#define CPUSTATE_KERNEL_CPU1_KICK  3 /* Boot cpu 1 */
#define CPUSTATE_KERNEL_CPU1_OK    4  /* Cpu 1 has checked in */
#define CPUSTATE_KERNEL_OK         5 /* Terminal state */
#define CPUSTATE_KERNEL_RESET   14 /* Board reset via SW*/
#define CPUSTATE_KERNEL_HALT   15 /* Board halted via SW*/
status information. A read will fail if there is no operation in progress. As a special case, the device can be reset with a write operation, and in this case, no following read is expected, or permitted. There are no ioctl() operations. Any single operation may transfer at most PG_MAX_DATA bytes. Note that the driver must copy the data through an internal buffer. In keeping with all current ATAPI devices, command packets are assumed to be exactly 12 bytes in length. To permit future changes to this interface, the headers in the read and write buffers contain a single character "magic" flag. Currently this flag must be the character "P". */ #define PG_MAGIC 'P' #define PG_RESET 'Z' #define PG_COMMAND 'C' #define PG_MAX_DATA 32768 struct pg_write_hdr { char magic; /* == PG_MAGIC */ char func; /* PG_RESET or PG_COMMAND */ int dlen; /* number of bytes expected to transfer */ int timeout; /* number of seconds before timeout */ char packet[12]; /* packet command */ }; struct pg_read_hdr { char magic; /* == PG_MAGIC */ char scsi; /* "scsi" status == sense key */ int dlen; /* size of device transfer request */ int duration; /* time in seconds command took */ char pad[12]; /* not used */ }; /* end of pg.h */