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generated by cgit v1.2.2 (git 2.25.0) at 2025-03-08 09:59:30 -0500
"hl opt">{ TIM_START = 1<<2, /* Start Timer */ TIM_STOP = 1<<1, /* Stop Timer */ TIM_CLR_IRQ = 1<<0, /* Clear Timer IRQ (!IRQM) */ }; /* B2_TI_TEST 8 Bit Timer Test */ /* B2_IRQM_TEST 8 bit IRQ Moderation Timer Test */ /* B28_DPT_TST 8 bit Descriptor Poll Timer Test Reg */ enum { TIM_T_ON = 1<<2, /* Test mode on */ TIM_T_OFF = 1<<1, /* Test mode off */ TIM_T_STEP = 1<<0, /* Test step */ }; /* B2_GP_IO 32 bit General Purpose I/O Register */ enum { GP_DIR_9 = 1<<25, /* IO_9 direct, 0=In/1=Out */ GP_DIR_8 = 1<<24, /* IO_8 direct, 0=In/1=Out */ GP_DIR_7 = 1<<23, /* IO_7 direct, 0=In/1=Out */ GP_DIR_6 = 1<<22, /* IO_6 direct, 0=In/1=Out */ GP_DIR_5 = 1<<21, /* IO_5 direct, 0=In/1=Out */ GP_DIR_4 = 1<<20, /* IO_4 direct, 0=In/1=Out */ GP_DIR_3 = 1<<19, /* IO_3 direct, 0=In/1=Out */ GP_DIR_2 = 1<<18, /* IO_2 direct, 0=In/1=Out */ GP_DIR_1 = 1<<17, /* IO_1 direct, 0=In/1=Out */ GP_DIR_0 = 1<<16, /* IO_0 direct, 0=In/1=Out */ GP_IO_9 = 1<<9, /* IO_9 pin */ GP_IO_8 = 1<<8, /* IO_8 pin */ GP_IO_7 = 1<<7, /* IO_7 pin */ GP_IO_6 = 1<<6, /* IO_6 pin */ GP_IO_5 = 1<<5, /* IO_5 pin */ GP_IO_4 = 1<<4, /* IO_4 pin */ GP_IO_3 = 1<<3, /* IO_3 pin */ GP_IO_2 = 1<<2, /* IO_2 pin */ GP_IO_1 = 1<<1, /* IO_1 pin */ GP_IO_0 = 1<<0, /* IO_0 pin */ }; /* Descriptor Bit Definition */ /* TxCtrl Transmit Buffer Control Field */ /* RxCtrl Receive Buffer Control Field */ enum { BMU_OWN = 1<<31, /* OWN bit: 0=host/1=BMU */ BMU_STF = 1<<30, /* Start of Frame */ BMU_EOF = 1<<29, /* End of Frame */ BMU_IRQ_EOB = 1<<28, /* Req "End of Buffer" IRQ */ BMU_IRQ_EOF = 1<<27, /* Req "End of Frame" IRQ */ /* TxCtrl specific bits */ BMU_STFWD = 1<<26, /* (Tx) Store & Forward Frame */ BMU_NO_FCS = 1<<25, /* (Tx) Disable MAC FCS (CRC) generation */ BMU_SW = 1<<24, /* (Tx) 1 bit res. for SW use */ /* RxCtrl specific bits */ BMU_DEV_0 = 1<<26, /* (Rx) Transfer data to Dev0 */ BMU_STAT_VAL = 1<<25, /* (Rx) Rx Status Valid */ BMU_TIST_VAL = 1<<24, /* (Rx) Rx TimeStamp Valid */ /* Bit 23..16: BMU Check Opcodes */ BMU_CHECK = 0x55<<16, /* Default BMU check */ BMU_TCP_CHECK = 0x56<<16, /* Descr with TCP ext */ BMU_UDP_CHECK = 0x57<<16, /* Descr with UDP ext (YUKON only) */ BMU_BBC = 0xffffL, /* Bit 15.. 0: Buffer Byte Counter */ }; /* B2_BSC_CTRL 8 bit Blink Source Counter Control */ enum { BSC_START = 1<<1, /* Start Blink Source Counter */ BSC_STOP = 1<<0, /* Stop Blink Source Counter */ }; /* B2_BSC_STAT 8 bit Blink Source Counter Status */ enum { BSC_SRC = 1<<0, /* Blink Source, 0=Off / 1=On */ }; /* B2_BSC_TST 16 bit Blink Source Counter Test Reg */ enum { BSC_T_ON = 1<<2, /* Test mode on */ BSC_T_OFF = 1<<1, /* Test mode off */ BSC_T_STEP = 1<<0, /* Test step */ }; /* B3_RAM_ADDR 32 bit RAM Address, to read or write */ /* Bit 31..19: reserved */ #define RAM_ADR_RAN 0x0007ffffL /* Bit 18.. 0: RAM Address Range */ /* RAM Interface Registers */ /* B3_RI_CTRL 16 bit RAM Iface Control Register */ enum { RI_CLR_RD_PERR = 1<<9, /* Clear IRQ RAM Read Parity Err */ RI_CLR_WR_PERR = 1<<8, /* Clear IRQ RAM Write Parity Err*/ RI_RST_CLR = 1<<1, /* Clear RAM Interface Reset */ RI_RST_SET = 1<<0, /* Set RAM Interface Reset */ }; /* MAC Arbiter Registers */ /* B3_MA_TO_CTRL 16 bit MAC Arbiter Timeout Ctrl Reg */ enum { MA_FOE_ON = 1<<3, /* XMAC Fast Output Enable ON */ MA_FOE_OFF = 1<<2, /* XMAC Fast Output Enable OFF */ MA_RST_CLR = 1<<1, /* Clear MAC Arbiter Reset */ MA_RST_SET = 1<<0, /* Set MAC Arbiter Reset */ }; /* Timeout values */ #define SK_MAC_TO_53 72 /* MAC arbiter timeout */ #define SK_PKT_TO_53 0x2000 /* Packet arbiter timeout */ #define SK_PKT_TO_MAX 0xffff /* Maximum value */ #define SK_RI_TO_53 36 /* RAM interface timeout */ /* Packet Arbiter Registers */ /* B3_PA_CTRL 16 bit Packet Arbiter Ctrl Register */ enum { PA_CLR_TO_TX2 = 1<<13, /* Clear IRQ Packet Timeout TX2 */ PA_CLR_TO_TX1 = 1<<12, /* Clear IRQ Packet Timeout TX1 */ PA_CLR_TO_RX2 = 1<<11, /* Clear IRQ Packet Timeout RX2 */ PA_CLR_TO_RX1 = 1<<10, /* Clear IRQ Packet Timeout RX1 */ PA_ENA_TO_TX2 = 1<<9, /* Enable Timeout Timer TX2 */ PA_DIS_TO_TX2 = 1<<8, /* Disable Timeout Timer TX2 */ PA_ENA_TO_TX1 = 1<<7, /* Enable Timeout Timer TX1 */ PA_DIS_TO_TX1 = 1<<6, /* Disable Timeout Timer TX1 */ PA_ENA_TO_RX2 = 1<<5, /* Enable Timeout Timer RX2 */ PA_DIS_TO_RX2 = 1<<4, /* Disable Timeout Timer RX2 */ PA_ENA_TO_RX1 = 1<<3, /* Enable Timeout Timer RX1 */ PA_DIS_TO_RX1 = 1<<2, /* Disable Timeout Timer RX1 */ PA_RST_CLR = 1<<1, /* Clear MAC Arbiter Reset */ PA_RST_SET = 1<<0, /* Set MAC Arbiter Reset */ }; #define PA_ENA_TO_ALL (PA_ENA_TO_RX1 | PA_ENA_TO_RX2 |\ PA_ENA_TO_TX1 | PA_ENA_TO_TX2) /* Transmit Arbiter Registers MAC 1 and 2, use SK_REG() to access */ /* TXA_ITI_INI 32 bit Tx Arb Interval Timer Init Val */ /* TXA_ITI_VAL 32 bit Tx Arb Interval Timer Value */ /* TXA_LIM_INI 32 bit Tx Arb Limit Counter Init Val */ /* TXA_LIM_VAL 32 bit Tx Arb Limit Counter Value */ #define TXA_MAX_VAL 0x00ffffffUL /* Bit 23.. 0: Max TXA Timer/Cnt Val */ /* TXA_CTRL 8 bit Tx Arbiter Control Register */ enum { TXA_ENA_FSYNC = 1<<7, /* Enable force of sync Tx queue */ TXA_DIS_FSYNC = 1<<6, /* Disable force of sync Tx queue */ TXA_ENA_ALLOC = 1<<5, /* Enable alloc of free bandwidth */ TXA_DIS_ALLOC = 1<<4, /* Disable alloc of free bandwidth */ TXA_START_RC = 1<<3, /* Start sync Rate Control */ TXA_STOP_RC = 1<<2, /* Stop sync Rate Control */ TXA_ENA_ARB = 1<<1, /* Enable Tx Arbiter */ TXA_DIS_ARB = 1<<0, /* Disable Tx Arbiter */ }; /* * Bank 4 - 5 */ /* Transmit Arbiter Registers MAC 1 and 2, use SK_REG() to access */ enum { TXA_ITI_INI = 0x0200,/* 32 bit Tx Arb Interval Timer Init Val*/ TXA_ITI_VAL = 0x0204,/* 32 bit Tx Arb Interval Timer Value */ TXA_LIM_INI = 0x0208,/* 32 bit Tx Arb Limit Counter Init Val */ TXA_LIM_VAL = 0x020c,/* 32 bit Tx Arb Limit Counter Value */ TXA_CTRL = 0x0210,/* 8 bit Tx Arbiter Control Register */ TXA_TEST = 0x0211,/* 8 bit Tx Arbiter Test Register */ TXA_STAT = 0x0212,/* 8 bit Tx Arbiter Status Register */ }; enum { B6_EXT_REG = 0x0300,/* External registers (GENESIS only) */ B7_CFG_SPC = 0x0380,/* copy of the Configuration register */ B8_RQ1_REGS = 0x0400,/* Receive Queue 1 */ B8_RQ2_REGS = 0x0480,/* Receive Queue 2 */ B8_TS1_REGS = 0x0600,/* Transmit sync queue 1 */ B8_TA1_REGS = 0x0680,/* Transmit async queue 1 */ B8_TS2_REGS = 0x0700,/* Transmit sync queue 2 */ B8_TA2_REGS = 0x0780,/* Transmit sync queue 2 */ B16_RAM_REGS = 0x0800,/* RAM Buffer Registers */ }; /* Queue Register Offsets, use Q_ADDR() to access */ enum { B8_Q_REGS = 0x0400, /* base of Queue registers */ Q_D = 0x00, /* 8*32 bit Current Descriptor */ Q_DA_L = 0x20, /* 32 bit Current Descriptor Address Low dWord */ Q_DA_H = 0x24, /* 32 bit Current Descriptor Address High dWord */ Q_AC_L = 0x28, /* 32 bit Current Address Counter Low dWord */ Q_AC_H = 0x2c, /* 32 bit Current Address Counter High dWord */ Q_BC = 0x30, /* 32 bit Current Byte Counter */ Q_CSR = 0x34, /* 32 bit BMU Control/Status Register */ Q_F = 0x38, /* 32 bit Flag Register */ Q_T1 = 0x3c, /* 32 bit Test Register 1 */ Q_T1_TR = 0x3c, /* 8 bit Test Register 1 Transfer SM */ Q_T1_WR = 0x3d, /* 8 bit Test Register 1 Write Descriptor SM */ Q_T1_RD = 0x3e, /* 8 bit Test Register 1 Read Descriptor SM */ Q_T1_SV = 0x3f, /* 8 bit Test Register 1 Supervisor SM */ Q_T2 = 0x40, /* 32 bit Test Register 2 */ Q_T3 = 0x44, /* 32 bit Test Register 3 */ }; #define Q_ADDR(reg, offs) (B8_Q_REGS + (reg) + (offs)) /* RAM Buffer Register Offsets */ enum { RB_START = 0x00,/* 32 bit RAM Buffer Start Address */ RB_END = 0x04,/* 32 bit RAM Buffer End Address */ RB_WP = 0x08,/* 32 bit RAM Buffer Write Pointer */ RB_RP = 0x0c,/* 32 bit RAM Buffer Read Pointer */ RB_RX_UTPP = 0x10,/* 32 bit Rx Upper Threshold, Pause Packet */ RB_RX_LTPP = 0x14,/* 32 bit Rx Lower Threshold, Pause Packet */ RB_RX_UTHP = 0x18,/* 32 bit Rx Upper Threshold, High Prio */ RB_RX_LTHP = 0x1c,/* 32 bit Rx Lower Threshold, High Prio */ /* 0x10 - 0x1f: reserved at Tx RAM Buffer Registers */ RB_PC = 0x20,/* 32 bit RAM Buffer Packet Counter */ RB_LEV = 0x24,/* 32 bit RAM Buffer Level Register */ RB_CTRL = 0x28,/* 32 bit RAM Buffer Control Register */ RB_TST1 = 0x29,/* 8 bit RAM Buffer Test Register 1 */ RB_TST2 = 0x2a,/* 8 bit RAM Buffer Test Register 2 */ }; /* Receive and Transmit Queues */ enum { Q_R1 = 0x0000, /* Receive Queue 1 */ Q_R2 = 0x0080, /* Receive Queue 2 */ Q_XS1 = 0x0200, /* Synchronous Transmit Queue 1 */ Q_XA1 = 0x0280, /* Asynchronous Transmit Queue 1 */ Q_XS2 = 0x0300, /* Synchronous Transmit Queue 2 */ Q_XA2 = 0x0380, /* Asynchronous Transmit Queue 2 */ }; /* Different MAC Types */ enum { SK_MAC_XMAC = 0, /* Xaqti XMAC II */ SK_MAC_GMAC = 1, /* Marvell GMAC */ }; /* Different PHY Types */ enum { SK_PHY_XMAC = 0,/* integrated in XMAC II */ SK_PHY_BCOM = 1,/* Broadcom BCM5400 */ SK_PHY_LONE = 2,/* Level One LXT1000 [not supported]*/ SK_PHY_NAT = 3,/* National DP83891 [not supported] */ SK_PHY_MARV_COPPER= 4,/* Marvell 88E1011S */ SK_PHY_MARV_FIBER = 5,/* Marvell 88E1011S working on fiber */ }; /* PHY addresses (bits 12..8 of PHY address reg) */ enum { PHY_ADDR_XMAC = 0<<8, PHY_ADDR_BCOM = 1<<8, /* GPHY address (bits 15..11 of SMI control reg) */ PHY_ADDR_MARV = 0, }; #define RB_ADDR(offs, queue) (B16_RAM_REGS + (queue) + (offs)) /* Receive MAC FIFO, Receive LED, and Link_Sync regs (GENESIS only) */ enum { RX_MFF_EA = 0x0c00,/* 32 bit Receive MAC FIFO End Address */ RX_MFF_WP = 0x0c04,/* 32 bit Receive MAC FIFO Write Pointer */ RX_MFF_RP = 0x0c0c,/* 32 bit Receive MAC FIFO Read Pointer */ RX_MFF_PC = 0x0c10,/* 32 bit Receive MAC FIFO Packet Cnt */ RX_MFF_LEV = 0x0c14,/* 32 bit Receive MAC FIFO Level */ RX_MFF_CTRL1 = 0x0c18,/* 16 bit Receive MAC FIFO Control Reg 1*/ RX_MFF_STAT_TO = 0x0c1a,/* 8 bit Receive MAC Status Timeout */ RX_MFF_TIST_TO = 0x0c1b,/* 8 bit Receive MAC Time Stamp Timeout */ RX_MFF_CTRL2 = 0x0c1c,/* 8 bit Receive MAC FIFO Control Reg 2*/ RX_MFF_TST1 = 0x0c1d,/* 8 bit Receive MAC FIFO Test Reg 1 */ RX_MFF_TST2 = 0x0c1e,/* 8 bit Receive MAC FIFO Test Reg 2 */ RX_LED_INI = 0x0c20,/* 32 bit Receive LED Cnt Init Value */ RX_LED_VAL = 0x0c24,/* 32 bit Receive LED Cnt Current Value */ RX_LED_CTRL = 0x0c28,/* 8 bit Receive LED Cnt Control Reg */ RX_LED_TST = 0x0c29,/* 8 bit Receive LED Cnt Test Register */ LNK_SYNC_INI = 0x0c30,/* 32 bit Link Sync Cnt Init Value */ LNK_SYNC_VAL = 0x0c34,/* 32 bit Link Sync Cnt Current Value */ LNK_SYNC_CTRL = 0x0c38,/* 8 bit Link Sync Cnt Control Register */ LNK_SYNC_TST = 0x0c39,/* 8 bit Link Sync Cnt Test Register */ LNK_LED_REG = 0x0c3c,/* 8 bit Link LED Register */ }; /* Receive and Transmit MAC FIFO Registers (GENESIS only) */ /* RX_MFF_CTRL1 16 bit Receive MAC FIFO Control Reg 1 */ enum { MFF_ENA_RDY_PAT = 1<<13, /* Enable Ready Patch */ MFF_DIS_RDY_PAT = 1<<12, /* Disable Ready Patch */ MFF_ENA_TIM_PAT = 1<<11, /* Enable Timing Patch */ MFF_DIS_TIM_PAT = 1<<10, /* Disable Timing Patch */ MFF_ENA_ALM_FUL = 1<<9, /* Enable AlmostFull Sign */ MFF_DIS_ALM_FUL = 1<<8, /* Disable AlmostFull Sign */ MFF_ENA_PAUSE = 1<<7, /* Enable Pause Signaling */ MFF_DIS_PAUSE = 1<<6, /* Disable Pause Signaling */ MFF_ENA_FLUSH = 1<<5, /* Enable Frame Flushing */ MFF_DIS_FLUSH = 1<<4, /* Disable Frame Flushing */ MFF_ENA_TIST = 1<<3, /* Enable Time Stamp Gener */ MFF_DIS_TIST = 1<<2, /* Disable Time Stamp Gener */ MFF_CLR_INTIST = 1<<1, /* Clear IRQ No Time Stamp */ MFF_CLR_INSTAT = 1<<0, /* Clear IRQ No Status */ #define MFF_RX_CTRL_DEF MFF_ENA_TIM_PAT }; /* TX_MFF_CTRL1 16 bit Transmit MAC FIFO Control Reg 1 */ enum { MFF_CLR_PERR = 1<<15, /* Clear Parity Error IRQ */ /* Bit 14: reserved */ MFF_ENA_PKT_REC = 1<<13, /* Enable Packet Recovery */ MFF_DIS_PKT_REC = 1<<12, /* Disable Packet Recovery */ MFF_ENA_W4E = 1<<7, /* Enable Wait for Empty */ MFF_DIS_W4E = 1<<6, /* Disable Wait for Empty */ MFF_ENA_LOOPB = 1<<3, /* Enable Loopback */ MFF_DIS_LOOPB = 1<<2, /* Disable Loopback */ MFF_CLR_MAC_RST = 1<<1, /* Clear XMAC Reset */ MFF_SET_MAC_RST = 1<<0, /* Set XMAC Reset */ }; #define MFF_TX_CTRL_DEF (MFF_ENA_PKT_REC | MFF_ENA_TIM_PAT | MFF_ENA_FLUSH) /* RX_MFF_TST2 8 bit Receive MAC FIFO Test Register 2 */ /* TX_MFF_TST2 8 bit Transmit MAC FIFO Test Register 2 */ enum { MFF_WSP_T_ON = 1<<6, /* Tx: Write Shadow Ptr TestOn */ MFF_WSP_T_OFF = 1<<5, /* Tx: Write Shadow Ptr TstOff */ MFF_WSP_INC = 1<<4, /* Tx: Write Shadow Ptr Increment */ MFF_PC_DEC = 1<<3, /* Packet Counter Decrement */ MFF_PC_T_ON = 1<<2, /* Packet Counter Test On */ MFF_PC_T_OFF = 1<<1, /* Packet Counter Test Off */ MFF_PC_INC = 1<<0, /* Packet Counter Increment */ }; /* RX_MFF_TST1 8 bit Receive MAC FIFO Test Register 1 */ /* TX_MFF_TST1 8 bit Transmit MAC FIFO Test Register 1 */ enum { MFF_WP_T_ON = 1<<6, /* Write Pointer Test On */ MFF_WP_T_OFF = 1<<5, /* Write Pointer Test Off */ MFF_WP_INC = 1<<4, /* Write Pointer Increm */ MFF_RP_T_ON = 1<<2, /* Read Pointer Test On */ MFF_RP_T_OFF = 1<<1, /* Read Pointer Test Off */ MFF_RP_DEC = 1<<0, /* Read Pointer Decrement */ }; /* RX_MFF_CTRL2 8 bit Receive MAC FIFO Control Reg 2 */ /* TX_MFF_CTRL2 8 bit Transmit MAC FIFO Control Reg 2 */ enum { MFF_ENA_OP_MD = 1<<3, /* Enable Operation Mode */ MFF_DIS_OP_MD = 1<<2, /* Disable Operation Mode */ MFF_RST_CLR = 1<<1, /* Clear MAC FIFO Reset */ MFF_RST_SET = 1<<0, /* Set MAC FIFO Reset */ }; /* Link LED Counter Registers (GENESIS only) */ /* RX_LED_CTRL 8 bit Receive LED Cnt Control Reg */ /* TX_LED_CTRL 8 bit Transmit LED Cnt Control Reg */ /* LNK_SYNC_CTRL 8 bit Link Sync Cnt Control Register */ enum { LED_START = 1<<2, /* Start Timer */ LED_STOP = 1<<1, /* Stop Timer */ LED_STATE = 1<<0, /* Rx/Tx: LED State, 1=LED on */ }; /* RX_LED_TST 8 bit Receive LED Cnt Test Register */ /* TX_LED_TST 8 bit Transmit LED Cnt Test Register */ /* LNK_SYNC_TST 8 bit Link Sync Cnt Test Register */ enum { LED_T_ON = 1<<2, /* LED Counter Test mode On */ LED_T_OFF = 1<<1, /* LED Counter Test mode Off */ LED_T_STEP = 1<<0, /* LED Counter Step */ }; /* LNK_LED_REG 8 bit Link LED Register */ enum { LED_BLK_ON = 1<<5, /* Link LED Blinking On */ LED_BLK_OFF = 1<<4, /* Link LED Blinking Off */ LED_SYNC_ON = 1<<3, /* Use Sync Wire to switch LED */ LED_SYNC_OFF = 1<<2, /* Disable Sync Wire Input */ LED_ON = 1<<1, /* switch LED on */ LED_OFF = 1<<0, /* switch LED off */ }; /* Receive GMAC FIFO (YUKON) */ enum { RX_GMF_EA = 0x0c40,/* 32 bit Rx GMAC FIFO End Address */ RX_GMF_AF_THR = 0x0c44,/* 32 bit Rx GMAC FIFO Almost Full Thresh. */ RX_GMF_CTRL_T = 0x0c48,/* 32 bit Rx GMAC FIFO Control/Test */ RX_GMF_FL_MSK = 0x0c4c,/* 32 bit Rx GMAC FIFO Flush Mask */ RX_GMF_FL_THR = 0x0c50,/* 32 bit Rx GMAC FIFO Flush Threshold */ RX_GMF_WP = 0x0c60,/* 32 bit Rx GMAC FIFO Write Pointer */ RX_GMF_WLEV = 0x0c68,/* 32 bit Rx GMAC FIFO Write Level */ RX_GMF_RP = 0x0c70,/* 32 bit Rx GMAC FIFO Read Pointer */ RX_GMF_RLEV = 0x0c78,/* 32 bit Rx GMAC FIFO Read Level */ }; /* TXA_TEST 8 bit Tx Arbiter Test Register */ enum { TXA_INT_T_ON = 1<<5, /* Tx Arb Interval Timer Test On */ TXA_INT_T_OFF = 1<<4, /* Tx Arb Interval Timer Test Off */ TXA_INT_T_STEP = 1<<3, /* Tx Arb Interval Timer Step */ TXA_LIM_T_ON = 1<<2, /* Tx Arb Limit Timer Test On */ TXA_LIM_T_OFF = 1<<1, /* Tx Arb Limit Timer Test Off */ TXA_LIM_T_STEP = 1<<0, /* Tx Arb Limit Timer Step */ }; /* TXA_STAT 8 bit Tx Arbiter Status Register */ enum { TXA_PRIO_XS = 1<<0, /* sync queue has prio to send */ }; /* Q_BC 32 bit Current Byte Counter */ /* BMU Control Status Registers */ /* B0_R1_CSR 32 bit BMU Ctrl/Stat Rx Queue 1 */ /* B0_R2_CSR 32 bit BMU Ctrl/Stat Rx Queue 2 */ /* B0_XA1_CSR 32 bit BMU Ctrl/Stat Sync Tx Queue 1 */ /* B0_XS1_CSR 32 bit BMU Ctrl/Stat Async Tx Queue 1 */ /* B0_XA2_CSR 32 bit BMU Ctrl/Stat Sync Tx Queue 2 */ /* B0_XS2_CSR 32 bit BMU Ctrl/Stat Async Tx Queue 2 */ /* Q_CSR 32 bit BMU Control/Status Register */ enum { CSR_SV_IDLE = 1<<24, /* BMU SM Idle */ CSR_DESC_CLR = 1<<21, /* Clear Reset for Descr */ CSR_DESC_SET = 1<<20, /* Set Reset for Descr */ CSR_FIFO_CLR = 1<<19, /* Clear Reset for FIFO */ CSR_FIFO_SET = 1<<18, /* Set Reset for FIFO */ CSR_HPI_RUN = 1<<17, /* Release HPI SM */ CSR_HPI_RST = 1<<16, /* Reset HPI SM to Idle */ CSR_SV_RUN = 1<<15, /* Release Supervisor SM */ CSR_SV_RST = 1<<14, /* Reset Supervisor SM */ CSR_DREAD_RUN = 1<<13, /* Release Descr Read SM */ CSR_DREAD_RST = 1<<12, /* Reset Descr Read SM */ CSR_DWRITE_RUN = 1<<11, /* Release Descr Write SM */ CSR_DWRITE_RST = 1<<10, /* Reset Descr Write SM */ CSR_TRANS_RUN = 1<<9, /* Release Transfer SM */ CSR_TRANS_RST = 1<<8, /* Reset Transfer SM */ CSR_ENA_POL = 1<<7, /* Enable Descr Polling */ CSR_DIS_POL = 1<<6, /* Disable Descr Polling */ CSR_STOP = 1<<5, /* Stop Rx/Tx Queue */ CSR_START = 1<<4, /* Start Rx/Tx Queue */ CSR_IRQ_CL_P = 1<<3, /* (Rx) Clear Parity IRQ */ CSR_IRQ_CL_B = 1<<2, /* Clear EOB IRQ */ CSR_IRQ_CL_F = 1<<1, /* Clear EOF IRQ */ CSR_IRQ_CL_C = 1<<0, /* Clear ERR IRQ */ }; #define CSR_SET_RESET (CSR_DESC_SET | CSR_FIFO_SET | CSR_HPI_RST |\ CSR_SV_RST | CSR_DREAD_RST | CSR_DWRITE_RST |\ CSR_TRANS_RST) #define CSR_CLR_RESET (CSR_DESC_CLR | CSR_FIFO_CLR | CSR_HPI_RUN |\ CSR_SV_RUN | CSR_DREAD_RUN | CSR_DWRITE_RUN |\ CSR_TRANS_RUN) /* Q_F 32 bit Flag Register */ enum { F_ALM_FULL = 1<<27, /* Rx FIFO: almost full */ F_EMPTY = 1<<27, /* Tx FIFO: empty flag */ F_FIFO_EOF = 1<<26, /* Tag (EOF Flag) bit in FIFO */ F_WM_REACHED = 1<<25, /* Watermark reached */ F_FIFO_LEVEL = 0x1fL<<16, /* Bit 23..16: # of Qwords in FIFO */ F_WATER_MARK = 0x0007ffL, /* Bit 10.. 0: Watermark */ }; /* RAM Buffer Register Offsets, use RB_ADDR(Queue, Offs) to access */ /* RB_START 32 bit RAM Buffer Start Address */ /* RB_END 32 bit RAM Buffer End Address */ /* RB_WP 32 bit RAM Buffer Write Pointer */ /* RB_RP 32 bit RAM Buffer Read Pointer */ /* RB_RX_UTPP 32 bit Rx Upper Threshold, Pause Pack */ /* RB_RX_LTPP 32 bit Rx Lower Threshold, Pause Pack */ /* RB_RX_UTHP 32 bit Rx Upper Threshold, High Prio */ /* RB_RX_LTHP 32 bit Rx Lower Threshold, High Prio */ /* RB_PC 32 bit RAM Buffer Packet Counter */ /* RB_LEV 32 bit RAM Buffer Level Register */ #define RB_MSK 0x0007ffff /* Bit 18.. 0: RAM Buffer Pointer Bits */ /* RB_TST2 8 bit RAM Buffer Test Register 2 */ /* RB_TST1 8 bit RAM Buffer Test Register 1 */ /* RB_CTRL 8 bit RAM Buffer Control Register */ enum { RB_ENA_STFWD = 1<<5, /* Enable Store & Forward */ RB_DIS_STFWD = 1<<4, /* Disable Store & Forward */ RB_ENA_OP_MD = 1<<3, /* Enable Operation Mode */ RB_DIS_OP_MD = 1<<2, /* Disable Operation Mode */ RB_RST_CLR = 1<<1, /* Clear RAM Buf STM Reset */ RB_RST_SET = 1<<0, /* Set RAM Buf STM Reset */ }; /* Transmit MAC FIFO and Transmit LED Registers (GENESIS only), */ enum { TX_MFF_EA = 0x0d00,/* 32 bit Transmit MAC FIFO End Address */ TX_MFF_WP = 0x0d04,/* 32 bit Transmit MAC FIFO WR Pointer */ TX_MFF_WSP = 0x0d08,/* 32 bit Transmit MAC FIFO WR Shadow Ptr */ TX_MFF_RP = 0x0d0c,/* 32 bit Transmit MAC FIFO RD Pointer */ TX_MFF_PC = 0x0d10,/* 32 bit Transmit MAC FIFO Packet Cnt */ TX_MFF_LEV = 0x0d14,/* 32 bit Transmit MAC FIFO Level */ TX_MFF_CTRL1 = 0x0d18,/* 16 bit Transmit MAC FIFO Ctrl Reg 1 */ TX_MFF_WAF = 0x0d1a,/* 8 bit Transmit MAC Wait after flush */ TX_MFF_CTRL2 = 0x0d1c,/* 8 bit Transmit MAC FIFO Ctrl Reg 2 */ TX_MFF_TST1 = 0x0d1d,/* 8 bit Transmit MAC FIFO Test Reg 1 */ TX_MFF_TST2 = 0x0d1e,/* 8 bit Transmit MAC FIFO Test Reg 2 */ TX_LED_INI = 0x0d20,/* 32 bit Transmit LED Cnt Init Value */ TX_LED_VAL = 0x0d24,/* 32 bit Transmit LED Cnt Current Val */ TX_LED_CTRL = 0x0d28,/* 8 bit Transmit LED Cnt Control Reg */ TX_LED_TST = 0x0d29,/* 8 bit Transmit LED Cnt Test Reg */ }; /* Counter and Timer constants, for a host clock of 62.5 MHz */ #define SK_XMIT_DUR 0x002faf08UL /* 50 ms */ #define SK_BLK_DUR 0x01dcd650UL /* 500 ms */ #define SK_DPOLL_DEF 0x00ee6b28UL /* 250 ms at 62.5 MHz */ #define SK_DPOLL_MAX 0x00ffffffUL /* 268 ms at 62.5 MHz */ /* 215 ms at 78.12 MHz */ #define SK_FACT_62 100 /* is given in percent */ #define SK_FACT_53 85 /* on GENESIS: 53.12 MHz */ #define SK_FACT_78 125 /* on YUKON: 78.12 MHz */ /* Transmit GMAC FIFO (YUKON only) */ enum { TX_GMF_EA = 0x0d40,/* 32 bit Tx GMAC FIFO End Address */ TX_GMF_AE_THR = 0x0d44,/* 32 bit Tx GMAC FIFO Almost Empty Thresh.*/ TX_GMF_CTRL_T = 0x0d48,/* 32 bit Tx GMAC FIFO Control/Test */ TX_GMF_WP = 0x0d60,/* 32 bit Tx GMAC FIFO Write Pointer */ TX_GMF_WSP = 0x0d64,/* 32 bit Tx GMAC FIFO Write Shadow Ptr. */ TX_GMF_WLEV = 0x0d68,/* 32 bit Tx GMAC FIFO Write Level */ TX_GMF_RP = 0x0d70,/* 32 bit Tx GMAC FIFO Read Pointer */ TX_GMF_RSTP = 0x0d74,/* 32 bit Tx GMAC FIFO Restart Pointer */ TX_GMF_RLEV = 0x0d78,/* 32 bit Tx GMAC FIFO Read Level */ /* Descriptor Poll Timer Registers */ B28_DPT_INI = 0x0e00,/* 24 bit Descriptor Poll Timer Init Val */ B28_DPT_VAL = 0x0e04,/* 24 bit Descriptor Poll Timer Curr Val */ B28_DPT_CTRL = 0x0e08,/* 8 bit Descriptor Poll Timer Ctrl Reg */ B28_DPT_TST = 0x0e0a,/* 8 bit Descriptor Poll Timer Test Reg */ /* Time Stamp Timer Registers (YUKON only) */ GMAC_TI_ST_VAL = 0x0e14,/* 32 bit Time Stamp Timer Curr Val */ GMAC_TI_ST_CTRL = 0x0e18,/* 8 bit Time Stamp Timer Ctrl Reg */ GMAC_TI_ST_TST = 0x0e1a,/* 8 bit Time Stamp Timer Test Reg */ }; enum { LINKLED_OFF = 0x01, LINKLED_ON = 0x02, LINKLED_LINKSYNC_OFF = 0x04, LINKLED_LINKSYNC_ON = 0x08, LINKLED_BLINK_OFF = 0x10, LINKLED_BLINK_ON = 0x20, }; /* GMAC and GPHY Control Registers (YUKON only) */ enum { GMAC_CTRL = 0x0f00,/* 32 bit GMAC Control Reg */ GPHY_CTRL = 0x0f04,/* 32 bit GPHY Control Reg */ GMAC_IRQ_SRC = 0x0f08,/* 8 bit GMAC Interrupt Source Reg */ GMAC_IRQ_MSK = 0x0f0c,/* 8 bit GMAC Interrupt Mask Reg */ GMAC_LINK_CTRL = 0x0f10,/* 16 bit Link Control Reg */ /* Wake-up Frame Pattern Match Control Registers (YUKON only) */ WOL_REG_OFFS = 0x20,/* HW-Bug: Address is + 0x20 against spec. */ WOL_CTRL_STAT = 0x0f20,/* 16 bit WOL Control/Status Reg */ WOL_MATCH_CTL = 0x0f22,/* 8 bit WOL Match Control Reg */ WOL_MATCH_RES = 0x0f23,/* 8 bit WOL Match Result Reg */ WOL_MAC_ADDR = 0x0f24,/* 32 bit WOL MAC Address */ WOL_PATT_RPTR = 0x0f2c,/* 8 bit WOL Pattern Read Pointer */ /* WOL Pattern Length Registers (YUKON only) */ WOL_PATT_LEN_LO = 0x0f30,/* 32 bit WOL Pattern Length 3..0 */ WOL_PATT_LEN_HI = 0x0f34,/* 24 bit WOL Pattern Length 6..4 */ /* WOL Pattern Counter Registers (YUKON only) */ WOL_PATT_CNT_0 = 0x0f38,/* 32 bit WOL Pattern Counter 3..0 */ WOL_PATT_CNT_4 = 0x0f3c,/* 24 bit WOL Pattern Counter 6..4 */ }; enum { WOL_PATT_RAM_1 = 0x1000,/* WOL Pattern RAM Link 1 */ WOL_PATT_RAM_2 = 0x1400,/* WOL Pattern RAM Link 2 */ }; enum { BASE_XMAC_1 = 0x2000,/* XMAC 1 registers */ BASE_GMAC_1 = 0x2800,/* GMAC 1 registers */ BASE_XMAC_2 = 0x3000,/* XMAC 2 registers */ BASE_GMAC_2 = 0x3800,/* GMAC 2 registers */ }; /* * Receive Frame Status Encoding */ enum { XMR_FS_LEN = 0x3fff<<18, /* Bit 31..18: Rx Frame Length */ XMR_FS_LEN_SHIFT = 18, XMR_FS_2L_VLAN = 1<<17, /* Bit 17: tagged wh 2Lev VLAN ID*/ XMR_FS_1_VLAN = 1<<16, /* Bit 16: tagged wh 1ev VLAN ID*/ XMR_FS_BC = 1<<15, /* Bit 15: Broadcast Frame */ XMR_FS_MC = 1<<14, /* Bit 14: Multicast Frame */ XMR_FS_UC = 1<<13, /* Bit 13: Unicast Frame */ XMR_FS_BURST = 1<<11, /* Bit 11: Burst Mode */ XMR_FS_CEX_ERR = 1<<10, /* Bit 10: Carrier Ext. Error */ XMR_FS_802_3 = 1<<9, /* Bit 9: 802.3 Frame */ XMR_FS_COL_ERR = 1<<8, /* Bit 8: Collision Error */ XMR_FS_CAR_ERR = 1<<7, /* Bit 7: Carrier Event Error */ XMR_FS_LEN_ERR = 1<<6, /* Bit 6: In-Range Length Error */ XMR_FS_FRA_ERR = 1<<5, /* Bit 5: Framing Error */ XMR_FS_RUNT = 1<<4, /* Bit 4: Runt Frame */ XMR_FS_LNG_ERR = 1<<3, /* Bit 3: Giant (Jumbo) Frame */ XMR_FS_FCS_ERR = 1<<2, /* Bit 2: Frame Check Sequ Err */ XMR_FS_ERR = 1<<1, /* Bit 1: Frame Error */ XMR_FS_MCTRL = 1<<0, /* Bit 0: MAC Control Packet */ /* * XMR_FS_ERR will be set if * XMR_FS_FCS_ERR, XMR_FS_LNG_ERR, XMR_FS_RUNT, * XMR_FS_FRA_ERR, XMR_FS_LEN_ERR, or XMR_FS_CEX_ERR * is set. XMR_FS_LNG_ERR and XMR_FS_LEN_ERR will issue * XMR_FS_ERR unless the corresponding bit in the Receive Command * Register is set. */ }; /* ,* XMAC-PHY Registers, indirect addressed over the XMAC */ enum { PHY_XMAC_CTRL = 0x00,/* 16 bit r/w PHY Control Register */ PHY_XMAC_STAT = 0x01,/* 16 bit r/w PHY Status Register */ PHY_XMAC_ID0 = 0x02,/* 16 bit r/o PHY ID0 Register */ PHY_XMAC_ID1 = 0x03,/* 16 bit r/o PHY ID1 Register */ PHY_XMAC_AUNE_ADV = 0x04,/* 16 bit r/w Auto-Neg. Advertisement */ PHY_XMAC_AUNE_LP = 0x05,/* 16 bit r/o Link Partner Abi Reg */ PHY_XMAC_AUNE_EXP = 0x06,/* 16 bit r/o Auto-Neg. Expansion Reg */ PHY_XMAC_NEPG = 0x07,/* 16 bit r/w Next Page Register */ PHY_XMAC_NEPG_LP = 0x08,/* 16 bit r/o Next Page Link Partner */ PHY_XMAC_EXT_STAT = 0x0f,/* 16 bit r/o Ext Status Register */ PHY_XMAC_RES_ABI = 0x10,/* 16 bit r/o PHY Resolved Ability */ }; /* * Broadcom-PHY Registers, indirect addressed over XMAC */ enum { PHY_BCOM_CTRL = 0x00,/* 16 bit r/w PHY Control Register */ PHY_BCOM_STAT = 0x01,/* 16 bit r/o PHY Status Register */ PHY_BCOM_ID0 = 0x02,/* 16 bit r/o PHY ID0 Register */ PHY_BCOM_ID1 = 0x03,/* 16 bit r/o PHY ID1 Register */ PHY_BCOM_AUNE_ADV = 0x04,/* 16 bit r/w Auto-Neg. Advertisement */ PHY_BCOM_AUNE_LP = 0x05,/* 16 bit r/o Link Part Ability Reg */ PHY_BCOM_AUNE_EXP = 0x06,/* 16 bit r/o Auto-Neg. Expansion Reg */ PHY_BCOM_NEPG = 0x07,/* 16 bit r/w Next Page Register */ PHY_BCOM_NEPG_LP = 0x08,/* 16 bit r/o Next Page Link Partner */ /* Broadcom-specific registers */ PHY_BCOM_1000T_CTRL = 0x09,/* 16 bit r/w 1000Base-T Control Reg */ PHY_BCOM_1000T_STAT = 0x0a,/* 16 bit r/o 1000Base-T Status Reg */ PHY_BCOM_EXT_STAT = 0x0f,/* 16 bit r/o Extended Status Reg */ PHY_BCOM_P_EXT_CTRL = 0x10,/* 16 bit r/w PHY Extended Ctrl Reg */ PHY_BCOM_P_EXT_STAT = 0x11,/* 16 bit r/o PHY Extended Stat Reg */ PHY_BCOM_RE_CTR = 0x12,/* 16 bit r/w Receive Error Counter */ PHY_BCOM_FC_CTR = 0x13,/* 16 bit r/w False Carrier Sense Cnt */ PHY_BCOM_RNO_CTR = 0x14,/* 16 bit r/w Receiver NOT_OK Cnt */ PHY_BCOM_AUX_CTRL = 0x18,/* 16 bit r/w Auxiliary Control Reg */ PHY_BCOM_AUX_STAT = 0x19,/* 16 bit r/o Auxiliary Stat Summary */ PHY_BCOM_INT_STAT = 0x1a,/* 16 bit r/o Interrupt Status Reg */ PHY_BCOM_INT_MASK = 0x1b,/* 16 bit r/w Interrupt Mask Reg */ }; /* * Marvel-PHY Registers, indirect addressed over GMAC */ enum { PHY_MARV_CTRL = 0x00,/* 16 bit r/w PHY Control Register */ PHY_MARV_STAT = 0x01,/* 16 bit r/o PHY Status Register */ PHY_MARV_ID0 = 0x02,/* 16 bit r/o PHY ID0 Register */ PHY_MARV_ID1 = 0x03,/* 16 bit r/o PHY ID1 Register */ PHY_MARV_AUNE_ADV = 0x04,/* 16 bit r/w Auto-Neg. Advertisement */ PHY_MARV_AUNE_LP = 0x05,/* 16 bit r/o Link Part Ability Reg */ PHY_MARV_AUNE_EXP = 0x06,/* 16 bit r/o Auto-Neg. Expansion Reg */ PHY_MARV_NEPG = 0x07,/* 16 bit r/w Next Page Register */ PHY_MARV_NEPG_LP = 0x08,/* 16 bit r/o Next Page Link Partner */ /* Marvel-specific registers */ PHY_MARV_1000T_CTRL = 0x09,/* 16 bit r/w 1000Base-T Control Reg */ PHY_MARV_1000T_STAT = 0x0a,/* 16 bit r/o 1000Base-T Status Reg */ PHY_MARV_EXT_STAT = 0x0f,/* 16 bit r/o Extended Status Reg */ PHY_MARV_PHY_CTRL = 0x10,/* 16 bit r/w PHY Specific Ctrl Reg */ PHY_MARV_PHY_STAT = 0x11,/* 16 bit r/o PHY Specific Stat Reg */ PHY_MARV_INT_MASK = 0x12,/* 16 bit r/w Interrupt Mask Reg */ PHY_MARV_INT_STAT = 0x13,/* 16 bit r/o Interrupt Status Reg */ PHY_MARV_EXT_CTRL = 0x14,/* 16 bit r/w Ext. PHY Specific Ctrl */ PHY_MARV_RXE_CNT = 0x15,/* 16 bit r/w Receive Error Counter */ PHY_MARV_EXT_ADR = 0x16,/* 16 bit r/w Ext. Ad. for Cable Diag. */ PHY_MARV_PORT_IRQ = 0x17,/* 16 bit r/o Port 0 IRQ (88E1111 only) */ PHY_MARV_LED_CTRL = 0x18,/* 16 bit r/w LED Control Reg */ PHY_MARV_LED_OVER = 0x19,/* 16 bit r/w Manual LED Override Reg */ PHY_MARV_EXT_CTRL_2 = 0x1a,/* 16 bit r/w Ext. PHY Specific Ctrl 2 */ PHY_MARV_EXT_P_STAT = 0x1b,/* 16 bit r/w Ext. PHY Spec. Stat Reg */ PHY_MARV_CABLE_DIAG = 0x1c,/* 16 bit r/o Cable Diagnostic Reg */ PHY_MARV_PAGE_ADDR = 0x1d,/* 16 bit r/w Extended Page Address Reg */ PHY_MARV_PAGE_DATA = 0x1e,/* 16 bit r/w Extended Page Data Reg */ /* for 10/100 Fast Ethernet PHY (88E3082 only) */ PHY_MARV_FE_LED_PAR = 0x16,/* 16 bit r/w LED Parallel Select Reg. */ PHY_MARV_FE_LED_SER = 0x17,/* 16 bit r/w LED Stream Select S. LED */ PHY_MARV_FE_VCT_TX = 0x1a,/* 16 bit r/w VCT Reg. for TXP/N Pins */ PHY_MARV_FE_VCT_RX = 0x1b,/* 16 bit r/o VCT Reg. for RXP/N Pins */ PHY_MARV_FE_SPEC_2 = 0x1c,/* 16 bit r/w Specific Control Reg. 2 */ }; enum { PHY_CT_RESET = 1<<15, /* Bit 15: (sc) clear all PHY related regs */ PHY_CT_LOOP = 1<<14, /* Bit 14: enable Loopback over PHY */ PHY_CT_SPS_LSB = 1<<13, /* Bit 13: Speed select, lower bit */ PHY_CT_ANE = 1<<12, /* Bit 12: Auto-Negotiation Enabled */ PHY_CT_PDOWN = 1<<11, /* Bit 11: Power Down Mode */ PHY_CT_ISOL = 1<<10, /* Bit 10: Isolate Mode */ PHY_CT_RE_CFG = 1<<9, /* Bit 9: (sc) Restart Auto-Negotiation */ PHY_CT_DUP_MD = 1<<8, /* Bit 8: Duplex Mode */ PHY_CT_COL_TST = 1<<7, /* Bit 7: Collision Test enabled */ PHY_CT_SPS_MSB = 1<<6, /* Bit 6: Speed select, upper bit */ }; enum { PHY_CT_SP1000 = PHY_CT_SPS_MSB, /* enable speed of 1000 Mbps */ PHY_CT_SP100 = PHY_CT_SPS_LSB, /* enable speed of 100 Mbps */ PHY_CT_SP10 = 0, /* enable speed of 10 Mbps */ }; enum { PHY_ST_EXT_ST = 1<<8, /* Bit 8: Extended Status Present */ PHY_ST_PRE_SUP = 1<<6, /* Bit 6: Preamble Suppression */ PHY_ST_AN_OVER = 1<<5, /* Bit 5: Auto-Negotiation Over */ PHY_ST_REM_FLT = 1<<4, /* Bit 4: Remote Fault Condition Occured */ PHY_ST_AN_CAP = 1<<3, /* Bit 3: Auto-Negotiation Capability */ PHY_ST_LSYNC = 1<<2, /* Bit 2: Link Synchronized */ PHY_ST_JAB_DET = 1<<1, /* Bit 1: Jabber Detected */ PHY_ST_EXT_REG = 1<<0, /* Bit 0: Extended Register available */ }; enum { PHY_I1_OUI_MSK = 0x3f<<10, /* Bit 15..10: Organization Unique ID */ PHY_I1_MOD_NUM = 0x3f<<4, /* Bit 9.. 4: Model Number */ PHY_I1_REV_MSK = 0xf, /* Bit 3.. 0: Revision Number */ }; /* different Broadcom PHY Ids */ enum { PHY_BCOM_ID1_A1 = 0x6041, PHY_BCOM_ID1_B2 = 0x6043, PHY_BCOM_ID1_C0 = 0x6044, PHY_BCOM_ID1_C5 = 0x6047, }; /* different Marvell PHY Ids */ enum { PHY_MARV_ID0_VAL= 0x0141, /* Marvell Unique Identifier */ PHY_MARV_ID1_B0 = 0x0C23, /* Yukon (PHY 88E1011) */ PHY_MARV_ID1_B2 = 0x0C25, /* Yukon-Plus (PHY 88E1011) */ PHY_MARV_ID1_C2 = 0x0CC2, /* Yukon-EC (PHY 88E1111) */ PHY_MARV_ID1_Y2 = 0x0C91, /* Yukon-2 (PHY 88E1112) */ }; /* Advertisement register bits */ enum { PHY_AN_NXT_PG = 1<<15, /* Bit 15: Request Next Page */ PHY_AN_ACK = 1<<14, /* Bit 14: (ro) Acknowledge Received */ PHY_AN_RF = 1<<13, /* Bit 13: Remote Fault Bits */ PHY_AN_PAUSE_ASYM = 1<<11,/* Bit 11: Try for asymmetric */ PHY_AN_PAUSE_CAP = 1<<10, /* Bit 10: Try for pause */ PHY_AN_100BASE4 = 1<<9, /* Bit 9: Try for 100mbps 4k packets */ PHY_AN_100FULL = 1<<8, /* Bit 8: Try for 100mbps full-duplex */ PHY_AN_100HALF = 1<<7, /* Bit 7: Try for 100mbps half-duplex */ PHY_AN_10FULL = 1<<6, /* Bit 6: Try for 10mbps full-duplex */ PHY_AN_10HALF = 1<<5, /* Bit 5: Try for 10mbps half-duplex */ PHY_AN_CSMA = 1<<0, /* Bit 0: Only selector supported */ PHY_AN_SEL = 0x1f, /* Bit 4..0: Selector Field, 00001=Ethernet*/ PHY_AN_FULL = PHY_AN_100FULL | PHY_AN_10FULL | PHY_AN_CSMA, PHY_AN_ALL = PHY_AN_10HALF | PHY_AN_10FULL | PHY_AN_100HALF | PHY_AN_100FULL, }; /* Xmac Specific */ enum { PHY_X_AN_NXT_PG = 1<<15, /* Bit 15: Request Next Page */ PHY_X_AN_ACK = 1<<14, /* Bit 14: (ro) Acknowledge Received */ PHY_X_AN_RFB = 3<<12,/* Bit 13..12: Remote Fault Bits */ PHY_X_AN_PAUSE = 3<<7,/* Bit 8.. 7: Pause Bits */ PHY_X_AN_HD = 1<<6, /* Bit 6: Half Duplex */ PHY_X_AN_FD = 1<<5, /* Bit 5: Full Duplex */ }; /* Pause Bits (PHY_X_AN_PAUSE and PHY_X_RS_PAUSE) encoding */ enum { PHY_X_P_NO_PAUSE= 0<<7,/* Bit 8..7: no Pause Mode */ PHY_X_P_SYM_MD = 1<<7, /* Bit 8..7: symmetric Pause Mode */ PHY_X_P_ASYM_MD = 2<<7,/* Bit 8..7: asymmetric Pause Mode */ PHY_X_P_BOTH_MD = 3<<7,/* Bit 8..7: both Pause Mode */ }; /***** PHY_XMAC_EXT_STAT 16 bit r/w Extended Status Register *****/ enum { PHY_X_EX_FD = 1<<15, /* Bit 15: Device Supports Full Duplex */ PHY_X_EX_HD = 1<<14, /* Bit 14: Device Supports Half Duplex */ }; /***** PHY_XMAC_RES_ABI 16 bit r/o PHY Resolved Ability *****/ enum { PHY_X_RS_PAUSE = 3<<7, /* Bit 8..7: selected Pause Mode */ PHY_X_RS_HD = 1<<6, /* Bit 6: Half Duplex Mode selected */ PHY_X_RS_FD = 1<<5, /* Bit 5: Full Duplex Mode selected */ PHY_X_RS_ABLMIS = 1<<4, /* Bit 4: duplex or pause cap mismatch */ PHY_X_RS_PAUMIS = 1<<3, /* Bit 3: pause capability mismatch */ }; /* Remote Fault Bits (PHY_X_AN_RFB) encoding */ enum { X_RFB_OK = 0<<12,/* Bit 13..12 No errors, Link OK */ X_RFB_LF = 1<<12,/* Bit 13..12 Link Failure */ X_RFB_OFF = 2<<12,/* Bit 13..12 Offline */ X_RFB_AN_ERR = 3<<12,/* Bit 13..12 Auto-Negotiation Error */ }; /* Broadcom-Specific */ /***** PHY_BCOM_1000T_CTRL 16 bit r/w 1000Base-T Control Reg *****/ enum { PHY_B_1000C_TEST = 7<<13,/* Bit 15..13: Test Modes */ PHY_B_1000C_MSE = 1<<12, /* Bit 12: Master/Slave Enable */ PHY_B_1000C_MSC = 1<<11, /* Bit 11: M/S Configuration */ PHY_B_1000C_RD = 1<<10, /* Bit 10: Repeater/DTE */ PHY_B_1000C_AFD = 1<<9, /* Bit 9: Advertise Full Duplex */ PHY_B_1000C_AHD = 1<<8, /* Bit 8: Advertise Half Duplex */ }; /***** PHY_BCOM_1000T_STAT 16 bit r/o 1000Base-T Status Reg *****/ /***** PHY_MARV_1000T_STAT 16 bit r/o 1000Base-T Status Reg *****/ enum { PHY_B_1000S_MSF = 1<<15, /* Bit 15: Master/Slave Fault */ PHY_B_1000S_MSR = 1<<14, /* Bit 14: Master/Slave Result */ PHY_B_1000S_LRS = 1<<13, /* Bit 13: Local Receiver Status */ PHY_B_1000S_RRS = 1<<12, /* Bit 12: Remote Receiver Status */ PHY_B_1000S_LP_FD = 1<<11, /* Bit 11: Link Partner can FD */ PHY_B_1000S_LP_HD = 1<<10, /* Bit 10: Link Partner can HD */ /* Bit 9..8: reserved */ PHY_B_1000S_IEC = 0xff, /* Bit 7..0: Idle Error Count */ }; /***** PHY_BCOM_EXT_STAT 16 bit r/o Extended Status Register *****/ enum { PHY_B_ES_X_FD_CAP = 1<<15, /* Bit 15: 1000Base-X FD capable */ PHY_B_ES_X_HD_CAP = 1<<14, /* Bit 14: 1000Base-X HD capable */ PHY_B_ES_T_FD_CAP = 1<<13, /* Bit 13: 1000Base-T FD capable */ PHY_B_ES_T_HD_CAP = 1<<12, /* Bit 12: 1000Base-T HD capable */ }; /***** PHY_BCOM_P_EXT_CTRL 16 bit r/w PHY Extended Control Reg *****/ enum { PHY_B_PEC_MAC_PHY = 1<<15, /* Bit 15: 10BIT/GMI-Interface */ PHY_B_PEC_DIS_CROSS = 1<<14, /* Bit 14: Disable MDI Crossover */ PHY_B_PEC_TX_DIS = 1<<13, /* Bit 13: Tx output Disabled */ PHY_B_PEC_INT_DIS = 1<<12, /* Bit 12: Interrupts Disabled */ PHY_B_PEC_F_INT = 1<<11, /* Bit 11: Force Interrupt */ PHY_B_PEC_BY_45 = 1<<10, /* Bit 10: Bypass 4B5B-Decoder */ PHY_B_PEC_BY_SCR = 1<<9, /* Bit 9: Bypass Scrambler */ PHY_B_PEC_BY_MLT3 = 1<<8, /* Bit 8: Bypass MLT3 Encoder */ PHY_B_PEC_BY_RXA = 1<<7, /* Bit 7: Bypass Rx Alignm. */ PHY_B_PEC_RES_SCR = 1<<6, /* Bit 6: Reset Scrambler */ PHY_B_PEC_EN_LTR = 1<<5, /* Bit 5: Ena LED Traffic Mode */ PHY_B_PEC_LED_ON = 1<<4, /* Bit 4: Force LED's on */ PHY_B_PEC_LED_OFF = 1<<3, /* Bit 3: Force LED's off */ PHY_B_PEC_EX_IPG = 1<<2, /* Bit 2: Extend Tx IPG Mode */ PHY_B_PEC_3_LED = 1<<1, /* Bit 1: Three Link LED mode */ PHY_B_PEC_HIGH_LA = 1<<0, /* Bit 0: GMII FIFO Elasticy */ }; /***** PHY_BCOM_P_EXT_STAT 16 bit r/o PHY Extended Status Reg *****/ enum { PHY_B_PES_CROSS_STAT = 1<<13, /* Bit 13: MDI Crossover Status */ PHY_B_PES_INT_STAT = 1<<12, /* Bit 12: Interrupt Status */ PHY_B_PES_RRS = 1<<11, /* Bit 11: Remote Receiver Stat. */ PHY_B_PES_LRS = 1<<10, /* Bit 10: Local Receiver Stat. */ PHY_B_PES_LOCKED = 1<<9, /* Bit 9: Locked */ PHY_B_PES_LS = 1<<8, /* Bit 8: Link Status */ PHY_B_PES_RF = 1<<7, /* Bit 7: Remote Fault */ PHY_B_PES_CE_ER = 1<<6, /* Bit 6: Carrier Ext Error */ PHY_B_PES_BAD_SSD = 1<<5, /* Bit 5: Bad SSD */ PHY_B_PES_BAD_ESD = 1<<4, /* Bit 4: Bad ESD */ PHY_B_PES_RX_ER = 1<<3, /* Bit 3: Receive Error */ PHY_B_PES_TX_ER = 1<<2, /* Bit 2: Transmit Error */ PHY_B_PES_LOCK_ER = 1<<1, /* Bit 1: Lock Error */ PHY_B_PES_MLT3_ER = 1<<0, /* Bit 0: MLT3 code Error */ }; /* PHY_BCOM_AUNE_ADV 16 bit r/w Auto-Negotiation Advertisement *****/ /* PHY_BCOM_AUNE_LP 16 bit r/o Link Partner Ability Reg *****/ enum { PHY_B_AN_RF = 1<<13, /* Bit 13: Remote Fault */ PHY_B_AN_ASP = 1<<11, /* Bit 11: Asymmetric Pause */ PHY_B_AN_PC = 1<<10, /* Bit 10: Pause Capable */ }; /***** PHY_BCOM_FC_CTR 16 bit r/w False Carrier Counter *****/ enum { PHY_B_FC_CTR = 0xff, /* Bit 7..0: False Carrier Counter */ /***** PHY_BCOM_RNO_CTR 16 bit r/w Receive NOT_OK Counter *****/ PHY_B_RC_LOC_MSK = 0xff00, /* Bit 15..8: Local Rx NOT_OK cnt */ PHY_B_RC_REM_MSK = 0x00ff, /* Bit 7..0: Remote Rx NOT_OK cnt */ /***** PHY_BCOM_AUX_CTRL 16 bit r/w Auxiliary Control Reg *****/ PHY_B_AC_L_SQE = 1<<15, /* Bit 15: Low Squelch */ PHY_B_AC_LONG_PACK = 1<<14, /* Bit 14: Rx Long Packets */ PHY_B_AC_ER_CTRL = 3<<12,/* Bit 13..12: Edgerate Control */ /* Bit 11: reserved */ PHY_B_AC_TX_TST = 1<<10, /* Bit 10: Tx test bit, always 1 */ /* Bit 9.. 8: reserved */ PHY_B_AC_DIS_PRF = 1<<7, /* Bit 7: dis part resp filter */ /* Bit 6: reserved */ PHY_B_AC_DIS_PM = 1<<5, /* Bit 5: dis power management */ /* Bit 4: reserved */ PHY_B_AC_DIAG = 1<<3, /* Bit 3: Diagnostic Mode */ }; /***** PHY_BCOM_AUX_STAT 16 bit r/o Auxiliary Status Reg *****/ enum { PHY_B_AS_AN_C = 1<<15, /* Bit 15: AutoNeg complete */ PHY_B_AS_AN_CA = 1<<14, /* Bit 14: AN Complete Ack */ PHY_B_AS_ANACK_D = 1<<13, /* Bit 13: AN Ack Detect */ PHY_B_AS_ANAB_D = 1<<12, /* Bit 12: AN Ability Detect */ PHY_B_AS_NPW = 1<<11, /* Bit 11: AN Next Page Wait */ PHY_B_AS_AN_RES_MSK = 7<<8,/* Bit 10..8: AN HDC */ PHY_B_AS_PDF = 1<<7, /* Bit 7: Parallel Detect. Fault */ PHY_B_AS_RF = 1<<6, /* Bit 6: Remote Fault */ PHY_B_AS_ANP_R = 1<<5, /* Bit 5: AN Page Received */ PHY_B_AS_LP_ANAB = 1<<4, /* Bit 4: LP AN Ability */ PHY_B_AS_LP_NPAB = 1<<3, /* Bit 3: LP Next Page Ability */ PHY_B_AS_LS = 1<<2, /* Bit 2: Link Status */ PHY_B_AS_PRR = 1<<1, /* Bit 1: Pause Resolution-Rx */ PHY_B_AS_PRT = 1<<0, /* Bit 0: Pause Resolution-Tx */ }; #define PHY_B_AS_PAUSE_MSK (PHY_B_AS_PRR | PHY_B_AS_PRT) /***** PHY_BCOM_INT_STAT 16 bit r/o Interrupt Status Reg *****/ /***** PHY_BCOM_INT_MASK 16 bit r/w Interrupt Mask Reg *****/ enum { PHY_B_IS_PSE = 1<<14, /* Bit 14: Pair Swap Error */ PHY_B_IS_MDXI_SC = 1<<13, /* Bit 13: MDIX Status Change */ PHY_B_IS_HCT = 1<<12, /* Bit 12: counter above 32k */ PHY_B_IS_LCT = 1<<11, /* Bit 11: counter above 128 */ PHY_B_IS_AN_PR = 1<<10, /* Bit 10: Page Received */ PHY_B_IS_NO_HDCL = 1<<9, /* Bit 9: No HCD Link */ PHY_B_IS_NO_HDC = 1<<8, /* Bit 8: No HCD */ PHY_B_IS_NEG_USHDC = 1<<7, /* Bit 7: Negotiated Unsup. HCD */ PHY_B_IS_SCR_S_ER = 1<<6, /* Bit 6: Scrambler Sync Error */ PHY_B_IS_RRS_CHANGE = 1<<5, /* Bit 5: Remote Rx Stat Change */ PHY_B_IS_LRS_CHANGE = 1<<4, /* Bit 4: Local Rx Stat Change */ PHY_B_IS_DUP_CHANGE = 1<<3, /* Bit 3: Duplex Mode Change */ PHY_B_IS_LSP_CHANGE = 1<<2, /* Bit 2: Link Speed Change */ PHY_B_IS_LST_CHANGE = 1<<1, /* Bit 1: Link Status Changed */ PHY_B_IS_CRC_ER = 1<<0, /* Bit 0: CRC Error */ }; #define PHY_B_DEF_MSK \ (~(PHY_B_IS_PSE | PHY_B_IS_AN_PR | PHY_B_IS_DUP_CHANGE | \ PHY_B_IS_LSP_CHANGE | PHY_B_IS_LST_CHANGE)) /* Pause Bits (PHY_B_AN_ASP and PHY_B_AN_PC) encoding */ enum { PHY_B_P_NO_PAUSE = 0<<10,/* Bit 11..10: no Pause Mode */ PHY_B_P_SYM_MD = 1<<10, /* Bit 11..10: symmetric Pause Mode */ PHY_B_P_ASYM_MD = 2<<10,/* Bit 11..10: asymmetric Pause Mode */ PHY_B_P_BOTH_MD = 3<<10,/* Bit 11..10: both Pause Mode */ }; /* * Resolved Duplex mode and Capabilities (Aux Status Summary Reg) */ enum { PHY_B_RES_1000FD = 7<<8,/* Bit 10..8: 1000Base-T Full Dup. */ PHY_B_RES_1000HD = 6<<8,/* Bit 10..8: 1000Base-T Half Dup. */ }; /** Marvell-Specific */ enum { PHY_M_AN_NXT_PG = 1<<15, /* Request Next Page */ PHY_M_AN_ACK = 1<<14, /* (ro) Acknowledge Received */