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|
/*
* MPC8548 CDS Device Tree Source
*
* Copyright 2006, 2008 Freescale Semiconductor Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
/dts-v1/;
/ {
model = "MPC8548CDS";
compatible = "MPC8548CDS", "MPC85xxCDS";
#address-cells = <1>;
#size-cells = <1>;
aliases {
ethernet0 = &enet0;
ethernet1 = &enet1;
/*
ethernet2 = &enet2;
ethernet3 = &enet3;
*/
serial0 = &serial0;
serial1 = &serial1;
pci0 = &pci0;
pci1 = &pci1;
pci2 = &pci2;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
PowerPC,8548@0 {
device_type = "cpu";
reg = <0x0>;
d-cache-line-size = <32>; // 32 bytes
i-cache-line-size = <32>; // 32 bytes
d-cache-size = <0x8000>; // L1, 32K
i-cache-size = <0x8000>; // L1, 32K
timebase-frequency = <0>; // 33 MHz, from uboot
bus-frequency = <0>; // 166 MHz
clock-frequency = <0>; // 825 MHz, from uboot
};
};
memory {
device_type = "memory";
reg = <0x0 0x8000000>; // 128M at 0x0
};
soc8548@e0000000 {
#address-cells = <1>;
#size-cells = <1>;
device_type = "soc";
ranges = <0x0 0xe0000000 0x100000>;
reg = <0xe0000000 0x1000>; // CCSRBAR
bus-frequency = <0>;
memory-controller@2000 {
compatible = "fsl,8548-memory-controller";
reg = <0x2000 0x1000>;
interrupt-parent = <&mpic>;
interrupts = <18 2>;
};
l2-cache-controller@20000 {
compatible = "fsl,8548-l2-cache-controller";
reg = <0x20000 0x1000>;
cache-line-size = <32>; // 32 bytes
cache-size = <0x80000>; // L2, 512K
interrupt-parent = <&mpic>;
interrupts = <16 2>;
};
i2c@3000 {
#address-cells = <1>;
#size-cells = <0>;
cell-index = <0>;
compatible = "fsl-i2c";
reg = <0x3000 0x100>;
interrupts = <43 2>;
interrupt-parent = <&mpic>;
dfsrr;
};
i2c@3100 {
#address-cells = <1>;
#size-cells = <0>;
cell-index = <1>;
compatible = "fsl-i2c";
reg = <0x3100 0x100>;
interrupts = <43 2>;
interrupt-parent = <&mpic>;
dfsrr;
};
mdio@24520 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,gianfar-mdio";
reg = <0x24520 0x20>;
phy0: ethernet-phy@0 {
interrupt-parent = <&mpic>;
interrupts = <5 1>;
reg = <0x0>;
device_type = "ethernet-phy";
};
phy1: ethernet-phy@1 {
interrupt-parent = <&mpic>;
interrupts = <5 1>;
reg = <0x1>;
device_type = "ethernet-phy";
};
phy2: ethernet-phy@2 {
interrupt-parent = <&mpic>;
interrupts = <5 1>;
reg = <0x2>;
device_type = "ethernet-phy";
};
phy3: ethernet-phy@3 {
interrupt-parent = <&mpic>;
interrupts = <5 1>;
reg = <0x3>;
device_type = "ethernet-phy";
};
};
enet0: ethernet@24000 {
cell-index = <0>;
device_type = "network";
model = "eTSEC";
compatible = "gianfar";
reg = <0x24000 0x1000>;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <29 2 30 2 34 2>;
interrupt-parent = <&mpic>;
phy-handle = <&phy0>;
};
enet1: ethernet@25000 {
cell-index = <1>;
device_type = "network";
model = "eTSEC";
compatible = "gianfar";
reg = <0x25000 0x1000>;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <35 2 36 2 40 2>;
interrupt-parent = <&mpic>;
phy-handle = <&phy1>;
};
/* eTSEC 3/4 are currently broken
enet2: ethernet@26000 {
cell-index = <2>;
device_type = "network";
model = "eTSEC";
compatible = "gianfar";
reg = <0x26000 0x1000>;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <31 2 32 2 33 2>;
interrupt-parent = <&mpic>;
phy-handle = <&phy2>;
};
enet3: ethernet@27000 {
cell-index = <3>;
device_type = "network";
model = "eTSEC";
compatible = "gianfar";
reg = <0x27000 0x1000>;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <37 2 38 2 39 2>;
interrupt-parent = <&mpic>;
phy-handle = <&phy3>;
};
*/
serial0: serial@4500 {
cell-index = <0>;
device_type = "serial";
compatible = "ns16550";
reg = <0x4500 0x100>; // reg base, size
clock-frequency = <0>; // should we fill in in uboot?
interrupts = <42 2>;
interrupt-parent = <&mpic>;
};
serial1: serial@4600 {
cell-index = <1>;
device_type = "serial";
compatible = "ns16550";
reg = <0x4600 0x100>; // reg base, size
clock-frequency = <0>; // should we fill in in uboot?
interrupts = <42 2>;
interrupt-parent = <&mpic>;
};
global-utilities@e0000 { //global utilities reg
compatible = "fsl,mpc8548-guts";
reg = <0xe0000 0x1000>;
fsl,has-rstcr;
};
mpic: pic@40000 {
clock-frequency = <0>;
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <2>;
reg = <0x40000 0x40000>;
compatible = "chrp,open-pic";
device_type = "open-pic";
big-endian;
};
};
pci0: pci@e0008000 {
cell-index = <0>;
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
interrupt-map = <
/* IDSEL 0x4 (PCIX Slot 2) */
0x2000 0x0 0x0 0x1 &mpic 0x0 0x1
0x2000 0x0 0x0 0x2 &mpic 0x1 0x1
0x2000 0x0 0x0 0x3 &mpic 0x2 0x1
0x2000 0x0 0x0 0x4 &mpic 0x3 0x1
/* IDSEL 0x5 (PCIX Slot 3) */
0x2800 0x0 0x0 0x1 &mpic 0x1 0x1
0x2800 0x0 0x0 0x2 &mpic 0x2 0x1
0x2800 0x0 0x0 0x3 &mpic 0x3 0x1
0x2800 0x0 0x0 0x4 &mpic 0x0 0x1
/* IDSEL 0x6 (PCIX Slot 4) */
0x3000 0x0 0x0 0x1 &mpic 0x2 0x1
0x3000 0x0 0x0 0x2 &mpic 0x3 0x1
0x3000 0x0 0x0 0x3 &mpic 0x0 0x1
0x3000 0x0 0x0 0x4 &mpic 0x1 0x1
/* IDSEL 0x8 (PCIX Slot 5) */
0x4000 0x0 0x0 0x1 &mpic 0x0 0x1
0x4000 0x0 0x0 0x2 &mpic 0x1 0x1
0x4000 0x0 0x0 0x3 &mpic 0x2 0x1
0x4000 0x0 0x0 0x4 &mpic 0x3 0x1
/* IDSEL 0xC (Tsi310 bridge) */
0x6000 0x0 0x0 0x1 &mpic 0x0 0x1
0x6000 0x0 0x0 0x2 &mpic 0x1 0x1
0x6000 0x0 0x0 0x3 &mpic 0x2 0x1
0x6000 0x0 0x0 0x4 &mpic 0x3 0x1
/* IDSEL 0x14 (Slot 2) */
0xa000 0x0 0x0 0x1 &mpic 0x0 0x1
0xa000 0x0 0x0 0x2 &mpic 0x1 0x1
0xa000 0x0 0x0 0x3 &mpic 0x2 0x1
0xa000 0x0 0x0 0x4 &mpic 0x3 0x1
/* IDSEL 0x15 (Slot 3) */
0xa800 0x0 0x0 0x1 &mpic 0x1 0x1
0xa800 0x0 0x0 0x2 &mpic 0x2 0x1
0xa800 0x0 0x0 0x3 &mpic 0x3 0x1
0xa800 0x0 0x0 0x4 &mpic 0x0 0x1
/* IDSEL 0x16 (Slot 4) */
0xb000 0x0 0x0 0x1 &mpic 0x2 0x1
0xb000 0x0 0x0 0x2 &mpic 0x3 0x1
0xb000 0x0 0x0 0x3 &mpic 0x0 0x1
0xb000 0x0 0x0 0x4 &mpic 0x1 0x1
/* IDSEL 0x18 (Slot 5) */
0xc000 0x0 0x0 0x1 &mpic 0x0 0x1
0xc000 0x0 0x0 0x2 &mpic 0x1 0x1
0xc000 0x0 0x0 0x3 &mpic 0x2 0x1
0xc000 0x0 0x0 0x4 &mpic 0x3 0x1
/* IDSEL 0x1C (Tsi310 bridge PCI primary) */
0xe000 0x0 0x0 0x1 &mpic 0x0 0x1
0xe000 0x0 0x0 0x2 &mpic 0x1 0x1
0xe000 0x0 0x0 0x3 &mpic 0x2 0x1
0xe000 0x0 0x0 0x4 &mpic 0x3 0x1>;
interrupt-parent = <&mpic>;
interrupts = <24 2>;
bus-range = <0 0>;
ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x10000000
0x1000000 0x0 0x0 0xe2000000 0x0 0x800000>;
clock-frequency = <66666666>;
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
reg = <0xe0008000 0x1000>;
compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
device_type = "pci";
pci_bridge@1c {
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
interrupt-map = <
/* IDSEL 0x00 (PrPMC Site) */
0000 0x0 0x0 0x1 &mpic 0x0 0x1
0000 0x0 0x0 0x2 &mpic 0x1 0x1
0000 0x0 0x0 0x3 &mpic 0x2 0x1
0000 0x0 0x0 0x4 &mpic 0x3 0x1
/* IDSEL 0x04 (VIA chip) */
0x2000 0x0 0x0 0x1 &mpic 0x0 0x1
0x2000 0x0 0x0 0x2 &mpic 0x1 0x1
0x2000 0x0 0x0 0x3 &mpic 0x2 0x1
0x2000 0x0 0x0 0x4 &mpic 0x3 0x1
/* IDSEL 0x05 (8139) */
0x2800 0x0 0x0 0x1 &mpic 0x1 0x1
/* IDSEL 0x06 (Slot 6) */
0x3000 0x0 0x0 0x1 &mpic 0x2 0x1
0x3000 0x0 0x0 0x2 &mpic 0x3 0x1
0x3000 0x0 0x0 0x3 &mpic 0x0 0x1
0x3000 0x0 0x0 0x4 &mpic 0x1 0x1
/* IDESL 0x07 (Slot 7) */
0x3800 0x0 0x0 0x1 &mpic 0x3 0x1
0x3800 0x0 0x0 0x2 &mpic 0x0 0x1
0x3800 0x0 0x0 0x3 &mpic 0x1 0x1
0x3800 0x0 0x0 0x4 &mpic 0x2 0x1>;
reg = <0xe000 0x0 0x0 0x0 0x0>;
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
ranges = <0x2000000 0x0 0x80000000
0x2000000 0x0 0x80000000
0x0 0x20000000
0x1000000 0x0 0x0
0x1000000 0x0 0x0
0x0 0x80000>;
clock-frequency = <33333333>;
isa@4 {
device_type = "isa";
#interrupt-cells = <2>;
#size-cells = <1>;
#address-cells = <2>;
reg = <0x2000 0x0 0x0 0x0 0x0>;
ranges = <0x1 0x0 0x1000000 0x0 0x0 0x1000>;
interrupt-parent = <&i8259>;
i8259: interrupt-controller@20 {
interrupt-controller;
device_type = "interrupt-controller";
reg = <0x1 0x20 0x2
0x1 0xa0 0x2
0x1 0x4d0 0x2>;
#address-cells = <0>;
#interrupt-cells = <2>;
compatible = "chrp,iic";
interrupts = <0 1>;
interrupt-parent = <&mpic>;
};
rtc@70 {
compatible = "pnpPNP,b00";
reg = <0x1 0x70 0x2>;
};
};
};
};
pci1: pci@e0009000 {
cell-index = <1>;
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
interrupt-map = <
/* IDSEL 0x15 */
0xa800 0x0 0x0 0x1 &mpic 0xb 0x1
0xa800 0x0 0x0 0x2 &mpic 0x1 0x1
0xa800 0x0 0x0 0x3 &mpic 0x2 0x1
0xa800 0x0 0x0 0x4 &mpic 0x3 0x1>;
interrupt-parent = <&mpic>;
interrupts = <25 2>;
bus-range = <0 0>;
ranges = <0x2000000 0x0 0x90000000 0x90000000 0x0 0x10000000
0x1000000 0x0 0x0 0xe2800000 0x0 0x800000>;
clock-frequency = <66666666>;
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
reg = <0xe0009000 0x1000>;
compatible = "fsl,mpc8540-pci";
device_type = "pci";
};
pci2: pcie@e000a000 {
cell-index = <2>;
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
interrupt-map = <
/* IDSEL 0x0 (PEX) */
00000 0x0 0x0 0x1 &mpic 0x0 0x1
00000 0x0 0x0 0x2 &mpic 0x1 0x1
00000 0x0 0x0 0x3 &mpic 0x2 0x1
00000 0x0 0x0 0x4 &mpic 0x3 0x1>;
interrupt-parent = <&mpic>;
interrupts = <26 2>;
bus-range = <0 255>;
ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000
0x1000000 0x0 0x0 0xe3000000 0x0 0x100000>;
clock-frequency = <33333333>;
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
reg = <0xe000a000 0x1000>;
compatible = "fsl,mpc8548-pcie";
device_type = "pci";
pcie@0 {
reg = <0x0 0x0 0x0 0x0 0x0>;
#size-cells = <2>;
#address-cells = <3>;
device_type = "pci";
ranges = <0x2000000 0x0 0xa0000000
0x2000000 0x0 0xa0000000
0x0 0x20000000
0x1000000 0x0 0x0
0x1000000 0x0 0x0
0x0 0x100000>;
};
};
};
|
