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path: root/arch/arm/mach-pxa/trizeps4.c
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/*
 *  linux/arch/arm/mach-pxa/trizeps4.c
 *
 *  Support for the Keith und Koep Trizeps4 Module Platform.
 *
 *  Author:	Jürgen Schindele
 *  Created:	20 02, 2006
 *  Copyright:	Jürgen Schindele
 *
 *  This program is free software; you can redistribute it and/or modify
 *  it under the terms of the GNU General Public License version 2 as
 *  published by the Free Software Foundation.
 */

#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/platform_device.h>
#include <linux/sysdev.h>
#include <linux/interrupt.h>
#include <linux/sched.h>
#include <linux/bitops.h>
#include <linux/fb.h>
#include <linux/ioport.h>
#include <linux/delay.h>
#include <linux/serial_8250.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/physmap.h>
#include <linux/mtd/partitions.h>

#include <asm/types.h>
#include <asm/setup.h>
#include <asm/memory.h>
#include <asm/mach-types.h>
#include <asm/hardware.h>
#include <asm/irq.h>
#include <asm/sizes.h>

#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/mach/irq.h>
#include <asm/mach/flash.h>

#include <asm/arch/pxa-regs.h>
#include <asm/arch/pxa2xx-regs.h>
#include <asm/arch/pxa2xx-gpio.h>
#include <asm/arch/trizeps4.h>
#include <asm/arch/audio.h>
#include <asm/arch/pxafb.h>
#include <asm/arch/mmc.h>
#include <asm/arch/irda.h>
#include <asm/arch/ohci.h>

#include "generic.h"
#include "devices.h"

/********************************************************************************************
 * ONBOARD FLASH
 ********************************************************************************************/
static struct mtd_partition trizeps4_partitions[] = {
	{
		.name =		"Bootloader",
		.offset =	0x00000000,
		.size =		0x00040000,
		.mask_flags =	MTD_WRITEABLE  /* force read-only */
	},{
		.name =		"Backup",
		.offset =	0x00040000,
		.size =		0x00040000,
	},{
		.name =		"Image",
		.offset =	0x00080000,
		.size =		0x01080000,
	},{
		.name =		"IPSM",
		.offset =	0x01100000,
		.size =		0x00e00000,
	},{
		.name =		"Registry",
		.offset =	0x01f00000,
		.size =		MTDPART_SIZ_FULL,
	}
};

static struct physmap_flash_data trizeps4_flash_data[] = {
	{
		.width		= 4,			/* bankwidth in bytes */
		.parts		= trizeps4_partitions,
		.nr_parts	= ARRAY_SIZE(trizeps4_partitions)
	}
};

static struct resource flash_resource = {
	.start	= PXA_CS0_PHYS,
	.end	= PXA_CS0_PHYS + SZ_32M - 1,
	.flags	= IORESOURCE_MEM,
};

static struct platform_device flash_device = {
	.name		= "physmap-flash",
	.id		= 0,
	.dev = {
		.platform_data = trizeps4_flash_data,
	},
	.resource = &flash_resource,
	.num_resources = 1,
};

/********************************************************************************************
 * DAVICOM DM9000 Ethernet
 ********************************************************************************************/
static struct resource dm9000_resources[] = {
	[0] = {
		.start	= TRIZEPS4_ETH_PHYS+0x300,
		.end	= TRIZEPS4_ETH_PHYS+0x400-1,
		.flags	= IORESOURCE_MEM,
	},
	[1] = {
		.start	= TRIZEPS4_ETH_PHYS+0x8300,
		.end	= TRIZEPS4_ETH_PHYS+0x8400-1,
		.flags	= IORESOURCE_MEM,
	},
	[2] = {
		.start	= TRIZEPS4_ETH_IRQ,
		.end	= TRIZEPS4_ETH_IRQ,
		.flags	= (IORESOURCE_IRQ | IRQT_RISING),
	},
};

static struct platform_device dm9000_device = {
	.name		= "dm9000",
	.id		= -1,
	.num_resources	= ARRAY_SIZE(dm9000_resources),
	.resource	= dm9000_resources,
};

/********************************************************************************************
 * PXA270 serial ports
 ********************************************************************************************/
static struct plat_serial8250_port tri_serial_ports[] = {
#ifdef CONFIG_SERIAL_PXA
	/* this uses the own PXA driver */
	{
		0,
	},
#else
	/* this uses the generic 8520 driver */
	[0] = {
		.membase	= (void *)&FFUART,
		.irq		= IRQ_FFUART,
		.flags		= UPF_BOOT_AUTOCONF,
		.iotype		= UPIO_MEM32,
		.regshift	= 2,
		.uartclk	= (921600*16),
	},
	[1] = {
		.membase	= (void *)&BTUART,
		.irq		= IRQ_BTUART,
		.flags		= UPF_BOOT_AUTOCONF,
		.iotype		= UPIO_MEM32,
		.regshift	= 2,
		.uartclk	= (921600*16),
	},
	{
		0,
	},
#endif
};

static struct platform_device uart_devices = {
	.name		= "serial8250",
	.id		= 0,
	.dev		= {
		.platform_data	= tri_serial_ports,
	},
	.num_resources	= 0,
	.resource	= NULL,
};

static struct platform_device * trizeps4_devices[] __initdata = {
	&flash_device,
	&uart_devices,
	&dm9000_device,
};

#ifdef CONFIG_MACH_TRIZEPS4_CONXS
static short trizeps_conxs_bcr;

/* PCCARD power switching supports only 3,3V */
void board_pcmcia_power(int power)
{
	if (power) {
		/* switch power on, put in reset and enable buffers */
		trizeps_conxs_bcr |= power;
		trizeps_conxs_bcr |= ConXS_BCR_CF_RESET;
		trizeps_conxs_bcr &= ~(ConXS_BCR_CF_BUF_EN);
		ConXS_BCR = trizeps_conxs_bcr;
		/* wait a little */
		udelay(2000);
		/* take reset away */
		trizeps_conxs_bcr &= ~(ConXS_BCR_CF_RESET);
		ConXS_BCR = trizeps_conxs_bcr;
		udelay(2000);
	} else {
		/* put in reset */
		trizeps_conxs_bcr |= ConXS_BCR_CF_RESET;
		ConXS_BCR = trizeps_conxs_bcr;
		udelay(1000);
		/* switch power off */
		trizeps_conxs_bcr &= ~(0xf);
		ConXS_BCR = trizeps_conxs_bcr;

	}
	pr_debug("%s: o%s 0x%x\n", __func__, power ? "n": "ff", trizeps_conxs_bcr);
}

/* backlight power switching for LCD panel */
static void board_backlight_power(int on)
{
	if (on) {
		trizeps_conxs_bcr |= ConXS_BCR_L_DISP;
	} else {
		trizeps_conxs_bcr &= ~ConXS_BCR_L_DISP;
	}
	pr_debug("%s: o%s 0x%x\n", __func__, on ? "n" : "ff", trizeps_conxs_bcr);
	ConXS_BCR = trizeps_conxs_bcr;
}

/* Powersupply for MMC/SD cardslot */
static void board_mci_power(struct device *dev, unsigned int vdd)
{
	struct pxamci_platform_data* p_d = dev->platform_data;

	if (( 1 << vdd) & p_d->ocr_mask) {
		pr_debug("%s: on\n", __func__);
		/* FIXME fill in values here */
	} else {
		pr_debug("%s: off\n", __func__);
		/* FIXME fill in values here */
	}
}

static short trizeps_conxs_ircr;

/* Switch modes and Power for IRDA receiver */
static void board_irda_mode(struct device *dev, int mode)
{
	unsigned long flags;

	local_irq_save(flags);
	if (mode & IR_SIRMODE) {
		/* Slow mode */
		trizeps_conxs_ircr &= ~ConXS_IRCR_MODE;
	} else if (mode & IR_FIRMODE) {
		/* Fast mode */
		trizeps_conxs_ircr |= ConXS_IRCR_MODE;
	}
	if (mode & IR_OFF) {
		trizeps_conxs_ircr |= ConXS_IRCR_SD;
	} else {
		trizeps_conxs_ircr &= ~ConXS_IRCR_SD;
	}
	/* FIXME write values to register */
	local_irq_restore(flags);
}

#else
/* for other baseboards define dummies */
void board_pcmcia_power(int power)	{;}
#define board_backlight_power		NULL
#define board_mci_power			NULL
#define board_irda_mode			NULL

#endif		/* CONFIG_MACH_TRIZEPS4_CONXS */
EXPORT_SYMBOL(board_pcmcia_power);

static int trizeps4_mci_init(struct device *dev, irq_handler_t mci_detect_int, void *data)
{
	int err;
	/* setup GPIO for PXA27x MMC controller */
	pxa_gpio_mode(GPIO32_MMCCLK_MD);
	pxa_gpio_mode(GPIO112_MMCCMD_MD);
	pxa_gpio_mode(GPIO92_MMCDAT0_MD);
	pxa_gpio_mode(GPIO109_MMCDAT1_MD);
	pxa_gpio_mode(GPIO110_MMCDAT2_MD);
	pxa_gpio_mode(GPIO111_MMCDAT3_MD);

	pxa_gpio_mode(GPIO_MMC_DET | GPIO_IN);

	err = request_irq(TRIZEPS4_MMC_IRQ, mci_detect_int,
			  IRQF_DISABLED | IRQF_TRIGGER_RISING,
			  "MMC card detect", data);
	if (err)
		printk(KERN_ERR "trizeps4_mci_init: MMC/SD: can't request MMC card detect IRQ\n");

	return err;
}

static void trizeps4_mci_exit(struct device *dev, void *data)
{
	free_irq(TRIZEPS4_MMC_IRQ, data);
}

static struct pxamci_platform_data trizeps4_mci_platform_data = {
	.ocr_mask	= MMC_VDD_32_33|MMC_VDD_33_34,
	.init 		= trizeps4_mci_init,
	.exit		= trizeps4_mci_exit,
	.setpower 	= board_mci_power,
};

static struct pxaficp_platform_data trizeps4_ficp_platform_data = {
	.transceiver_cap  = IR_SIRMODE | IR_FIRMODE | IR_OFF,
	.transceiver_mode = board_irda_mode,
};

static int trizeps4_ohci_init(struct device *dev)
{
	/* setup Port1 GPIO pin. */
	pxa_gpio_mode( 88 | GPIO_ALT_FN_1_IN);	/* USBHPWR1 */
	pxa_gpio_mode( 89 | GPIO_ALT_FN_2_OUT);	/* USBHPEN1 */

	/* Set the Power Control Polarity Low and Power Sense
	   Polarity Low to active low. */
	UHCHR = (UHCHR | UHCHR_PCPL | UHCHR_PSPL) &
		~(UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSEP3 | UHCHR_SSE);

	return 0;
}

static void trizeps4_ohci_exit(struct device *dev)
{
	;
}

static struct pxaohci_platform_data trizeps4_ohci_platform_data = {
	.port_mode	= PMM_PERPORT_MODE,
	.init		= trizeps4_ohci_init,
	.exit		= trizeps4_ohci_exit,
};

static struct map_desc trizeps4_io_desc[] __initdata = {
	{ 	/* ConXS CFSR */
		.virtual	= TRIZEPS4_CFSR_VIRT,
		.pfn		= __phys_to_pfn(TRIZEPS4_CFSR_PHYS),
		.length		= 0x00001000,
		.type		= MT_DEVICE
	},
	{	/* ConXS BCR */
		.virtual	= TRIZEPS4_BOCR_VIRT,
		.pfn		= __phys_to_pfn(TRIZEPS4_BOCR_PHYS),
		.length		= 0x00001000,
		.type		= MT_DEVICE
	},
	{ 	/* ConXS IRCR */
		.virtual	= TRIZEPS4_IRCR_VIRT,
		.pfn		= __phys_to_pfn(TRIZEPS4_IRCR_PHYS),
		.length		= 0x00001000,
		.type		= MT_DEVICE
	},
	{	/* ConXS DCR */
		.virtual	= TRIZEPS4_DICR_VIRT,
		.pfn		= __phys_to_pfn(TRIZEPS4_DICR_PHYS),
		.length		= 0x00001000,
		.type		= MT_DEVICE
	},
	{	/* ConXS UPSR */
		.virtual	= TRIZEPS4_UPSR_VIRT,
		.pfn		= __phys_to_pfn(TRIZEPS4_UPSR_PHYS),
		.length		= 0x00001000,
		.type		= MT_DEVICE
	}
};

static struct pxafb_mode_info sharp_lcd_mode = {
    .pixclock		= 78000,
    .xres		= 640,
    .yres		= 480,
    .bpp		= 8,
    .hsync_len		= 4,
    .left_margin	= 4,
    .right_margin	= 4,
    .vsync_len		= 2,
    .upper_margin	= 0,
    .lower_margin	= 0,
    .sync		= FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
    .cmap_greyscale	= 0,
};

static struct pxafb_mach_info sharp_lcd = {
    .modes		= &sharp_lcd_mode,
    .num_modes	= 1,
    .cmap_inverse	= 0,
    .cmap_static	= 0,
    .lccr0		= LCCR0_Color | LCCR0_Pas | LCCR0_Dual,
    .lccr3		= 0x0340ff02,
    .pxafb_backlight_power = board_backlight_power,
};

static struct pxafb_mode_info toshiba_lcd_mode = {
    .pixclock		= 39720,
    .xres		= 640,
    .yres		= 480,
    .bpp		= 8,
    .hsync_len		= 63,
    .left_margin	= 12,
    .right_margin	= 12,
    .vsync_len		= 4,
    .upper_margin	= 32,
    .lower_margin	= 10,
    .sync		= 0,
    .cmap_greyscale	= 0,
};

static struct pxafb_mach_info toshiba_lcd = {
    .modes		= &toshiba_lcd_mode,
    .num_modes	= 1,
    .cmap_inverse	= 0,
    .cmap_static	= 0,
    .lccr0		= LCCR0_Color | LCCR0_Act,
    .lccr3		= 0x03400002,
    .pxafb_backlight_power = board_backlight_power,
};

static void __init trizeps4_init(void)
{
	platform_add_devices(trizeps4_devices, ARRAY_SIZE(trizeps4_devices));

/*	set_pxa_fb_info(&sharp_lcd); */
	set_pxa_fb_info(&toshiba_lcd);

	pxa_set_mci_info(&trizeps4_mci_platform_data);
	pxa_set_ficp_info(&trizeps4_ficp_platform_data);
	pxa_set_ohci_info(&trizeps4_ohci_platform_data);
	pxa_set_ac97_info(NULL);
}

static void __init trizeps4_map_io(void)
{
	pxa_map_io();
	iotable_init(trizeps4_io_desc, ARRAY_SIZE(trizeps4_io_desc));

	/* for DiskOnChip */
	pxa_gpio_mode(GPIO15_nCS_1_MD);

	/* for off-module PIC on ConXS board */
	pxa_gpio_mode(GPIO_PIC | GPIO_IN);

	/* UCB1400 irq */
	pxa_gpio_mode(GPIO_UCB1400 | GPIO_IN);

	/* for DM9000 LAN */
	pxa_gpio_mode(GPIO78_nCS_2_MD);
	pxa_gpio_mode(GPIO_DM9000 | GPIO_IN);

	/* for PCMCIA device */
	pxa_gpio_mode(GPIO_PCD | GPIO_IN);
	pxa_gpio_mode(GPIO_PRDY | GPIO_IN);

	/* for I2C adapter */
	pxa_gpio_mode(GPIO117_I2CSCL_MD);
	pxa_gpio_mode(GPIO118_I2CSDA_MD);

	/* MMC_DET s.o. */
	pxa_gpio_mode(GPIO_MMC_DET | GPIO_IN);

	/* whats that for ??? */
	pxa_gpio_mode(GPIO79_nCS_3_MD);

#ifdef CONFIG_LEDS
	pxa_gpio_mode( GPIO_SYS_BUSY_LED  | GPIO_OUT);		/* LED1 */
	pxa_gpio_mode( GPIO_HEARTBEAT_LED | GPIO_OUT);		/* LED2 */
#endif
#ifdef CONFIG_MACH_TRIZEPS4_CONXS
#ifdef CONFIG_IDE_PXA_CF
	/* if boot direct from compact flash dont disable power */
	trizeps_conxs_bcr = 0x0009;
#else
	/* this is the reset value */
	trizeps_conxs_bcr = 0x00A0;
#endif
	ConXS_BCR = trizeps_conxs_bcr;
#endif

#warning FIXME - accessing PM registers directly is deprecated
	PWER  = 0x00000002;
	PFER  = 0x00000000;
	PRER  = 0x00000002;
	PGSR0 = 0x0158C000;
	PGSR1 = 0x00FF0080;
	PGSR2 = 0x0001C004;
	/* Stop 3.6MHz and drive HIGH to PCMCIA and CS */
	PCFR |= PCFR_OPDE;
}

MACHINE_START(TRIZEPS4, "Keith und Koep Trizeps IV module")
	/* MAINTAINER("Jürgen Schindele") */
	.phys_io	= 0x40000000,
	.io_pg_offst	= (io_p2v(0x40000000) >> 18) & 0xfffc,
	.boot_params	= TRIZEPS4_SDRAM_BASE + 0x100,
	.init_machine	= trizeps4_init,
	.map_io		= trizeps4_map_io,
	.init_irq	= pxa27x_init_irq,
	.timer		= &pxa_timer,
MACHINE_END

d; struct nvm_dev; typedef int (nvm_l2p_update_fn)(u64, u32, __le64 *, void *); typedef int (nvm_bb_update_fn)(struct ppa_addr, int, u8 *, void *); typedef int (nvm_id_fn)(struct nvm_dev *, struct nvm_id *); typedef int (nvm_get_l2p_tbl_fn)(struct nvm_dev *, u64, u32, nvm_l2p_update_fn *, void *); typedef int (nvm_op_bb_tbl_fn)(struct nvm_dev *, struct ppa_addr, int, nvm_bb_update_fn *, void *); typedef int (nvm_op_set_bb_fn)(struct nvm_dev *, struct nvm_rq *, int); typedef int (nvm_submit_io_fn)(struct nvm_dev *, struct nvm_rq *); typedef int (nvm_erase_blk_fn)(struct nvm_dev *, struct nvm_rq *); typedef void *(nvm_create_dma_pool_fn)(struct nvm_dev *, char *); typedef void (nvm_destroy_dma_pool_fn)(void *); typedef void *(nvm_dev_dma_alloc_fn)(struct nvm_dev *, void *, gfp_t, dma_addr_t *); typedef void (nvm_dev_dma_free_fn)(void *, void*, dma_addr_t); struct nvm_dev_ops { nvm_id_fn *identity; nvm_get_l2p_tbl_fn *get_l2p_tbl; nvm_op_bb_tbl_fn *get_bb_tbl; nvm_op_set_bb_fn *set_bb_tbl; nvm_submit_io_fn *submit_io; nvm_erase_blk_fn *erase_block; nvm_create_dma_pool_fn *create_dma_pool; nvm_destroy_dma_pool_fn *destroy_dma_pool; nvm_dev_dma_alloc_fn *dev_dma_alloc; nvm_dev_dma_free_fn *dev_dma_free; unsigned int max_phys_sect; }; #ifdef CONFIG_NVM #include <linux/blkdev.h> #include <linux/file.h> #include <linux/dmapool.h> #include <uapi/linux/lightnvm.h> enum { /* HW Responsibilities */ NVM_RSP_L2P = 1 << 0, NVM_RSP_ECC = 1 << 1, /* Physical Adressing Mode */ NVM_ADDRMODE_LINEAR = 0, NVM_ADDRMODE_CHANNEL = 1, /* Plane programming mode for LUN */ NVM_PLANE_SINGLE = 0, NVM_PLANE_DOUBLE = 1, NVM_PLANE_QUAD = 2, /* Status codes */ NVM_RSP_SUCCESS = 0x0, NVM_RSP_NOT_CHANGEABLE = 0x1, NVM_RSP_ERR_FAILWRITE = 0x40ff, NVM_RSP_ERR_EMPTYPAGE = 0x42ff, /* Device opcodes */ NVM_OP_HBREAD = 0x02, NVM_OP_HBWRITE = 0x81, NVM_OP_PWRITE = 0x91, NVM_OP_PREAD = 0x92, NVM_OP_ERASE = 0x90, /* PPA Command Flags */ NVM_IO_SNGL_ACCESS = 0x0, NVM_IO_DUAL_ACCESS = 0x1, NVM_IO_QUAD_ACCESS = 0x2, /* NAND Access Modes */ NVM_IO_SUSPEND = 0x80, NVM_IO_SLC_MODE = 0x100, NVM_IO_SCRAMBLE_DISABLE = 0x200, /* Block Types */ NVM_BLK_T_FREE = 0x0, NVM_BLK_T_BAD = 0x1, NVM_BLK_T_GRWN_BAD = 0x2, NVM_BLK_T_DEV = 0x4, NVM_BLK_T_HOST = 0x8, /* Memory capabilities */ NVM_ID_CAP_SLC = 0x1, NVM_ID_CAP_CMD_SUSPEND = 0x2, NVM_ID_CAP_SCRAMBLE = 0x4, NVM_ID_CAP_ENCRYPT = 0x8, /* Memory types */ NVM_ID_FMTYPE_SLC = 0, NVM_ID_FMTYPE_MLC = 1, }; struct nvm_id_lp_mlc { u16 num_pairs; u8 pairs[886]; }; struct nvm_id_lp_tbl { __u8 id[8]; struct nvm_id_lp_mlc mlc; }; struct nvm_id_group { u8 mtype; u8 fmtype; u8 num_ch; u8 num_lun; u8 num_pln; u16 num_blk; u16 num_pg; u16 fpg_sz; u16 csecs; u16 sos; u32 trdt; u32 trdm; u32 tprt; u32 tprm; u32 tbet; u32 tbem; u32 mpos; u32 mccap; u16 cpar; struct nvm_id_lp_tbl lptbl; }; struct nvm_addr_format { u8 ch_offset; u8 ch_len; u8 lun_offset; u8 lun_len; u8 pln_offset; u8 pln_len; u8 blk_offset; u8 blk_len; u8 pg_offset; u8 pg_len; u8 sect_offset; u8 sect_len; }; struct nvm_id { u8 ver_id; u8 vmnt; u8 cgrps; u32 cap; u32 dom; struct nvm_addr_format ppaf; struct nvm_id_group groups[4]; } __packed; struct nvm_target { struct list_head list; struct nvm_tgt_type *type; struct gendisk *disk; }; struct nvm_tgt_instance { struct nvm_tgt_type *tt; }; #define ADDR_EMPTY (~0ULL) #define NVM_VERSION_MAJOR 1 #define NVM_VERSION_MINOR 0 #define NVM_VERSION_PATCH 0 struct nvm_rq; typedef void (nvm_end_io_fn)(struct nvm_rq *); struct nvm_rq { struct nvm_tgt_instance *ins; struct nvm_dev *dev; struct bio *bio; union { struct ppa_addr ppa_addr; dma_addr_t dma_ppa_list; }; struct ppa_addr *ppa_list; void *metadata; dma_addr_t dma_metadata; struct completion *wait; nvm_end_io_fn *end_io; uint8_t opcode; uint16_t nr_pages; uint16_t flags; int error; }; static inline struct nvm_rq *nvm_rq_from_pdu(void *pdu) { return pdu - sizeof(struct nvm_rq); } static inline void *nvm_rq_to_pdu(struct nvm_rq *rqdata) { return rqdata + 1; } struct nvm_block; struct nvm_lun { int id; int lun_id; int chnl_id; /* It is up to the target to mark blocks as closed. If the target does * not do it, all blocks are marked as open, and nr_open_blocks * represents the number of blocks in use */ unsigned int nr_open_blocks; /* Number of used, writable blocks */ unsigned int nr_closed_blocks; /* Number of used, read-only blocks */ unsigned int nr_free_blocks; /* Number of unused blocks */ unsigned int nr_bad_blocks; /* Number of bad blocks */ spinlock_t lock; struct nvm_block *blocks; }; enum { NVM_BLK_ST_FREE = 0x1, /* Free block */ NVM_BLK_ST_OPEN = 0x2, /* Open block - read-write */ NVM_BLK_ST_CLOSED = 0x4, /* Closed block - read-only */ NVM_BLK_ST_BAD = 0x8, /* Bad block */ }; struct nvm_block { struct list_head list; struct nvm_lun *lun; unsigned long id; void *priv; int state; }; /* system block cpu representation */ struct nvm_sb_info { unsigned long seqnr; unsigned long erase_cnt; unsigned int version; char mmtype[NVM_MMTYPE_LEN]; struct ppa_addr fs_ppa; }; struct nvm_dev { struct nvm_dev_ops *ops; struct list_head devices; struct list_head online_targets; /* Media manager */ struct nvmm_type *mt; void *mp; /* System blocks */ struct nvm_sb_info sb; /* Device information */ int nr_chnls; int nr_planes; int luns_per_chnl; int sec_per_pg; /* only sectors for a single page */ int pgs_per_blk; int blks_per_lun; int sec_size; int oob_size; int mccap; struct nvm_addr_format ppaf; /* Calculated/Cached values. These do not reflect the actual usable * blocks at run-time. */ int max_rq_size; int plane_mode; /* drive device in single, double or quad mode */ int sec_per_pl; /* all sectors across planes */ int sec_per_blk; int sec_per_lun; /* lower page table */ int lps_per_blk; int *lptbl; unsigned long total_pages; unsigned long total_blocks; int nr_luns; unsigned max_pages_per_blk; void *ppalist_pool; struct nvm_id identity; /* Backend device */ struct request_queue *q; char name[DISK_NAME_LEN]; struct mutex mlock; }; static inline struct ppa_addr generic_to_dev_addr(struct nvm_dev *dev, struct ppa_addr r) { struct ppa_addr l; l.ppa = ((u64)r.g.blk) << dev->ppaf.blk_offset; l.ppa |= ((u64)r.g.pg) << dev->ppaf.pg_offset; l.ppa |= ((u64)r.g.sec) << dev->ppaf.sect_offset; l.ppa |= ((u64)r.g.pl) << dev->ppaf.pln_offset; l.ppa |= ((u64)r.g.lun) << dev->ppaf.lun_offset; l.ppa |= ((u64)r.g.ch) << dev->ppaf.ch_offset; return l; } static inline struct ppa_addr dev_to_generic_addr(struct nvm_dev *dev, struct ppa_addr r) { struct ppa_addr l; /* * (r.ppa << X offset) & X len bitmask. X eq. blk, pg, etc. */ l.g.blk = (r.ppa >> dev->ppaf.blk_offset) & (((1 << dev->ppaf.blk_len) - 1)); l.g.pg |= (r.ppa >> dev->ppaf.pg_offset) & (((1 << dev->ppaf.pg_len) - 1)); l.g.sec |= (r.ppa >> dev->ppaf.sect_offset) & (((1 << dev->ppaf.sect_len) - 1)); l.g.pl |= (r.ppa >> dev->ppaf.pln_offset) & (((1 << dev->ppaf.pln_len) - 1)); l.g.lun |= (r.ppa >> dev->ppaf.lun_offset) & (((1 << dev->ppaf.lun_len) - 1)); l.g.ch |= (r.ppa >> dev->ppaf.ch_offset) & (((1 << dev->ppaf.ch_len) - 1)); return l; } static inline int ppa_empty(struct ppa_addr ppa_addr) { return (ppa_addr.ppa == ADDR_EMPTY); } static inline void ppa_set_empty(struct ppa_addr *ppa_addr) { ppa_addr->ppa = ADDR_EMPTY; } static inline struct ppa_addr block_to_ppa(struct nvm_dev *dev, struct nvm_block *blk) { struct ppa_addr ppa; struct nvm_lun *lun = blk->lun; ppa.ppa = 0; ppa.g.blk = blk->id % dev->blks_per_lun; ppa.g.lun = lun->lun_id; ppa.g.ch = lun->chnl_id; return ppa; } static inline int ppa_to_slc(struct nvm_dev *dev, int slc_pg) { return dev->lptbl[slc_pg]; } typedef blk_qc_t (nvm_tgt_make_rq_fn)(struct request_queue *, struct bio *); typedef sector_t (nvm_tgt_capacity_fn)(void *); typedef void *(nvm_tgt_init_fn)(struct nvm_dev *, struct gendisk *, int, int); typedef void (nvm_tgt_exit_fn)(void *); struct nvm_tgt_type { const char *name; unsigned int version[3]; /* target entry points */ nvm_tgt_make_rq_fn *make_rq; nvm_tgt_capacity_fn *capacity; nvm_end_io_fn *end_io; /* module-specific init/teardown */ nvm_tgt_init_fn *init; nvm_tgt_exit_fn *exit; /* For internal use */ struct list_head list; }; extern int nvm_register_target(struct nvm_tgt_type *); extern void nvm_unregister_target(struct nvm_tgt_type *); extern void *nvm_dev_dma_alloc(struct nvm_dev *, gfp_t, dma_addr_t *); extern void nvm_dev_dma_free(struct nvm_dev *, void *, dma_addr_t); typedef int (nvmm_register_fn)(struct nvm_dev *); typedef void (nvmm_unregister_fn)(struct nvm_dev *); typedef struct nvm_block *(nvmm_get_blk_fn)(struct nvm_dev *, struct nvm_lun *, unsigned long); typedef void (nvmm_put_blk_fn)(struct nvm_dev *, struct nvm_block *); typedef int (nvmm_open_blk_fn)(struct nvm_dev *, struct nvm_block *); typedef int (nvmm_close_blk_fn)(struct nvm_dev *, struct nvm_block *); typedef void (nvmm_flush_blk_fn)(struct nvm_dev *, struct nvm_block *); typedef int (nvmm_submit_io_fn)(struct nvm_dev *, struct nvm_rq *); typedef int (nvmm_erase_blk_fn)(struct nvm_dev *, struct nvm_block *, unsigned long); typedef struct nvm_lun *(nvmm_get_lun_fn)(struct nvm_dev *, int); typedef void (nvmm_lun_info_print_fn)(struct nvm_dev *); struct nvmm_type { const char *name; unsigned int version[3]; nvmm_register_fn *register_mgr; nvmm_unregister_fn *unregister_mgr; /* Block administration callbacks */ nvmm_get_blk_fn *get_blk_unlocked; nvmm_put_blk_fn *put_blk_unlocked; nvmm_get_blk_fn *get_blk; nvmm_put_blk_fn *put_blk; nvmm_open_blk_fn *open_blk; nvmm_close_blk_fn *close_blk; nvmm_flush_blk_fn *flush_blk; nvmm_submit_io_fn *submit_io; nvmm_erase_blk_fn *erase_blk; /* Configuration management */ nvmm_get_lun_fn *get_lun; /* Statistics */ nvmm_lun_info_print_fn *lun_info_print; struct list_head list; }; extern int nvm_register_mgr(struct nvmm_type *); extern void nvm_unregister_mgr(struct nvmm_type *); extern struct nvm_block *nvm_get_blk_unlocked(struct nvm_dev *, struct nvm_lun *, unsigned long); extern void nvm_put_blk_unlocked(struct nvm_dev *, struct nvm_block *); extern struct nvm_block *nvm_get_blk(struct nvm_dev *, struct nvm_lun *, unsigned long); extern void nvm_put_blk(struct nvm_dev *, struct nvm_block *); extern int nvm_register(struct request_queue *, char *, struct nvm_dev_ops *); extern void nvm_unregister(char *); extern int nvm_submit_io(struct nvm_dev *, struct nvm_rq *); extern void nvm_generic_to_addr_mode(struct nvm_dev *, struct nvm_rq *); extern void nvm_addr_to_generic_mode(struct nvm_dev *, struct nvm_rq *); extern int nvm_set_rqd_ppalist(struct nvm_dev *, struct nvm_rq *, struct ppa_addr *, int); extern void nvm_free_rqd_ppalist(struct nvm_dev *, struct nvm_rq *); extern int nvm_erase_ppa(struct nvm_dev *, struct ppa_addr *, int); extern int nvm_erase_blk(struct nvm_dev *, struct nvm_block *); extern void nvm_end_io(struct nvm_rq *, int); extern int nvm_submit_ppa(struct nvm_dev *, struct ppa_addr *, int, int, int, void *, int); /* sysblk.c */ #define NVM_SYSBLK_MAGIC 0x4E564D53 /* "NVMS" */ /* system block on disk representation */ struct nvm_system_block { __be32 magic; /* magic signature */ __be32 seqnr; /* sequence number */ __be32 erase_cnt; /* erase count */ __be16 version; /* version number */ u8 mmtype[NVM_MMTYPE_LEN]; /* media manager name */ __be64 fs_ppa; /* PPA for media manager * superblock */ }; extern int nvm_get_sysblock(struct nvm_dev *, struct nvm_sb_info *); extern int nvm_update_sysblock(struct nvm_dev *, struct nvm_sb_info *); extern int nvm_init_sysblock(struct nvm_dev *, struct nvm_sb_info *); extern int nvm_dev_factory(struct nvm_dev *, int flags); #else /* CONFIG_NVM */ struct nvm_dev_ops; static inline int nvm_register(struct request_queue *q, char *disk_name, struct nvm_dev_ops *ops) { return -EINVAL; } static inline void nvm_unregister(char *disk_name) {} #endif /* CONFIG_NVM */ #endif /* LIGHTNVM.H */