1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
|
/*
* System controller support for Armada 370, 375 and XP platforms.
*
* Copyright (C) 2012 Marvell
*
* Lior Amsalem <alior@marvell.com>
* Gregory CLEMENT <gregory.clement@free-electrons.com>
* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*
* The Armada 370, 375 and Armada XP SoCs have a range of
* miscellaneous registers, that do not belong to a particular device,
* but rather provide system-level features. This basic
* system-controller driver provides a device tree binding for those
* registers, and implements utility functions offering various
* features related to those registers.
*
* For now, the feature set is limited to restarting the platform by a
* soft-reset, but it might be extended in the future.
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/of_address.h>
#include <linux/io.h>
#include <linux/reboot.h>
#include "common.h"
#include "mvebu-soc-id.h"
#include "pmsu.h"
#define ARMADA_375_CRYPT0_ENG_TARGET 41
#define ARMADA_375_CRYPT0_ENG_ATTR 1
static void __iomem *system_controller_base;
static phys_addr_t system_controller_phys_base;
struct mvebu_system_controller {
u32 rstoutn_mask_offset;
u32 system_soft_reset_offset;
u32 rstoutn_mask_reset_out_en;
u32 system_soft_reset;
u32 resume_boot_addr;
u32 dev_id;
u32 rev_id;
};
static struct mvebu_system_controller *mvebu_sc;
static const struct mvebu_system_controller armada_370_xp_system_controller = {
.rstoutn_mask_offset = 0x60,
.system_soft_reset_offset = 0x64,
.rstoutn_mask_reset_out_en = 0x1,
.system_soft_reset = 0x1,
.dev_id = 0x38,
.rev_id = 0x3c,
};
static const struct mvebu_system_controller armada_375_system_controller = {
.rstoutn_mask_offset = 0x54,
.system_soft_reset_offset = 0x58,
.rstoutn_mask_reset_out_en = 0x1,
.system_soft_reset = 0x1,
.resume_boot_addr = 0xd4,
.dev_id = 0x38,
.rev_id = 0x3c,
};
static const struct mvebu_system_controller orion_system_controller = {
.rstoutn_mask_offset = 0x108,
.system_soft_reset_offset = 0x10c,
.rstoutn_mask_reset_out_en = 0x4,
.system_soft_reset = 0x1,
};
static const struct of_device_id of_system_controller_table[] = {
{
.compatible = "marvell,orion-system-controller",
.data = (void *) &orion_system_controller,
}, {
.compatible = "marvell,armada-370-xp-system-controller",
.data = (void *) &armada_370_xp_system_controller,
}, {
.compatible = "marvell,armada-375-system-controller",
.data = (void *) &armada_375_system_controller,
},
{ /* end of list */ },
};
void mvebu_restart(enum reboot_mode mode, const char *cmd)
{
if (!system_controller_base) {
pr_err("Cannot restart, system-controller not available: check the device tree\n");
} else {
/*
* Enable soft reset to assert RSTOUTn.
*/
writel(mvebu_sc->rstoutn_mask_reset_out_en,
system_controller_base +
mvebu_sc->rstoutn_mask_offset);
/*
* Assert soft reset.
*/
writel(mvebu_sc->system_soft_reset,
system_controller_base +
mvebu_sc->system_soft_reset_offset);
}
while (1)
;
}
int mvebu_system_controller_get_soc_id(u32 *dev, u32 *rev)
{
if (of_machine_is_compatible("marvell,armada380") &&
system_controller_base) {
*dev = readl(system_controller_base + mvebu_sc->dev_id) >> 16;
*rev = (readl(system_controller_base + mvebu_sc->rev_id) >> 8)
& 0xF;
return 0;
} else
return -ENODEV;
}
#ifdef CONFIG_SMP
void mvebu_armada375_smp_wa_init(void)
{
u32 dev, rev;
phys_addr_t resume_addr_reg;
if (mvebu_get_soc_id(&dev, &rev) != 0)
return;
if (rev != ARMADA_375_Z1_REV)
return;
resume_addr_reg = system_controller_phys_base +
mvebu_sc->resume_boot_addr;
mvebu_setup_boot_addr_wa(ARMADA_375_CRYPT0_ENG_TARGET,
ARMADA_375_CRYPT0_ENG_ATTR,
resume_addr_reg);
}
void mvebu_system_controller_set_cpu_boot_addr(void *boot_addr)
{
BUG_ON(system_controller_base == NULL);
BUG_ON(mvebu_sc->resume_boot_addr == 0);
if (of_machine_is_compatible("marvell,armada375"))
mvebu_armada375_smp_wa_init();
writel(virt_to_phys(boot_addr), system_controller_base +
mvebu_sc->resume_boot_addr);
}
#endif
static int __init mvebu_system_controller_init(void)
{
const struct of_device_id *match;
struct device_node *np;
np = of_find_matching_node_and_match(NULL, of_system_controller_table,
&match);
if (np) {
struct resource res;
system_controller_base = of_iomap(np, 0);
of_address_to_resource(np, 0, &res);
system_controller_phys_base = res.start;
mvebu_sc = (struct mvebu_system_controller *)match->data;
of_node_put(np);
}
return 0;
}
early_initcall(mvebu_system_controller_init);
|
