1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
|
/*
* arch/arm/mach-mv78xx0/irq.c
*
* MV78xx0 IRQ handling.
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/pci.h>
#include <linux/irq.h>
#include <asm/gpio.h>
#include <mach/mv78xx0.h>
#include <plat/irq.h>
#include "common.h"
static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
{
BUG_ON(irq < IRQ_MV78XX0_GPIO_0_7 || irq > IRQ_MV78XX0_GPIO_24_31);
orion_gpio_irq_handler((irq - IRQ_MV78XX0_GPIO_0_7) << 3);
}
void __init mv78xx0_init_irq(void)
{
int i;
orion_irq_init(0, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF));
orion_irq_init(32, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF));
orion_irq_init(64, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_ERR_OFF));
/*
* Mask and clear GPIO IRQ interrupts.
*/
writel(0, GPIO_LEVEL_MASK(0));
writel(0, GPIO_EDGE_MASK(0));
writel(0, GPIO_EDGE_CAUSE(0));
for (i = IRQ_MV78XX0_GPIO_START; i < NR_IRQS; i++) {
set_irq_chip(i, &orion_gpio_irq_level_chip);
set_irq_handler(i, handle_level_irq);
irq_desc[i].status |= IRQ_LEVEL;
set_irq_flags(i, IRQF_VALID);
}
set_irq_chained_handler(IRQ_MV78XX0_GPIO_0_7, gpio_irq_handler);
set_irq_chained_handler(IRQ_MV78XX0_GPIO_8_15, gpio_irq_handler);
set_irq_chained_handler(IRQ_MV78XX0_GPIO_16_23, gpio_irq_handler);
set_irq_chained_handler(IRQ_MV78XX0_GPIO_24_31, gpio_irq_handler);
}
|
