Documentation/devicetree/bindings/clock/sunxi.txt


1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44

Device Tree Clock bindings for arch-sunxi

This binding uses the common clock binding[1].

[1] Documentation/devicetree/bindings/clock/clock-bindings.txt

Required properties:
- compatible : shall be one of the following:
	"allwinner,sun4i-osc-clk" - for a gatable oscillator
	"allwinner,sun4i-pll1-clk" - for the main PLL clock
	"allwinner,sun4i-cpu-clk" - for the CPU multiplexer clock
	"allwinner,sun4i-axi-clk" - for the AXI clock
	"allwinner,sun4i-ahb-clk" - for the AHB clock
	"allwinner,sun4i-apb0-clk" - for the APB0 clock
	"allwinner,sun4i-apb1-clk" - for the APB1 clock
	"allwinner,sun4i-apb1-mux-clk" - for the APB1 clock muxing

Required properties for all clocks:
- reg : shall be the control register address for the clock.
- clocks : shall be the input parent clock(s) phandle for the clock
- #clock-cells : from common clock binding; shall be set to 0.

For example:

osc24M: osc24M@01c20050 {
	#clock-cells = <0>;
	compatible = "allwinner,sun4i-osc-clk";
	reg = <0x01c20050 0x4>;
	clocks = <&osc24M_fixed>;
};

pll1: pll1@01c20000 {
	#clock-cells = <0>;
	compatible = "allwinner,sun4i-pll1-clk";
	reg = <0x01c20000 0x4>;
	clocks = <&osc24M>;
};

cpu: cpu@01c20054 {
	#clock-cells = <0>;
	compatible = "allwinner,sun4i-cpu-clk";
	reg = <0x01c20054 0x4>;
	clocks = <&osc32k>, <&osc24M>, <&pll1>;
};