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BranchCommit messageAuthorAge
archive/unc-master-3.0P-FP: fix BUG_ON releated to priority inheritanceBjoern Brandenburg12 years
archived-2013.1uncachedev: mmap memory that is not cached by CPUsGlenn Elliott12 years
archived-private-masterMerge branch 'wip-2.6.34' into old-private-masterAndrea Bastoni15 years
archived-semi-partMerge branch 'wip-semi-part' of ssh://cvs/cvs/proj/litmus/repo/litmus2010 int...Andrea Bastoni14 years
demoFurther refinementsJonathan Herman13 years
ecrts-pgm-finalMerge branch 'wip-ecrts14-pgm' of ssh://rtsrv.cs.unc.edu/home/litmus/litmus-r...Glenn Elliott11 years
ecrts14-pgm-finalMerge branch 'wip-ecrts14-pgm' of ssh://rtsrv.cs.unc.edu/home/litmus/litmus-r...Glenn Elliott11 years
gpusync-rtss12Final GPUSync implementation.Glenn Elliott12 years
gpusync/stagingRename IKGLP R2DGLP.Glenn Elliott11 years
linux-tipMerge branch 'slab/urgent' of git://git.kernel.org/pub/scm/linux/kernel/git/p...Linus Torvalds14 years
litmus2008-patch-seriesadd i386 feather-trace implementationBjoern B. Brandenburg15 years
masterPSN-EDF: use inferred_sporadic_job_release_atBjoern Brandenburg9 years
pgmmake it compileGlenn Elliott12 years
prop/litmus-signalsInfrastructure for Litmus signals.Glenn Elliott12 years
prop/robust-tie-breakFixed bug in edf_higher_prio().Glenn Elliott12 years
stagingFix tracepoint compilation errorFelipe Cerqueira12 years
test9/23/2016Namhoon Kim8 years
tracing-develTest kernel tracing events capabilitiesAndrea Bastoni15 years
v2.6.34-with-arm-patchessmsc911x: Add spinlocks around registers accessCatalin Marinas15 years
v2015.1Add ARM syscall def for get_current_budgetBjoern Brandenburg9 years
wip-2011.2-bbbLitmus core: simplify np-section protocolBjoern B. Brandenburg13 years
wip-2011.2-bbb-traceRefactor sched_trace_log_message() -> debug_trace_log_message()Andrea Bastoni13 years
wip-2012.3-gpuSOBLIV draining support for C-EDF.Glenn Elliott12 years
wip-2012.3-gpu-preportpick up last C-RM fileGlenn Elliott11 years
wip-2012.3-gpu-rtss13Fix critical bug in GPU tracker.Glenn Elliott11 years
wip-2012.3-gpu-sobliv-budget-w-ksharkProper sobliv draining and many bug fixes.Glenn Elliott12 years
wip-aedzl-finalMake it easier to compile AEDZL interfaces in liblitmus.Glenn Elliott14 years
wip-aedzl-revisedAdd sched_trace data for Apative EDZLGlenn Elliott14 years
wip-arbit-deadlineFix compilation bug.Glenn Elliott13 years
wip-aux-tasksDescription of refined aux task inheritance.Glenn Elliott12 years
wip-bbbGSN-EDF & Core: improve debug TRACE'ing for NP sectionsBjoern B. Brandenburg14 years
wip-bbb-prio-donuse correct timestampBjoern B. Brandenburg14 years
wip-better-breakImplement hash-based EDF tie-breaking.Glenn Elliott13 years
wip-binary-heapMake C-EDF work with simplified binheap_deleteGlenn Elliott13 years
wip-budgetAdded support for choices in budget policy enforcement.Glenn Elliott15 years
wip-colorSummarize schedulability with final recordJonathan Herman13 years
wip-color-jlhsched_color: Fixed two bugs causing crashing on experiment restart and a rare...Jonathan Herman13 years
wip-d10-hz1000Enable HZ=1000 on District 10Bjoern B. Brandenburg14 years
wip-default-clusteringFeature: Make default C-EDF clustering compile-time configurable.Glenn Elliott14 years
wip-dissipation-jericksoUpdate from 2.6.36 to 2.6.36.4Jeremy Erickson11 years
wip-dissipation2-jericksoUpdate 2.6.36 to 2.6.36.4Jeremy Erickson11 years
wip-ecrts14-pgmMerge branch 'wip-ecrts14-pgm' of ssh://rtsrv.cs.unc.edu/home/litmus/litmus-r...Glenn Elliott11 years
wip-edf-hsblast tested versionJonathan Herman14 years
wip-edf-osLookup table EDF-osJeremy Erickson12 years
wip-edf-tie-breakMerge branch 'wip-edf-tie-break' of ssh://rtsrv.cs.unc.edu/home/litmus/litmus...Glenn Elliott12 years
wip-edzl-critiqueUse hr_timer's active checks instead of having own flag.Glenn Elliott14 years
wip-edzl-finalImplementation of the EDZL scheduler.Glenn Elliott14 years
wip-edzl-revisedClean up comments.Glenn Elliott14 years
wip-eventsAdded support for tracing arbitrary actions.Jonathan Herman14 years
wip-extra-debugDBG: add additional tracingBjoern B. Brandenburg14 years
wip-fix-switch-jericksoAttempt to fix race condition with plugin switchingJeremy Erickson14 years
wip-fix3sched: show length of runqueue clock deactivation in /proc/sched_debugBjoern B. Brandenburg14 years
wip-fmlp-dequeueImprove FMLP queue management.Glenn Elliott14 years
wip-ft-irq-flagFeather-Trace: keep track of interrupt-related interference.Bjoern B. Brandenburg13 years
wip-gpu-cleanupEnable sched_trace log injection from userspaceGlenn Elliott12 years
wip-gpu-interruptsRemove option for threading of all softirqs.Glenn Elliott13 years
wip-gpu-rtas12Generalized GPU cost predictors + EWMA. (untested)Glenn Elliott12 years
wip-gpu-rtss12Final GPUSync implementation.Glenn Elliott13 years
wip-gpu-rtss12-srpexperimental changes to support GPUs under SRPGlenn Elliott13 years
wip-gpusync-mergeCleanup priority tracking for budget enforcement.Glenn Elliott11 years
wip-ikglpMove RSM and IKGLP imp. to own .c filesGlenn Elliott13 years
wip-k-fmlpMerge branch 'mpi-master' into wip-k-fmlpGlenn Elliott13 years
wip-kernel-coloringAdded recolor syscallNamhoon Kim7 years
wip-kernthreadsKludge work-queue processing into klitirqd.Glenn Elliott14 years
wip-klmirqd-to-auxAllow klmirqd threads to be given names.Glenn Elliott12 years
wip-ksharkMerge branch 'mpi-staging' into wip-ksharkJonathan Herman12 years
wip-litmus-3.2Merge commit 'v3.2' into litmus-stagingAndrea Bastoni12 years
wip-litmus2011.2Cleanup: Coding conformance for affinity stuff.Glenn Elliott14 years
wip-litmus3.0-2011.2Feather-Trace: keep track of interrupt-related interference.Bjoern B. Brandenburg13 years
wip-master-2.6.33-rtAvoid deadlock when switching task policy to BACKGROUND (ugly)Andrea Bastoni15 years
wip-mcRemoved ARM-specific hacks which disabled less common mixed-criticality featu...Jonathan Herman12 years
wip-mc-bipasaMC-EDF addedbipasa chattopadhyay13 years
wip-mc-jericksoSplit C/D queuesJeremy Erickson14 years
wip-mc2-cache-slackManually patched mc^2 related codeMing Yang9 years
wip-mcrit-maccosmeticMac Mollison14 years
wip-merge-3.0Prevent Linux to send IPI and queue tasks on remote CPUs.Andrea Bastoni14 years
wip-merge-v3.0Prevent Linux to send IPI and queue tasks on remote CPUs.Andrea Bastoni13 years
wip-migration-affinityNULL affinity dereference in C-EDF.Glenn Elliott14 years
wip-mmap-uncacheshare branch with othersGlenn Elliott12 years
wip-modechangeRTSS 2017 submissionNamhoon Kim8 years
wip-nested-lockingAppears to be working.Bryan Ward12 years
wip-omlp-gedfFirst implementation of G-OMLP.Glenn Elliott15 years
wip-paiSome cleanup of PAIGlenn Elliott13 years
wip-percore-lib9/21/2016Namhoon Kim8 years
wip-performanceCONFIG_DONT_PREEMPT_ON_TIE: Don't preeempt a scheduled task on priority tie.Glenn Elliott14 years
wip-pgmAdd PGM support to C-FLGlenn Elliott11 years
wip-pgm-splitFirst draft of C-FL-splitNamhoon Kim11 years
wip-pm-ovdAdd preemption-and-migration overhead tracing supportAndrea Bastoni15 years
wip-prio-inhP-EDF updated to use the generic pi framework.Glenn Elliott15 years
wip-prioq-dglBUG FIX: Support DGLs with PRIOQ_MUTEXGlenn Elliott12 years
wip-refactored-gedfGeneralizd architecture for GEDF-style scheduelrs to reduce code redundancy.Glenn Elliott14 years
wip-release-master-fixbugfix: release master CPU must signal task was pickedBjoern B. Brandenburg14 years
wip-robust-tie-breakEDF priority tie-breaks.Glenn Elliott12 years
wip-rt-ksharkMove task time accounting into the complete_job method.Jonathan Herman12 years
wip-rtas12-pgmScheduling of PGM jobs.Glenn Elliott13 years
wip-semi-partFix compile error with newer GCCJeremy Erickson12 years
wip-semi-part-edfos-jericksoUse initial CPU set by clientJeremy Erickson12 years
wip-shared-libTODO: Fix condition checks in replicate_page_move_mapping()Namhoon Kim8 years
wip-shared-lib2RTAS 2017 Submission ver.Namhoon Kim8 years
wip-shared-memInitial commit for shared libraryNamhoon Kim8 years
wip-splitting-jericksoFix release behaviorJeremy Erickson12 years
wip-splitting-omlp-jericksoBjoern's Dissertation Code with Priority DonationJeremy Erickson12 years
wip-stage-binheapAn efficient binary heap implementation.Glenn Elliott13 years
wip-sun-portDynamic memory allocation and clean exit for FeatherTraceChristopher Kenna14 years
wip-timer-tracebugfix: C-EDF, clear scheduled field of the correct CPU upon task_exitAndrea Bastoni14 years
wip-tracepointsAdd kernel-style events for sched_trace_XXX() functionsAndrea Bastoni13 years
 
TagDownloadAuthorAge
2015.1commit 8e51b37822...Bjoern Brandenburg10 years
2013.1commit bcaacec1ca...Glenn Elliott12 years
2012.3commit c158b5fbe4...Jonathan Herman12 years
2012.2commit b53c479a0f...Glenn Elliott13 years
2012.1commit 83b11ea1c6...Bjoern B. Brandenburg13 years
rtas12-mc-beta-expcommit 8e236ee20f...Christopher Kenna13 years
2011.1commit d11808b5c6...Christopher Kenna14 years
v2.6.37-rc4commit e8a7e48bb2...Linus Torvalds14 years
v2.6.37-rc3commit 3561d43fd2...Linus Torvalds14 years
v2.6.37-rc2commit e53beacd23...Linus Torvalds14 years
v2.6.37-rc1commit c8ddb2713c...Linus Torvalds14 years
v2.6.36commit f6f94e2ab1...Linus Torvalds14 years
2010.2commit 5c5456402d...Bjoern B. Brandenburg14 years
v2.6.36-rc8commit cd07202cc8...Linus Torvalds14 years
v2.6.36-rc7commit cb655d0f3d...Linus Torvalds14 years
v2.6.36-rc6commit 899611ee7d...Linus Torvalds14 years
v2.6.36-rc5commit b30a3f6257...Linus Torvalds14 years
v2.6.36-rc4commit 49553c2ef8...Linus Torvalds14 years
v2.6.36-rc3commit 2bfc96a127...Linus Torvalds14 years
v2.6.36-rc2commit 76be97c1fc...Linus Torvalds15 years
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v2.6.35-rc2commit e44a21b726...Linus Torvalds15 years
v2.6.35-rc1commit 67a3e12b05...Linus Torvalds15 years
2010.1commit 7c1ff4c544...Andrea Bastoni15 years
v2.6.34commit e40152ee1e...Linus Torvalds15 years
v2.6.33.4commit 4640b4e7d9...Greg Kroah-Hartman15 years
v2.6.34-rc7commit b57f95a382...Linus Torvalds15 years
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v2.6.15-rc3commit 624f54be20...Linus Torvalds19 years
v2.6.15-rc2commit 3bedff1d73...Linus Torvalds19 years
v2.6.15-rc1commit cd52d1ee9a...Linus Torvalds19 years
v2.6.14commit 741b2252a5...Linus Torvalds19 years
v2.6.14-rc5commit 93918e9afc...Linus Torvalds19 years
v2.6.14-rc4commit 907a426179...Linus Torvalds19 years
v2.6.14-rc3commit 1c9426e8a5...Linus Torvalds19 years
v2.6.14-rc2commit 676d55ae30...Linus Torvalds19 years
v2.6.14-rc1commit 2f4ba45a75...Linus Torvalds19 years
v2.6.13commit 02b3e4e2d7...Linus Torvalds19 years
v2.6.13-rc7commit 0572e3da3f...Linus Torvalds20 years
v2.6.13-rc6commit 6fc32179de...Linus Torvalds20 years
v2.6.13-rc5commit 9a351e30d7...Linus Torvalds20 years
v2.6.13-rc4commit 6395352334...Linus Torvalds20 years
v2.6.11tree c39ae07f39...
v2.6.11-treetree c39ae07f39...
v2.6.12commit 9ee1c939d1...
v2.6.12-rc2commit 1da177e4c3...
v2.6.12-rc3commit a2755a80f4...
v2.6.12-rc4commit 88d7bd8cb9...
v2.6.12-rc5commit 2a24ab628a...
v2.6.12-rc6commit 7cef5677ef...
v2.6.13-rc1commit 4c91aedb75...
v2.6.13-rc2commit a18bcb7450...
v2.6.13-rc3commit c32511e271...
ass="hl num">1 << 11), RT_IDX_VLAN_FILTER = (1 << 12), RT_IDX_ETH_SKIP1 = (1 << 13), RT_IDX_ETH_SKIP2 = (1 << 14), RT_IDX_BCAST_MCAST_MATCH = (1 << 15), RT_IDX_802_3 = (1 << 16), RT_IDX_LLDP = (1 << 17), RT_IDX_UNUSED018 = (1 << 18), RT_IDX_UNUSED019 = (1 << 19), RT_IDX_UNUSED20 = (1 << 20), RT_IDX_UNUSED21 = (1 << 21), RT_IDX_ERR = (1 << 22), RT_IDX_VALID = (1 << 23), RT_IDX_TU_CSUM_ERR = (1 << 24), RT_IDX_IP_CSUM_ERR = (1 << 25), RT_IDX_MAC_ERR = (1 << 26), RT_IDX_RSS_TCP6 = (1 << 27), RT_IDX_RSS_TCP4 = (1 << 28), RT_IDX_RSS_IPV6 = (1 << 29), RT_IDX_RSS_IPV4 = (1 << 30), RT_IDX_RSS_MATCH = (1 << 31), /* Hierarchy for the NIC Queue Mask */ RT_IDX_ALL_ERR_SLOT = 0, RT_IDX_MAC_ERR_SLOT = 0, RT_IDX_IP_CSUM_ERR_SLOT = 1, RT_IDX_TCP_UDP_CSUM_ERR_SLOT = 2, RT_IDX_BCAST_SLOT = 3, RT_IDX_MCAST_MATCH_SLOT = 4, RT_IDX_ALLMULTI_SLOT = 5, RT_IDX_UNUSED6_SLOT = 6, RT_IDX_UNUSED7_SLOT = 7, RT_IDX_RSS_MATCH_SLOT = 8, RT_IDX_RSS_IPV4_SLOT = 8, RT_IDX_RSS_IPV6_SLOT = 9, RT_IDX_RSS_TCP4_SLOT = 10, RT_IDX_RSS_TCP6_SLOT = 11, RT_IDX_CAM_HIT_SLOT = 12, RT_IDX_UNUSED013 = 13, RT_IDX_UNUSED014 = 14, RT_IDX_PROMISCUOUS_SLOT = 15, RT_IDX_MAX_SLOTS = 16, }; /* * Control Register Set Map */ enum { PROC_ADDR = 0, /* Use semaphore */ PROC_DATA = 0x04, /* Use semaphore */ SYS = 0x08, RST_FO = 0x0c, FSC = 0x10, CSR = 0x14, LED = 0x18, ICB_RID = 0x1c, /* Use semaphore */ ICB_L = 0x20, /* Use semaphore */ ICB_H = 0x24, /* Use semaphore */ CFG = 0x28, BIOS_ADDR = 0x2c, STS = 0x30, INTR_EN = 0x34, INTR_MASK = 0x38, ISR1 = 0x3c, ISR2 = 0x40, ISR3 = 0x44, ISR4 = 0x48, REV_ID = 0x4c, FRC_ECC_ERR = 0x50, ERR_STS = 0x54, RAM_DBG_ADDR = 0x58, RAM_DBG_DATA = 0x5c, ECC_ERR_CNT = 0x60, SEM = 0x64, GPIO_1 = 0x68, /* Use semaphore */ GPIO_2 = 0x6c, /* Use semaphore */ GPIO_3 = 0x70, /* Use semaphore */ RSVD2 = 0x74, XGMAC_ADDR = 0x78, /* Use semaphore */ XGMAC_DATA = 0x7c, /* Use semaphore */ NIC_ETS = 0x80, CNA_ETS = 0x84, FLASH_ADDR = 0x88, /* Use semaphore */ FLASH_DATA = 0x8c, /* Use semaphore */ CQ_STOP = 0x90, PAGE_TBL_RID = 0x94, WQ_PAGE_TBL_LO = 0x98, WQ_PAGE_TBL_HI = 0x9c, CQ_PAGE_TBL_LO = 0xa0, CQ_PAGE_TBL_HI = 0xa4, MAC_ADDR_IDX = 0xa8, /* Use semaphore */ MAC_ADDR_DATA = 0xac, /* Use semaphore */ COS_DFLT_CQ1 = 0xb0, COS_DFLT_CQ2 = 0xb4, ETYPE_SKIP1 = 0xb8, ETYPE_SKIP2 = 0xbc, SPLT_HDR = 0xc0, FC_PAUSE_THRES = 0xc4, NIC_PAUSE_THRES = 0xc8, FC_ETHERTYPE = 0xcc, FC_RCV_CFG = 0xd0, NIC_RCV_CFG = 0xd4, FC_COS_TAGS = 0xd8, NIC_COS_TAGS = 0xdc, MGMT_RCV_CFG = 0xe0, RT_IDX = 0xe4, RT_DATA = 0xe8, RSVD7 = 0xec, XG_SERDES_ADDR = 0xf0, XG_SERDES_DATA = 0xf4, PRB_MX_ADDR = 0xf8, /* Use semaphore */ PRB_MX_DATA = 0xfc, /* Use semaphore */ }; /* * CAM output format. */ enum { CAM_OUT_ROUTE_FC = 0, CAM_OUT_ROUTE_NIC = 1, CAM_OUT_FUNC_SHIFT = 2, CAM_OUT_RV = (1 << 4), CAM_OUT_SH = (1 << 15), CAM_OUT_CQ_ID_SHIFT = 5, }; /* * Mailbox definitions */ enum { /* Asynchronous Event Notifications */ AEN_SYS_ERR = 0x00008002, AEN_LINK_UP = 0x00008011, AEN_LINK_DOWN = 0x00008012, AEN_IDC_CMPLT = 0x00008100, AEN_IDC_REQ = 0x00008101, AEN_FW_INIT_DONE = 0x00008400, AEN_FW_INIT_FAIL = 0x00008401, /* Mailbox Command Opcodes. */ MB_CMD_NOP = 0x00000000, MB_CMD_EX_FW = 0x00000002, MB_CMD_MB_TEST = 0x00000006, MB_CMD_CSUM_TEST = 0x00000007, /* Verify Checksum */ MB_CMD_ABOUT_FW = 0x00000008, MB_CMD_LOAD_RISC_RAM = 0x0000000b, MB_CMD_DUMP_RISC_RAM = 0x0000000c, MB_CMD_WRITE_RAM = 0x0000000d, MB_CMD_READ_RAM = 0x0000000f, MB_CMD_STOP_FW = 0x00000014, MB_CMD_MAKE_SYS_ERR = 0x0000002a, MB_CMD_INIT_FW = 0x00000060, MB_CMD_GET_INIT_CB = 0x00000061, MB_CMD_GET_FW_STATE = 0x00000069, MB_CMD_IDC_REQ = 0x00000100, /* Inter-Driver Communication */ MB_CMD_IDC_ACK = 0x00000101, /* Inter-Driver Communication */ MB_CMD_SET_WOL_MODE = 0x00000110, /* Wake On Lan */ MB_WOL_DISABLE = 0x00000000, MB_WOL_MAGIC_PKT = 0x00000001, MB_WOL_FLTR = 0x00000002, MB_WOL_UCAST = 0x00000004, MB_WOL_MCAST = 0x00000008, MB_WOL_BCAST = 0x00000010, MB_WOL_LINK_UP = 0x00000020, MB_WOL_LINK_DOWN = 0x00000040, MB_CMD_SET_WOL_FLTR = 0x00000111, /* Wake On Lan Filter */ MB_CMD_CLEAR_WOL_FLTR = 0x00000112, /* Wake On Lan Filter */ MB_CMD_SET_WOL_MAGIC = 0x00000113, /* Wake On Lan Magic Packet */ MB_CMD_CLEAR_WOL_MAGIC = 0x00000114, /* Wake On Lan Magic Packet */ MB_CMD_PORT_RESET = 0x00000120, MB_CMD_SET_PORT_CFG = 0x00000122, MB_CMD_GET_PORT_CFG = 0x00000123, MB_CMD_SET_ASIC_VOLTS = 0x00000130, MB_CMD_GET_SNS_DATA = 0x00000131, /* Temp and Volt Sense data. */ /* Mailbox Command Status. */ MB_CMD_STS_GOOD = 0x00004000, /* Success. */ MB_CMD_STS_INTRMDT = 0x00001000, /* Intermediate Complete. */ MB_CMD_STS_ERR = 0x00004005, /* Error. */ }; struct mbox_params { u32 mbox_in[MAILBOX_COUNT]; u32 mbox_out[MAILBOX_COUNT]; int in_count; int out_count; }; struct flash_params { u8 dev_id_str[4]; u16 size; u16 csum; u16 ver; u16 sub_dev_id; u8 mac_addr[6]; u16 res; }; /* * doorbell space for the rx ring context */ struct rx_doorbell_context { u32 cnsmr_idx; /* 0x00 */ u32 valid; /* 0x04 */ u32 reserved[4]; /* 0x08-0x14 */ u32 lbq_prod_idx; /* 0x18 */ u32 sbq_prod_idx; /* 0x1c */ }; /* * doorbell space for the tx ring context */ struct tx_doorbell_context { u32 prod_idx; /* 0x00 */ u32 valid; /* 0x04 */ u32 reserved[4]; /* 0x08-0x14 */ u32 lbq_prod_idx; /* 0x18 */ u32 sbq_prod_idx; /* 0x1c */ }; /* DATA STRUCTURES SHARED WITH HARDWARE. */ struct bq_element { u32 addr_lo; #define BQ_END 0x00000001 #define BQ_CONT 0x00000002 #define BQ_MASK 0x00000003 u32 addr_hi; } __attribute((packed)); struct tx_buf_desc { __le64 addr; __le32 len; #define TX_DESC_LEN_MASK 0x000fffff #define TX_DESC_C 0x40000000 #define TX_DESC_E 0x80000000 } __attribute((packed)); /* * IOCB Definitions... */ #define OPCODE_OB_MAC_IOCB 0x01 #define OPCODE_OB_MAC_TSO_IOCB 0x02 #define OPCODE_IB_MAC_IOCB 0x20 #define OPCODE_IB_MPI_IOCB 0x21 #define OPCODE_IB_AE_IOCB 0x3f struct ob_mac_iocb_req { u8 opcode; u8 flags1; #define OB_MAC_IOCB_REQ_OI 0x01 #define OB_MAC_IOCB_REQ_I 0x02 #define OB_MAC_IOCB_REQ_D 0x08 #define OB_MAC_IOCB_REQ_F 0x10 u8 flags2; u8 flags3; #define OB_MAC_IOCB_DFP 0x02 #define OB_MAC_IOCB_V 0x04 __le32 reserved1[2]; __le16 frame_len; #define OB_MAC_IOCB_LEN_MASK 0x3ffff __le16 reserved2; __le32 tid; __le32 txq_idx; __le32 reserved3; __le16 vlan_tci; __le16 reserved4; struct tx_buf_desc tbd[TX_DESC_PER_IOCB]; } __attribute((packed)); struct ob_mac_iocb_rsp { u8 opcode; /* */ u8 flags1; /* */ #define OB_MAC_IOCB_RSP_OI 0x01 /* */ #define OB_MAC_IOCB_RSP_I 0x02 /* */ #define OB_MAC_IOCB_RSP_E 0x08 /* */ #define OB_MAC_IOCB_RSP_S 0x10 /* too Short */ #define OB_MAC_IOCB_RSP_L 0x20 /* too Large */ #define OB_MAC_IOCB_RSP_P 0x40 /* Padded */ u8 flags2; /* */ u8 flags3; /* */ #define OB_MAC_IOCB_RSP_B 0x80 /* */ __le32 tid; __le32 txq_idx; __le32 reserved[13]; } __attribute((packed)); struct ob_mac_tso_iocb_req { u8 opcode; u8 flags1; #define OB_MAC_TSO_IOCB_OI 0x01 #define OB_MAC_TSO_IOCB_I 0x02 #define OB_MAC_TSO_IOCB_D 0x08 #define OB_MAC_TSO_IOCB_IP4 0x40 #define OB_MAC_TSO_IOCB_IP6 0x80 u8 flags2; #define OB_MAC_TSO_IOCB_LSO 0x20 #define OB_MAC_TSO_IOCB_UC 0x40 #define OB_MAC_TSO_IOCB_TC 0x80 u8 flags3; #define OB_MAC_TSO_IOCB_IC 0x01 #define OB_MAC_TSO_IOCB_DFP 0x02 #define OB_MAC_TSO_IOCB_V 0x04 __le32 reserved1[2]; __le32 frame_len; __le32 tid; __le32 txq_idx; __le16 total_hdrs_len; __le16 net_trans_offset; #define OB_MAC_TRANSPORT_HDR_SHIFT 6 __le16 vlan_tci; __le16 mss; struct tx_buf_desc tbd[TX_DESC_PER_IOCB]; } __attribute((packed)); struct ob_mac_tso_iocb_rsp { u8 opcode; u8 flags1; #define OB_MAC_TSO_IOCB_RSP_OI 0x01 #define OB_MAC_TSO_IOCB_RSP_I 0x02 #define OB_MAC_TSO_IOCB_RSP_E 0x08 #define OB_MAC_TSO_IOCB_RSP_S 0x10 #define OB_MAC_TSO_IOCB_RSP_L 0x20 #define OB_MAC_TSO_IOCB_RSP_P 0x40 u8 flags2; /* */ u8 flags3; /* */ #define OB_MAC_TSO_IOCB_RSP_B 0x8000 __le32 tid; __le32 txq_idx; __le32 reserved2[13]; } __attribute((packed)); struct ib_mac_iocb_rsp { u8 opcode; /* 0x20 */ u8 flags1; #define IB_MAC_IOCB_RSP_OI 0x01 /* Overide intr delay */ #define IB_MAC_IOCB_RSP_I 0x02 /* Disble Intr Generation */ #define IB_MAC_IOCB_RSP_TE 0x04 /* Checksum error */ #define IB_MAC_IOCB_RSP_NU 0x08 /* No checksum rcvd */ #define IB_MAC_IOCB_RSP_IE 0x10 /* IPv4 checksum error */ #define IB_MAC_IOCB_RSP_M_MASK 0x60 /* Multicast info */ #define IB_MAC_IOCB_RSP_M_NONE 0x00 /* Not mcast frame */ #define IB_MAC_IOCB_RSP_M_HASH 0x20 /* HASH mcast frame */ #define IB_MAC_IOCB_RSP_M_REG 0x40 /* Registered mcast frame */ #define IB_MAC_IOCB_RSP_M_PROM 0x60 /* Promiscuous mcast frame */ #define IB_MAC_IOCB_RSP_B 0x80 /* Broadcast frame */ u8 flags2; #define IB_MAC_IOCB_RSP_P 0x01 /* Promiscuous frame */ #define IB_MAC_IOCB_RSP_V 0x02 /* Vlan tag present */ #define IB_MAC_IOCB_RSP_ERR_MASK 0x1c /* */ #define IB_MAC_IOCB_RSP_ERR_CODE_ERR 0x04 #define IB_MAC_IOCB_RSP_ERR_OVERSIZE 0x08 #define IB_MAC_IOCB_RSP_ERR_UNDERSIZE 0x10 #define IB_MAC_IOCB_RSP_ERR_PREAMBLE 0x14 #define IB_MAC_IOCB_RSP_ERR_FRAME_LEN 0x18 #define IB_MAC_IOCB_RSP_ERR_CRC 0x1c #define IB_MAC_IOCB_RSP_U 0x20 /* UDP packet */ #define IB_MAC_IOCB_RSP_T 0x40 /* TCP packet */ #define IB_MAC_IOCB_RSP_FO 0x80 /* Failover port */ u8 flags3; #define IB_MAC_IOCB_RSP_RSS_MASK 0x07 /* RSS mask */ #define IB_MAC_IOCB_RSP_M_NONE 0x00 /* No RSS match */ #define IB_MAC_IOCB_RSP_M_IPV4 0x04 /* IPv4 RSS match */ #define IB_MAC_IOCB_RSP_M_IPV6 0x02 /* IPv6 RSS match */ #define IB_MAC_IOCB_RSP_M_TCP_V4 0x05 /* TCP with IPv4 */ #define IB_MAC_IOCB_RSP_M_TCP_V6 0x03 /* TCP with IPv6 */ #define IB_MAC_IOCB_RSP_V4 0x08 /* IPV4 */ #define IB_MAC_IOCB_RSP_V6 0x10 /* IPV6 */ #define IB_MAC_IOCB_RSP_IH 0x20 /* Split after IP header */ #define IB_MAC_IOCB_RSP_DS 0x40 /* data is in small buffer */ #define IB_MAC_IOCB_RSP_DL 0x80 /* data is in large buffer */ __le32 data_len; /* */ __le32 data_addr_lo; /* */ __le32 data_addr_hi; /* */ __le32 rss; /* */ __le16 vlan_id; /* 12 bits */ #define IB_MAC_IOCB_RSP_C 0x1000 /* VLAN CFI bit */ #define IB_MAC_IOCB_RSP_COS_SHIFT 12 /* class of service value */ __le16 reserved1; __le32 reserved2[6]; __le32 flags4; #define IB_MAC_IOCB_RSP_HV 0x20000000 /* */ #define IB_MAC_IOCB_RSP_HS 0x40000000 /* */ #define IB_MAC_IOCB_RSP_HL 0x80000000 /* */ __le32 hdr_len; /* */ __le32 hdr_addr_lo; /* */ __le32 hdr_addr_hi; /* */ } __attribute((packed)); struct ib_ae_iocb_rsp { u8 opcode; u8 flags1; #define IB_AE_IOCB_RSP_OI 0x01 #define IB_AE_IOCB_RSP_I 0x02 u8 event; #define LINK_UP_EVENT 0x00 #define LINK_DOWN_EVENT 0x01 #define CAM_LOOKUP_ERR_EVENT 0x06 #define SOFT_ECC_ERROR_EVENT 0x07 #define MGMT_ERR_EVENT 0x08 #define TEN_GIG_MAC_EVENT 0x09 #define GPI0_H2L_EVENT 0x10 #define GPI0_L2H_EVENT 0x20 #define GPI1_H2L_EVENT 0x11 #define GPI1_L2H_EVENT 0x21 #define PCI_ERR_ANON_BUF_RD 0x40 u8 q_id; __le32 reserved[15]; } __attribute((packed)); /* * These three structures are for generic * handling of ib and ob iocbs. */ struct ql_net_rsp_iocb { u8 opcode; u8 flags0; __le16 length; __le32 tid; __le32 reserved[14]; } __attribute((packed)); struct net_req_iocb { u8 opcode; u8 flags0; __le16 flags1; __le32 tid; __le32 reserved1[30]; } __attribute((packed)); /* * tx ring initialization control block for chip. * It is defined as: * "Work Queue Initialization Control Block" */ struct wqicb { __le16 len; #define Q_LEN_V (1 << 4) #define Q_LEN_CPP_CONT 0x0000 #define Q_LEN_CPP_16 0x0001 #define Q_LEN_CPP_32 0x0002 #define Q_LEN_CPP_64 0x0003 __le16 flags; #define Q_PRI_SHIFT 1 #define Q_FLAGS_LC 0x1000 #define Q_FLAGS_LB 0x2000 #define Q_FLAGS_LI 0x4000 #define Q_FLAGS_LO 0x8000 __le16 cq_id_rss; #define Q_CQ_ID_RSS_RV 0x8000 __le16 rid; __le32 addr_lo; __le32 addr_hi; __le32 cnsmr_idx_addr_lo; __le32 cnsmr_idx_addr_hi; } __attribute((packed)); /* * rx ring initialization control block for chip. * It is defined as: * "Completion Queue Initialization Control Block" */ struct cqicb { u8 msix_vect; u8 reserved1; u8 reserved2; u8 flags; #define FLAGS_LV 0x08 #define FLAGS_LS 0x10 #define FLAGS_LL 0x20 #define FLAGS_LI 0x40 #define FLAGS_LC 0x80 __le16 len; #define LEN_V (1 << 4) #define LEN_CPP_CONT 0x0000 #define LEN_CPP_32 0x0001 #define LEN_CPP_64 0x0002 #define LEN_CPP_128 0x0003 __le16 rid; __le32 addr_lo; __le32 addr_hi; __le32 prod_idx_addr_lo; __le32 prod_idx_addr_hi; __le16 pkt_delay; __le16 irq_delay; __le32 lbq_addr_lo; __le32 lbq_addr_hi; __le16 lbq_buf_size; __le16 lbq_len; /* entry count */ __le32 sbq_addr_lo; __le32 sbq_addr_hi; __le16 sbq_buf_size; __le16 sbq_len; /* entry count */ } __attribute((packed)); struct ricb { u8 base_cq; #define RSS_L4K 0x80 u8 flags; #define RSS_L6K 0x01 #define RSS_LI 0x02 #define RSS_LB 0x04 #define RSS_LM 0x08 #define RSS_RI4 0x10 #define RSS_RT4 0x20 #define RSS_RI6 0x40 #define RSS_RT6 0x80 __le16 mask; __le32 hash_cq_id[256]; __le32 ipv6_hash_key[10]; __le32 ipv4_hash_key[4]; } __attribute((packed)); /* SOFTWARE/DRIVER DATA STRUCTURES. */ struct oal { struct tx_buf_desc oal[TX_DESC_PER_OAL]; }; struct map_list { DECLARE_PCI_UNMAP_ADDR(mapaddr); DECLARE_PCI_UNMAP_LEN(maplen); }; struct tx_ring_desc { struct sk_buff *skb; struct ob_mac_iocb_req *queue_entry; int index; struct oal oal; struct map_list map[MAX_SKB_FRAGS + 1]; int map_cnt; struct tx_ring_desc *next; }; struct bq_desc { union { struct page *lbq_page; struct sk_buff *skb; } p; struct bq_element *bq; int index; DECLARE_PCI_UNMAP_ADDR(mapaddr); DECLARE_PCI_UNMAP_LEN(maplen); }; #define QL_TXQ_IDX(qdev, skb) (smp_processor_id()%(qdev->tx_ring_count)) struct tx_ring { /* * queue info. */ struct wqicb wqicb; /* structure used to inform chip of new queue */ void *wq_base; /* pci_alloc:virtual addr for tx */ dma_addr_t wq_base_dma; /* pci_alloc:dma addr for tx */ u32 *cnsmr_idx_sh_reg; /* shadow copy of consumer idx */ dma_addr_t cnsmr_idx_sh_reg_dma; /* dma-shadow copy of consumer */ u32 wq_size; /* size in bytes of queue area */ u32 wq_len; /* number of entries in queue */ void __iomem *prod_idx_db_reg; /* doorbell area index reg at offset 0x00 */ void __iomem *valid_db_reg; /* doorbell area valid reg at offset 0x04 */ u16 prod_idx; /* current value for prod idx */ u16 cq_id; /* completion (rx) queue for tx completions */ u8 wq_id; /* queue id for this entry */ u8 reserved1[3]; struct tx_ring_desc *q; /* descriptor list for the queue */ spinlock_t lock; atomic_t tx_count; /* counts down for every outstanding IO */ atomic_t queue_stopped; /* Turns queue off when full. */ struct delayed_work tx_work; struct ql_adapter *qdev; }; /* * Type of inbound queue. */ enum { DEFAULT_Q = 2, /* Handles slow queue and chip/MPI events. */ TX_Q = 3, /* Handles outbound completions. */ RX_Q = 4, /* Handles inbound completions. */ }; struct rx_ring { struct cqicb cqicb; /* The chip's completion queue init control block. */ /* Completion queue elements. */ void *cq_base; dma_addr_t cq_base_dma; u32 cq_size; u32 cq_len; u16 cq_id; u32 *prod_idx_sh_reg; /* Shadowed producer register. */ dma_addr_t prod_idx_sh_reg_dma; void __iomem *cnsmr_idx_db_reg; /* PCI doorbell mem area + 0 */ u32 cnsmr_idx; /* current sw idx */ struct ql_net_rsp_iocb *curr_entry; /* next entry on queue */ void __iomem *valid_db_reg; /* PCI doorbell mem area + 0x04 */ /* Large buffer queue elements. */ u32 lbq_len; /* entry count */ u32 lbq_size; /* size in bytes of queue */ u32 lbq_buf_size; void *lbq_base; dma_addr_t lbq_base_dma; void *lbq_base_indirect; dma_addr_t lbq_base_indirect_dma; struct bq_desc *lbq; /* array of control blocks */ void __iomem *lbq_prod_idx_db_reg; /* PCI doorbell mem area + 0x18 */ u32 lbq_prod_idx; /* current sw prod idx */ u32 lbq_curr_idx; /* next entry we expect */ u32 lbq_clean_idx; /* beginning of new descs */ u32 lbq_free_cnt; /* free buffer desc cnt */ /* Small buffer queue elements. */ u32 sbq_len; /* entry count */ u32 sbq_size; /* size in bytes of queue */ u32 sbq_buf_size; void *sbq_base; dma_addr_t sbq_base_dma; void *sbq_base_indirect; dma_addr_t sbq_base_indirect_dma; struct bq_desc *sbq; /* array of control blocks */ void __iomem *sbq_prod_idx_db_reg; /* PCI doorbell mem area + 0x1c */ u32 sbq_prod_idx; /* current sw prod idx */ u32 sbq_curr_idx; /* next entry we expect */ u32 sbq_clean_idx; /* beginning of new descs */ u32 sbq_free_cnt; /* free buffer desc cnt */ /* Misc. handler elements. */ u32 type; /* Type of queue, tx, rx, or default. */ u32 irq; /* Which vector this ring is assigned. */ u32 cpu; /* Which CPU this should run on. */ char name[IFNAMSIZ + 5]; struct napi_struct napi; struct delayed_work rx_work; u8 reserved; struct ql_adapter *qdev; }; /* * RSS Initialization Control Block */ struct hash_id { u8 value[4]; }; struct nic_stats { /* * These stats come from offset 200h to 278h * in the XGMAC register. */ u64 tx_pkts; u64 tx_bytes; u64 tx_mcast_pkts; u64 tx_bcast_pkts; u64 tx_ucast_pkts; u64 tx_ctl_pkts; u64 tx_pause_pkts; u64 tx_64_pkt; u64 tx_65_to_127_pkt; u64 tx_128_to_255_pkt; u64 tx_256_511_pkt; u64 tx_512_to_1023_pkt; u64 tx_1024_to_1518_pkt; u64 tx_1519_to_max_pkt; u64 tx_undersize_pkt; u64 tx_oversize_pkt; /* * These stats come from offset 300h to 3C8h * in the XGMAC register. */ u64 rx_bytes; u64 rx_bytes_ok; u64 rx_pkts; u64 rx_pkts_ok; u64 rx_bcast_pkts; u64 rx_mcast_pkts; u64 rx_ucast_pkts; u64 rx_undersize_pkts; u64 rx_oversize_pkts; u64 rx_jabber_pkts; u64 rx_undersize_fcerr_pkts; u64 rx_drop_events; u64 rx_fcerr_pkts; u64 rx_align_err; u64 rx_symbol_err; u64 rx_mac_err; u64 rx_ctl_pkts; u64 rx_pause_pkts; u64 rx_64_pkts; u64 rx_65_to_127_pkts; u64 rx_128_255_pkts; u64 rx_256_511_pkts; u64 rx_512_to_1023_pkts; u64 rx_1024_to_1518_pkts; u64 rx_1519_to_max_pkts; u64 rx_len_err_pkts; }; /* * intr_context structure is used during initialization * to hook the interrupts. It is also used in a single * irq environment as a context to the ISR. */ struct intr_context { struct ql_adapter *qdev; u32 intr; u32 hooked; u32 intr_en_mask; /* value/mask used to enable this intr */ u32 intr_dis_mask; /* value/mask used to disable this intr */ u32 intr_read_mask; /* value/mask used to read this intr */ char name[IFNAMSIZ * 2]; atomic_t irq_cnt; /* irq_cnt is used in single vector * environment. It's incremented for each * irq handler that is scheduled. When each * handler finishes it decrements irq_cnt and * enables interrupts if it's zero. */ irq_handler_t handler; }; /* adapter flags definitions. */ enum { QL_ADAPTER_UP = (1 << 0), /* Adapter has been brought up. */ QL_LEGACY_ENABLED = (1 << 3), QL_MSI_ENABLED = (1 << 3), QL_MSIX_ENABLED = (1 << 4), QL_DMA64 = (1 << 5), QL_PROMISCUOUS = (1 << 6), QL_ALLMULTI = (1 << 7), }; /* link_status bit definitions */ enum { LOOPBACK_MASK = 0x00000700, LOOPBACK_PCS = 0x00000100, LOOPBACK_HSS = 0x00000200, LOOPBACK_EXT = 0x00000300, PAUSE_MASK = 0x000000c0, PAUSE_STD = 0x00000040, PAUSE_PRI = 0x00000080, SPEED_MASK = 0x00000038, SPEED_100Mb = 0x00000000, SPEED_1Gb = 0x00000008, SPEED_10Gb = 0x00000010, LINK_TYPE_MASK = 0x00000007, LINK_TYPE_XFI = 0x00000001, LINK_TYPE_XAUI = 0x00000002, LINK_TYPE_XFI_BP = 0x00000003, LINK_TYPE_XAUI_BP = 0x00000004, LINK_TYPE_10GBASET = 0x00000005, }; /* * The main Adapter structure definition. * This structure has all fields relevant to the hardware. */ struct ql_adapter { struct ricb ricb; unsigned long flags; u32 wol; struct nic_stats nic_stats; struct vlan_group *vlgrp; /* PCI Configuration information for this device */ struct pci_dev *pdev; struct net_device *ndev; /* Parent NET device */ /* Hardware information */ u32 chip_rev_id; u32 func; /* PCI function for this adapter */ spinlock_t adapter_lock; spinlock_t hw_lock; spinlock_t stats_lock; spinlock_t legacy_lock; /* used for maintaining legacy intr sync */ /* PCI Bus Relative Register Addresses */ void __iomem *reg_base; void __iomem *doorbell_area; u32 doorbell_area_size; u32 msg_enable; /* Page for Shadow Registers */ void *rx_ring_shadow_reg_area; dma_addr_t rx_ring_shadow_reg_dma; void *tx_ring_shadow_reg_area; dma_addr_t tx_ring_shadow_reg_dma; u32 mailbox_in; u32 mailbox_out; int tx_ring_size; int rx_ring_size; u32 intr_count; struct msix_entry *msi_x_entry; struct intr_context intr_context[MAX_RX_RINGS]; int (*legacy_check) (struct ql_adapter *); int tx_ring_count; /* One per online CPU. */ u32 rss_ring_first_cq_id;/* index of first inbound (rss) rx_ring */ u32 rss_ring_count; /* One per online CPU. */ /* * rx_ring_count = * one default queue + * (CPU count * outbound completion rx_ring) + * (CPU count * inbound (RSS) completion rx_ring) */ int rx_ring_count; int ring_mem_size; void *ring_mem; struct rx_ring *rx_ring; int rx_csum; struct tx_ring *tx_ring; u32 default_rx_queue; u16 rx_coalesce_usecs; /* cqicb->int_delay */ u16 rx_max_coalesced_frames; /* cqicb->pkt_int_delay */ u16 tx_coalesce_usecs; /* cqicb->int_delay */ u16 tx_max_coalesced_frames; /* cqicb->pkt_int_delay */ u32 xg_sem_mask; u32 port_link_up; u32 port_init; u32 link_status; struct flash_params flash; struct net_device_stats stats; struct workqueue_struct *q_workqueue; struct workqueue_struct *workqueue; struct delayed_work asic_reset_work; struct delayed_work mpi_reset_work; struct delayed_work mpi_work; }; /* * Typical Register accessor for memory mapped device. */ static inline u32 ql_read32(const struct ql_adapter *qdev, int reg) { return readl(qdev->reg_base + reg); } /* * Typical Register accessor for memory mapped device. */ static inline void ql_write32(const struct ql_adapter *qdev, int reg, u32 val) { writel(val, qdev->reg_base + reg); } /* * Doorbell Registers: * Doorbell registers are virtual registers in the PCI memory space. * The space is allocated by the chip during PCI initialization. The * device driver finds the doorbell address in BAR 3 in PCI config space. * The registers are used to control outbound and inbound queues. For * example, the producer index for an outbound queue. Each queue uses * 1 4k chunk of memory. The lower half of the space is for outbound * queues. The upper half is for inbound queues. */ static inline void ql_write_db_reg(u32 val, void __iomem *addr) { writel(val, addr); mmiowb(); } /* * Shadow Registers: * Outbound queues have a consumer index that is maintained by the chip. * Inbound queues have a producer index that is maintained by the chip. * For lower overhead, these registers are "shadowed" to host memory * which allows the device driver to track the queue progress without * PCI reads. When an entry is placed on an inbound queue, the chip will * update the relevant index register and then copy the value to the * shadow register in host memory. */ static inline unsigned int ql_read_sh_reg(const volatile void *addr) { return *(volatile unsigned int __force *)addr; } extern char qlge_driver_name[]; extern const char qlge_driver_version[]; extern const struct ethtool_ops qlge_ethtool_ops; extern int ql_sem_spinlock(struct ql_adapter *qdev, u32 sem_mask); extern void ql_sem_unlock(struct ql_adapter *qdev, u32 sem_mask); extern int ql_read_xgmac_reg(struct ql_adapter *qdev, u32 reg, u32 *data); extern int ql_get_mac_addr_reg(struct ql_adapter *qdev, u32 type, u16 index, u32 *value); extern int ql_get_routing_reg(struct ql_adapter *qdev, u32 index, u32 *value); extern int ql_write_cfg(struct ql_adapter *qdev, void *ptr, int size, u32 bit, u16 q_id); void ql_queue_fw_error(struct ql_adapter *qdev); void ql_mpi_work(struct work_struct *work); void ql_mpi_reset_work(struct work_struct *work); int ql_wait_reg_rdy(struct ql_adapter *qdev, u32 reg, u32 bit, u32 ebit); void ql_queue_asic_error(struct ql_adapter *qdev); void ql_enable_completion_interrupt(struct ql_adapter *qdev, u32 intr); void ql_set_ethtool_ops(struct net_device *ndev); int ql_read_xgmac_reg64(struct ql_adapter *qdev, u32 reg, u64 *data); #if 1 #define QL_ALL_DUMP #define QL_REG_DUMP #define QL_DEV_DUMP #define QL_CB_DUMP /* #define QL_IB_DUMP */ /* #define QL_OB_DUMP */ #endif #ifdef QL_REG_DUMP extern void ql_dump_xgmac_control_regs(struct ql_adapter *qdev); extern void ql_dump_routing_entries(struct ql_adapter *qdev); extern void ql_dump_regs(struct ql_adapter *qdev); #define QL_DUMP_REGS(qdev) ql_dump_regs(qdev) #define QL_DUMP_ROUTE(qdev) ql_dump_routing_entries(qdev) #define QL_DUMP_XGMAC_CONTROL_REGS(qdev) ql_dump_xgmac_control_regs(qdev) #else #define QL_DUMP_REGS(qdev) #define QL_DUMP_ROUTE(qdev) #define QL_DUMP_XGMAC_CONTROL_REGS(qdev) #endif #ifdef QL_STAT_DUMP extern void ql_dump_stat(struct ql_adapter *qdev); #define QL_DUMP_STAT(qdev) ql_dump_stat(qdev) #else #define QL_DUMP_STAT(qdev) #endif #ifdef QL_DEV_DUMP extern void ql_dump_qdev(struct ql_adapter *qdev); #define QL_DUMP_QDEV(qdev) ql_dump_qdev(qdev) #else #define QL_DUMP_QDEV(qdev) #endif #ifdef QL_CB_DUMP extern void ql_dump_wqicb(struct wqicb *wqicb); extern void ql_dump_tx_ring(struct tx_ring *tx_ring); extern void ql_dump_ricb(struct ricb *ricb); extern void ql_dump_cqicb(struct cqicb *cqicb); extern void ql_dump_rx_ring(struct rx_ring *rx_ring); extern void ql_dump_hw_cb(struct ql_adapter *qdev, int size, u32 bit, u16 q_id); #define QL_DUMP_RICB(ricb) ql_dump_ricb(ricb) #define QL_DUMP_WQICB(wqicb) ql_dump_wqicb(wqicb) #define QL_DUMP_TX_RING(tx_ring) ql_dump_tx_ring(tx_ring) #define QL_DUMP_CQICB(cqicb) ql_dump_cqicb(cqicb) #define QL_DUMP_RX_RING(rx_ring) ql_dump_rx_ring(rx_ring) #define QL_DUMP_HW_CB(qdev, size, bit, q_id) \ ql_dump_hw_cb(qdev, size, bit, q_id) #else #define QL_DUMP_RICB(ricb) #define QL_DUMP_WQICB(wqicb) #define QL_DUMP_TX_RING(tx_ring) #define QL_DUMP_CQICB(cqicb) #define QL_DUMP_RX_RING(rx_ring) #define QL_DUMP_HW_CB(qdev, size, bit, q_id) #endif #ifdef QL_OB_DUMP extern void ql_dump_tx_desc(struct tx_buf_desc *tbd); extern void ql_dump_ob_mac_iocb(struct ob_mac_iocb_req *ob_mac_iocb); extern void ql_dump_ob_mac_rsp(struct ob_mac_iocb_rsp *ob_mac_rsp); #define QL_DUMP_OB_MAC_IOCB(ob_mac_iocb) ql_dump_ob_mac_iocb(ob_mac_iocb) #define QL_DUMP_OB_MAC_RSP(ob_mac_rsp) ql_dump_ob_mac_rsp(ob_mac_rsp) #else #define QL_DUMP_OB_MAC_IOCB(ob_mac_iocb) #define QL_DUMP_OB_MAC_RSP(ob_mac_rsp) #endif #ifdef QL_IB_DUMP extern void ql_dump_ib_mac_rsp(struct ib_mac_iocb_rsp *ib_mac_rsp); #define QL_DUMP_IB_MAC_RSP(ib_mac_rsp) ql_dump_ib_mac_rsp(ib_mac_rsp) #else #define QL_DUMP_IB_MAC_RSP(ib_mac_rsp) #endif #ifdef QL_ALL_DUMP extern void ql_dump_all(struct ql_adapter *qdev); #define QL_DUMP_ALL(qdev) ql_dump_all(qdev) #else #define QL_DUMP_ALL(qdev) #endif #endif /* _QLGE_H_ */