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BranchCommit messageAuthorAge
archive/unc-master-3.0P-FP: fix BUG_ON releated to priority inheritanceBjoern Brandenburg13 years
archived-2013.1uncachedev: mmap memory that is not cached by CPUsGlenn Elliott12 years
archived-private-masterMerge branch 'wip-2.6.34' into old-private-masterAndrea Bastoni15 years
archived-semi-partMerge branch 'wip-semi-part' of ssh://cvs/cvs/proj/litmus/repo/litmus2010 int...Andrea Bastoni15 years
demoFurther refinementsJonathan Herman14 years
ecrts-pgm-finalMerge branch 'wip-ecrts14-pgm' of ssh://rtsrv.cs.unc.edu/home/litmus/litmus-r...Glenn Elliott12 years
ecrts14-pgm-finalMerge branch 'wip-ecrts14-pgm' of ssh://rtsrv.cs.unc.edu/home/litmus/litmus-r...Glenn Elliott12 years
gpusync-rtss12Final GPUSync implementation.Glenn Elliott12 years
gpusync/stagingRename IKGLP R2DGLP.Glenn Elliott12 years
linux-tipMerge branch 'slab/urgent' of git://git.kernel.org/pub/scm/linux/kernel/git/p...Linus Torvalds15 years
litmus2008-patch-seriesadd i386 feather-trace implementationBjoern B. Brandenburg16 years
masterPSN-EDF: use inferred_sporadic_job_release_atBjoern Brandenburg9 years
pgmmake it compileGlenn Elliott12 years
prop/litmus-signalsInfrastructure for Litmus signals.Glenn Elliott13 years
prop/robust-tie-breakFixed bug in edf_higher_prio().Glenn Elliott13 years
stagingFix tracepoint compilation errorFelipe Cerqueira13 years
test9/23/2016Namhoon Kim9 years
tracing-develTest kernel tracing events capabilitiesAndrea Bastoni16 years
v2.6.34-with-arm-patchessmsc911x: Add spinlocks around registers accessCatalin Marinas15 years
v2015.1Add ARM syscall def for get_current_budgetBjoern Brandenburg10 years
wip-2011.2-bbbLitmus core: simplify np-section protocolBjoern B. Brandenburg14 years
wip-2011.2-bbb-traceRefactor sched_trace_log_message() -> debug_trace_log_message()Andrea Bastoni14 years
wip-2012.3-gpuSOBLIV draining support for C-EDF.Glenn Elliott12 years
wip-2012.3-gpu-preportpick up last C-RM fileGlenn Elliott12 years
wip-2012.3-gpu-rtss13Fix critical bug in GPU tracker.Glenn Elliott12 years
wip-2012.3-gpu-sobliv-budget-w-ksharkProper sobliv draining and many bug fixes.Glenn Elliott12 years
wip-aedzl-finalMake it easier to compile AEDZL interfaces in liblitmus.Glenn Elliott15 years
wip-aedzl-revisedAdd sched_trace data for Apative EDZLGlenn Elliott15 years
wip-arbit-deadlineFix compilation bug.Glenn Elliott13 years
wip-aux-tasksDescription of refined aux task inheritance.Glenn Elliott13 years
wip-bbbGSN-EDF & Core: improve debug TRACE'ing for NP sectionsBjoern B. Brandenburg14 years
wip-bbb-prio-donuse correct timestampBjoern B. Brandenburg14 years
wip-better-breakImplement hash-based EDF tie-breaking.Glenn Elliott13 years
wip-binary-heapMake C-EDF work with simplified binheap_deleteGlenn Elliott13 years
wip-budgetAdded support for choices in budget policy enforcement.Glenn Elliott15 years
wip-colorSummarize schedulability with final recordJonathan Herman13 years
wip-color-jlhsched_color: Fixed two bugs causing crashing on experiment restart and a rare...Jonathan Herman13 years
wip-d10-hz1000Enable HZ=1000 on District 10Bjoern B. Brandenburg15 years
wip-default-clusteringFeature: Make default C-EDF clustering compile-time configurable.Glenn Elliott15 years
wip-dissipation-jericksoUpdate from 2.6.36 to 2.6.36.4Jeremy Erickson11 years
wip-dissipation2-jericksoUpdate 2.6.36 to 2.6.36.4Jeremy Erickson11 years
wip-ecrts14-pgmMerge branch 'wip-ecrts14-pgm' of ssh://rtsrv.cs.unc.edu/home/litmus/litmus-r...Glenn Elliott12 years
wip-edf-hsblast tested versionJonathan Herman14 years
wip-edf-osLookup table EDF-osJeremy Erickson12 years
wip-edf-tie-breakMerge branch 'wip-edf-tie-break' of ssh://rtsrv.cs.unc.edu/home/litmus/litmus...Glenn Elliott13 years
wip-edzl-critiqueUse hr_timer's active checks instead of having own flag.Glenn Elliott15 years
wip-edzl-finalImplementation of the EDZL scheduler.Glenn Elliott15 years
wip-edzl-revisedClean up comments.Glenn Elliott15 years
wip-eventsAdded support for tracing arbitrary actions.Jonathan Herman15 years
wip-extra-debugDBG: add additional tracingBjoern B. Brandenburg15 years
wip-fix-switch-jericksoAttempt to fix race condition with plugin switchingJeremy Erickson15 years
wip-fix3sched: show length of runqueue clock deactivation in /proc/sched_debugBjoern B. Brandenburg15 years
wip-fmlp-dequeueImprove FMLP queue management.Glenn Elliott14 years
wip-ft-irq-flagFeather-Trace: keep track of interrupt-related interference.Bjoern B. Brandenburg14 years
wip-gpu-cleanupEnable sched_trace log injection from userspaceGlenn Elliott13 years
wip-gpu-interruptsRemove option for threading of all softirqs.Glenn Elliott14 years
wip-gpu-rtas12Generalized GPU cost predictors + EWMA. (untested)Glenn Elliott13 years
wip-gpu-rtss12Final GPUSync implementation.Glenn Elliott13 years
wip-gpu-rtss12-srpexperimental changes to support GPUs under SRPGlenn Elliott13 years
wip-gpusync-mergeCleanup priority tracking for budget enforcement.Glenn Elliott11 years
wip-ikglpMove RSM and IKGLP imp. to own .c filesGlenn Elliott13 years
wip-k-fmlpMerge branch 'mpi-master' into wip-k-fmlpGlenn Elliott14 years
wip-kernel-coloringAdded recolor syscallNamhoon Kim7 years
wip-kernthreadsKludge work-queue processing into klitirqd.Glenn Elliott15 years
wip-klmirqd-to-auxAllow klmirqd threads to be given names.Glenn Elliott13 years
wip-ksharkMerge branch 'mpi-staging' into wip-ksharkJonathan Herman13 years
wip-litmus-3.2Merge commit 'v3.2' into litmus-stagingAndrea Bastoni13 years
wip-litmus2011.2Cleanup: Coding conformance for affinity stuff.Glenn Elliott14 years
wip-litmus3.0-2011.2Feather-Trace: keep track of interrupt-related interference.Bjoern B. Brandenburg14 years
wip-master-2.6.33-rtAvoid deadlock when switching task policy to BACKGROUND (ugly)Andrea Bastoni15 years
wip-mcRemoved ARM-specific hacks which disabled less common mixed-criticality featu...Jonathan Herman12 years
wip-mc-bipasaMC-EDF addedbipasa chattopadhyay13 years
wip-mc-jericksoSplit C/D queuesJeremy Erickson15 years
wip-mc2-cache-slackManually patched mc^2 related codeMing Yang10 years
wip-mcrit-maccosmeticMac Mollison15 years
wip-merge-3.0Prevent Linux to send IPI and queue tasks on remote CPUs.Andrea Bastoni14 years
wip-merge-v3.0Prevent Linux to send IPI and queue tasks on remote CPUs.Andrea Bastoni14 years
wip-migration-affinityNULL affinity dereference in C-EDF.Glenn Elliott14 years
wip-mmap-uncacheshare branch with othersGlenn Elliott13 years
wip-modechangeRTSS 2017 submissionNamhoon Kim8 years
wip-nested-lockingAppears to be working.Bryan Ward12 years
wip-omlp-gedfFirst implementation of G-OMLP.Glenn Elliott15 years
wip-paiSome cleanup of PAIGlenn Elliott14 years
wip-percore-lib9/21/2016Namhoon Kim9 years
wip-performanceCONFIG_DONT_PREEMPT_ON_TIE: Don't preeempt a scheduled task on priority tie.Glenn Elliott14 years
wip-pgmAdd PGM support to C-FLGlenn Elliott12 years
wip-pgm-splitFirst draft of C-FL-splitNamhoon Kim12 years
wip-pm-ovdAdd preemption-and-migration overhead tracing supportAndrea Bastoni15 years
wip-prio-inhP-EDF updated to use the generic pi framework.Glenn Elliott15 years
wip-prioq-dglBUG FIX: Support DGLs with PRIOQ_MUTEXGlenn Elliott13 years
wip-refactored-gedfGeneralizd architecture for GEDF-style scheduelrs to reduce code redundancy.Glenn Elliott15 years
wip-release-master-fixbugfix: release master CPU must signal task was pickedBjoern B. Brandenburg14 years
wip-robust-tie-breakEDF priority tie-breaks.Glenn Elliott13 years
wip-rt-ksharkMove task time accounting into the complete_job method.Jonathan Herman13 years
wip-rtas12-pgmScheduling of PGM jobs.Glenn Elliott13 years
wip-semi-partFix compile error with newer GCCJeremy Erickson12 years
wip-semi-part-edfos-jericksoUse initial CPU set by clientJeremy Erickson12 years
wip-shared-libTODO: Fix condition checks in replicate_page_move_mapping()Namhoon Kim9 years
wip-shared-lib2RTAS 2017 Submission ver.Namhoon Kim9 years
wip-shared-memInitial commit for shared libraryNamhoon Kim9 years
wip-splitting-jericksoFix release behaviorJeremy Erickson13 years
wip-splitting-omlp-jericksoBjoern's Dissertation Code with Priority DonationJeremy Erickson13 years
wip-stage-binheapAn efficient binary heap implementation.Glenn Elliott13 years
wip-sun-portDynamic memory allocation and clean exit for FeatherTraceChristopher Kenna15 years
wip-timer-tracebugfix: C-EDF, clear scheduled field of the correct CPU upon task_exitAndrea Bastoni15 years
wip-tracepointsAdd kernel-style events for sched_trace_XXX() functionsAndrea Bastoni14 years
 
TagDownloadAuthorAge
2015.1commit 8e51b37822...Bjoern Brandenburg10 years
2013.1commit bcaacec1ca...Glenn Elliott12 years
2012.3commit c158b5fbe4...Jonathan Herman13 years
2012.2commit b53c479a0f...Glenn Elliott13 years
2012.1commit 83b11ea1c6...Bjoern B. Brandenburg14 years
rtas12-mc-beta-expcommit 8e236ee20f...Christopher Kenna14 years
2011.1commit d11808b5c6...Christopher Kenna15 years
v2.6.37-rc4commit e8a7e48bb2...Linus Torvalds15 years
v2.6.37-rc3commit 3561d43fd2...Linus Torvalds15 years
v2.6.37-rc2commit e53beacd23...Linus Torvalds15 years
v2.6.37-rc1commit c8ddb2713c...Linus Torvalds15 years
v2.6.36commit f6f94e2ab1...Linus Torvalds15 years
2010.2commit 5c5456402d...Bjoern B. Brandenburg15 years
v2.6.36-rc8commit cd07202cc8...Linus Torvalds15 years
v2.6.36-rc7commit cb655d0f3d...Linus Torvalds15 years
v2.6.36-rc6commit 899611ee7d...Linus Torvalds15 years
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2010.1commit 7c1ff4c544...Andrea Bastoni15 years
v2.6.34commit e40152ee1e...Linus Torvalds15 years
v2.6.33.4commit 4640b4e7d9...Greg Kroah-Hartman15 years
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v2.6.15-rc3commit 624f54be20...Linus Torvalds20 years
v2.6.15-rc2commit 3bedff1d73...Linus Torvalds20 years
v2.6.15-rc1commit cd52d1ee9a...Linus Torvalds20 years
v2.6.14commit 741b2252a5...Linus Torvalds20 years
v2.6.14-rc5commit 93918e9afc...Linus Torvalds20 years
v2.6.14-rc4commit 907a426179...Linus Torvalds20 years
v2.6.14-rc3commit 1c9426e8a5...Linus Torvalds20 years
v2.6.14-rc2commit 676d55ae30...Linus Torvalds20 years
v2.6.14-rc1commit 2f4ba45a75...Linus Torvalds20 years
v2.6.13commit 02b3e4e2d7...Linus Torvalds20 years
v2.6.13-rc7commit 0572e3da3f...Linus Torvalds20 years
v2.6.13-rc6commit 6fc32179de...Linus Torvalds20 years
v2.6.13-rc5commit 9a351e30d7...Linus Torvalds20 years
v2.6.13-rc4commit 6395352334...Linus Torvalds20 years
v2.6.11tree c39ae07f39...
v2.6.11-treetree c39ae07f39...
v2.6.12commit 9ee1c939d1...
v2.6.12-rc2commit 1da177e4c3...
v2.6.12-rc3commit a2755a80f4...
v2.6.12-rc4commit 88d7bd8cb9...
v2.6.12-rc5commit 2a24ab628a...
v2.6.12-rc6commit 7cef5677ef...
v2.6.13-rc1commit 4c91aedb75...
v2.6.13-rc2commit a18bcb7450...
v2.6.13-rc3commit c32511e271...
/span> link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL); switch ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) >> RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT) { case RADEON_PCIE_LC_LINK_WIDTH_X0: return 0; case RADEON_PCIE_LC_LINK_WIDTH_X1: return 1; case RADEON_PCIE_LC_LINK_WIDTH_X2: return 2; case RADEON_PCIE_LC_LINK_WIDTH_X4: return 4; case RADEON_PCIE_LC_LINK_WIDTH_X8: return 8; case RADEON_PCIE_LC_LINK_WIDTH_X16: default: return 16; } } #if defined(CONFIG_DEBUG_FS) static int rv370_debugfs_pcie_gart_info(struct seq_file *m, void *data) { struct drm_info_node *node = (struct drm_info_node *) m->private; struct drm_device *dev = node->minor->dev; struct radeon_device *rdev = dev->dev_private; uint32_t tmp; tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL); seq_printf(m, "PCIE_TX_GART_CNTL 0x%08x\n", tmp); tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_BASE); seq_printf(m, "PCIE_TX_GART_BASE 0x%08x\n", tmp); tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_START_LO); seq_printf(m, "PCIE_TX_GART_START_LO 0x%08x\n", tmp); tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_START_HI); seq_printf(m, "PCIE_TX_GART_START_HI 0x%08x\n", tmp); tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_END_LO); seq_printf(m, "PCIE_TX_GART_END_LO 0x%08x\n", tmp); tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_END_HI); seq_printf(m, "PCIE_TX_GART_END_HI 0x%08x\n", tmp); tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_ERROR); seq_printf(m, "PCIE_TX_GART_ERROR 0x%08x\n", tmp); return 0; } static struct drm_info_list rv370_pcie_gart_info_list[] = { {"rv370_pcie_gart_info", rv370_debugfs_pcie_gart_info, 0, NULL}, }; #endif static int rv370_debugfs_pcie_gart_info_init(struct radeon_device *rdev) { #if defined(CONFIG_DEBUG_FS) return radeon_debugfs_add_files(rdev, rv370_pcie_gart_info_list, 1); #else return 0; #endif } static int r300_packet0_check(struct radeon_cs_parser *p, struct radeon_cs_packet *pkt, unsigned idx, unsigned reg) { struct radeon_cs_reloc *reloc; struct r100_cs_track *track; volatile uint32_t *ib; uint32_t tmp, tile_flags = 0; unsigned i; int r; u32 idx_value; ib = p->ib->ptr; track = (struct r100_cs_track *)p->track; idx_value = radeon_get_ib_value(p, idx); switch(reg) { case AVIVO_D1MODE_VLINE_START_END: case RADEON_CRTC_GUI_TRIG_VLINE: r = r100_cs_packet_parse_vline(p); if (r) { DRM_ERROR("No reloc for ib[%d]=0x%04X\n", idx, reg); r100_cs_dump_packet(p, pkt); return r; } break; case RADEON_DST_PITCH_OFFSET: case RADEON_SRC_PITCH_OFFSET: r = r100_reloc_pitch_offset(p, pkt, idx, reg); if (r) return r; break; case R300_RB3D_COLOROFFSET0: case R300_RB3D_COLOROFFSET1: case R300_RB3D_COLOROFFSET2: case R300_RB3D_COLOROFFSET3: i = (reg - R300_RB3D_COLOROFFSET0) >> 2; r = r100_cs_packet_next_reloc(p, &reloc); if (r) { DRM_ERROR("No reloc for ib[%d]=0x%04X\n", idx, reg); r100_cs_dump_packet(p, pkt); return r; } track->cb[i].robj = reloc->robj; track->cb[i].offset = idx_value; track->cb_dirty = true; ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); break; case R300_ZB_DEPTHOFFSET: r = r100_cs_packet_next_reloc(p, &reloc); if (r) { DRM_ERROR("No reloc for ib[%d]=0x%04X\n", idx, reg); r100_cs_dump_packet(p, pkt); return r; } track->zb.robj = reloc->robj; track->zb.offset = idx_value; track->zb_dirty = true; ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); break; case R300_TX_OFFSET_0: case R300_TX_OFFSET_0+4: case R300_TX_OFFSET_0+8: case R300_TX_OFFSET_0+12: case R300_TX_OFFSET_0+16: case R300_TX_OFFSET_0+20: case R300_TX_OFFSET_0+24: case R300_TX_OFFSET_0+28: case R300_TX_OFFSET_0+32: case R300_TX_OFFSET_0+36: case R300_TX_OFFSET_0+40: case R300_TX_OFFSET_0+44: case R300_TX_OFFSET_0+48: case R300_TX_OFFSET_0+52: case R300_TX_OFFSET_0+56: case R300_TX_OFFSET_0+60: i = (reg - R300_TX_OFFSET_0) >> 2; r = r100_cs_packet_next_reloc(p, &reloc); if (r) { DRM_ERROR("No reloc for ib[%d]=0x%04X\n", idx, reg); r100_cs_dump_packet(p, pkt); return r; } if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) tile_flags |= R300_TXO_MACRO_TILE; if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) tile_flags |= R300_TXO_MICRO_TILE; else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO_SQUARE) tile_flags |= R300_TXO_MICRO_TILE_SQUARE; tmp = idx_value + ((u32)reloc->lobj.gpu_offset); tmp |= tile_flags; ib[idx] = tmp; track->textures[i].robj = reloc->robj; track->tex_dirty = true; break; /* Tracked registers */ case 0x2084: /* VAP_VF_CNTL */ track->vap_vf_cntl = idx_value; break; case 0x20B4: /* VAP_VTX_SIZE */ track->vtx_size = idx_value & 0x7F; break; case 0x2134: /* VAP_VF_MAX_VTX_INDX */ track->max_indx = idx_value & 0x00FFFFFFUL; break; case 0x2088: /* VAP_ALT_NUM_VERTICES - only valid on r500 */ if (p->rdev->family < CHIP_RV515) goto fail; track->vap_alt_nverts = idx_value & 0xFFFFFF; break; case 0x43E4: /* SC_SCISSOR1 */ track->maxy = ((idx_value >> 13) & 0x1FFF) + 1; if (p->rdev->family < CHIP_RV515) { track->maxy -= 1440; } track->cb_dirty = true; track->zb_dirty = true; break; case 0x4E00: /* RB3D_CCTL */ if ((idx_value & (1 << 10)) && /* CMASK_ENABLE */ p->rdev->cmask_filp != p->filp) { DRM_ERROR("Invalid RB3D_CCTL: Cannot enable CMASK.\n"); return -EINVAL; } track->num_cb = ((idx_value >> 5) & 0x3) + 1; track->cb_dirty = true; break; case 0x4E38: case 0x4E3C: case 0x4E40: case 0x4E44: /* RB3D_COLORPITCH0 */ /* RB3D_COLORPITCH1 */ /* RB3D_COLORPITCH2 */ /* RB3D_COLORPITCH3 */ r = r100_cs_packet_next_reloc(p, &reloc); if (r) { DRM_ERROR("No reloc for ib[%d]=0x%04X\n", idx, reg); r100_cs_dump_packet(p, pkt); return r; } if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) tile_flags |= R300_COLOR_TILE_ENABLE; if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) tile_flags |= R300_COLOR_MICROTILE_ENABLE; else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO_SQUARE) tile_flags |= R300_COLOR_MICROTILE_SQUARE_ENABLE; tmp = idx_value & ~(0x7 << 16); tmp |= tile_flags; ib[idx] = tmp; i = (reg - 0x4E38) >> 2; track->cb[i].pitch = idx_value & 0x3FFE; switch (((idx_value >> 21) & 0xF)) { case 9: case 11: case 12: track->cb[i].cpp = 1; break; case 3: case 4: case 13: case 15: track->cb[i].cpp = 2; break; case 5: if (p->rdev->family < CHIP_RV515) { DRM_ERROR("Invalid color buffer format (%d)!\n", ((idx_value >> 21) & 0xF)); return -EINVAL; } /* Pass through. */ case 6: track->cb[i].cpp = 4; break; case 10: track->cb[i].cpp = 8; break; case 7: track->cb[i].cpp = 16; break; default: DRM_ERROR("Invalid color buffer format (%d) !\n", ((idx_value >> 21) & 0xF)); return -EINVAL; } track->cb_dirty = true; break; case 0x4F00: /* ZB_CNTL */ if (idx_value & 2) { track->z_enabled = true; } else { track->z_enabled = false; } track->zb_dirty = true; break; case 0x4F10: /* ZB_FORMAT */ switch ((idx_value & 0xF)) { case 0: case 1: track->zb.cpp = 2; break; case 2: track->zb.cpp = 4; break; default: DRM_ERROR("Invalid z buffer format (%d) !\n", (idx_value & 0xF)); return -EINVAL; } track->zb_dirty = true; break; case 0x4F24: /* ZB_DEPTHPITCH */ r = r100_cs_packet_next_reloc(p, &reloc); if (r) { DRM_ERROR("No reloc for ib[%d]=0x%04X\n", idx, reg); r100_cs_dump_packet(p, pkt); return r; } if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) tile_flags |= R300_DEPTHMACROTILE_ENABLE; if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) tile_flags |= R300_DEPTHMICROTILE_TILED; else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO_SQUARE) tile_flags |= R300_DEPTHMICROTILE_TILED_SQUARE; tmp = idx_value & ~(0x7 << 16); tmp |= tile_flags; ib[idx] = tmp; track->zb.pitch = idx_value & 0x3FFC; track->zb_dirty = true; break; case 0x4104: /* TX_ENABLE */ for (i = 0; i < 16; i++) { bool enabled; enabled = !!(idx_value & (1 << i)); track->textures[i].enabled = enabled; } track->tex_dirty = true; break; case 0x44C0: case 0x44C4: case 0x44C8: case 0x44CC: case 0x44D0: case 0x44D4: case 0x44D8: case 0x44DC: case 0x44E0: case 0x44E4: case 0x44E8: case 0x44EC: case 0x44F0: case 0x44F4: case 0x44F8: case 0x44FC: /* TX_FORMAT1_[0-15] */ i = (reg - 0x44C0) >> 2; tmp = (idx_value >> 25) & 0x3; track->textures[i].tex_coord_type = tmp; switch ((idx_value & 0x1F)) { case R300_TX_FORMAT_X8: case R300_TX_FORMAT_Y4X4: case R300_TX_FORMAT_Z3Y3X2: track->textures[i].cpp = 1; track->textures[i].compress_format = R100_TRACK_COMP_NONE; break; case R300_TX_FORMAT_X16: case R300_TX_FORMAT_FL_I16: case R300_TX_FORMAT_Y8X8: case R300_TX_FORMAT_Z5Y6X5: case R300_TX_FORMAT_Z6Y5X5: case R300_TX_FORMAT_W4Z4Y4X4: case R300_TX_FORMAT_W1Z5Y5X5: case R300_TX_FORMAT_D3DMFT_CxV8U8: case R300_TX_FORMAT_B8G8_B8G8: case R300_TX_FORMAT_G8R8_G8B8: track->textures[i].cpp = 2; track->textures[i].compress_format = R100_TRACK_COMP_NONE; break; case R300_TX_FORMAT_Y16X16: case R300_TX_FORMAT_FL_I16A16: case R300_TX_FORMAT_Z11Y11X10: case R300_TX_FORMAT_Z10Y11X11: case R300_TX_FORMAT_W8Z8Y8X8: case R300_TX_FORMAT_W2Z10Y10X10: case 0x17: case R300_TX_FORMAT_FL_I32: case 0x1e: track->textures[i].cpp = 4; track->textures[i].compress_format = R100_TRACK_COMP_NONE; break; case R300_TX_FORMAT_W16Z16Y16X16: case R300_TX_FORMAT_FL_R16G16B16A16: case R300_TX_FORMAT_FL_I32A32: track->textures[i].cpp = 8; track->textures[i].compress_format = R100_TRACK_COMP_NONE; break; case R300_TX_FORMAT_FL_R32G32B32A32: track->textures[i].cpp = 16; track->textures[i].compress_format = R100_TRACK_COMP_NONE; break; case R300_TX_FORMAT_DXT1: track->textures[i].cpp = 1; track->textures[i].compress_format = R100_TRACK_COMP_DXT1; break; case R300_TX_FORMAT_ATI2N: if (p->rdev->family < CHIP_R420) { DRM_ERROR("Invalid texture format %u\n", (idx_value & 0x1F)); return -EINVAL; } /* The same rules apply as for DXT3/5. */ /* Pass through. */ case R300_TX_FORMAT_DXT3: case R300_TX_FORMAT_DXT5: track->textures[i].cpp = 1; track->textures[i].compress_format = R100_TRACK_COMP_DXT35; break; default: DRM_ERROR("Invalid texture format %u\n", (idx_value & 0x1F)); return -EINVAL; } track->tex_dirty = true; break; case 0x4400: case 0x4404: case 0x4408: case 0x440C: case 0x4410: case 0x4414: case 0x4418: case 0x441C: case 0x4420: case 0x4424: case 0x4428: case 0x442C: case 0x4430: case 0x4434: case 0x4438: case 0x443C: /* TX_FILTER0_[0-15] */ i = (reg - 0x4400) >> 2; tmp = idx_value & 0x7; if (tmp == 2 || tmp == 4 || tmp == 6) { track->textures[i].roundup_w = false; } tmp = (idx_value >> 3) & 0x7; if (tmp == 2 || tmp == 4 || tmp == 6) { track->textures[i].roundup_h = false; } track->tex_dirty = true; break; case 0x4500: case 0x4504: case 0x4508: case 0x450C: case 0x4510: case 0x4514: case 0x4518: case 0x451C: case 0x4520: case 0x4524: case 0x4528: case 0x452C: case 0x4530: case 0x4534: case 0x4538: case 0x453C: /* TX_FORMAT2_[0-15] */ i = (reg - 0x4500) >> 2; tmp = idx_value & 0x3FFF; track->textures[i].pitch = tmp + 1; if (p->rdev->family >= CHIP_RV515) { tmp = ((idx_value >> 15) & 1) << 11; track->textures[i].width_11 = tmp; tmp = ((idx_value >> 16) & 1) << 11; track->textures[i].height_11 = tmp; /* ATI1N */ if (idx_value & (1 << 14)) { /* The same rules apply as for DXT1. */ track->textures[i].compress_format = R100_TRACK_COMP_DXT1; } } else if (idx_value & (1 << 14)) { DRM_ERROR("Forbidden bit TXFORMAT_MSB\n"); return -EINVAL; } track->tex_dirty = true; break; case 0x4480: case 0x4484: case 0x4488: case 0x448C: case 0x4490: case 0x4494: case 0x4498: case 0x449C: case 0x44A0: case 0x44A4: case 0x44A8: case 0x44AC: case 0x44B0: case 0x44B4: case 0x44B8: case 0x44BC: /* TX_FORMAT0_[0-15] */ i = (reg - 0x4480) >> 2; tmp = idx_value & 0x7FF; track->textures[i].width = tmp + 1; tmp = (idx_value >> 11) & 0x7FF; track->textures[i].height = tmp + 1; tmp = (idx_value >> 26) & 0xF; track->textures[i].num_levels = tmp; tmp = idx_value & (1 << 31); track->textures[i].use_pitch = !!tmp; tmp = (idx_value >> 22) & 0xF; track->textures[i].txdepth = tmp; track->tex_dirty = true; break; case R300_ZB_ZPASS_ADDR: r = r100_cs_packet_next_reloc(p, &reloc); if (r) { DRM_ERROR("No reloc for ib[%d]=0x%04X\n", idx, reg); r100_cs_dump_packet(p, pkt); return r; } ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); break; case 0x4e0c: /* RB3D_COLOR_CHANNEL_MASK */ track->color_channel_mask = idx_value; track->cb_dirty = true; break; case 0x43a4: /* SC_HYPERZ_EN */ /* r300c emits this register - we need to disable hyperz for it * without complaining */ if (p->rdev->hyperz_filp != p->filp) { if (idx_value & 0x1) ib[idx] = idx_value & ~1; } break; case 0x4f1c: /* ZB_BW_CNTL */ track->zb_cb_clear = !!(idx_value & (1 << 5)); track->cb_dirty = true; track->zb_dirty = true; if (p->rdev->hyperz_filp != p->filp) { if (idx_value & (R300_HIZ_ENABLE | R300_RD_COMP_ENABLE | R300_WR_COMP_ENABLE | R300_FAST_FILL_ENABLE)) goto fail; } break; case 0x4e04: /* RB3D_BLENDCNTL */ track->blend_read_enable = !!(idx_value & (1 << 2)); track->cb_dirty = true; break; case R300_RB3D_AARESOLVE_OFFSET: r = r100_cs_packet_next_reloc(p, &reloc); if (r) { DRM_ERROR("No reloc for ib[%d]=0x%04X\n", idx, reg); r100_cs_dump_packet(p, pkt); return r; } track->aa.robj = reloc->robj; track->aa.offset = idx_value; track->aa_dirty = true; ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); break; case R300_RB3D_AARESOLVE_PITCH: track->aa.pitch = idx_value & 0x3FFE; track->aa_dirty = true; break; case R300_RB3D_AARESOLVE_CTL: track->aaresolve = idx_value & 0x1; track->aa_dirty = true; break; case 0x4f30: /* ZB_MASK_OFFSET */ case 0x4f34: /* ZB_ZMASK_PITCH */ case 0x4f44: /* ZB_HIZ_OFFSET */ case 0x4f54: /* ZB_HIZ_PITCH */ if (idx_value && (p->rdev->hyperz_filp != p->filp)) goto fail; break; case 0x4028: if (idx_value && (p->rdev->hyperz_filp != p->filp)) goto fail; /* GB_Z_PEQ_CONFIG */ if (p->rdev->family >= CHIP_RV350) break; goto fail; break; case 0x4be8: /* valid register only on RV530 */ if (p->rdev->family == CHIP_RV530) break; /* fallthrough do not move */ default: goto fail; } return 0; fail: printk(KERN_ERR "Forbidden register 0x%04X in cs at %d (val=%08x)\n", reg, idx, idx_value); return -EINVAL; } static int r300_packet3_check(struct radeon_cs_parser *p, struct radeon_cs_packet *pkt) { struct radeon_cs_reloc *reloc; struct r100_cs_track *track; volatile uint32_t *ib; unsigned idx; int r; ib = p->ib->ptr; idx = pkt->idx + 1; track = (struct r100_cs_track *)p->track; switch(pkt->opcode) { case PACKET3_3D_LOAD_VBPNTR: r = r100_packet3_load_vbpntr(p, pkt, idx); if (r) return r; break; case PACKET3_INDX_BUFFER: r = r100_cs_packet_next_reloc(p, &reloc); if (r) { DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode); r100_cs_dump_packet(p, pkt); return r; } ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->lobj.gpu_offset); r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj); if (r) { return r; } break; /* Draw packet */ case PACKET3_3D_DRAW_IMMD: /* Number of dwords is vtx_size * (num_vertices - 1) * PRIM_WALK must be equal to 3 vertex data in embedded * in cmd stream */ if (((radeon_get_ib_value(p, idx + 1) >> 4) & 0x3) != 3) { DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n"); return -EINVAL; } track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1); track->immd_dwords = pkt->count - 1; r = r100_cs_track_check(p->rdev, track); if (r) { return r; } break; case PACKET3_3D_DRAW_IMMD_2: /* Number of dwords is vtx_size * (num_vertices - 1) * PRIM_WALK must be equal to 3 vertex data in embedded * in cmd stream */ if (((radeon_get_ib_value(p, idx) >> 4) & 0x3) != 3) { DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n"); return -EINVAL; } track->vap_vf_cntl = radeon_get_ib_value(p, idx); track->immd_dwords = pkt->count; r = r100_cs_track_check(p->rdev, track); if (r) { return r; } break; case PACKET3_3D_DRAW_VBUF: track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1); r = r100_cs_track_check(p->rdev, track); if (r) { return r; } break; case PACKET3_3D_DRAW_VBUF_2: track->vap_vf_cntl = radeon_get_ib_value(p, idx); r = r100_cs_track_check(p->rdev, track); if (r) { return r; } break; case PACKET3_3D_DRAW_INDX: track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1); r = r100_cs_track_check(p->rdev, track); if (r) { return r; } break; case PACKET3_3D_DRAW_INDX_2: track->vap_vf_cntl = radeon_get_ib_value(p, idx); r = r100_cs_track_check(p->rdev, track); if (r) { return r; } break; case PACKET3_3D_CLEAR_HIZ: case PACKET3_3D_CLEAR_ZMASK: if (p->rdev->hyperz_filp != p->filp) return -EINVAL; break; case PACKET3_3D_CLEAR_CMASK: if (p->rdev->cmask_filp != p->filp) return -EINVAL; break; case PACKET3_NOP: break; default: DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode); return -EINVAL; } return 0; } int r300_cs_parse(struct radeon_cs_parser *p) { struct radeon_cs_packet pkt; struct r100_cs_track *track; int r; track = kzalloc(sizeof(*track), GFP_KERNEL); if (track == NULL) return -ENOMEM; r100_cs_track_clear(p->rdev, track); p->track = track; do { r = r100_cs_packet_parse(p, &pkt, p->idx); if (r) { return r; } p->idx += pkt.count + 2; switch (pkt.type) { case PACKET_TYPE0: r = r100_cs_parse_packet0(p, &pkt, p->rdev->config.r300.reg_safe_bm, p->rdev->config.r300.reg_safe_bm_size, &r300_packet0_check); break; case PACKET_TYPE2: break; case PACKET_TYPE3: r = r300_packet3_check(p, &pkt); break; default: DRM_ERROR("Unknown packet type %d !\n", pkt.type); return -EINVAL; } if (r) { return r; } } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw); return 0; } void r300_set_reg_safe(struct radeon_device *rdev) { rdev->config.r300.reg_safe_bm = r300_reg_safe_bm; rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(r300_reg_safe_bm); } void r300_mc_program(struct radeon_device *rdev) { struct r100_mc_save save; int r; r = r100_debugfs_mc_info_init(rdev); if (r) { dev_err(rdev->dev, "Failed to create r100_mc debugfs file.\n"); } /* Stops all mc clients */ r100_mc_stop(rdev, &save); if (rdev->flags & RADEON_IS_AGP) { WREG32(R_00014C_MC_AGP_LOCATION, S_00014C_MC_AGP_START(rdev->mc.gtt_start >> 16) | S_00014C_MC_AGP_TOP(rdev->mc.gtt_end >> 16)); WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base)); WREG32(R_00015C_AGP_BASE_2, upper_32_bits(rdev->mc.agp_base) & 0xff); } else { WREG32(R_00014C_MC_AGP_LOCATION, 0x0FFFFFFF); WREG32(R_000170_AGP_BASE, 0); WREG32(R_00015C_AGP_BASE_2, 0); } /* Wait for mc idle */ if (r300_mc_wait_for_idle(rdev)) DRM_INFO("Failed to wait MC idle before programming MC.\n"); /* Program MC, should be a 32bits limited address space */ WREG32(R_000148_MC_FB_LOCATION, S_000148_MC_FB_START(rdev->mc.vram_start >> 16) | S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16)); r100_mc_resume(rdev, &save); } void r300_clock_startup(struct radeon_device *rdev) { u32 tmp; if (radeon_dynclks != -1 && radeon_dynclks) radeon_legacy_set_clock_gating(rdev, 1); /* We need to force on some of the block */ tmp = RREG32_PLL(R_00000D_SCLK_CNTL); tmp |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1); if ((rdev->family == CHIP_RV350) || (rdev->family == CHIP_RV380)) tmp |= S_00000D_FORCE_VAP(1); WREG32_PLL(R_00000D_SCLK_CNTL, tmp); } static int r300_startup(struct radeon_device *rdev) { int r; /* set common regs */ r100_set_common_regs(rdev); /* program mc */ r300_mc_program(rdev); /* Resume clock */ r300_clock_startup(rdev); /* Initialize GPU configuration (# pipes, ...) */ r300_gpu_init(rdev); /* Initialize GART (initialize after TTM so we can allocate * memory through TTM but finalize after TTM) */ if (rdev->flags & RADEON_IS_PCIE) { r = rv370_pcie_gart_enable(rdev); if (r) return r; } if (rdev->family == CHIP_R300 || rdev->family == CHIP_R350 || rdev->family == CHIP_RV350) r100_enable_bm(rdev); if (rdev->flags & RADEON_IS_PCI) { r = r100_pci_gart_enable(rdev); if (r) return r; } /* allocate wb buffer */ r = radeon_wb_init(rdev); if (r) return r; /* Enable IRQ */ r100_irq_set(rdev); rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); /* 1M ring buffer */ r = r100_cp_init(rdev, 1024 * 1024); if (r) { dev_err(rdev->dev, "failed initializing CP (%d).\n", r); return r; } r = r100_ib_init(rdev); if (r) { dev_err(rdev->dev, "failed initializing IB (%d).\n", r); return r; } return 0; } int r300_resume(struct radeon_device *rdev) { /* Make sur GART are not working */ if (rdev->flags & RADEON_IS_PCIE) rv370_pcie_gart_disable(rdev); if (rdev->flags & RADEON_IS_PCI) r100_pci_gart_disable(rdev); /* Resume clock before doing reset */ r300_clock_startup(rdev); /* Reset gpu before posting otherwise ATOM will enter infinite loop */ if (radeon_asic_reset(rdev)) { dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", RREG32(R_000E40_RBBM_STATUS), RREG32(R_0007C0_CP_STAT)); } /* post */ radeon_combios_asic_init(rdev->ddev); /* Resume clock after posting */ r300_clock_startup(rdev); /* Initialize surface registers */ radeon_surface_init(rdev); return r300_startup(rdev); } int r300_suspend(struct radeon_device *rdev) { r100_cp_disable(rdev); radeon_wb_disable(rdev); r100_irq_disable(rdev); if (rdev->flags & RADEON_IS_PCIE) rv370_pcie_gart_disable(rdev); if (rdev->flags & RADEON_IS_PCI) r100_pci_gart_disable(rdev); return 0; } void r300_fini(struct radeon_device *rdev) { r100_cp_fini(rdev); radeon_wb_fini(rdev); r100_ib_fini(rdev); radeon_gem_fini(rdev); if (rdev->flags & RADEON_IS_PCIE) rv370_pcie_gart_fini(rdev); if (rdev->flags & RADEON_IS_PCI) r100_pci_gart_fini(rdev); radeon_agp_fini(rdev); radeon_irq_kms_fini(rdev); radeon_fence_driver_fini(rdev); radeon_bo_fini(rdev); radeon_atombios_fini(rdev); kfree(rdev->bios); rdev->bios = NULL; } int r300_init(struct radeon_device *rdev) { int r; /* Disable VGA */ r100_vga_render_disable(rdev); /* Initialize scratch registers */ radeon_scratch_init(rdev); /* Initialize surface registers */ radeon_surface_init(rdev); /* TODO: disable VGA need to use VGA request */ /* restore some register to sane defaults */ r100_restore_sanity(rdev); /* BIOS*/ if (!radeon_get_bios(rdev)) { if (ASIC_IS_AVIVO(rdev)) return -EINVAL; } if (rdev->is_atom_bios) { dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n"); return -EINVAL; } else { r = radeon_combios_init(rdev); if (r) return r; } /* Reset gpu before posting otherwise ATOM will enter infinite loop */ if (radeon_asic_reset(rdev)) { dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", RREG32(R_000E40_RBBM_STATUS), RREG32(R_0007C0_CP_STAT)); } /* check if cards are posted or not */ if (radeon_boot_test_post_card(rdev) == false) return -EINVAL; /* Set asic errata */ r300_errata(rdev); /* Initialize clocks */ radeon_get_clock_info(rdev->ddev); /* initialize AGP */ if (rdev->flags & RADEON_IS_AGP) { r = radeon_agp_init(rdev); if (r) { radeon_agp_disable(rdev); } } /* initialize memory controller */ r300_mc_init(rdev); /* Fence driver */ r = radeon_fence_driver_init(rdev); if (r) return r; r = radeon_irq_kms_init(rdev); if (r) return r; /* Memory manager */ r = radeon_bo_init(rdev); if (r) return r; if (rdev->flags & RADEON_IS_PCIE) { r = rv370_pcie_gart_init(rdev); if (r) return r; } if (rdev->flags & RADEON_IS_PCI) { r = r100_pci_gart_init(rdev); if (r) return r; } r300_set_reg_safe(rdev); rdev->accel_working = true; r = r300_startup(rdev); if (r) { /* Somethings want wront with the accel init stop accel */ dev_err(rdev->dev, "Disabling GPU acceleration\n"); r100_cp_fini(rdev); radeon_wb_fini(rdev); r100_ib_fini(rdev); radeon_irq_kms_fini(rdev); if (rdev->flags & RADEON_IS_PCIE) rv370_pcie_gart_fini(rdev); if (rdev->flags & RADEON_IS_PCI) r100_pci_gart_fini(rdev); radeon_agp_fini(rdev); rdev->accel_working = false; } return 0; }