litmus-rt.git - The LITMUS^RT kernel.

Branch	Commit message	Author	Age
archive/unc-master-3.0	P-FP: fix BUG_ON releated to priority inheritance	Bjoern Brandenburg	13 years
archived-2013.1	uncachedev: mmap memory that is not cached by CPUs	Glenn Elliott	12 years
archived-private-master	Merge branch 'wip-2.6.34' into old-private-master	Andrea Bastoni	15 years
archived-semi-part	Merge branch 'wip-semi-part' of ssh://cvs/cvs/proj/litmus/repo/litmus2010 int...	Andrea Bastoni	15 years
demo	Further refinements	Jonathan Herman	14 years
ecrts-pgm-final	Merge branch 'wip-ecrts14-pgm' of ssh://rtsrv.cs.unc.edu/home/litmus/litmus-r...	Glenn Elliott	12 years
ecrts14-pgm-final	Merge branch 'wip-ecrts14-pgm' of ssh://rtsrv.cs.unc.edu/home/litmus/litmus-r...	Glenn Elliott	12 years
gpusync-rtss12	Final GPUSync implementation.	Glenn Elliott	12 years
gpusync/staging	Rename IKGLP R2DGLP.	Glenn Elliott	12 years
linux-tip	Merge branch 'slab/urgent' of git://git.kernel.org/pub/scm/linux/kernel/git/p...	Linus Torvalds	15 years
litmus2008-patch-series	add i386 feather-trace implementation	Bjoern B. Brandenburg	16 years
master	PSN-EDF: use inferred_sporadic_job_release_at	Bjoern Brandenburg	9 years
pgm	make it compile	Glenn Elliott	12 years
prop/litmus-signals	Infrastructure for Litmus signals.	Glenn Elliott	13 years
prop/robust-tie-break	Fixed bug in edf_higher_prio().	Glenn Elliott	13 years
staging	Fix tracepoint compilation error	Felipe Cerqueira	13 years
test	9/23/2016	Namhoon Kim	9 years
tracing-devel	Test kernel tracing events capabilities	Andrea Bastoni	16 years
v2.6.34-with-arm-patches	smsc911x: Add spinlocks around registers access	Catalin Marinas	15 years
v2015.1	Add ARM syscall def for get_current_budget	Bjoern Brandenburg	10 years
wip-2011.2-bbb	Litmus core: simplify np-section protocol	Bjoern B. Brandenburg	14 years
wip-2011.2-bbb-trace	Refactor sched_trace_log_message() -> debug_trace_log_message()	Andrea Bastoni	14 years
wip-2012.3-gpu	SOBLIV draining support for C-EDF.	Glenn Elliott	12 years
wip-2012.3-gpu-preport	pick up last C-RM file	Glenn Elliott	12 years
wip-2012.3-gpu-rtss13	Fix critical bug in GPU tracker.	Glenn Elliott	12 years
wip-2012.3-gpu-sobliv-budget-w-kshark	Proper sobliv draining and many bug fixes.	Glenn Elliott	12 years
wip-aedzl-final	Make it easier to compile AEDZL interfaces in liblitmus.	Glenn Elliott	15 years
wip-aedzl-revised	Add sched_trace data for Apative EDZL	Glenn Elliott	15 years
wip-arbit-deadline	Fix compilation bug.	Glenn Elliott	13 years
wip-aux-tasks	Description of refined aux task inheritance.	Glenn Elliott	13 years
wip-bbb	GSN-EDF & Core: improve debug TRACE'ing for NP sections	Bjoern B. Brandenburg	14 years
wip-bbb-prio-don	use correct timestamp	Bjoern B. Brandenburg	14 years
wip-better-break	Implement hash-based EDF tie-breaking.	Glenn Elliott	13 years
wip-binary-heap	Make C-EDF work with simplified binheap_delete	Glenn Elliott	13 years
wip-budget	Added support for choices in budget policy enforcement.	Glenn Elliott	15 years
wip-color	Summarize schedulability with final record	Jonathan Herman	13 years
wip-color-jlh	sched_color: Fixed two bugs causing crashing on experiment restart and a rare...	Jonathan Herman	13 years
wip-d10-hz1000	Enable HZ=1000 on District 10	Bjoern B. Brandenburg	15 years
wip-default-clustering	Feature: Make default C-EDF clustering compile-time configurable.	Glenn Elliott	15 years
wip-dissipation-jerickso	Update from 2.6.36 to 2.6.36.4	Jeremy Erickson	11 years
wip-dissipation2-jerickso	Update 2.6.36 to 2.6.36.4	Jeremy Erickson	11 years
wip-ecrts14-pgm	Merge branch 'wip-ecrts14-pgm' of ssh://rtsrv.cs.unc.edu/home/litmus/litmus-r...	Glenn Elliott	12 years
wip-edf-hsb	last tested version	Jonathan Herman	14 years
wip-edf-os	Lookup table EDF-os	Jeremy Erickson	12 years
wip-edf-tie-break	Merge branch 'wip-edf-tie-break' of ssh://rtsrv.cs.unc.edu/home/litmus/litmus...	Glenn Elliott	13 years
wip-edzl-critique	Use hr_timer's active checks instead of having own flag.	Glenn Elliott	15 years
wip-edzl-final	Implementation of the EDZL scheduler.	Glenn Elliott	15 years
wip-edzl-revised	Clean up comments.	Glenn Elliott	15 years
wip-events	Added support for tracing arbitrary actions.	Jonathan Herman	15 years
wip-extra-debug	DBG: add additional tracing	Bjoern B. Brandenburg	15 years
wip-fix-switch-jerickso	Attempt to fix race condition with plugin switching	Jeremy Erickson	15 years
wip-fix3	sched: show length of runqueue clock deactivation in /proc/sched_debug	Bjoern B. Brandenburg	15 years
wip-fmlp-dequeue	Improve FMLP queue management.	Glenn Elliott	14 years
wip-ft-irq-flag	Feather-Trace: keep track of interrupt-related interference.	Bjoern B. Brandenburg	14 years
wip-gpu-cleanup	Enable sched_trace log injection from userspace	Glenn Elliott	13 years
wip-gpu-interrupts	Remove option for threading of all softirqs.	Glenn Elliott	14 years
wip-gpu-rtas12	Generalized GPU cost predictors + EWMA. (untested)	Glenn Elliott	13 years
wip-gpu-rtss12	Final GPUSync implementation.	Glenn Elliott	13 years
wip-gpu-rtss12-srp	experimental changes to support GPUs under SRP	Glenn Elliott	13 years
wip-gpusync-merge	Cleanup priority tracking for budget enforcement.	Glenn Elliott	11 years
wip-ikglp	Move RSM and IKGLP imp. to own .c files	Glenn Elliott	13 years
wip-k-fmlp	Merge branch 'mpi-master' into wip-k-fmlp	Glenn Elliott	14 years
wip-kernel-coloring	Added recolor syscall	Namhoon Kim	7 years
wip-kernthreads	Kludge work-queue processing into klitirqd.	Glenn Elliott	15 years
wip-klmirqd-to-aux	Allow klmirqd threads to be given names.	Glenn Elliott	13 years
wip-kshark	Merge branch 'mpi-staging' into wip-kshark	Jonathan Herman	13 years
wip-litmus-3.2	Merge commit 'v3.2' into litmus-staging	Andrea Bastoni	13 years
wip-litmus2011.2	Cleanup: Coding conformance for affinity stuff.	Glenn Elliott	14 years
wip-litmus3.0-2011.2	Feather-Trace: keep track of interrupt-related interference.	Bjoern B. Brandenburg	14 years
wip-master-2.6.33-rt	Avoid deadlock when switching task policy to BACKGROUND (ugly)	Andrea Bastoni	15 years
wip-mc	Removed ARM-specific hacks which disabled less common mixed-criticality featu...	Jonathan Herman	12 years
wip-mc-bipasa	MC-EDF added	bipasa chattopadhyay	13 years
wip-mc-jerickso	Split C/D queues	Jeremy Erickson	15 years
wip-mc2-cache-slack	Manually patched mc^2 related code	Ming Yang	10 years
wip-mcrit-mac	cosmetic	Mac Mollison	15 years
wip-merge-3.0	Prevent Linux to send IPI and queue tasks on remote CPUs.	Andrea Bastoni	14 years
wip-merge-v3.0	Prevent Linux to send IPI and queue tasks on remote CPUs.	Andrea Bastoni	14 years
wip-migration-affinity	NULL affinity dereference in C-EDF.	Glenn Elliott	14 years
wip-mmap-uncache	share branch with others	Glenn Elliott	13 years
wip-modechange	RTSS 2017 submission	Namhoon Kim	8 years
wip-nested-locking	Appears to be working.	Bryan Ward	12 years
wip-omlp-gedf	First implementation of G-OMLP.	Glenn Elliott	15 years
wip-pai	Some cleanup of PAI	Glenn Elliott	14 years
wip-percore-lib	9/21/2016	Namhoon Kim	9 years
wip-performance	CONFIG_DONT_PREEMPT_ON_TIE: Don't preeempt a scheduled task on priority tie.	Glenn Elliott	14 years
wip-pgm	Add PGM support to C-FL	Glenn Elliott	12 years
wip-pgm-split	First draft of C-FL-split	Namhoon Kim	12 years
wip-pm-ovd	Add preemption-and-migration overhead tracing support	Andrea Bastoni	15 years
wip-prio-inh	P-EDF updated to use the generic pi framework.	Glenn Elliott	15 years
wip-prioq-dgl	BUG FIX: Support DGLs with PRIOQ_MUTEX	Glenn Elliott	13 years
wip-refactored-gedf	Generalizd architecture for GEDF-style scheduelrs to reduce code redundancy.	Glenn Elliott	15 years
wip-release-master-fix	bugfix: release master CPU must signal task was picked	Bjoern B. Brandenburg	14 years
wip-robust-tie-break	EDF priority tie-breaks.	Glenn Elliott	13 years
wip-rt-kshark	Move task time accounting into the complete_job method.	Jonathan Herman	13 years
wip-rtas12-pgm	Scheduling of PGM jobs.	Glenn Elliott	13 years
wip-semi-part	Fix compile error with newer GCC	Jeremy Erickson	12 years
wip-semi-part-edfos-jerickso	Use initial CPU set by client	Jeremy Erickson	12 years
wip-shared-lib	TODO: Fix condition checks in replicate_page_move_mapping()	Namhoon Kim	9 years
wip-shared-lib2	RTAS 2017 Submission ver.	Namhoon Kim	9 years
wip-shared-mem	Initial commit for shared library	Namhoon Kim	9 years
wip-splitting-jerickso	Fix release behavior	Jeremy Erickson	13 years
wip-splitting-omlp-jerickso	Bjoern's Dissertation Code with Priority Donation	Jeremy Erickson	13 years
wip-stage-binheap	An efficient binary heap implementation.	Glenn Elliott	13 years
wip-sun-port	Dynamic memory allocation and clean exit for FeatherTrace	Christopher Kenna	15 years
wip-timer-trace	bugfix: C-EDF, clear scheduled field of the correct CPU upon task_exit	Andrea Bastoni	15 years
wip-tracepoints	Add kernel-style events for sched_trace_XXX() functions	Andrea Bastoni	14 years

Tag	Download	Author	Age
2015.1	commit 8e51b37822...	Bjoern Brandenburg	10 years
2013.1	commit bcaacec1ca...	Glenn Elliott	12 years
2012.3	commit c158b5fbe4...	Jonathan Herman	13 years
2012.2	commit b53c479a0f...	Glenn Elliott	13 years
2012.1	commit 83b11ea1c6...	Bjoern B. Brandenburg	14 years
rtas12-mc-beta-exp	commit 8e236ee20f...	Christopher Kenna	14 years
2011.1	commit d11808b5c6...	Christopher Kenna	15 years
v2.6.37-rc4	commit e8a7e48bb2...	Linus Torvalds	15 years
v2.6.37-rc3	commit 3561d43fd2...	Linus Torvalds	15 years
v2.6.37-rc2	commit e53beacd23...	Linus Torvalds	15 years
v2.6.37-rc1	commit c8ddb2713c...	Linus Torvalds	15 years
v2.6.36	commit f6f94e2ab1...	Linus Torvalds	15 years
2010.2	commit 5c5456402d...	Bjoern B. Brandenburg	15 years
v2.6.36-rc8	commit cd07202cc8...	Linus Torvalds	15 years
v2.6.36-rc7	commit cb655d0f3d...	Linus Torvalds	15 years
v2.6.36-rc6	commit 899611ee7d...	Linus Torvalds	15 years
v2.6.36-rc5	commit b30a3f6257...	Linus Torvalds	15 years
v2.6.36-rc4	commit 49553c2ef8...	Linus Torvalds	15 years
v2.6.36-rc3	commit 2bfc96a127...	Linus Torvalds	15 years
v2.6.36-rc2	commit 76be97c1fc...	Linus Torvalds	15 years
v2.6.36-rc1	commit da5cabf80e...	Linus Torvalds	15 years
v2.6.35	commit 9fe6206f40...	Linus Torvalds	15 years
v2.6.35-rc6	commit b37fa16e78...	Linus Torvalds	15 years
v2.6.35-rc5	commit 1c5474a65b...	Linus Torvalds	15 years
v2.6.35-rc4	commit 815c4163b6...	Linus Torvalds	15 years
v2.6.35-rc3	commit 7e27d6e778...	Linus Torvalds	15 years
v2.6.35-rc2	commit e44a21b726...	Linus Torvalds	15 years
v2.6.35-rc1	commit 67a3e12b05...	Linus Torvalds	15 years
2010.1	commit 7c1ff4c544...	Andrea Bastoni	15 years
v2.6.34	commit e40152ee1e...	Linus Torvalds	15 years
v2.6.33.4	commit 4640b4e7d9...	Greg Kroah-Hartman	15 years
v2.6.34-rc7	commit b57f95a382...	Linus Torvalds	15 years
v2.6.34-rc6	commit 66f41d4c5c...	Linus Torvalds	15 years
v2.6.33.3	commit 3e7ad8ed97...	Greg Kroah-Hartman	15 years
v2.6.34-rc5	commit 01bf0b6457...	Linus Torvalds	15 years
v2.6.34-rc4	commit 0d0fb0f9c5...	Linus Torvalds	15 years
v2.6.33.2	commit 19f00f070c...	Greg Kroah-Hartman	15 years
v2.6.34-rc3	commit 2eaa9cfdf3...	Linus Torvalds	15 years
v2.6.34-rc2	commit 220bf991b0...	Linus Torvalds	15 years
v2.6.33.1	commit dbdafe5ccf...	Greg Kroah-Hartman	16 years
v2.6.34-rc1	commit 57d54889cd...	Linus Torvalds	16 years
v2.6.33	commit 60b341b778...	Linus Torvalds	16 years
v2.6.33-rc8	commit 724e6d3fe8...	Linus Torvalds	16 years
v2.6.33-rc7	commit 29275254ca...	Linus Torvalds	16 years
v2.6.33-rc6	commit abe94c756c...	Linus Torvalds	16 years
v2.6.33-rc5	commit 92dcffb916...	Linus Torvalds	16 years
v2.6.33-rc4	commit 7284ce6c9f...	Linus Torvalds	16 years
v2.6.33-rc3	commit 74d2e4f8d7...	Linus Torvalds	16 years
v2.6.33-rc2	commit 6b7b284958...	Linus Torvalds	16 years
v2.6.33-rc1	commit 55639353a0...	Linus Torvalds	16 years
v2.6.32	commit 22763c5cf3...	Linus Torvalds	16 years
v2.6.32-rc8	commit 648f4e3e50...	Linus Torvalds	16 years
v2.6.32-rc7	commit 156171c71a...	Linus Torvalds	16 years
v2.6.32-rc6	commit b419148e56...	Linus Torvalds	16 years
v2.6.32-rc5	commit 012abeea66...	Linus Torvalds	16 years
v2.6.32-rc4	commit 161291396e...	Linus Torvalds	16 years
v2.6.32-rc3	commit 374576a8b6...	Linus Torvalds	16 years
v2.6.32-rc1	commit 17d857be64...	Linus Torvalds	16 years
v2.6.32-rc2	commit 17d857be64...	Linus Torvalds	16 years
v2.6.31	commit 74fca6a428...	Linus Torvalds	16 years
v2.6.31-rc9	commit e07cccf404...	Linus Torvalds	16 years
v2.6.31-rc8	commit 326ba5010a...	Linus Torvalds	16 years
v2.6.31-rc7	commit 422bef879e...	Linus Torvalds	16 years
v2.6.31-rc6	commit 64f1607ffb...	Linus Torvalds	16 years
v2.6.31-rc5	commit ed680c4ad4...	Linus Torvalds	16 years
v2.6.31-rc4	commit 4be3bd7849...	Linus Torvalds	16 years
v2.6.31-rc3	commit 6847e154e3...	Linus Torvalds	16 years
v2.6.31-rc2	commit 8e4a718ff3...	Linus Torvalds	16 years
v2.6.31-rc1	commit 28d0325ce6...	Linus Torvalds	16 years
v2.6.30	commit 07a2039b8e...	Linus Torvalds	16 years
v2.6.30-rc8	commit 9fa7eb283c...	Linus Torvalds	16 years
v2.6.30-rc7	commit 59a3759d0f...	Linus Torvalds	16 years
v2.6.30-rc6	commit 1406de8e11...	Linus Torvalds	16 years
v2.6.30-rc5	commit 091bf7624d...	Linus Torvalds	16 years
v2.6.30-rc4	commit 091438dd56...	Linus Torvalds	16 years
v2.6.30-rc3	commit 0910697403...	Linus Torvalds	16 years
v2.6.30-rc2	commit 0882e8dd3a...	Linus Torvalds	16 years
v2.6.30-rc1	commit 577c9c456f...	Linus Torvalds	16 years
v2.6.29	commit 8e0ee43bc2...	Linus Torvalds	16 years
v2.6.29-rc8	commit 041b62374c...	Linus Torvalds	17 years
v2.6.29-rc7	commit fec6c6fec3...	Linus Torvalds	17 years
v2.6.29-rc6	commit 20f4d6c3a2...	Linus Torvalds	17 years
v2.6.29-rc5	commit d2f8d7ee1a...	Linus Torvalds	17 years
v2.6.29-rc4	commit 8e4921515c...	Linus Torvalds	17 years
v2.6.29-rc3	commit 18e352e4a7...	Linus Torvalds	17 years
v2.6.29-rc2	commit 1de9e8e70f...	Linus Torvalds	17 years
v2.6.29-rc1	commit c59765042f...	Linus Torvalds	17 years
v2.6.28	commit 4a6908a3a0...	Linus Torvalds	17 years
v2.6.28-rc9	commit 929096fe9f...	Linus Torvalds	17 years
v2.6.28-rc8	commit 8b1fae4e42...	Linus Torvalds	17 years
v2.6.28-rc7	commit 061e41fdb5...	Linus Torvalds	17 years
v2.6.28-rc6	commit 13d428afc0...	Linus Torvalds	17 years
v2.6.28-rc5	commit 9bf1a2445f...	Linus Torvalds	17 years
v2.6.28-rc4	commit f7160c7573...	Linus Torvalds	17 years
v2.6.28-rc3	commit 45beca08dd...	Linus Torvalds	17 years
v2.6.28-rc2	commit 0173a3265b...	Linus Torvalds	17 years
v2.6.28-rc1	commit 57f8f7b60d...	Linus Torvalds	17 years
v2.6.27	commit 3fa8749e58...	Linus Torvalds	17 years
v2.6.27-rc9	commit 4330ed8ed4...	Linus Torvalds	17 years
v2.6.27-rc8	commit 94aca1dac6...	Linus Torvalds	17 years
v2.6.27-rc7	commit 72d31053f6...	Linus Torvalds	17 years
v2.6.27-rc6	commit adee14b2e1...	Linus Torvalds	17 years
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v2.6.27-rc4	commit 6a55617ed5...	Linus Torvalds	17 years
v2.6.27-rc3	commit 30a2f3c60a...	Linus Torvalds	17 years
v2.6.27-rc2	commit 0967d61ea0...	Linus Torvalds	17 years
v2.6.27-rc1	commit 6e86841d05...	Linus Torvalds	17 years
v2.6.26	commit bce7f793da...	Linus Torvalds	17 years
v2.6.26-rc9	commit b7279469d6...	Linus Torvalds	17 years
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v2.6.26-rc3	commit b8291ad07a...	Linus Torvalds	17 years
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v2.6.25	commit 4b119e21d0...	Linus Torvalds	17 years
v2.6.25-rc9	commit 120dd64cac...	Linus Torvalds	17 years
v2.6.25-rc8	commit 0e81a8ae37...	Linus Torvalds	17 years
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v2.6.25-rc6	commit a978b30af3...	Linus Torvalds	17 years
v2.6.25-rc5	commit cdeeeae056...	Linus Torvalds	18 years
v2.6.25-rc4	commit 29e8c3c304...	Linus Torvalds	18 years
v2.6.25-rc3	commit bfa274e243...	Linus Torvalds	18 years
v2.6.25-rc2	commit 101142c37b...	Linus Torvalds	18 years
v2.6.25-rc1	commit 19af35546d...	Linus Torvalds	18 years
v2.6.24	commit 49914084e7...	Linus Torvalds	18 years
v2.6.24-rc8	commit cbd9c88369...	Linus Torvalds	18 years
v2.6.24-rc7	commit 3ce5445046...	Linus Torvalds	18 years
v2.6.24-rc6	commit ea67db4cdb...	Linus Torvalds	18 years
v2.6.24-rc5	commit 82d29bf6dc...	Linus Torvalds	18 years
v2.6.24-rc4	commit 09b56adc98...	Linus Torvalds	18 years
v2.6.24-rc3	commit d9f8bcbf67...	Linus Torvalds	18 years
v2.6.24-rc2	commit dbeeb816e8...	Linus Torvalds	18 years
v2.6.24-rc1	commit c9927c2bf4...	Linus Torvalds	18 years
v2.6.23	commit bbf25010f1...	Linus Torvalds	18 years
v2.6.23-rc9	commit 3146b39c18...	Linus Torvalds	18 years
v2.6.23-rc8	commit 4942de4a0e...	Linus Torvalds	18 years
v2.6.23-rc7	commit 81cfe79b9c...	Linus Torvalds	18 years
v2.6.23-rc6	commit 0d4cbb5e7f...	Linus Torvalds	18 years
v2.6.23-rc5	commit 40ffbfad6b...	Linus Torvalds	18 years
v2.6.23-rc4	commit b07d68b5ca...	Linus Torvalds	18 years
v2.6.23-rc3	commit 39d3520c92...	Linus Torvalds	18 years
v2.6.23-rc2	commit d4ac2477fa...	Linus Torvalds	18 years
v2.6.23-rc1	commit f695baf2df...	Linus Torvalds	18 years
v2.6.22	commit 7dcca30a32...	Linus Torvalds	18 years
v2.6.22-rc7	commit a38d6181ff...	Linus Torvalds	18 years
v2.6.22-rc6	commit 189548642c...	Linus Torvalds	18 years
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v2.6.22-rc4	commit 5ecd3100e6...	Linus Torvalds	18 years
v2.6.22-rc3	commit c420bc9f09...	Linus Torvalds	18 years
v2.6.22-rc2	commit 55b637c6a0...	Linus Torvalds	18 years
v2.6.22-rc1	commit 39403865d2...	Linus Torvalds	18 years
v2.6.21	commit de46c33745...	Linus Torvalds	18 years
v2.6.21-rc7	commit 94a05509a9...	Linus Torvalds	18 years
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v2.6.20	commit 62d0cfcb27...	Linus Torvalds	19 years
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v2.6.20-rc4	commit bf81b46482...	Linus Torvalds	19 years
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/* * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and * VA Linux Systems Inc., Fremont, California. * * All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining * a copy of this software and associated documentation files (the * "Software"), to deal in the Software without restriction, including * without limitation on the rights to use, copy, modify, merge, * publish, distribute, sublicense, and/or sell copies of the Software, * and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice (including the * next paragraph) shall be included in all copies or substantial * portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * DEALINGS IN THE SOFTWARE. */ /* * Authors: * Kevin E. Martin <martin@xfree86.org> * Rickard E. Faith <faith@valinux.com> * Alan Hourihane <alanh@fairlite.demon.co.uk> * * References: * * !!!! FIXME !!!! * RAGE 128 VR/ RAGE 128 GL Register Reference Manual (Technical * Reference Manual P/N RRG-G04100-C Rev. 0.04), ATI Technologies: April * 1999. * * !!!! FIXME !!!! * RAGE 128 Software Development Manual (Technical Reference Manual P/N * SDK-G04000 Rev. 0.01), ATI Technologies: June 1999. * */ /* !!!! FIXME !!!! NOTE: THIS FILE HAS BEEN CONVERTED FROM r128_reg.h * AND CONTAINS REGISTERS AND REGISTER DEFINITIONS THAT ARE NOT CORRECT * ON THE RADEON. A FULL AUDIT OF THIS CODE IS NEEDED! */ #ifndef _RADEON_REG_H_ #define _RADEON_REG_H_ #include "r300_reg.h" #include "r500_reg.h" #include "r600_reg.h" #include "evergreen_reg.h" #include "ni_reg.h" #define RADEON_MC_AGP_LOCATION 0x014c #define RADEON_MC_AGP_START_MASK 0x0000FFFF #define RADEON_MC_AGP_START_SHIFT 0 #define RADEON_MC_AGP_TOP_MASK 0xFFFF0000 #define RADEON_MC_AGP_TOP_SHIFT 16 #define RADEON_MC_FB_LOCATION 0x0148 #define RADEON_MC_FB_START_MASK 0x0000FFFF #define RADEON_MC_FB_START_SHIFT 0 #define RADEON_MC_FB_TOP_MASK 0xFFFF0000 #define RADEON_MC_FB_TOP_SHIFT 16 #define RADEON_AGP_BASE_2 0x015c /* r200+ only */ #define RADEON_AGP_BASE 0x0170 #define ATI_DATATYPE_VQ 0 #define ATI_DATATYPE_CI4 1 #define ATI_DATATYPE_CI8 2 #define ATI_DATATYPE_ARGB1555 3 #define ATI_DATATYPE_RGB565 4 #define ATI_DATATYPE_RGB888 5 #define ATI_DATATYPE_ARGB8888 6 #define ATI_DATATYPE_RGB332 7 #define ATI_DATATYPE_Y8 8 #define ATI_DATATYPE_RGB8 9 #define ATI_DATATYPE_CI16 10 #define ATI_DATATYPE_VYUY_422 11 #define ATI_DATATYPE_YVYU_422 12 #define ATI_DATATYPE_AYUV_444 14 #define ATI_DATATYPE_ARGB4444 15 /* Registers for 2D/Video/Overlay */ #define RADEON_ADAPTER_ID 0x0f2c /* PCI */ #define RADEON_AGP_BASE 0x0170 #define RADEON_AGP_CNTL 0x0174 # define RADEON_AGP_APER_SIZE_256MB (0x00 << 0) # define RADEON_AGP_APER_SIZE_128MB (0x20 << 0) # define RADEON_AGP_APER_SIZE_64MB (0x30 << 0) # define RADEON_AGP_APER_SIZE_32MB (0x38 << 0) # define RADEON_AGP_APER_SIZE_16MB (0x3c << 0) # define RADEON_AGP_APER_SIZE_8MB (0x3e << 0) # define RADEON_AGP_APER_SIZE_4MB (0x3f << 0) # define RADEON_AGP_APER_SIZE_MASK (0x3f << 0) #define RADEON_STATUS_PCI_CONFIG 0x06 # define RADEON_CAP_LIST 0x100000 #define RADEON_CAPABILITIES_PTR_PCI_CONFIG 0x34 /* offset in PCI config*/ # define RADEON_CAP_PTR_MASK 0xfc /* mask off reserved bits of CAP_PTR */ # define RADEON_CAP_ID_NULL 0x00 /* End of capability list */ # define RADEON_CAP_ID_AGP 0x02 /* AGP capability ID */ # define RADEON_CAP_ID_EXP 0x10 /* PCI Express */ #define RADEON_AGP_COMMAND 0x0f60 /* PCI */ #define RADEON_AGP_COMMAND_PCI_CONFIG 0x0060 /* offset in PCI config*/ # define RADEON_AGP_ENABLE (1<<8) #define RADEON_AGP_PLL_CNTL 0x000b /* PLL */ #define RADEON_AGP_STATUS 0x0f5c /* PCI */ # define RADEON_AGP_1X_MODE 0x01 # define RADEON_AGP_2X_MODE 0x02 # define RADEON_AGP_4X_MODE 0x04 # define RADEON_AGP_FW_MODE 0x10 # define RADEON_AGP_MODE_MASK 0x17 # define RADEON_AGPv3_MODE 0x08 # define RADEON_AGPv3_4X_MODE 0x01 # define RADEON_AGPv3_8X_MODE 0x02 #define RADEON_ATTRDR 0x03c1 /* VGA */ #define RADEON_ATTRDW 0x03c0 /* VGA */ #define RADEON_ATTRX 0x03c0 /* VGA */ #define RADEON_AUX_SC_CNTL 0x1660 # define RADEON_AUX1_SC_EN (1 << 0) # define RADEON_AUX1_SC_MODE_OR (0 << 1) # define RADEON_AUX1_SC_MODE_NAND (1 << 1) # define RADEON_AUX2_SC_EN (1 << 2) # define RADEON_AUX2_SC_MODE_OR (0 << 3) # define RADEON_AUX2_SC_MODE_NAND (1 << 3) # define RADEON_AUX3_SC_EN (1 << 4) # define RADEON_AUX3_SC_MODE_OR (0 << 5) # define RADEON_AUX3_SC_MODE_NAND (1 << 5) #define RADEON_AUX1_SC_BOTTOM 0x1670 #define RADEON_AUX1_SC_LEFT 0x1664 #define RADEON_AUX1_SC_RIGHT 0x1668 #define RADEON_AUX1_SC_TOP 0x166c #define RADEON_AUX2_SC_BOTTOM 0x1680 #define RADEON_AUX2_SC_LEFT 0x1674 #define RADEON_AUX2_SC_RIGHT 0x1678 #define RADEON_AUX2_SC_TOP 0x167c #define RADEON_AUX3_SC_BOTTOM 0x1690 #define RADEON_AUX3_SC_LEFT 0x1684 #define RADEON_AUX3_SC_RIGHT 0x1688 #define RADEON_AUX3_SC_TOP 0x168c #define RADEON_AUX_WINDOW_HORZ_CNTL 0x02d8 #define RADEON_AUX_WINDOW_VERT_CNTL 0x02dc #define RADEON_BASE_CODE 0x0f0b #define RADEON_BIOS_0_SCRATCH 0x0010 # define RADEON_FP_PANEL_SCALABLE (1 << 16) # define RADEON_FP_PANEL_SCALE_EN (1 << 17) # define RADEON_FP_CHIP_SCALE_EN (1 << 18) # define RADEON_DRIVER_BRIGHTNESS_EN (1 << 26) # define RADEON_DISPLAY_ROT_MASK (3 << 28) # define RADEON_DISPLAY_ROT_00 (0 << 28) # define RADEON_DISPLAY_ROT_90 (1 << 28) # define RADEON_DISPLAY_ROT_180 (2 << 28) # define RADEON_DISPLAY_ROT_270 (3 << 28) #define RADEON_BIOS_1_SCRATCH 0x0014 #define RADEON_BIOS_2_SCRATCH 0x0018 #define RADEON_BIOS_3_SCRATCH 0x001c #define RADEON_BIOS_4_SCRATCH 0x0020 # define RADEON_CRT1_ATTACHED_MASK (3 << 0) # define RADEON_CRT1_ATTACHED_MONO (1 << 0) # define RADEON_CRT1_ATTACHED_COLOR (2 << 0) # define RADEON_LCD1_ATTACHED (1 << 2) # define RADEON_DFP1_ATTACHED (1 << 3) # define RADEON_TV1_ATTACHED_MASK (3 << 4) # define RADEON_TV1_ATTACHED_COMP (1 << 4) # define RADEON_TV1_ATTACHED_SVIDEO (2 << 4) # define RADEON_CRT2_ATTACHED_MASK (3 << 8) # define RADEON_CRT2_ATTACHED_MONO (1 << 8) # define RADEON_CRT2_ATTACHED_COLOR (2 << 8) # define RADEON_DFP2_ATTACHED (1 << 11) #define RADEON_BIOS_5_SCRATCH 0x0024 # define RADEON_LCD1_ON (1 << 0) # define RADEON_CRT1_ON (1 << 1) # define RADEON_TV1_ON (1 << 2) # define RADEON_DFP1_ON (1 << 3) # define RADEON_CRT2_ON (1 << 5) # define RADEON_CV1_ON (1 << 6) # define RADEON_DFP2_ON (1 << 7) # define RADEON_LCD1_CRTC_MASK (1 << 8) # define RADEON_LCD1_CRTC_SHIFT 8 # define RADEON_CRT1_CRTC_MASK (1 << 9) # define RADEON_CRT1_CRTC_SHIFT 9 # define RADEON_TV1_CRTC_MASK (1 << 10) # define RADEON_TV1_CRTC_SHIFT 10 # define RADEON_DFP1_CRTC_MASK (1 << 11) # define RADEON_DFP1_CRTC_SHIFT 11 # define RADEON_CRT2_CRTC_MASK (1 << 12) # define RADEON_CRT2_CRTC_SHIFT 12 # define RADEON_CV1_CRTC_MASK (1 << 13) # define RADEON_CV1_CRTC_SHIFT 13 # define RADEON_DFP2_CRTC_MASK (1 << 14) # define RADEON_DFP2_CRTC_SHIFT 14 # define RADEON_ACC_REQ_LCD1 (1 << 16) # define RADEON_ACC_REQ_CRT1 (1 << 17) # define RADEON_ACC_REQ_TV1 (1 << 18) # define RADEON_ACC_REQ_DFP1 (1 << 19) # define RADEON_ACC_REQ_CRT2 (1 << 21) # define RADEON_ACC_REQ_TV2 (1 << 22) # define RADEON_ACC_REQ_DFP2 (1 << 23) #define RADEON_BIOS_6_SCRATCH 0x0028 # define RADEON_ACC_MODE_CHANGE (1 << 2) # define RADEON_EXT_DESKTOP_MODE (1 << 3) # define RADEON_LCD_DPMS_ON (1 << 20) # define RADEON_CRT_DPMS_ON (1 << 21) # define RADEON_TV_DPMS_ON (1 << 22) # define RADEON_DFP_DPMS_ON (1 << 23) # define RADEON_DPMS_MASK (3 << 24) # define RADEON_DPMS_ON (0 << 24) # define RADEON_DPMS_STANDBY (1 << 24) # define RADEON_DPMS_SUSPEND (2 << 24) # define RADEON_DPMS_OFF (3 << 24) # define RADEON_SCREEN_BLANKING (1 << 26) # define RADEON_DRIVER_CRITICAL (1 << 27) # define RADEON_DISPLAY_SWITCHING_DIS (1 << 30) #define RADEON_BIOS_7_SCRATCH 0x002c # define RADEON_SYS_HOTKEY (1 << 10) # define RADEON_DRV_LOADED (1 << 12) #define RADEON_BIOS_ROM 0x0f30 /* PCI */ #define RADEON_BIST 0x0f0f /* PCI */ #define RADEON_BRUSH_DATA0 0x1480 #define RADEON_BRUSH_DATA1 0x1484 #define RADEON_BRUSH_DATA10 0x14a8 #define RADEON_BRUSH_DATA11 0x14ac #define RADEON_BRUSH_DATA12 0x14b0 #define RADEON_BRUSH_DATA13 0x14b4 #define RADEON_BRUSH_DATA14 0x14b8 #define RADEON_BRUSH_DATA15 0x14bc #define RADEON_BRUSH_DATA16 0x14c0 #define RADEON_BRUSH_DATA17 0x14c4 #define RADEON_BRUSH_DATA18 0x14c8 #define RADEON_BRUSH_DATA19 0x14cc #define RADEON_BRUSH_DATA2 0x1488 #define RADEON_BRUSH_DATA20 0x14d0 #define RADEON_BRUSH_DATA21 0x14d4 #define RADEON_BRUSH_DATA22 0x14d8 #define RADEON_BRUSH_DATA23 0x14dc #define RADEON_BRUSH_DATA24 0x14e0 #define RADEON_BRUSH_DATA25 0x14e4 #define RADEON_BRUSH_DATA26 0x14e8 #define RADEON_BRUSH_DATA27 0x14ec #define RADEON_BRUSH_DATA28 0x14f0 #define RADEON_BRUSH_DATA29 0x14f4 #define RADEON_BRUSH_DATA3 0x148c #define RADEON_BRUSH_DATA30 0x14f8 #define RADEON_BRUSH_DATA31 0x14fc #define RADEON_BRUSH_DATA32 0x1500 #define RADEON_BRUSH_DATA33 0x1504 #define RADEON_BRUSH_DATA34 0x1508 #define RADEON_BRUSH_DATA35 0x150c #define RADEON_BRUSH_DATA36 0x1510 #define RADEON_BRUSH_DATA37 0x1514 #define RADEON_BRUSH_DATA38 0x1518 #define RADEON_BRUSH_DATA39 0x151c #define RADEON_BRUSH_DATA4 0x1490 #define RADEON_BRUSH_DATA40 0x1520 #define RADEON_BRUSH_DATA41 0x1524 #define RADEON_BRUSH_DATA42 0x1528 #define RADEON_BRUSH_DATA43 0x152c #define RADEON_BRUSH_DATA44 0x1530 #define RADEON_BRUSH_DATA45 0x1534 #define RADEON_BRUSH_DATA46 0x1538 #define RADEON_BRUSH_DATA47 0x153c #define RADEON_BRUSH_DATA48 0x1540 #define RADEON_BRUSH_DATA49 0x1544 #define RADEON_BRUSH_DATA5 0x1494 #define RADEON_BRUSH_DATA50 0x1548 #define RADEON_BRUSH_DATA51 0x154c #define RADEON_BRUSH_DATA52 0x1550 #define RADEON_BRUSH_DATA53 0x1554 #define RADEON_BRUSH_DATA54 0x1558 #define RADEON_BRUSH_DATA55 0x155c #define RADEON_BRUSH_DATA56 0x1560 #define RADEON_BRUSH_DATA57 0x1564 #define RADEON_BRUSH_DATA58 0x1568 #define RADEON_BRUSH_DATA59 0x156c #define RADEON_BRUSH_DATA6 0x1498 #define RADEON_BRUSH_DATA60 0x1570 #define RADEON_BRUSH_DATA61 0x1574 #define RADEON_BRUSH_DATA62 0x1578 #define RADEON_BRUSH_DATA63 0x157c #define RADEON_BRUSH_DATA7 0x149c #define RADEON_BRUSH_DATA8 0x14a0 #define RADEON_BRUSH_DATA9 0x14a4 #define RADEON_BRUSH_SCALE 0x1470 #define RADEON_BRUSH_Y_X 0x1474 #define RADEON_BUS_CNTL 0x0030 # define RADEON_BUS_MASTER_DIS (1 << 6) # define RADEON_BUS_BIOS_DIS_ROM (1 << 12) # define RS600_BUS_MASTER_DIS (1 << 14) # define RS600_MSI_REARM (1 << 20) /* rs600/rs690/rs740 */ # define RADEON_BUS_RD_DISCARD_EN (1 << 24) # define RADEON_BUS_RD_ABORT_EN (1 << 25) # define RADEON_BUS_MSTR_DISCONNECT_EN (1 << 28) # define RADEON_BUS_WRT_BURST (1 << 29) # define RADEON_BUS_READ_BURST (1 << 30) #define RADEON_BUS_CNTL1 0x0034 # define RADEON_BUS_WAIT_ON_LOCK_EN (1 << 4) #define RV370_BUS_CNTL 0x004c # define RV370_BUS_BIOS_DIS_ROM (1 << 2) /* rv370/rv380, rv410, r423/r430/r480, r5xx */ #define RADEON_MSI_REARM_EN 0x0160 # define RV370_MSI_REARM_EN (1 << 0) /* #define RADEON_PCIE_INDEX 0x0030 */ /* #define RADEON_PCIE_DATA 0x0034 */ #define RADEON_PCIE_LC_LINK_WIDTH_CNTL 0xa2 /* PCIE */ # define RADEON_PCIE_LC_LINK_WIDTH_SHIFT 0 # define RADEON_PCIE_LC_LINK_WIDTH_MASK 0x7 # define RADEON_PCIE_LC_LINK_WIDTH_X0 0 # define RADEON_PCIE_LC_LINK_WIDTH_X1 1 # define RADEON_PCIE_LC_LINK_WIDTH_X2 2 # define RADEON_PCIE_LC_LINK_WIDTH_X4 3 # define RADEON_PCIE_LC_LINK_WIDTH_X8 4 # define RADEON_PCIE_LC_LINK_WIDTH_X12 5 # define RADEON_PCIE_LC_LINK_WIDTH_X16 6 # define RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT 4 # define RADEON_PCIE_LC_LINK_WIDTH_RD_MASK 0x70 # define RADEON_PCIE_LC_RECONFIG_NOW (1 << 8) # define RADEON_PCIE_LC_RECONFIG_LATER (1 << 9) # define RADEON_PCIE_LC_SHORT_RECONFIG_EN (1 << 10) # define R600_PCIE_LC_RECONFIG_ARC_MISSING_ESCAPE (1 << 7) # define R600_PCIE_LC_RENEGOTIATION_SUPPORT (1 << 9) # define R600_PCIE_LC_RENEGOTIATE_EN (1 << 10) # define R600_PCIE_LC_SHORT_RECONFIG_EN (1 << 11) # define R600_PCIE_LC_UPCONFIGURE_SUPPORT (1 << 12) # define R600_PCIE_LC_UPCONFIGURE_DIS (1 << 13) #define R600_TARGET_AND_CURRENT_PROFILE_INDEX 0x70c #define R700_TARGET_AND_CURRENT_PROFILE_INDEX 0x66c #define RADEON_CACHE_CNTL 0x1724 #define RADEON_CACHE_LINE 0x0f0c /* PCI */ #define RADEON_CAPABILITIES_ID 0x0f50 /* PCI */ #define RADEON_CAPABILITIES_PTR 0x0f34 /* PCI */ #define RADEON_CLK_PIN_CNTL 0x0001 /* PLL */ # define RADEON_DONT_USE_XTALIN (1 << 4) # define RADEON_SCLK_DYN_START_CNTL (1 << 15) #define RADEON_CLOCK_CNTL_DATA 0x000c #define RADEON_CLOCK_CNTL_INDEX 0x0008 # define RADEON_PLL_WR_EN (1 << 7) # define RADEON_PLL_DIV_SEL (3 << 8) # define RADEON_PLL2_DIV_SEL_MASK (~(3 << 8)) #define RADEON_CLK_PWRMGT_CNTL 0x0014 # define RADEON_ENGIN_DYNCLK_MODE (1 << 12) # define RADEON_ACTIVE_HILO_LAT_MASK (3 << 13) # define RADEON_ACTIVE_HILO_LAT_SHIFT 13 # define RADEON_DISP_DYN_STOP_LAT_MASK (1 << 12) # define RADEON_MC_BUSY (1 << 16) # define RADEON_DLL_READY (1 << 19) # define RADEON_CG_NO1_DEBUG_0 (1 << 24) # define RADEON_CG_NO1_DEBUG_MASK (0x1f << 24) # define RADEON_DYN_STOP_MODE_MASK (7 << 21) # define RADEON_TVPLL_PWRMGT_OFF (1 << 30) # define RADEON_TVCLK_TURNOFF (1 << 31) #define RADEON_PLL_PWRMGT_CNTL 0x0015 /* PLL */ # define RADEON_PM_MODE_SEL (1 << 13) # define RADEON_TCL_BYPASS_DISABLE (1 << 20) #define RADEON_CLR_CMP_CLR_3D 0x1a24 #define RADEON_CLR_CMP_CLR_DST 0x15c8 #define RADEON_CLR_CMP_CLR_SRC 0x15c4 #define RADEON_CLR_CMP_CNTL 0x15c0 # define RADEON_SRC_CMP_EQ_COLOR (4 << 0) # define RADEON_SRC_CMP_NEQ_COLOR (5 << 0) # define RADEON_CLR_CMP_SRC_SOURCE (1 << 24) #define RADEON_CLR_CMP_MASK 0x15cc # define RADEON_CLR_CMP_MSK 0xffffffff #define RADEON_CLR_CMP_MASK_3D 0x1A28 #define RADEON_COMMAND 0x0f04 /* PCI */ #define RADEON_COMPOSITE_SHADOW_ID 0x1a0c #define RADEON_CONFIG_APER_0_BASE 0x0100 #define RADEON_CONFIG_APER_1_BASE 0x0104 #define RADEON_CONFIG_APER_SIZE 0x0108 #define RADEON_CONFIG_BONDS 0x00e8 #define RADEON_CONFIG_CNTL 0x00e0 # define RADEON_CFG_VGA_RAM_EN (1 << 8) # define RADEON_CFG_VGA_IO_DIS (1 << 9) # define RADEON_CFG_ATI_REV_A11 (0 << 16) # define RADEON_CFG_ATI_REV_A12 (1 << 16) # define RADEON_CFG_ATI_REV_A13 (2 << 16) # define RADEON_CFG_ATI_REV_ID_MASK (0xf << 16) #define RADEON_CONFIG_MEMSIZE 0x00f8 #define RADEON_CONFIG_MEMSIZE_EMBEDDED 0x0114 #define RADEON_CONFIG_REG_1_BASE 0x010c #define RADEON_CONFIG_REG_APER_SIZE 0x0110 #define RADEON_CONFIG_XSTRAP 0x00e4 #define RADEON_CONSTANT_COLOR_C 0x1d34 # define RADEON_CONSTANT_COLOR_MASK 0x00ffffff # define RADEON_CONSTANT_COLOR_ONE 0x00ffffff # define RADEON_CONSTANT_COLOR_ZERO 0x00000000 #define RADEON_CRC_CMDFIFO_ADDR 0x0740 #define RADEON_CRC_CMDFIFO_DOUT 0x0744 #define RADEON_GRPH_BUFFER_CNTL 0x02f0 # define RADEON_GRPH_START_REQ_MASK (0x7f) # define RADEON_GRPH_START_REQ_SHIFT 0 # define RADEON_GRPH_STOP_REQ_MASK (0x7f<<8) # define RADEON_GRPH_STOP_REQ_SHIFT 8 # define RADEON_GRPH_CRITICAL_POINT_MASK (0x7f<<16) # define RADEON_GRPH_CRITICAL_POINT_SHIFT 16 # define RADEON_GRPH_CRITICAL_CNTL (1<<28) # define RADEON_GRPH_BUFFER_SIZE (1<<29) # define RADEON_GRPH_CRITICAL_AT_SOF (1<<30) # define RADEON_GRPH_STOP_CNTL (1<<31) #define RADEON_GRPH2_BUFFER_CNTL 0x03f0 # define RADEON_GRPH2_START_REQ_MASK (0x7f) # define RADEON_GRPH2_START_REQ_SHIFT 0 # define RADEON_GRPH2_STOP_REQ_MASK (0x7f<<8) # define RADEON_GRPH2_STOP_REQ_SHIFT 8 # define RADEON_GRPH2_CRITICAL_POINT_MASK (0x7f<<16) # define RADEON_GRPH2_CRITICAL_POINT_SHIFT 16 # define RADEON_GRPH2_CRITICAL_CNTL (1<<28) # define RADEON_GRPH2_BUFFER_SIZE (1<<29) # define RADEON_GRPH2_CRITICAL_AT_SOF (1<<30) # define RADEON_GRPH2_STOP_CNTL (1<<31) #define RADEON_CRTC_CRNT_FRAME 0x0214 #define RADEON_CRTC_EXT_CNTL 0x0054 # define RADEON_CRTC_VGA_XOVERSCAN (1 << 0) # define RADEON_VGA_ATI_LINEAR (1 << 3) # define RADEON_XCRT_CNT_EN (1 << 6) # define RADEON_CRTC_HSYNC_DIS (1 << 8) # define RADEON_CRTC_VSYNC_DIS (1 << 9) # define RADEON_CRTC_DISPLAY_DIS (1 << 10) # define RADEON_CRTC_SYNC_TRISTAT (1 << 11) # define RADEON_CRTC_CRT_ON (1 << 15) #define RADEON_CRTC_EXT_CNTL_DPMS_BYTE 0x0055 # define RADEON_CRTC_HSYNC_DIS_BYTE (1 << 0) # define RADEON_CRTC_VSYNC_DIS_BYTE (1 << 1) # define RADEON_CRTC_DISPLAY_DIS_BYTE (1 << 2) #define RADEON_CRTC_GEN_CNTL 0x0050 # define RADEON_CRTC_DBL_SCAN_EN (1 << 0) # define RADEON_CRTC_INTERLACE_EN (1 << 1) # define RADEON_CRTC_CSYNC_EN (1 << 4) # define RADEON_CRTC_ICON_EN (1 << 15) # define RADEON_CRTC_CUR_EN (1 << 16) # define RADEON_CRTC_VSTAT_MODE_MASK (3 << 17) # define RADEON_CRTC_CUR_MODE_MASK (7 << 20) # define RADEON_CRTC_CUR_MODE_SHIFT 20 # define RADEON_CRTC_CUR_MODE_MONO 0 # define RADEON_CRTC_CUR_MODE_24BPP 2 # define RADEON_CRTC_EXT_DISP_EN (1 << 24) # define RADEON_CRTC_EN (1 << 25) # define RADEON_CRTC_DISP_REQ_EN_B (1 << 26) #define RADEON_CRTC2_GEN_CNTL 0x03f8 # define RADEON_CRTC2_DBL_SCAN_EN (1 << 0) # define RADEON_CRTC2_INTERLACE_EN (1 << 1) # define RADEON_CRTC2_SYNC_TRISTAT (1 << 4) # define RADEON_CRTC2_HSYNC_TRISTAT (1 << 5) # define RADEON_CRTC2_VSYNC_TRISTAT (1 << 6) # define RADEON_CRTC2_CRT2_ON (1 << 7) # define RADEON_CRTC2_PIX_WIDTH_SHIFT 8 # define RADEON_CRTC2_PIX_WIDTH_MASK (0xf << 8) # define RADEON_CRTC2_ICON_EN (1 << 15) # define RADEON_CRTC2_CUR_EN (1 << 16) # define RADEON_CRTC2_CUR_MODE_MASK (7 << 20) # define RADEON_CRTC2_DISP_DIS (1 << 23) # define RADEON_CRTC2_EN (1 << 25) # define RADEON_CRTC2_DISP_REQ_EN_B (1 << 26) # define RADEON_CRTC2_CSYNC_EN (1 << 27) # define RADEON_CRTC2_HSYNC_DIS (1 << 28) # define RADEON_CRTC2_VSYNC_DIS (1 << 29) #define RADEON_CRTC_MORE_CNTL 0x27c # define RADEON_CRTC_AUTO_HORZ_CENTER_EN (1<<2) # define RADEON_CRTC_AUTO_VERT_CENTER_EN (1<<3) # define RADEON_CRTC_H_CUTOFF_ACTIVE_EN (1<<4) # define RADEON_CRTC_V_CUTOFF_ACTIVE_EN (1<<5) #define RADEON_CRTC_GUI_TRIG_VLINE 0x0218 #define RADEON_CRTC_H_SYNC_STRT_WID 0x0204 # define RADEON_CRTC_H_SYNC_STRT_PIX (0x07 << 0) # define RADEON_CRTC_H_SYNC_STRT_CHAR (0x3ff << 3) # define RADEON_CRTC_H_SYNC_STRT_CHAR_SHIFT 3 # define RADEON_CRTC_H_SYNC_WID (0x3f << 16) # define RADEON_CRTC_H_SYNC_WID_SHIFT 16 # define RADEON_CRTC_H_SYNC_POL (1 << 23) #define RADEON_CRTC2_H_SYNC_STRT_WID 0x0304 # define RADEON_CRTC2_H_SYNC_STRT_PIX (0x07 << 0) # define RADEON_CRTC2_H_SYNC_STRT_CHAR (0x3ff << 3) # define RADEON_CRTC2_H_SYNC_STRT_CHAR_SHIFT 3 # define RADEON_CRTC2_H_SYNC_WID (0x3f << 16) # define RADEON_CRTC2_H_SYNC_WID_SHIFT 16 # define RADEON_CRTC2_H_SYNC_POL (1 << 23) #define RADEON_CRTC_H_TOTAL_DISP 0x0200 # define RADEON_CRTC_H_TOTAL (0x03ff << 0) # define RADEON_CRTC_H_TOTAL_SHIFT 0 # define RADEON_CRTC_H_DISP (0x01ff << 16) # define RADEON_CRTC_H_DISP_SHIFT 16 #define RADEON_CRTC2_H_TOTAL_DISP 0x0300 # define RADEON_CRTC2_H_TOTAL (0x03ff << 0) # define RADEON_CRTC2_H_TOTAL_SHIFT 0 # define RADEON_CRTC2_H_DISP (0x01ff << 16) # define RADEON_CRTC2_H_DISP_SHIFT 16 #define RADEON_CRTC_OFFSET_RIGHT 0x0220 #define RADEON_CRTC_OFFSET 0x0224 # define RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET (1<<30) # define RADEON_CRTC_OFFSET__OFFSET_LOCK (1<<31) #define RADEON_CRTC2_OFFSET 0x0324 # define RADEON_CRTC2_OFFSET__GUI_TRIG_OFFSET (1<<30) # define RADEON_CRTC2_OFFSET__OFFSET_LOCK (1<<31) #define RADEON_CRTC_OFFSET_CNTL 0x0228 # define RADEON_CRTC_TILE_LINE_SHIFT 0 # define RADEON_CRTC_TILE_LINE_RIGHT_SHIFT 4 # define R300_CRTC_X_Y_MODE_EN_RIGHT (1 << 6) # define R300_CRTC_MICRO_TILE_BUFFER_RIGHT_MASK (3 << 7) # define R300_CRTC_MICRO_TILE_BUFFER_RIGHT_AUTO (0 << 7) # define R300_CRTC_MICRO_TILE_BUFFER_RIGHT_SINGLE (1 << 7) # define R300_CRTC_MICRO_TILE_BUFFER_RIGHT_DOUBLE (2 << 7) # define R300_CRTC_MICRO_TILE_BUFFER_RIGHT_DIS (3 << 7) # define R300_CRTC_X_Y_MODE_EN (1 << 9) # define R300_CRTC_MICRO_TILE_BUFFER_MASK (3 << 10) # define R300_CRTC_MICRO_TILE_BUFFER_AUTO (0 << 10) # define R300_CRTC_MICRO_TILE_BUFFER_SINGLE (1 << 10) # define R300_CRTC_MICRO_TILE_BUFFER_DOUBLE (2 << 10) # define R300_CRTC_MICRO_TILE_BUFFER_DIS (3 << 10) # define R300_CRTC_MICRO_TILE_EN_RIGHT (1 << 12) # define R300_CRTC_MICRO_TILE_EN (1 << 13) # define R300_CRTC_MACRO_TILE_EN_RIGHT (1 << 14) # define R300_CRTC_MACRO_TILE_EN (1 << 15) # define RADEON_CRTC_TILE_EN_RIGHT (1 << 14) # define RADEON_CRTC_TILE_EN (1 << 15) # define RADEON_CRTC_OFFSET_FLIP_CNTL (1 << 16) # define RADEON_CRTC_STEREO_OFFSET_EN (1 << 17) # define RADEON_CRTC_GUI_TRIG_OFFSET_LEFT_EN (1 << 28) # define RADEON_CRTC_GUI_TRIG_OFFSET_RIGHT_EN (1 << 29) #define R300_CRTC_TILE_X0_Y0 0x0350 #define R300_CRTC2_TILE_X0_Y0 0x0358 #define RADEON_CRTC2_OFFSET_CNTL 0x0328 # define RADEON_CRTC2_OFFSET_FLIP_CNTL (1 << 16) # define RADEON_CRTC2_TILE_EN (1 << 15) #define RADEON_CRTC_PITCH 0x022c # define RADEON_CRTC_PITCH__SHIFT 0 # define RADEON_CRTC_PITCH__RIGHT_SHIFT 16 #define RADEON_CRTC2_PITCH 0x032c #define RADEON_CRTC_STATUS 0x005c # define RADEON_CRTC_VBLANK_SAVE (1 << 1) # define RADEON_CRTC_VBLANK_SAVE_CLEAR (1 << 1) #define RADEON_CRTC2_STATUS 0x03fc # define RADEON_CRTC2_VBLANK_SAVE (1 << 1) # define RADEON_CRTC2_VBLANK_SAVE_CLEAR (1 << 1) #define RADEON_CRTC_V_SYNC_STRT_WID 0x020c # define RADEON_CRTC_V_SYNC_STRT (0x7ff << 0) # define RADEON_CRTC_V_SYNC_STRT_SHIFT 0 # define RADEON_CRTC_V_SYNC_WID (0x1f << 16) # define RADEON_CRTC_V_SYNC_WID_SHIFT 16 # define RADEON_CRTC_V_SYNC_POL (1 << 23) #define RADEON_CRTC2_V_SYNC_STRT_WID 0x030c # define RADEON_CRTC2_V_SYNC_STRT (0x7ff << 0) # define RADEON_CRTC2_V_SYNC_STRT_SHIFT 0 # define RADEON_CRTC2_V_SYNC_WID (0x1f << 16) # define RADEON_CRTC2_V_SYNC_WID_SHIFT 16 # define RADEON_CRTC2_V_SYNC_POL (1 << 23) #define RADEON_CRTC_V_TOTAL_DISP 0x0208 # define RADEON_CRTC_V_TOTAL (0x07ff << 0) # define RADEON_CRTC_V_TOTAL_SHIFT 0 # define RADEON_CRTC_V_DISP (0x07ff << 16) # define RADEON_CRTC_V_DISP_SHIFT 16 #define RADEON_CRTC2_V_TOTAL_DISP 0x0308 # define RADEON_CRTC2_V_TOTAL (0x07ff << 0) # define RADEON_CRTC2_V_TOTAL_SHIFT 0 # define RADEON_CRTC2_V_DISP (0x07ff << 16) # define RADEON_CRTC2_V_DISP_SHIFT 16 #define RADEON_CRTC_VLINE_CRNT_VLINE 0x0210 # define RADEON_CRTC_CRNT_VLINE_MASK (0x7ff << 16) #define RADEON_CRTC2_CRNT_FRAME 0x0314 #define RADEON_CRTC2_GUI_TRIG_VLINE 0x0318 #define RADEON_CRTC2_VLINE_CRNT_VLINE 0x0310 #define RADEON_CRTC8_DATA 0x03d5 /* VGA, 0x3b5 */ #define RADEON_CRTC8_IDX 0x03d4 /* VGA, 0x3b4 */ #define RADEON_CUR_CLR0 0x026c #define RADEON_CUR_CLR1 0x0270 #define RADEON_CUR_HORZ_VERT_OFF 0x0268 #define RADEON_CUR_HORZ_VERT_POSN 0x0264 #define RADEON_CUR_OFFSET 0x0260 # define RADEON_CUR_LOCK (1 << 31) #define RADEON_CUR2_CLR0 0x036c #define RADEON_CUR2_CLR1 0x0370 #define RADEON_CUR2_HORZ_VERT_OFF 0x0368 #define RADEON_CUR2_HORZ_VERT_POSN 0x0364 #define RADEON_CUR2_OFFSET 0x0360 # define RADEON_CUR2_LOCK (1 << 31) #define RADEON_DAC_CNTL 0x0058 # define RADEON_DAC_RANGE_CNTL (3 << 0) # define RADEON_DAC_RANGE_CNTL_PS2 (2 << 0) # define RADEON_DAC_RANGE_CNTL_MASK 0x03 # define RADEON_DAC_BLANKING (1 << 2) # define RADEON_DAC_CMP_EN (1 << 3) # define RADEON_DAC_CMP_OUTPUT (1 << 7) # define RADEON_DAC_8BIT_EN (1 << 8) # define RADEON_DAC_TVO_EN (1 << 10) # define RADEON_DAC_VGA_ADR_EN (1 << 13) # define RADEON_DAC_PDWN (1 << 15) # define RADEON_DAC_MASK_ALL (0xff << 24) #define RADEON_DAC_CNTL2 0x007c # define RADEON_DAC2_TV_CLK_SEL (0 << 1) # define RADEON_DAC2_DAC_CLK_SEL (1 << 0) # define RADEON_DAC2_DAC2_CLK_SEL (1 << 1) # define RADEON_DAC2_PALETTE_ACC_CTL (1 << 5) # define RADEON_DAC2_CMP_EN (1 << 7) # define RADEON_DAC2_CMP_OUT_R (1 << 8) # define RADEON_DAC2_CMP_OUT_G (1 << 9) # define RADEON_DAC2_CMP_OUT_B (1 << 10) # define RADEON_DAC2_CMP_OUTPUT (1 << 11) #define RADEON_DAC_EXT_CNTL 0x0280 # define RADEON_DAC2_FORCE_BLANK_OFF_EN (1 << 0) # define RADEON_DAC2_FORCE_DATA_EN (1 << 1) # define RADEON_DAC_FORCE_BLANK_OFF_EN (1 << 4) # define RADEON_DAC_FORCE_DATA_EN (1 << 5) # define RADEON_DAC_FORCE_DATA_SEL_MASK (3 << 6) # define RADEON_DAC_FORCE_DATA_SEL_R (0 << 6) # define RADEON_DAC_FORCE_DATA_SEL_G (1 << 6) # define RADEON_DAC_FORCE_DATA_SEL_B (2 << 6) # define RADEON_DAC_FORCE_DATA_SEL_RGB (3 << 6) # define RADEON_DAC_FORCE_DATA_MASK 0x0003ff00 # define RADEON_DAC_FORCE_DATA_SHIFT 8 #define RADEON_DAC_MACRO_CNTL 0x0d04 # define RADEON_DAC_PDWN_R (1 << 16) # define RADEON_DAC_PDWN_G (1 << 17) # define RADEON_DAC_PDWN_B (1 << 18) #define RADEON_DISP_PWR_MAN 0x0d08 # define RADEON_DISP_PWR_MAN_D3_CRTC_EN (1 << 0) # define RADEON_DISP_PWR_MAN_D3_CRTC2_EN (1 << 4) # define RADEON_DISP_PWR_MAN_DPMS_ON (0 << 8) # define RADEON_DISP_PWR_MAN_DPMS_STANDBY (1 << 8) # define RADEON_DISP_PWR_MAN_DPMS_SUSPEND (2 << 8) # define RADEON_DISP_PWR_MAN_DPMS_OFF (3 << 8) # define RADEON_DISP_D3_RST (1 << 16) # define RADEON_DISP_D3_REG_RST (1 << 17) # define RADEON_DISP_D3_GRPH_RST (1 << 18) # define RADEON_DISP_D3_SUBPIC_RST (1 << 19) # define RADEON_DISP_D3_OV0_RST (1 << 20) # define RADEON_DISP_D1D2_GRPH_RST (1 << 21) # define RADEON_DISP_D1D2_SUBPIC_RST (1 << 22) # define RADEON_DISP_D1D2_OV0_RST (1 << 23) # define RADEON_DIG_TMDS_ENABLE_RST (1 << 24) # define RADEON_TV_ENABLE_RST (1 << 25) # define RADEON_AUTO_PWRUP_EN (1 << 26) #define RADEON_TV_DAC_CNTL 0x088c # define RADEON_TV_DAC_NBLANK (1 << 0) # define RADEON_TV_DAC_NHOLD (1 << 1) # define RADEON_TV_DAC_PEDESTAL (1 << 2) # define RADEON_TV_MONITOR_DETECT_EN (1 << 4) # define RADEON_TV_DAC_CMPOUT (1 << 5) # define RADEON_TV_DAC_STD_MASK (3 << 8) # define RADEON_TV_DAC_STD_PAL (0 << 8) # define RADEON_TV_DAC_STD_NTSC (1 << 8) # define RADEON_TV_DAC_STD_PS2 (2 << 8) # define RADEON_TV_DAC_STD_RS343 (3 << 8) # define RADEON_TV_DAC_BGSLEEP (1 << 6) # define RADEON_TV_DAC_BGADJ_MASK (0xf << 16) # define RADEON_TV_DAC_BGADJ_SHIFT 16 # define RADEON_TV_DAC_DACADJ_MASK (0xf << 20) # define RADEON_TV_DAC_DACADJ_SHIFT 20 # define RADEON_TV_DAC_RDACPD (1 << 24) # define RADEON_TV_DAC_GDACPD (1 << 25) # define RADEON_TV_DAC_BDACPD (1 << 26) # define RADEON_TV_DAC_RDACDET (1 << 29) # define RADEON_TV_DAC_GDACDET (1 << 30) # define RADEON_TV_DAC_BDACDET (1 << 31) # define R420_TV_DAC_DACADJ_MASK (0x1f << 20) # define R420_TV_DAC_RDACPD (1 << 25) # define R420_TV_DAC_GDACPD (1 << 26) # define R420_TV_DAC_BDACPD (1 << 27) # define R420_TV_DAC_TVENABLE (1 << 28) #define RADEON_DISP_HW_DEBUG 0x0d14 # define RADEON_CRT2_DISP1_SEL (1 << 5) #define RADEON_DISP_OUTPUT_CNTL 0x0d64 # define RADEON_DISP_DAC_SOURCE_MASK 0x03 # define RADEON_DISP_DAC2_SOURCE_MASK 0x0c # define RADEON_DISP_DAC_SOURCE_CRTC2 0x01 # define RADEON_DISP_DAC_SOURCE_RMX 0x02 # define RADEON_DISP_DAC_SOURCE_LTU 0x03 # define RADEON_DISP_DAC2_SOURCE_CRTC2 0x04 # define RADEON_DISP_TVDAC_SOURCE_MASK (0x03 << 2) # define RADEON_DISP_TVDAC_SOURCE_CRTC 0x0 # define RADEON_DISP_TVDAC_SOURCE_CRTC2 (0x01 << 2) # define RADEON_DISP_TVDAC_SOURCE_RMX (0x02 << 2) # define RADEON_DISP_TVDAC_SOURCE_LTU (0x03 << 2) # define RADEON_DISP_TRANS_MATRIX_MASK (0x03 << 4) # define RADEON_DISP_TRANS_MATRIX_ALPHA_MSB (0x00 << 4) # define RADEON_DISP_TRANS_MATRIX_GRAPHICS (0x01 << 4) # define RADEON_DISP_TRANS_MATRIX_VIDEO (0x02 << 4) # define RADEON_DISP_TV_SOURCE_CRTC (1 << 16) /* crtc1 or crtc2 */ # define RADEON_DISP_TV_SOURCE_LTU (0 << 16) /* linear transform unit */ #define RADEON_DISP_TV_OUT_CNTL 0x0d6c # define RADEON_DISP_TV_PATH_SRC_CRTC2 (1 << 16) # define RADEON_DISP_TV_PATH_SRC_CRTC1 (0 << 16) #define RADEON_DAC_CRC_SIG 0x02cc #define RADEON_DAC_DATA 0x03c9 /* VGA */ #define RADEON_DAC_MASK 0x03c6 /* VGA */ #define RADEON_DAC_R_INDEX 0x03c7 /* VGA */ #define RADEON_DAC_W_INDEX 0x03c8 /* VGA */ #define RADEON_DDA_CONFIG 0x02e0 #define RADEON_DDA_ON_OFF 0x02e4 #define RADEON_DEFAULT_OFFSET 0x16e0 #define RADEON_DEFAULT_PITCH 0x16e4 #define RADEON_DEFAULT_SC_BOTTOM_RIGHT 0x16e8 # define RADEON_DEFAULT_SC_RIGHT_MAX (0x1fff << 0) # define RADEON_DEFAULT_SC_BOTTOM_MAX (0x1fff << 16) #define RADEON_DESTINATION_3D_CLR_CMP_VAL 0x1820 #define RADEON_DESTINATION_3D_CLR_CMP_MSK 0x1824 #define RADEON_DEVICE_ID 0x0f02 /* PCI */ #define RADEON_DISP_MISC_CNTL 0x0d00 # define RADEON_SOFT_RESET_GRPH_PP (1 << 0) #define RADEON_DISP_MERGE_CNTL 0x0d60 # define RADEON_DISP_ALPHA_MODE_MASK 0x03 # define RADEON_DISP_ALPHA_MODE_KEY 0 # define RADEON_DISP_ALPHA_MODE_PER_PIXEL 1 # define RADEON_DISP_ALPHA_MODE_GLOBAL 2 # define RADEON_DISP_RGB_OFFSET_EN (1 << 8) # define RADEON_DISP_GRPH_ALPHA_MASK (0xff << 16) # define RADEON_DISP_OV0_ALPHA_MASK (0xff << 24) # define RADEON_DISP_LIN_TRANS_BYPASS (0x01 << 9) #define RADEON_DISP2_MERGE_CNTL 0x0d68 # define RADEON_DISP2_RGB_OFFSET_EN (1 << 8) #define RADEON_DISP_LIN_TRANS_GRPH_A 0x0d80 #define RADEON_DISP_LIN_TRANS_GRPH_B 0x0d84 #define RADEON_DISP_LIN_TRANS_GRPH_C 0x0d88 #define RADEON_DISP_LIN_TRANS_GRPH_D 0x0d8c #define RADEON_DISP_LIN_TRANS_GRPH_E 0x0d90 #define RADEON_DISP_LIN_TRANS_GRPH_F 0x0d98 #define RADEON_DP_BRUSH_BKGD_CLR 0x1478 #define RADEON_DP_BRUSH_FRGD_CLR 0x147c #define RADEON_DP_CNTL 0x16c0 # define RADEON_DST_X_LEFT_TO_RIGHT (1 << 0) # define RADEON_DST_Y_TOP_TO_BOTTOM (1 << 1) # define RADEON_DP_DST_TILE_LINEAR (0 << 3) # define RADEON_DP_DST_TILE_MACRO (1 << 3) # define RADEON_DP_DST_TILE_MICRO (2 << 3) # define RADEON_DP_DST_TILE_BOTH (3 << 3) #define RADEON_DP_CNTL_XDIR_YDIR_YMAJOR 0x16d0 # define RADEON_DST_Y_MAJOR (1 << 2) # define RADEON_DST_Y_DIR_TOP_TO_BOTTOM (1 << 15) # define RADEON_DST_X_DIR_LEFT_TO_RIGHT (1 << 31) #define RADEON_DP_DATATYPE 0x16c4 # define RADEON_HOST_BIG_ENDIAN_EN (1 << 29) #define RADEON_DP_GUI_MASTER_CNTL 0x146c # define RADEON_GMC_SRC_PITCH_OFFSET_CNTL (1 << 0) # define RADEON_GMC_DST_PITCH_OFFSET_CNTL (1 << 1) # define RADEON_GMC_SRC_CLIPPING (1 << 2) # define RADEON_GMC_DST_CLIPPING (1 << 3) # define RADEON_GMC_BRUSH_DATATYPE_MASK (0x0f << 4) # define RADEON_GMC_BRUSH_8X8_MONO_FG_BG (0 << 4) # define RADEON_GMC_BRUSH_8X8_MONO_FG_LA (1 << 4) # define RADEON_GMC_BRUSH_1X8_MONO_FG_BG (4 << 4) # define RADEON_GMC_BRUSH_1X8_MONO_FG_LA (5 << 4) # define RADEON_GMC_BRUSH_32x1_MONO_FG_BG (6 << 4) # define RADEON_GMC_BRUSH_32x1_MONO_FG_LA (7 << 4) # define RADEON_GMC_BRUSH_32x32_MONO_FG_BG (8 << 4) # define RADEON_GMC_BRUSH_32x32_MONO_FG_LA (9 << 4) # define RADEON_GMC_BRUSH_8x8_COLOR (10 << 4) # define RADEON_GMC_BRUSH_1X8_COLOR (12 << 4) # define RADEON_GMC_BRUSH_SOLID_COLOR (13 << 4) # define RADEON_GMC_BRUSH_NONE (15 << 4) # define RADEON_GMC_DST_8BPP_CI (2 << 8) # define RADEON_GMC_DST_15BPP (3 << 8) # define RADEON_GMC_DST_16BPP (4 << 8) # define RADEON_GMC_DST_24BPP (5 << 8) # define RADEON_GMC_DST_32BPP (6 << 8) # define RADEON_GMC_DST_8BPP_RGB (7 << 8) # define RADEON_GMC_DST_Y8 (8 << 8) # define RADEON_GMC_DST_RGB8 (9 << 8) # define RADEON_GMC_DST_VYUY (11 << 8) # define RADEON_GMC_DST_YVYU (12 << 8) # define RADEON_GMC_DST_AYUV444 (14 << 8) # define RADEON_GMC_DST_ARGB4444 (15 << 8) # define RADEON_GMC_DST_DATATYPE_MASK (0x0f << 8) # define RADEON_GMC_DST_DATATYPE_SHIFT 8 # define RADEON_GMC_SRC_DATATYPE_MASK (3 << 12) # define RADEON_GMC_SRC_DATATYPE_MONO_FG_BG (0 << 12) # define RADEON_GMC_SRC_DATATYPE_MONO_FG_LA (1 << 12) # define RADEON_GMC_SRC_DATATYPE_COLOR (3 << 12) # define RADEON_GMC_BYTE_PIX_ORDER (1 << 14) # define RADEON_GMC_BYTE_MSB_TO_LSB (0 << 14) # define RADEON_GMC_BYTE_LSB_TO_MSB (1 << 14) # define RADEON_GMC_CONVERSION_TEMP (1 << 15) # define RADEON_GMC_CONVERSION_TEMP_6500 (0 << 15) # define RADEON_GMC_CONVERSION_TEMP_9300 (1 << 15) # define RADEON_GMC_ROP3_MASK (0xff << 16) # define RADEON_DP_SRC_SOURCE_MASK (7 << 24) # define RADEON_DP_SRC_SOURCE_MEMORY (2 << 24) # define RADEON_DP_SRC_SOURCE_HOST_DATA (3 << 24) # define RADEON_GMC_3D_FCN_EN (1 << 27) # define RADEON_GMC_CLR_CMP_CNTL_DIS (1 << 28) # define RADEON_GMC_AUX_CLIP_DIS (1 << 29) # define RADEON_GMC_WR_MSK_DIS (1 << 30) # define RADEON_GMC_LD_BRUSH_Y_X (1 << 31) # define RADEON_ROP3_ZERO 0x00000000 # define RADEON_ROP3_DSa 0x00880000 # define RADEON_ROP3_SDna 0x00440000 # define RADEON_ROP3_S 0x00cc0000 # define RADEON_ROP3_DSna 0x00220000 # define RADEON_ROP3_D 0x00aa0000 # define RADEON_ROP3_DSx 0x00660000 # define RADEON_ROP3_DSo 0x00ee0000 # define RADEON_ROP3_DSon 0x00110000 # define RADEON_ROP3_DSxn 0x00990000 # define RADEON_ROP3_Dn 0x00550000 # define RADEON_ROP3_SDno 0x00dd0000 # define RADEON_ROP3_Sn 0x00330000 # define RADEON_ROP3_DSno 0x00bb0000 # define RADEON_ROP3_DSan 0x00770000 # define RADEON_ROP3_ONE 0x00ff0000 # define RADEON_ROP3_DPa 0x00a00000 # define RADEON_ROP3_PDna 0x00500000 # define RADEON_ROP3_P 0x00f00000 # define RADEON_ROP3_DPna 0x000a0000 # define RADEON_ROP3_D 0x00aa0000 # define RADEON_ROP3_DPx 0x005a0000 # define RADEON_ROP3_DPo 0x00fa0000 # define RADEON_ROP3_DPon 0x00050000 # define RADEON_ROP3_PDxn 0x00a50000 # define RADEON_ROP3_PDno 0x00f50000 # define RADEON_ROP3_Pn 0x000f0000 # define RADEON_ROP3_DPno 0x00af0000 # define RADEON_ROP3_DPan 0x005f0000 #define RADEON_DP_GUI_MASTER_CNTL_C 0x1c84 #define RADEON_DP_MIX 0x16c8 #define RADEON_DP_SRC_BKGD_CLR 0x15dc #define RADEON_DP_SRC_FRGD_CLR 0x15d8 #define RADEON_DP_WRITE_MASK 0x16cc #define RADEON_DST_BRES_DEC 0x1630 #define RADEON_DST_BRES_ERR 0x1628 #define RADEON_DST_BRES_INC 0x162c #define RADEON_DST_BRES_LNTH 0x1634 #define RADEON_DST_BRES_LNTH_SUB 0x1638 #define RADEON_DST_HEIGHT 0x1410 #define RADEON_DST_HEIGHT_WIDTH 0x143c #define RADEON_DST_HEIGHT_WIDTH_8 0x158c #define RADEON_DST_HEIGHT_WIDTH_BW 0x15b4 #define RADEON_DST_HEIGHT_Y 0x15a0 #define RADEON_DST_LINE_START 0x1600 #define RADEON_DST_LINE_END 0x1604 #define RADEON_DST_LINE_PATCOUNT 0x1608 # define RADEON_BRES_CNTL_SHIFT 8 #define RADEON_DST_OFFSET 0x1404 #define RADEON_DST_PITCH 0x1408 #define RADEON_DST_PITCH_OFFSET 0x142c #define RADEON_DST_PITCH_OFFSET_C 0x1c80 # define RADEON_PITCH_SHIFT 21 # define RADEON_DST_TILE_LINEAR (0 << 30) # define RADEON_DST_TILE_MACRO (1 << 30) # define RADEON_DST_TILE_MICRO (2 << 30) # define RADEON_DST_TILE_BOTH (3 << 30) #define RADEON_DST_WIDTH 0x140c #define RADEON_DST_WIDTH_HEIGHT 0x1598 #define RADEON_DST_WIDTH_X 0x1588 #define RADEON_DST_WIDTH_X_INCY 0x159c #define RADEON_DST_X 0x141c #define RADEON_DST_X_SUB 0x15a4 #define RADEON_DST_X_Y 0x1594 #define RADEON_DST_Y 0x1420 #define RADEON_DST_Y_SUB 0x15a8 #define RADEON_DST_Y_X 0x1438 #define RADEON_FCP_CNTL 0x0910 # define RADEON_FCP0_SRC_PCICLK 0 # define RADEON_FCP0_SRC_PCLK 1 # define RADEON_FCP0_SRC_PCLKb 2 # define RADEON_FCP0_SRC_HREF 3 # define RADEON_FCP0_SRC_GND 4 # define RADEON_FCP0_SRC_HREFb 5 #define RADEON_FLUSH_1 0x1704 #define RADEON_FLUSH_2 0x1708 #define RADEON_FLUSH_3 0x170c #define RADEON_FLUSH_4 0x1710 #define RADEON_FLUSH_5 0x1714 #define RADEON_FLUSH_6 0x1718 #define RADEON_FLUSH_7 0x171c #define RADEON_FOG_3D_TABLE_START 0x1810 #define RADEON_FOG_3D_TABLE_END 0x1814 #define RADEON_FOG_3D_TABLE_DENSITY 0x181c #define RADEON_FOG_TABLE_INDEX 0x1a14 #define RADEON_FOG_TABLE_DATA 0x1a18 #define RADEON_FP_CRTC_H_TOTAL_DISP 0x0250 #define RADEON_FP_CRTC_V_TOTAL_DISP 0x0254 # define RADEON_FP_CRTC_H_TOTAL_MASK 0x000003ff # define RADEON_FP_CRTC_H_DISP_MASK 0x01ff0000 # define RADEON_FP_CRTC_V_TOTAL_MASK 0x00000fff # define RADEON_FP_CRTC_V_DISP_MASK 0x0fff0000 # define RADEON_FP_H_SYNC_STRT_CHAR_MASK 0x00001ff8 # define RADEON_FP_H_SYNC_WID_MASK 0x003f0000 # define RADEON_FP_V_SYNC_STRT_MASK 0x00000fff # define RADEON_FP_V_SYNC_WID_MASK 0x001f0000 # define RADEON_FP_CRTC_H_TOTAL_SHIFT 0x00000000 # define RADEON_FP_CRTC_H_DISP_SHIFT 0x00000010 # define RADEON_FP_CRTC_V_TOTAL_SHIFT 0x00000000 # define RADEON_FP_CRTC_V_DISP_SHIFT 0x00000010 # define RADEON_FP_H_SYNC_STRT_CHAR_SHIFT 0x00000003 # define RADEON_FP_H_SYNC_WID_SHIFT 0x00000010 # define RADEON_FP_V_SYNC_STRT_SHIFT 0x00000000 # define RADEON_FP_V_SYNC_WID_SHIFT 0x00000010 #define RADEON_FP_GEN_CNTL 0x0284 # define RADEON_FP_FPON (1 << 0) # define RADEON_FP_BLANK_EN (1 << 1) # define RADEON_FP_TMDS_EN (1 << 2) # define RADEON_FP_PANEL_FORMAT (1 << 3) # define RADEON_FP_EN_TMDS (1 << 7) # define RADEON_FP_DETECT_SENSE (1 << 8) # define RADEON_FP_DETECT_INT_POL (1 << 9) # define R200_FP_SOURCE_SEL_MASK (3 << 10) # define R200_FP_SOURCE_SEL_CRTC1 (0 << 10) # define R200_FP_SOURCE_SEL_CRTC2 (1 << 10) # define R200_FP_SOURCE_SEL_RMX (2 << 10) # define R200_FP_SOURCE_SEL_TRANS (3 << 10) # define RADEON_FP_SEL_CRTC1 (0 << 13) # define RADEON_FP_SEL_CRTC2 (1 << 13) # define R300_HPD_SEL(x) ((x) << 13) # define RADEON_FP_CRTC_DONT_SHADOW_HPAR (1 << 15) # define RADEON_FP_CRTC_DONT_SHADOW_VPAR (1 << 16) # define RADEON_FP_CRTC_DONT_SHADOW_HEND (1 << 17) # define RADEON_FP_CRTC_USE_SHADOW_VEND (1 << 18) # define RADEON_FP_RMX_HVSYNC_CONTROL_EN (1 << 20) # define RADEON_FP_DFP_SYNC_SEL (1 << 21) # define RADEON_FP_CRTC_LOCK_8DOT (1 << 22) # define RADEON_FP_CRT_SYNC_SEL (1 << 23) # define RADEON_FP_USE_SHADOW_EN (1 << 24) # define RADEON_FP_CRT_SYNC_ALT (1 << 26) #define RADEON_FP2_GEN_CNTL 0x0288 # define RADEON_FP2_BLANK_EN (1 << 1) # define RADEON_FP2_ON (1 << 2) # define RADEON_FP2_PANEL_FORMAT (1 << 3) # define RADEON_FP2_DETECT_SENSE (1 << 8) # define RADEON_FP2_DETECT_INT_POL (1 << 9) # define R200_FP2_SOURCE_SEL_MASK (3 << 10) # define R200_FP2_SOURCE_SEL_CRTC1 (0 << 10) # define R200_FP2_SOURCE_SEL_CRTC2 (1 << 10) # define R200_FP2_SOURCE_SEL_RMX (2 << 10) # define R200_FP2_SOURCE_SEL_TRANS_UNIT (3 << 10) # define RADEON_FP2_SRC_SEL_MASK (3 << 13) # define RADEON_FP2_SRC_SEL_CRTC2 (1 << 13) # define RADEON_FP2_FP_POL (1 << 16) # define RADEON_FP2_LP_POL (1 << 17) # define RADEON_FP2_SCK_POL (1 << 18) # define RADEON_FP2_LCD_CNTL_MASK (7 << 19) # define RADEON_FP2_PAD_FLOP_EN (1 << 22) # define RADEON_FP2_CRC_EN (1 << 23) # define RADEON_FP2_CRC_READ_EN (1 << 24) # define RADEON_FP2_DVO_EN (1 << 25) # define RADEON_FP2_DVO_RATE_SEL_SDR (1 << 26) # define R200_FP2_DVO_RATE_SEL_SDR (1 << 27) # define R300_FP2_DVO_CLOCK_MODE_SINGLE (1 << 28) # define R300_FP2_DVO_DUAL_CHANNEL_EN (1 << 29) #define RADEON_FP_H_SYNC_STRT_WID 0x02c4 #define RADEON_FP_H2_SYNC_STRT_WID 0x03c4 #define RADEON_FP_HORZ_STRETCH 0x028c #define RADEON_FP_HORZ2_STRETCH 0x038c # define RADEON_HORZ_STRETCH_RATIO_MASK 0xffff # define RADEON_HORZ_STRETCH_RATIO_MAX 4096 # define RADEON_HORZ_PANEL_SIZE (0x1ff << 16) # define RADEON_HORZ_PANEL_SHIFT 16 # define RADEON_HORZ_STRETCH_PIXREP (0 << 25) # define RADEON_HORZ_STRETCH_BLEND (1 << 26) # define RADEON_HORZ_STRETCH_ENABLE (1 << 25) # define RADEON_HORZ_AUTO_RATIO (1 << 27) # define RADEON_HORZ_FP_LOOP_STRETCH (0x7 << 28) # define RADEON_HORZ_AUTO_RATIO_INC (1 << 31) #define RADEON_FP_HORZ_VERT_ACTIVE 0x0278 #define RADEON_FP_V_SYNC_STRT_WID 0x02c8 #define RADEON_FP_VERT_STRETCH 0x0290 #define RADEON_FP_V2_SYNC_STRT_WID 0x03c8 #define RADEON_FP_VERT2_STRETCH 0x0390 # define RADEON_VERT_PANEL_SIZE (0xfff << 12) # define RADEON_VERT_PANEL_SHIFT 12 # define RADEON_VERT_STRETCH_RATIO_MASK 0xfff # define RADEON_VERT_STRETCH_RATIO_SHIFT 0 # define RADEON_VERT_STRETCH_RATIO_MAX 4096 # define RADEON_VERT_STRETCH_ENABLE (1 << 25) # define RADEON_VERT_STRETCH_LINEREP (0 << 26) # define RADEON_VERT_STRETCH_BLEND (1 << 26) # define RADEON_VERT_AUTO_RATIO_EN (1 << 27) # define RADEON_VERT_AUTO_RATIO_INC (1 << 31) # define RADEON_VERT_STRETCH_RESERVED 0x71000000 #define RS400_FP_2ND_GEN_CNTL 0x0384 # define RS400_FP_2ND_ON (1 << 0) # define RS400_FP_2ND_BLANK_EN (1 << 1) # define RS400_TMDS_2ND_EN (1 << 2) # define RS400_PANEL_FORMAT_2ND (1 << 3) # define RS400_FP_2ND_EN_TMDS (1 << 7) # define RS400_FP_2ND_DETECT_SENSE (1 << 8) # define RS400_FP_2ND_SOURCE_SEL_MASK (3 << 10) # define RS400_FP_2ND_SOURCE_SEL_CRTC1 (0 << 10) # define RS400_FP_2ND_SOURCE_SEL_CRTC2 (1 << 10) # define RS400_FP_2ND_SOURCE_SEL_RMX (2 << 10) # define RS400_FP_2ND_DETECT_EN (1 << 12) # define RS400_HPD_2ND_SEL (1 << 13) #define RS400_FP2_2_GEN_CNTL 0x0388 # define RS400_FP2_2_BLANK_EN (1 << 1) # define RS400_FP2_2_ON (1 << 2) # define RS400_FP2_2_PANEL_FORMAT (1 << 3) # define RS400_FP2_2_DETECT_SENSE (1 << 8) # define RS400_FP2_2_SOURCE_SEL_MASK (3 << 10) # define RS400_FP2_2_SOURCE_SEL_CRTC1 (0 << 10) # define RS400_FP2_2_SOURCE_SEL_CRTC2 (1 << 10) # define RS400_FP2_2_SOURCE_SEL_RMX (2 << 10) # define RS400_FP2_2_DVO2_EN (1 << 25) #define RS400_TMDS2_CNTL 0x0394 #define RS400_TMDS2_TRANSMITTER_CNTL 0x03a4 # define RS400_TMDS2_PLLEN (1 << 0) # define RS400_TMDS2_PLLRST (1 << 1) #define RADEON_GEN_INT_CNTL 0x0040 # define RADEON_CRTC_VBLANK_MASK (1 << 0) # define RADEON_FP_DETECT_MASK (1 << 4) # define RADEON_CRTC2_VBLANK_MASK (1 << 9) # define RADEON_FP2_DETECT_MASK (1 << 10) # define RADEON_GUI_IDLE_MASK (1 << 19) # define RADEON_SW_INT_ENABLE (1 << 25) #define RADEON_GEN_INT_STATUS 0x0044 # define AVIVO_DISPLAY_INT_STATUS (1 << 0) # define RADEON_CRTC_VBLANK_STAT (1 << 0) # define RADEON_CRTC_VBLANK_STAT_ACK (1 << 0) # define RADEON_FP_DETECT_STAT (1 << 4) # define RADEON_FP_DETECT_STAT_ACK (1 << 4) # define RADEON_CRTC2_VBLANK_STAT (1 << 9) # define RADEON_CRTC2_VBLANK_STAT_ACK (1 << 9) # define RADEON_FP2_DETECT_STAT (1 << 10) # define RADEON_FP2_DETECT_STAT_ACK (1 << 10) # define RADEON_GUI_IDLE_STAT (1 << 19) # define RADEON_GUI_IDLE_STAT_ACK (1 << 19) # define RADEON_SW_INT_FIRE (1 << 26) # define RADEON_SW_INT_TEST (1 << 25) # define RADEON_SW_INT_TEST_ACK (1 << 25) #define RADEON_GENENB 0x03c3 /* VGA */ #define RADEON_GENFC_RD 0x03ca /* VGA */ #define RADEON_GENFC_WT 0x03da /* VGA, 0x03ba */ #define RADEON_GENMO_RD 0x03cc /* VGA */ #define RADEON_GENMO_WT 0x03c2 /* VGA */ #define RADEON_GENS0 0x03c2 /* VGA */ #define RADEON_GENS1 0x03da /* VGA, 0x03ba */ #define RADEON_GPIO_MONID 0x0068 /* DDC interface via I2C */ /* DDC3 */ #define RADEON_GPIO_MONIDB 0x006c #define RADEON_GPIO_CRT2_DDC 0x006c #define RADEON_GPIO_DVI_DDC 0x0064 /* DDC2 */ #define RADEON_GPIO_VGA_DDC 0x0060 /* DDC1 */ # define RADEON_GPIO_A_0 (1 << 0) # define RADEON_GPIO_A_1 (1 << 1) # define RADEON_GPIO_Y_0 (1 << 8) # define RADEON_GPIO_Y_1 (1 << 9) # define RADEON_GPIO_Y_SHIFT_0 8 # define RADEON_GPIO_Y_SHIFT_1 9 # define RADEON_GPIO_EN_0 (1 << 16) # define RADEON_GPIO_EN_1 (1 << 17) # define RADEON_GPIO_MASK_0 (1 << 24) /*??*/ # define RADEON_GPIO_MASK_1 (1 << 25) /*??*/ #define RADEON_GRPH8_DATA 0x03cf /* VGA */ #define RADEON_GRPH8_IDX 0x03ce /* VGA */ #define RADEON_GUI_SCRATCH_REG0 0x15e0 #define RADEON_GUI_SCRATCH_REG1 0x15e4 #define RADEON_GUI_SCRATCH_REG2 0x15e8 #define RADEON_GUI_SCRATCH_REG3 0x15ec #define RADEON_GUI_SCRATCH_REG4 0x15f0 #define RADEON_GUI_SCRATCH_REG5 0x15f4 #define RADEON_HEADER 0x0f0e /* PCI */ #define RADEON_HOST_DATA0 0x17c0 #define RADEON_HOST_DATA1 0x17c4 #define RADEON_HOST_DATA2 0x17c8 #define RADEON_HOST_DATA3 0x17cc #define RADEON_HOST_DATA4 0x17d0 #define RADEON_HOST_DATA5 0x17d4 #define RADEON_HOST_DATA6 0x17d8 #define RADEON_HOST_DATA7 0x17dc #define RADEON_HOST_DATA_LAST 0x17e0 #define RADEON_HOST_PATH_CNTL 0x0130 # define RADEON_HP_LIN_RD_CACHE_DIS (1 << 24) # define RADEON_HDP_READ_BUFFER_INVALIDATE (1 << 27) # define RADEON_HDP_SOFT_RESET (1 << 26) # define RADEON_HDP_APER_CNTL (1 << 23) #define RADEON_HTOTAL_CNTL 0x0009 /* PLL */ # define RADEON_HTOT_CNTL_VGA_EN (1 << 28) #define RADEON_HTOTAL2_CNTL 0x002e /* PLL */ /* Multimedia I2C bus */ #define RADEON_I2C_CNTL_0 0x0090 # define RADEON_I2C_DONE (1 << 0) # define RADEON_I2C_NACK (1 << 1) # define RADEON_I2C_HALT (1 << 2) # define RADEON_I2C_SOFT_RST (1 << 5) # define RADEON_I2C_DRIVE_EN (1 << 6) # define RADEON_I2C_DRIVE_SEL (1 << 7) # define RADEON_I2C_START (1 << 8) # define RADEON_I2C_STOP (1 << 9) # define RADEON_I2C_RECEIVE (1 << 10) # define RADEON_I2C_ABORT (1 << 11) # define RADEON_I2C_GO (1 << 12) # define RADEON_I2C_PRESCALE_SHIFT 16 #define RADEON_I2C_CNTL_1 0x0094 # define RADEON_I2C_DATA_COUNT_SHIFT 0 # define RADEON_I2C_ADDR_COUNT_SHIFT 4 # define RADEON_I2C_INTRA_BYTE_DELAY_SHIFT 8 # define RADEON_I2C_SEL (1 << 16) # define RADEON_I2C_EN (1 << 17) # define RADEON_I2C_TIME_LIMIT_SHIFT 24 #define RADEON_I2C_DATA 0x0098 #define RADEON_DVI_I2C_CNTL_0 0x02e0 # define R200_DVI_I2C_PIN_SEL(x) ((x) << 3) # define R200_SEL_DDC1 0 /* depends on asic */ # define R200_SEL_DDC2 1 /* depends on asic */ # define R200_SEL_DDC3 2 /* depends on asic */ # define RADEON_SW_WANTS_TO_USE_DVI_I2C (1 << 13) # define RADEON_SW_CAN_USE_DVI_I2C (1 << 13) # define RADEON_SW_DONE_USING_DVI_I2C (1 << 14) # define RADEON_HW_NEEDS_DVI_I2C (1 << 14) # define RADEON_ABORT_HW_DVI_I2C (1 << 15) # define RADEON_HW_USING_DVI_I2C (1 << 15) #define RADEON_DVI_I2C_CNTL_1 0x02e4 #define RADEON_DVI_I2C_DATA 0x02e8 #define RADEON_INTERRUPT_LINE 0x0f3c /* PCI */ #define RADEON_INTERRUPT_PIN 0x0f3d /* PCI */ #define RADEON_IO_BASE 0x0f14 /* PCI */ #define RADEON_LATENCY 0x0f0d /* PCI */ #define RADEON_LEAD_BRES_DEC 0x1608 #define RADEON_LEAD_BRES_LNTH 0x161c #define RADEON_LEAD_BRES_LNTH_SUB 0x1624 #define RADEON_LVDS_GEN_CNTL 0x02d0 # define RADEON_LVDS_ON (1 << 0) # define RADEON_LVDS_DISPLAY_DIS (1 << 1) # define RADEON_LVDS_PANEL_TYPE (1 << 2) # define RADEON_LVDS_PANEL_FORMAT (1 << 3) # define RADEON_LVDS_NO_FM (0 << 4) # define RADEON_LVDS_2_GREY (1 << 4) # define RADEON_LVDS_4_GREY (2 << 4) # define RADEON_LVDS_RST_FM (1 << 6) # define RADEON_LVDS_EN (1 << 7) # define RADEON_LVDS_BL_MOD_LEVEL_SHIFT 8 # define RADEON_LVDS_BL_MOD_LEVEL_MASK (0xff << 8) # define RADEON_LVDS_BL_MOD_EN (1 << 16) # define RADEON_LVDS_BL_CLK_SEL (1 << 17) # define RADEON_LVDS_DIGON (1 << 18) # define RADEON_LVDS_BLON (1 << 19) # define RADEON_LVDS_FP_POL_LOW (1 << 20) # define RADEON_LVDS_LP_POL_LOW (1 << 21) # define RADEON_LVDS_DTM_POL_LOW (1 << 22) # define RADEON_LVDS_SEL_CRTC2 (1 << 23) # define RADEON_LVDS_FPDI_EN (1 << 27) # define RADEON_LVDS_HSYNC_DELAY_SHIFT 28 #define RADEON_LVDS_PLL_CNTL 0x02d4 # define RADEON_HSYNC_DELAY_SHIFT 28 # define RADEON_HSYNC_DELAY_MASK (0xf << 28) # define RADEON_LVDS_PLL_EN (1 << 16) # define RADEON_LVDS_PLL_RESET (1 << 17) # define R300_LVDS_SRC_SEL_MASK (3 << 18) # define R300_LVDS_SRC_SEL_CRTC1 (0 << 18) # define R300_LVDS_SRC_SEL_CRTC2 (1 << 18) # define R300_LVDS_SRC_SEL_RMX (2 << 18) #define RADEON_LVDS_SS_GEN_CNTL 0x02ec # define RADEON_LVDS_PWRSEQ_DELAY1_SHIFT 16 # define RADEON_LVDS_PWRSEQ_DELAY2_SHIFT 20 #define RADEON_MAX_LATENCY 0x0f3f /* PCI */ #define RADEON_DISPLAY_BASE_ADDR 0x23c #define RADEON_DISPLAY2_BASE_ADDR 0x33c #define RADEON_OV0_BASE_ADDR 0x43c #define RADEON_NB_TOM 0x15c #define R300_MC_INIT_MISC_LAT_TIMER 0x180 # define R300_MC_DISP0R_INIT_LAT_SHIFT 8 # define R300_MC_DISP0R_INIT_LAT_MASK 0xf # define R300_MC_DISP1R_INIT_LAT_SHIFT 12 # define R300_MC_DISP1R_INIT_LAT_MASK 0xf #define RADEON_MCLK_CNTL 0x0012 /* PLL */ # define RADEON_MCLKA_SRC_SEL_MASK 0x7 # define RADEON_FORCEON_MCLKA (1 << 16) # define RADEON_FORCEON_MCLKB (1 << 17) # define RADEON_FORCEON_YCLKA (1 << 18) # define RADEON_FORCEON_YCLKB (1 << 19) # define RADEON_FORCEON_MC (1 << 20) # define RADEON_FORCEON_AIC (1 << 21) # define R300_DISABLE_MC_MCLKA (1 << 21) # define R300_DISABLE_MC_MCLKB (1 << 21) #define RADEON_MCLK_MISC 0x001f /* PLL */ # define RADEON_MC_MCLK_MAX_DYN_STOP_LAT (1 << 12) # define RADEON_IO_MCLK_MAX_DYN_STOP_LAT (1 << 13) # define RADEON_MC_MCLK_DYN_ENABLE (1 << 14) # define RADEON_IO_MCLK_DYN_ENABLE (1 << 15) #define RADEON_GPIOPAD_MASK 0x0198 #define RADEON_GPIOPAD_A 0x019c #define RADEON_GPIOPAD_EN 0x01a0 #define RADEON_GPIOPAD_Y 0x01a4 #define RADEON_MDGPIO_MASK 0x01a8 #define RADEON_MDGPIO_A 0x01ac #define RADEON_MDGPIO_EN 0x01b0 #define RADEON_MDGPIO_Y 0x01b4 #define RADEON_MEM_ADDR_CONFIG 0x0148 #define RADEON_MEM_BASE 0x0f10 /* PCI */ #define RADEON_MEM_CNTL 0x0140 # define RADEON_MEM_NUM_CHANNELS_MASK 0x01 # define RADEON_MEM_USE_B_CH_ONLY (1 << 1) # define RV100_HALF_MODE (1 << 3) # define R300_MEM_NUM_CHANNELS_MASK 0x03 # define R300_MEM_USE_CD_CH_ONLY (1 << 2) #define RADEON_MEM_TIMING_CNTL 0x0144 /* EXT_MEM_CNTL */ #define RADEON_MEM_INIT_LAT_TIMER 0x0154 #define RADEON_MEM_INTF_CNTL 0x014c #define RADEON_MEM_SDRAM_MODE_REG 0x0158 # define RADEON_SDRAM_MODE_MASK 0xffff0000 # define RADEON_B3MEM_RESET_MASK 0x6fffffff # define RADEON_MEM_CFG_TYPE_DDR (1 << 30) #define RADEON_MEM_STR_CNTL 0x0150 # define RADEON_MEM_PWRUP_COMPL_A (1 << 0) # define RADEON_MEM_PWRUP_COMPL_B (1 << 1) # define R300_MEM_PWRUP_COMPL_C (1 << 2) # define R300_MEM_PWRUP_COMPL_D (1 << 3) # define RADEON_MEM_PWRUP_COMPLETE 0x03 # define R300_MEM_PWRUP_COMPLETE 0x0f #define RADEON_MC_STATUS 0x0150 # define RADEON_MC_IDLE (1 << 2) # define R300_MC_IDLE (1 << 4) #define RADEON_MEM_VGA_RP_SEL 0x003c #define RADEON_MEM_VGA_WP_SEL 0x0038 #define RADEON_MIN_GRANT 0x0f3e /* PCI */ #define RADEON_MM_DATA 0x0004 #define RADEON_MM_INDEX 0x0000 # define RADEON_MM_APER (1 << 31) #define RADEON_MPLL_CNTL 0x000e /* PLL */ #define RADEON_MPP_TB_CONFIG 0x01c0 /* ? */ #define RADEON_MPP_GP_CONFIG 0x01c8 /* ? */ #define RADEON_SEPROM_CNTL1 0x01c0 # define RADEON_SCK_PRESCALE_SHIFT 24 # define RADEON_SCK_PRESCALE_MASK (0xff << 24) #define R300_MC_IND_INDEX 0x01f8 # define R300_MC_IND_ADDR_MASK 0x3f # define R300_MC_IND_WR_EN (1 << 8) #define R300_MC_IND_DATA 0x01fc #define R300_MC_READ_CNTL_AB 0x017c # define R300_MEM_RBS_POSITION_A_MASK 0x03 #define R300_MC_READ_CNTL_CD_mcind 0x24 # define R300_MEM_RBS_POSITION_C_MASK 0x03 #define RADEON_N_VIF_COUNT 0x0248 #define RADEON_OV0_AUTO_FLIP_CNTL 0x0470 # define RADEON_OV0_AUTO_FLIP_CNTL_SOFT_BUF_NUM 0x00000007 # define RADEON_OV0_AUTO_FLIP_CNTL_SOFT_REPEAT_FIELD 0x00000008 # define RADEON_OV0_AUTO_FLIP_CNTL_SOFT_BUF_ODD 0x00000010 # define RADEON_OV0_AUTO_FLIP_CNTL_IGNORE_REPEAT_FIELD 0x00000020 # define RADEON_OV0_AUTO_FLIP_CNTL_SOFT_EOF_TOGGLE 0x00000040 # define RADEON_OV0_AUTO_FLIP_CNTL_VID_PORT_SELECT 0x00000300 # define RADEON_OV0_AUTO_FLIP_CNTL_P1_FIRST_LINE_EVEN 0x00010000 # define RADEON_OV0_AUTO_FLIP_CNTL_SHIFT_EVEN_DOWN 0x00040000 # define RADEON_OV0_AUTO_FLIP_CNTL_SHIFT_ODD_DOWN 0x00080000 # define RADEON_OV0_AUTO_FLIP_CNTL_FIELD_POL_SOURCE 0x00800000 #define RADEON_OV0_COLOUR_CNTL 0x04E0 #define RADEON_OV0_DEINTERLACE_PATTERN 0x0474 #define RADEON_OV0_EXCLUSIVE_HORZ 0x0408 # define RADEON_EXCL_HORZ_START_MASK 0x000000ff # define RADEON_EXCL_HORZ_END_MASK 0x0000ff00 # define RADEON_EXCL_HORZ_BACK_PORCH_MASK 0x00ff0000 # define RADEON_EXCL_HORZ_EXCLUSIVE_EN 0x80000000 #define RADEON_OV0_EXCLUSIVE_VERT 0x040C # define RADEON_EXCL_VERT_START_MASK 0x000003ff # define RADEON_EXCL_VERT_END_MASK 0x03ff0000 #define RADEON_OV0_FILTER_CNTL 0x04A0 # define RADEON_FILTER_PROGRAMMABLE_COEF 0x0 # define RADEON_FILTER_HC_COEF_HORZ_Y 0x1 # define RADEON_FILTER_HC_COEF_HORZ_UV 0x2 # define RADEON_FILTER_HC_COEF_VERT_Y 0x4 # define RADEON_FILTER_HC_COEF_VERT_UV 0x8 # define RADEON_FILTER_HARDCODED_COEF 0xf # define RADEON_FILTER_COEF_MASK 0xf #define RADEON_OV0_FOUR_TAP_COEF_0 0x04B0 #define RADEON_OV0_FOUR_TAP_COEF_1 0x04B4 #define RADEON_OV0_FOUR_TAP_COEF_2 0x04B8 #define RADEON_OV0_FOUR_TAP_COEF_3 0x04BC #define RADEON_OV0_FOUR_TAP_COEF_4 0x04C0 #define RADEON_OV0_FLAG_CNTL 0x04DC #define RADEON_OV0_GAMMA_000_00F 0x0d40 #define RADEON_OV0_GAMMA_010_01F 0x0d44 #define RADEON_OV0_GAMMA_020_03F 0x0d48 #define RADEON_OV0_GAMMA_040_07F 0x0d4c #define RADEON_OV0_GAMMA_080_0BF 0x0e00 #define RADEON_OV0_GAMMA_0C0_0FF 0x0e04 #define RADEON_OV0_GAMMA_100_13F 0x0e08 #define RADEON_OV0_GAMMA_140_17F 0x0e0c #define RADEON_OV0_GAMMA_180_1BF 0x0e10 #define RADEON_OV0_GAMMA_1C0_1FF 0x0e14 #define RADEON_OV0_GAMMA_200_23F 0x0e18 #define RADEON_OV0_GAMMA_240_27F 0x0e1c #define RADEON_OV0_GAMMA_280_2BF 0x0e20 #define RADEON_OV0_GAMMA_2C0_2FF 0x0e24 #define RADEON_OV0_GAMMA_300_33F 0x0e28 #define RADEON_OV0_GAMMA_340_37F 0x0e2c #define RADEON_OV0_GAMMA_380_3BF 0x0d50 #define RADEON_OV0_GAMMA_3C0_3FF 0x0d54 #define RADEON_OV0_GRAPHICS_KEY_CLR_LOW 0x04EC #define RADEON_OV0_GRAPHICS_KEY_CLR_HIGH 0x04F0 #define RADEON_OV0_H_INC 0x0480 #define RADEON_OV0_KEY_CNTL 0x04F4 # define RADEON_VIDEO_KEY_FN_MASK 0x00000003L # define RADEON_VIDEO_KEY_FN_FALSE 0x00000000L # define RADEON_VIDEO_KEY_FN_TRUE 0x00000001L # define RADEON_VIDEO_KEY_FN_EQ 0x00000002L # define RADEON_VIDEO_KEY_FN_NE 0x00000003L # define RADEON_GRAPHIC_KEY_FN_MASK 0x00000030L # define RADEON_GRAPHIC_KEY_FN_FALSE 0x00000000L # define RADEON_GRAPHIC_KEY_FN_TRUE 0x00000010L # define RADEON_GRAPHIC_KEY_FN_EQ 0x00000020L # define RADEON_GRAPHIC_KEY_FN_NE 0x00000030L # define RADEON_CMP_MIX_MASK 0x00000100L # define RADEON_CMP_MIX_OR 0x00000000L # define RADEON_CMP_MIX_AND 0x00000100L #define RADEON_OV0_LIN_TRANS_A 0x0d20 #define RADEON_OV0_LIN_TRANS_B 0x0d24 #define RADEON_OV0_LIN_TRANS_C 0x0d28 #define RADEON_OV0_LIN_TRANS_D 0x0d2c #define RADEON_OV0_LIN_TRANS_E 0x0d30 #define RADEON_OV0_LIN_TRANS_F 0x0d34 #define RADEON_OV0_P1_BLANK_LINES_AT_TOP 0x0430 # define RADEON_P1_BLNK_LN_AT_TOP_M1_MASK 0x00000fffL # define RADEON_P1_ACTIVE_LINES_M1 0x0fff0000L #define RADEON_OV0_P1_H_ACCUM_INIT 0x0488 #define RADEON_OV0_P1_V_ACCUM_INIT 0x0428 # define RADEON_OV0_P1_MAX_LN_IN_PER_LN_OUT 0x00000003L # define RADEON_OV0_P1_V_ACCUM_INIT_MASK 0x01ff8000L #define RADEON_OV0_P1_X_START_END 0x0494 #define RADEON_OV0_P2_X_START_END 0x0498 #define RADEON_OV0_P23_BLANK_LINES_AT_TOP 0x0434 # define RADEON_P23_BLNK_LN_AT_TOP_M1_MASK 0x000007ffL # define RADEON_P23_ACTIVE_LINES_M1 0x07ff0000L #define RADEON_OV0_P23_H_ACCUM_INIT 0x048C #define RADEON_OV0_P23_V_ACCUM_INIT 0x042C #define RADEON_OV0_P3_X_START_END 0x049C #define RADEON_OV0_REG_LOAD_CNTL 0x0410 # define RADEON_REG_LD_CTL_LOCK 0x00000001L # define RADEON_REG_LD_CTL_VBLANK_DURING_LOCK 0x00000002L # define RADEON_REG_LD_CTL_STALL_GUI_UNTIL_FLIP 0x00000004L # define RADEON_REG_LD_CTL_LOCK_READBACK 0x00000008L # define RADEON_REG_LD_CTL_FLIP_READBACK 0x00000010L #define RADEON_OV0_SCALE_CNTL 0x0420 # define RADEON_SCALER_HORZ_PICK_NEAREST 0x00000004L # define RADEON_SCALER_VERT_PICK_NEAREST 0x00000008L # define RADEON_SCALER_SIGNED_UV 0x00000010L # define RADEON_SCALER_GAMMA_SEL_MASK 0x00000060L # define RADEON_SCALER_GAMMA_SEL_BRIGHT 0x00000000L # define RADEON_SCALER_GAMMA_SEL_G22 0x00000020L # define RADEON_SCALER_GAMMA_SEL_G18 0x00000040L # define RADEON_SCALER_GAMMA_SEL_G14 0x00000060L # define RADEON_SCALER_COMCORE_SHIFT_UP_ONE 0x00000080L # define RADEON_SCALER_SURFAC_FORMAT 0x00000f00L # define RADEON_SCALER_SOURCE_15BPP 0x00000300L # define RADEON_SCALER_SOURCE_16BPP 0x00000400L # define RADEON_SCALER_SOURCE_32BPP 0x00000600L # define RADEON_SCALER_SOURCE_YUV9 0x00000900L # define RADEON_SCALER_SOURCE_YUV12 0x00000A00L # define RADEON_SCALER_SOURCE_VYUY422 0x00000B00L # define RADEON_SCALER_SOURCE_YVYU422 0x00000C00L # define RADEON_SCALER_ADAPTIVE_DEINT 0x00001000L # define RADEON_SCALER_TEMPORAL_DEINT 0x00002000L # define RADEON_SCALER_CRTC_SEL 0x00004000L # define RADEON_SCALER_SMART_SWITCH 0x00008000L # define RADEON_SCALER_BURST_PER_PLANE 0x007F0000L # define RADEON_SCALER_DOUBLE_BUFFER 0x01000000L # define RADEON_SCALER_DIS_LIMIT 0x08000000L # define RADEON_SCALER_LIN_TRANS_BYPASS 0x10000000L # define RADEON_SCALER_INT_EMU 0x20000000L # define RADEON_SCALER_ENABLE 0x40000000L # define RADEON_SCALER_SOFT_RESET 0x80000000L #define RADEON_OV0_STEP_BY 0x0484 #define RADEON_OV0_TEST 0x04F8 #define RADEON_OV0_V_INC 0x0424 #define RADEON_OV0_VID_BUF_PITCH0_VALUE 0x0460 #define RADEON_OV0_VID_BUF_PITCH1_VALUE 0x0464 #define RADEON_OV0_VID_BUF0_BASE_ADRS 0x0440 # define RADEON_VIF_BUF0_PITCH_SEL 0x00000001L # define RADEON_VIF_BUF0_TILE_ADRS 0x00000002L # define RADEON_VIF_BUF0_BASE_ADRS_MASK 0x03fffff0L # define RADEON_VIF_BUF0_1ST_LINE_LSBS_MASK 0x48000000L #define RADEON_OV0_VID_BUF1_BASE_ADRS 0x0444 # define RADEON_VIF_BUF1_PITCH_SEL 0x00000001L # define RADEON_VIF_BUF1_TILE_ADRS 0x00000002L # define RADEON_VIF_BUF1_BASE_ADRS_MASK 0x03fffff0L # define RADEON_VIF_BUF1_1ST_LINE_LSBS_MASK 0x48000000L #define RADEON_OV0_VID_BUF2_BASE_ADRS 0x0448 # define RADEON_VIF_BUF2_PITCH_SEL 0x00000001L # define RADEON_VIF_BUF2_TILE_ADRS 0x00000002L # define RADEON_VIF_BUF2_BASE_ADRS_MASK 0x03fffff0L # define RADEON_VIF_BUF2_1ST_LINE_LSBS_MASK 0x48000000L #define RADEON_OV0_VID_BUF3_BASE_ADRS 0x044C #define RADEON_OV0_VID_BUF4_BASE_ADRS 0x0450 #define RADEON_OV0_VID_BUF5_BASE_ADRS 0x0454 #define RADEON_OV0_VIDEO_KEY_CLR_HIGH 0x04E8 #define RADEON_OV0_VIDEO_KEY_CLR_LOW 0x04E4 #define RADEON_OV0_Y_X_START 0x0400 #define RADEON_OV0_Y_X_END 0x0404 #define RADEON_OV1_Y_X_START 0x0600 #define RADEON_OV1_Y_X_END 0x0604 #define RADEON_OVR_CLR 0x0230 #define RADEON_OVR_WID_LEFT_RIGHT 0x0234 #define RADEON_OVR_WID_TOP_BOTTOM 0x0238 #define RADEON_OVR2_CLR 0x0330 #define RADEON_OVR2_WID_LEFT_RIGHT 0x0334