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BranchCommit messageAuthorAge
archive/unc-master-3.0P-FP: fix BUG_ON releated to priority inheritanceBjoern Brandenburg13 years
archived-2013.1uncachedev: mmap memory that is not cached by CPUsGlenn Elliott12 years
archived-private-masterMerge branch 'wip-2.6.34' into old-private-masterAndrea Bastoni15 years
archived-semi-partMerge branch 'wip-semi-part' of ssh://cvs/cvs/proj/litmus/repo/litmus2010 int...Andrea Bastoni15 years
demoFurther refinementsJonathan Herman14 years
ecrts-pgm-finalMerge branch 'wip-ecrts14-pgm' of ssh://rtsrv.cs.unc.edu/home/litmus/litmus-r...Glenn Elliott12 years
ecrts14-pgm-finalMerge branch 'wip-ecrts14-pgm' of ssh://rtsrv.cs.unc.edu/home/litmus/litmus-r...Glenn Elliott12 years
gpusync-rtss12Final GPUSync implementation.Glenn Elliott12 years
gpusync/stagingRename IKGLP R2DGLP.Glenn Elliott12 years
linux-tipMerge branch 'slab/urgent' of git://git.kernel.org/pub/scm/linux/kernel/git/p...Linus Torvalds15 years
litmus2008-patch-seriesadd i386 feather-trace implementationBjoern B. Brandenburg16 years
masterPSN-EDF: use inferred_sporadic_job_release_atBjoern Brandenburg9 years
pgmmake it compileGlenn Elliott12 years
prop/litmus-signalsInfrastructure for Litmus signals.Glenn Elliott13 years
prop/robust-tie-breakFixed bug in edf_higher_prio().Glenn Elliott13 years
stagingFix tracepoint compilation errorFelipe Cerqueira13 years
test9/23/2016Namhoon Kim9 years
tracing-develTest kernel tracing events capabilitiesAndrea Bastoni16 years
v2.6.34-with-arm-patchessmsc911x: Add spinlocks around registers accessCatalin Marinas15 years
v2015.1Add ARM syscall def for get_current_budgetBjoern Brandenburg10 years
wip-2011.2-bbbLitmus core: simplify np-section protocolBjoern B. Brandenburg14 years
wip-2011.2-bbb-traceRefactor sched_trace_log_message() -> debug_trace_log_message()Andrea Bastoni14 years
wip-2012.3-gpuSOBLIV draining support for C-EDF.Glenn Elliott12 years
wip-2012.3-gpu-preportpick up last C-RM fileGlenn Elliott12 years
wip-2012.3-gpu-rtss13Fix critical bug in GPU tracker.Glenn Elliott12 years
wip-2012.3-gpu-sobliv-budget-w-ksharkProper sobliv draining and many bug fixes.Glenn Elliott12 years
wip-aedzl-finalMake it easier to compile AEDZL interfaces in liblitmus.Glenn Elliott15 years
wip-aedzl-revisedAdd sched_trace data for Apative EDZLGlenn Elliott15 years
wip-arbit-deadlineFix compilation bug.Glenn Elliott13 years
wip-aux-tasksDescription of refined aux task inheritance.Glenn Elliott13 years
wip-bbbGSN-EDF & Core: improve debug TRACE'ing for NP sectionsBjoern B. Brandenburg14 years
wip-bbb-prio-donuse correct timestampBjoern B. Brandenburg14 years
wip-better-breakImplement hash-based EDF tie-breaking.Glenn Elliott13 years
wip-binary-heapMake C-EDF work with simplified binheap_deleteGlenn Elliott13 years
wip-budgetAdded support for choices in budget policy enforcement.Glenn Elliott15 years
wip-colorSummarize schedulability with final recordJonathan Herman13 years
wip-color-jlhsched_color: Fixed two bugs causing crashing on experiment restart and a rare...Jonathan Herman13 years
wip-d10-hz1000Enable HZ=1000 on District 10Bjoern B. Brandenburg15 years
wip-default-clusteringFeature: Make default C-EDF clustering compile-time configurable.Glenn Elliott15 years
wip-dissipation-jericksoUpdate from 2.6.36 to 2.6.36.4Jeremy Erickson11 years
wip-dissipation2-jericksoUpdate 2.6.36 to 2.6.36.4Jeremy Erickson11 years
wip-ecrts14-pgmMerge branch 'wip-ecrts14-pgm' of ssh://rtsrv.cs.unc.edu/home/litmus/litmus-r...Glenn Elliott12 years
wip-edf-hsblast tested versionJonathan Herman14 years
wip-edf-osLookup table EDF-osJeremy Erickson12 years
wip-edf-tie-breakMerge branch 'wip-edf-tie-break' of ssh://rtsrv.cs.unc.edu/home/litmus/litmus...Glenn Elliott13 years
wip-edzl-critiqueUse hr_timer's active checks instead of having own flag.Glenn Elliott15 years
wip-edzl-finalImplementation of the EDZL scheduler.Glenn Elliott15 years
wip-edzl-revisedClean up comments.Glenn Elliott15 years
wip-eventsAdded support for tracing arbitrary actions.Jonathan Herman15 years
wip-extra-debugDBG: add additional tracingBjoern B. Brandenburg15 years
wip-fix-switch-jericksoAttempt to fix race condition with plugin switchingJeremy Erickson15 years
wip-fix3sched: show length of runqueue clock deactivation in /proc/sched_debugBjoern B. Brandenburg15 years
wip-fmlp-dequeueImprove FMLP queue management.Glenn Elliott14 years
wip-ft-irq-flagFeather-Trace: keep track of interrupt-related interference.Bjoern B. Brandenburg14 years
wip-gpu-cleanupEnable sched_trace log injection from userspaceGlenn Elliott13 years
wip-gpu-interruptsRemove option for threading of all softirqs.Glenn Elliott14 years
wip-gpu-rtas12Generalized GPU cost predictors + EWMA. (untested)Glenn Elliott13 years
wip-gpu-rtss12Final GPUSync implementation.Glenn Elliott13 years
wip-gpu-rtss12-srpexperimental changes to support GPUs under SRPGlenn Elliott13 years
wip-gpusync-mergeCleanup priority tracking for budget enforcement.Glenn Elliott11 years
wip-ikglpMove RSM and IKGLP imp. to own .c filesGlenn Elliott13 years
wip-k-fmlpMerge branch 'mpi-master' into wip-k-fmlpGlenn Elliott14 years
wip-kernel-coloringAdded recolor syscallNamhoon Kim7 years
wip-kernthreadsKludge work-queue processing into klitirqd.Glenn Elliott15 years
wip-klmirqd-to-auxAllow klmirqd threads to be given names.Glenn Elliott13 years
wip-ksharkMerge branch 'mpi-staging' into wip-ksharkJonathan Herman13 years
wip-litmus-3.2Merge commit 'v3.2' into litmus-stagingAndrea Bastoni13 years
wip-litmus2011.2Cleanup: Coding conformance for affinity stuff.Glenn Elliott14 years
wip-litmus3.0-2011.2Feather-Trace: keep track of interrupt-related interference.Bjoern B. Brandenburg14 years
wip-master-2.6.33-rtAvoid deadlock when switching task policy to BACKGROUND (ugly)Andrea Bastoni15 years
wip-mcRemoved ARM-specific hacks which disabled less common mixed-criticality featu...Jonathan Herman12 years
wip-mc-bipasaMC-EDF addedbipasa chattopadhyay13 years
wip-mc-jericksoSplit C/D queuesJeremy Erickson15 years
wip-mc2-cache-slackManually patched mc^2 related codeMing Yang10 years
wip-mcrit-maccosmeticMac Mollison15 years
wip-merge-3.0Prevent Linux to send IPI and queue tasks on remote CPUs.Andrea Bastoni14 years
wip-merge-v3.0Prevent Linux to send IPI and queue tasks on remote CPUs.Andrea Bastoni14 years
wip-migration-affinityNULL affinity dereference in C-EDF.Glenn Elliott14 years
wip-mmap-uncacheshare branch with othersGlenn Elliott13 years
wip-modechangeRTSS 2017 submissionNamhoon Kim8 years
wip-nested-lockingAppears to be working.Bryan Ward12 years
wip-omlp-gedfFirst implementation of G-OMLP.Glenn Elliott15 years
wip-paiSome cleanup of PAIGlenn Elliott14 years
wip-percore-lib9/21/2016Namhoon Kim9 years
wip-performanceCONFIG_DONT_PREEMPT_ON_TIE: Don't preeempt a scheduled task on priority tie.Glenn Elliott14 years
wip-pgmAdd PGM support to C-FLGlenn Elliott12 years
wip-pgm-splitFirst draft of C-FL-splitNamhoon Kim12 years
wip-pm-ovdAdd preemption-and-migration overhead tracing supportAndrea Bastoni15 years
wip-prio-inhP-EDF updated to use the generic pi framework.Glenn Elliott15 years
wip-prioq-dglBUG FIX: Support DGLs with PRIOQ_MUTEXGlenn Elliott13 years
wip-refactored-gedfGeneralizd architecture for GEDF-style scheduelrs to reduce code redundancy.Glenn Elliott15 years
wip-release-master-fixbugfix: release master CPU must signal task was pickedBjoern B. Brandenburg14 years
wip-robust-tie-breakEDF priority tie-breaks.Glenn Elliott13 years
wip-rt-ksharkMove task time accounting into the complete_job method.Jonathan Herman13 years
wip-rtas12-pgmScheduling of PGM jobs.Glenn Elliott13 years
wip-semi-partFix compile error with newer GCCJeremy Erickson12 years
wip-semi-part-edfos-jericksoUse initial CPU set by clientJeremy Erickson12 years
wip-shared-libTODO: Fix condition checks in replicate_page_move_mapping()Namhoon Kim9 years
wip-shared-lib2RTAS 2017 Submission ver.Namhoon Kim9 years
wip-shared-memInitial commit for shared libraryNamhoon Kim9 years
wip-splitting-jericksoFix release behaviorJeremy Erickson13 years
wip-splitting-omlp-jericksoBjoern's Dissertation Code with Priority DonationJeremy Erickson13 years
wip-stage-binheapAn efficient binary heap implementation.Glenn Elliott13 years
wip-sun-portDynamic memory allocation and clean exit for FeatherTraceChristopher Kenna15 years
wip-timer-tracebugfix: C-EDF, clear scheduled field of the correct CPU upon task_exitAndrea Bastoni15 years
wip-tracepointsAdd kernel-style events for sched_trace_XXX() functionsAndrea Bastoni14 years
 
TagDownloadAuthorAge
2015.1commit 8e51b37822...Bjoern Brandenburg10 years
2013.1commit bcaacec1ca...Glenn Elliott12 years
2012.3commit c158b5fbe4...Jonathan Herman13 years
2012.2commit b53c479a0f...Glenn Elliott13 years
2012.1commit 83b11ea1c6...Bjoern B. Brandenburg14 years
rtas12-mc-beta-expcommit 8e236ee20f...Christopher Kenna14 years
2011.1commit d11808b5c6...Christopher Kenna15 years
v2.6.37-rc4commit e8a7e48bb2...Linus Torvalds15 years
v2.6.37-rc3commit 3561d43fd2...Linus Torvalds15 years
v2.6.37-rc2commit e53beacd23...Linus Torvalds15 years
v2.6.37-rc1commit c8ddb2713c...Linus Torvalds15 years
v2.6.36commit f6f94e2ab1...Linus Torvalds15 years
2010.2commit 5c5456402d...Bjoern B. Brandenburg15 years
v2.6.36-rc8commit cd07202cc8...Linus Torvalds15 years
v2.6.36-rc7commit cb655d0f3d...Linus Torvalds15 years
v2.6.36-rc6commit 899611ee7d...Linus Torvalds15 years
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2010.1commit 7c1ff4c544...Andrea Bastoni15 years
v2.6.34commit e40152ee1e...Linus Torvalds15 years
v2.6.33.4commit 4640b4e7d9...Greg Kroah-Hartman15 years
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v2.6.15-rc3commit 624f54be20...Linus Torvalds20 years
v2.6.15-rc2commit 3bedff1d73...Linus Torvalds20 years
v2.6.15-rc1commit cd52d1ee9a...Linus Torvalds20 years
v2.6.14commit 741b2252a5...Linus Torvalds20 years
v2.6.14-rc5commit 93918e9afc...Linus Torvalds20 years
v2.6.14-rc4commit 907a426179...Linus Torvalds20 years
v2.6.14-rc3commit 1c9426e8a5...Linus Torvalds20 years
v2.6.14-rc2commit 676d55ae30...Linus Torvalds20 years
v2.6.14-rc1commit 2f4ba45a75...Linus Torvalds20 years
v2.6.13commit 02b3e4e2d7...Linus Torvalds20 years
v2.6.13-rc7commit 0572e3da3f...Linus Torvalds20 years
v2.6.13-rc6commit 6fc32179de...Linus Torvalds20 years
v2.6.13-rc5commit 9a351e30d7...Linus Torvalds20 years
v2.6.13-rc4commit 6395352334...Linus Torvalds20 years
v2.6.11tree c39ae07f39...
v2.6.11-treetree c39ae07f39...
v2.6.12commit 9ee1c939d1...
v2.6.12-rc2commit 1da177e4c3...
v2.6.12-rc3commit a2755a80f4...
v2.6.12-rc4commit 88d7bd8cb9...
v2.6.12-rc5commit 2a24ab628a...
v2.6.12-rc6commit 7cef5677ef...
v2.6.13-rc1commit 4c91aedb75...
v2.6.13-rc2commit a18bcb7450...
v2.6.13-rc3commit c32511e271...
TX_STATUS_ODI_OVERRUN 0x00000020 #define MAC_TX_LENGTHS 0x00000464 #define TX_LENGTHS_SLOT_TIME_MASK 0x000000ff #define TX_LENGTHS_SLOT_TIME_SHIFT 0 #define TX_LENGTHS_IPG_MASK 0x00000f00 #define TX_LENGTHS_IPG_SHIFT 8 #define TX_LENGTHS_IPG_CRS_MASK 0x00003000 #define TX_LENGTHS_IPG_CRS_SHIFT 12 #define MAC_RX_MODE 0x00000468 #define RX_MODE_RESET 0x00000001 #define RX_MODE_ENABLE 0x00000002 #define RX_MODE_FLOW_CTRL_ENABLE 0x00000004 #define RX_MODE_KEEP_MAC_CTRL 0x00000008 #define RX_MODE_KEEP_PAUSE 0x00000010 #define RX_MODE_ACCEPT_OVERSIZED 0x00000020 #define RX_MODE_ACCEPT_RUNTS 0x00000040 #define RX_MODE_LEN_CHECK 0x00000080 #define RX_MODE_PROMISC 0x00000100 #define RX_MODE_NO_CRC_CHECK 0x00000200 #define RX_MODE_KEEP_VLAN_TAG 0x00000400 #define RX_MODE_IPV6_CSUM_ENABLE 0x01000000 #define MAC_RX_STATUS 0x0000046c #define RX_STATUS_REMOTE_TX_XOFFED 0x00000001 #define RX_STATUS_XOFF_RCVD 0x00000002 #define RX_STATUS_XON_RCVD 0x00000004 #define MAC_HASH_REG_0 0x00000470 #define MAC_HASH_REG_1 0x00000474 #define MAC_HASH_REG_2 0x00000478 #define MAC_HASH_REG_3 0x0000047c #define MAC_RCV_RULE_0 0x00000480 #define MAC_RCV_VALUE_0 0x00000484 #define MAC_RCV_RULE_1 0x00000488 #define MAC_RCV_VALUE_1 0x0000048c #define MAC_RCV_RULE_2 0x00000490 #define MAC_RCV_VALUE_2 0x00000494 #define MAC_RCV_RULE_3 0x00000498 #define MAC_RCV_VALUE_3 0x0000049c #define MAC_RCV_RULE_4 0x000004a0 #define MAC_RCV_VALUE_4 0x000004a4 #define MAC_RCV_RULE_5 0x000004a8 #define MAC_RCV_VALUE_5 0x000004ac #define MAC_RCV_RULE_6 0x000004b0 #define MAC_RCV_VALUE_6 0x000004b4 #define MAC_RCV_RULE_7 0x000004b8 #define MAC_RCV_VALUE_7 0x000004bc #define MAC_RCV_RULE_8 0x000004c0 #define MAC_RCV_VALUE_8 0x000004c4 #define MAC_RCV_RULE_9 0x000004c8 #define MAC_RCV_VALUE_9 0x000004cc #define MAC_RCV_RULE_10 0x000004d0 #define MAC_RCV_VALUE_10 0x000004d4 #define MAC_RCV_RULE_11 0x000004d8 #define MAC_RCV_VALUE_11 0x000004dc #define MAC_RCV_RULE_12 0x000004e0 #define MAC_RCV_VALUE_12 0x000004e4 #define MAC_RCV_RULE_13 0x000004e8 #define MAC_RCV_VALUE_13 0x000004ec #define MAC_RCV_RULE_14 0x000004f0 #define MAC_RCV_VALUE_14 0x000004f4 #define MAC_RCV_RULE_15 0x000004f8 #define MAC_RCV_VALUE_15 0x000004fc #define RCV_RULE_DISABLE_MASK 0x7fffffff #define MAC_RCV_RULE_CFG 0x00000500 #define RCV_RULE_CFG_DEFAULT_CLASS 0x00000008 #define MAC_LOW_WMARK_MAX_RX_FRAME 0x00000504 /* 0x508 --> 0x520 unused */ #define MAC_HASHREGU_0 0x00000520 #define MAC_HASHREGU_1 0x00000524 #define MAC_HASHREGU_2 0x00000528 #define MAC_HASHREGU_3 0x0000052c #define MAC_EXTADDR_0_HIGH 0x00000530 #define MAC_EXTADDR_0_LOW 0x00000534 #define MAC_EXTADDR_1_HIGH 0x00000538 #define MAC_EXTADDR_1_LOW 0x0000053c #define MAC_EXTADDR_2_HIGH 0x00000540 #define MAC_EXTADDR_2_LOW 0x00000544 #define MAC_EXTADDR_3_HIGH 0x00000548 #define MAC_EXTADDR_3_LOW 0x0000054c #define MAC_EXTADDR_4_HIGH 0x00000550 #define MAC_EXTADDR_4_LOW 0x00000554 #define MAC_EXTADDR_5_HIGH 0x00000558 #define MAC_EXTADDR_5_LOW 0x0000055c #define MAC_EXTADDR_6_HIGH 0x00000560 #define MAC_EXTADDR_6_LOW 0x00000564 #define MAC_EXTADDR_7_HIGH 0x00000568 #define MAC_EXTADDR_7_LOW 0x0000056c #define MAC_EXTADDR_8_HIGH 0x00000570 #define MAC_EXTADDR_8_LOW 0x00000574 #define MAC_EXTADDR_9_HIGH 0x00000578 #define MAC_EXTADDR_9_LOW 0x0000057c #define MAC_EXTADDR_10_HIGH 0x00000580 #define MAC_EXTADDR_10_LOW 0x00000584 #define MAC_EXTADDR_11_HIGH 0x00000588 #define MAC_EXTADDR_11_LOW 0x0000058c #define MAC_SERDES_CFG 0x00000590 #define MAC_SERDES_CFG_EDGE_SELECT 0x00001000 #define MAC_SERDES_STAT 0x00000594 /* 0x598 --> 0x5b0 unused */ #define SERDES_RX_CTRL 0x000005b0 /* 5780/5714 only */ #define SERDES_RX_SIG_DETECT 0x00000400 #define SG_DIG_CTRL 0x000005b0 #define SG_DIG_USING_HW_AUTONEG 0x80000000 #define SG_DIG_SOFT_RESET 0x40000000 #define SG_DIG_DISABLE_LINKRDY 0x20000000 #define SG_DIG_CRC16_CLEAR_N 0x01000000 #define SG_DIG_EN10B 0x00800000 #define SG_DIG_CLEAR_STATUS 0x00400000 #define SG_DIG_LOCAL_DUPLEX_STATUS 0x00200000 #define SG_DIG_LOCAL_LINK_STATUS 0x00100000 #define SG_DIG_SPEED_STATUS_MASK 0x000c0000 #define SG_DIG_SPEED_STATUS_SHIFT 18 #define SG_DIG_JUMBO_PACKET_DISABLE 0x00020000 #define SG_DIG_RESTART_AUTONEG 0x00010000 #define SG_DIG_FIBER_MODE 0x00008000 #define SG_DIG_REMOTE_FAULT_MASK 0x00006000 #define SG_DIG_PAUSE_MASK 0x00001800 #define SG_DIG_GBIC_ENABLE 0x00000400 #define SG_DIG_CHECK_END_ENABLE 0x00000200 #define SG_DIG_SGMII_AUTONEG_TIMER 0x00000100 #define SG_DIG_CLOCK_PHASE_SELECT 0x00000080 #define SG_DIG_GMII_INPUT_SELECT 0x00000040 #define SG_DIG_MRADV_CRC16_SELECT 0x00000020 #define SG_DIG_COMMA_DETECT_ENABLE 0x00000010 #define SG_DIG_AUTONEG_TIMER_REDUCE 0x00000008 #define SG_DIG_AUTONEG_LOW_ENABLE 0x00000004 #define SG_DIG_REMOTE_LOOPBACK 0x00000002 #define SG_DIG_LOOPBACK 0x00000001 #define SG_DIG_STATUS 0x000005b4 #define SG_DIG_CRC16_BUS_MASK 0xffff0000 #define SG_DIG_PARTNER_FAULT_MASK 0x00600000 /* If !MRADV_CRC16_SELECT */ #define SG_DIG_PARTNER_ASYM_PAUSE 0x00100000 /* If !MRADV_CRC16_SELECT */ #define SG_DIG_PARTNER_PAUSE_CAPABLE 0x00080000 /* If !MRADV_CRC16_SELECT */ #define SG_DIG_PARTNER_HALF_DUPLEX 0x00040000 /* If !MRADV_CRC16_SELECT */ #define SG_DIG_PARTNER_FULL_DUPLEX 0x00020000 /* If !MRADV_CRC16_SELECT */ #define SG_DIG_PARTNER_NEXT_PAGE 0x00010000 /* If !MRADV_CRC16_SELECT */ #define SG_DIG_AUTONEG_STATE_MASK 0x00000ff0 #define SG_DIG_COMMA_DETECTOR 0x00000008 #define SG_DIG_MAC_ACK_STATUS 0x00000004 #define SG_DIG_AUTONEG_COMPLETE 0x00000002 #define SG_DIG_AUTONEG_ERROR 0x00000001 /* 0x5b8 --> 0x600 unused */ #define MAC_TX_MAC_STATE_BASE 0x00000600 /* 16 bytes */ #define MAC_RX_MAC_STATE_BASE 0x00000610 /* 20 bytes */ /* 0x624 --> 0x800 unused */ #define MAC_TX_STATS_OCTETS 0x00000800 #define MAC_TX_STATS_RESV1 0x00000804 #define MAC_TX_STATS_COLLISIONS 0x00000808 #define MAC_TX_STATS_XON_SENT 0x0000080c #define MAC_TX_STATS_XOFF_SENT 0x00000810 #define MAC_TX_STATS_RESV2 0x00000814 #define MAC_TX_STATS_MAC_ERRORS 0x00000818 #define MAC_TX_STATS_SINGLE_COLLISIONS 0x0000081c #define MAC_TX_STATS_MULT_COLLISIONS 0x00000820 #define MAC_TX_STATS_DEFERRED 0x00000824 #define MAC_TX_STATS_RESV3 0x00000828 #define MAC_TX_STATS_EXCESSIVE_COL 0x0000082c #define MAC_TX_STATS_LATE_COL 0x00000830 #define MAC_TX_STATS_RESV4_1 0x00000834 #define MAC_TX_STATS_RESV4_2 0x00000838 #define MAC_TX_STATS_RESV4_3 0x0000083c #define MAC_TX_STATS_RESV4_4 0x00000840 #define MAC_TX_STATS_RESV4_5 0x00000844 #define MAC_TX_STATS_RESV4_6 0x00000848 #define MAC_TX_STATS_RESV4_7 0x0000084c #define MAC_TX_STATS_RESV4_8 0x00000850 #define MAC_TX_STATS_RESV4_9 0x00000854 #define MAC_TX_STATS_RESV4_10 0x00000858 #define MAC_TX_STATS_RESV4_11 0x0000085c #define MAC_TX_STATS_RESV4_12 0x00000860 #define MAC_TX_STATS_RESV4_13 0x00000864 #define MAC_TX_STATS_RESV4_14 0x00000868 #define MAC_TX_STATS_UCAST 0x0000086c #define MAC_TX_STATS_MCAST 0x00000870 #define MAC_TX_STATS_BCAST 0x00000874 #define MAC_TX_STATS_RESV5_1 0x00000878 #define MAC_TX_STATS_RESV5_2 0x0000087c #define MAC_RX_STATS_OCTETS 0x00000880 #define MAC_RX_STATS_RESV1 0x00000884 #define MAC_RX_STATS_FRAGMENTS 0x00000888 #define MAC_RX_STATS_UCAST 0x0000088c #define MAC_RX_STATS_MCAST 0x00000890 #define MAC_RX_STATS_BCAST 0x00000894 #define MAC_RX_STATS_FCS_ERRORS 0x00000898 #define MAC_RX_STATS_ALIGN_ERRORS 0x0000089c #define MAC_RX_STATS_XON_PAUSE_RECVD 0x000008a0 #define MAC_RX_STATS_XOFF_PAUSE_RECVD 0x000008a4 #define MAC_RX_STATS_MAC_CTRL_RECVD 0x000008a8 #define MAC_RX_STATS_XOFF_ENTERED 0x000008ac #define MAC_RX_STATS_FRAME_TOO_LONG 0x000008b0 #define MAC_RX_STATS_JABBERS 0x000008b4 #define MAC_RX_STATS_UNDERSIZE 0x000008b8 /* 0x8bc --> 0xc00 unused */ /* Send data initiator control registers */ #define SNDDATAI_MODE 0x00000c00 #define SNDDATAI_MODE_RESET 0x00000001 #define SNDDATAI_MODE_ENABLE 0x00000002 #define SNDDATAI_MODE_STAT_OFLOW_ENAB 0x00000004 #define SNDDATAI_STATUS 0x00000c04 #define SNDDATAI_STATUS_STAT_OFLOW 0x00000004 #define SNDDATAI_STATSCTRL 0x00000c08 #define SNDDATAI_SCTRL_ENABLE 0x00000001 #define SNDDATAI_SCTRL_FASTUPD 0x00000002 #define SNDDATAI_SCTRL_CLEAR 0x00000004 #define SNDDATAI_SCTRL_FLUSH 0x00000008 #define SNDDATAI_SCTRL_FORCE_ZERO 0x00000010 #define SNDDATAI_STATSENAB 0x00000c0c #define SNDDATAI_STATSINCMASK 0x00000c10 /* 0xc14 --> 0xc80 unused */ #define SNDDATAI_COS_CNT_0 0x00000c80 #define SNDDATAI_COS_CNT_1 0x00000c84 #define SNDDATAI_COS_CNT_2 0x00000c88 #define SNDDATAI_COS_CNT_3 0x00000c8c #define SNDDATAI_COS_CNT_4 0x00000c90 #define SNDDATAI_COS_CNT_5 0x00000c94 #define SNDDATAI_COS_CNT_6 0x00000c98 #define SNDDATAI_COS_CNT_7 0x00000c9c #define SNDDATAI_COS_CNT_8 0x00000ca0 #define SNDDATAI_COS_CNT_9 0x00000ca4 #define SNDDATAI_COS_CNT_10 0x00000ca8 #define SNDDATAI_COS_CNT_11 0x00000cac #define SNDDATAI_COS_CNT_12 0x00000cb0 #define SNDDATAI_COS_CNT_13 0x00000cb4 #define SNDDATAI_COS_CNT_14 0x00000cb8 #define SNDDATAI_COS_CNT_15 0x00000cbc #define SNDDATAI_DMA_RDQ_FULL_CNT 0x00000cc0 #define SNDDATAI_DMA_PRIO_RDQ_FULL_CNT 0x00000cc4 #define SNDDATAI_SDCQ_FULL_CNT 0x00000cc8 #define SNDDATAI_NICRNG_SSND_PIDX_CNT 0x00000ccc #define SNDDATAI_STATS_UPDATED_CNT 0x00000cd0 #define SNDDATAI_INTERRUPTS_CNT 0x00000cd4 #define SNDDATAI_AVOID_INTERRUPTS_CNT 0x00000cd8 #define SNDDATAI_SND_THRESH_HIT_CNT 0x00000cdc /* 0xce0 --> 0x1000 unused */ /* Send data completion control registers */ #define SNDDATAC_MODE 0x00001000 #define SNDDATAC_MODE_RESET 0x00000001 #define SNDDATAC_MODE_ENABLE 0x00000002 /* 0x1004 --> 0x1400 unused */ /* Send BD ring selector */ #define SNDBDS_MODE 0x00001400 #define SNDBDS_MODE_RESET 0x00000001 #define SNDBDS_MODE_ENABLE 0x00000002 #define SNDBDS_MODE_ATTN_ENABLE 0x00000004 #define SNDBDS_STATUS 0x00001404 #define SNDBDS_STATUS_ERROR_ATTN 0x00000004 #define SNDBDS_HWDIAG 0x00001408 /* 0x140c --> 0x1440 */ #define SNDBDS_SEL_CON_IDX_0 0x00001440 #define SNDBDS_SEL_CON_IDX_1 0x00001444 #define SNDBDS_SEL_CON_IDX_2 0x00001448 #define SNDBDS_SEL_CON_IDX_3 0x0000144c #define SNDBDS_SEL_CON_IDX_4 0x00001450 #define SNDBDS_SEL_CON_IDX_5 0x00001454 #define SNDBDS_SEL_CON_IDX_6 0x00001458 #define SNDBDS_SEL_CON_IDX_7 0x0000145c #define SNDBDS_SEL_CON_IDX_8 0x00001460 #define SNDBDS_SEL_CON_IDX_9 0x00001464 #define SNDBDS_SEL_CON_IDX_10 0x00001468 #define SNDBDS_SEL_CON_IDX_11 0x0000146c #define SNDBDS_SEL_CON_IDX_12 0x00001470 #define SNDBDS_SEL_CON_IDX_13 0x00001474 #define SNDBDS_SEL_CON_IDX_14 0x00001478 #define SNDBDS_SEL_CON_IDX_15 0x0000147c /* 0x1480 --> 0x1800 unused */ /* Send BD initiator control registers */ #define SNDBDI_MODE 0x00001800 #define SNDBDI_MODE_RESET 0x00000001 #define SNDBDI_MODE_ENABLE 0x00000002 #define SNDBDI_MODE_ATTN_ENABLE 0x00000004 #define SNDBDI_STATUS 0x00001804 #define SNDBDI_STATUS_ERROR_ATTN 0x00000004 #define SNDBDI_IN_PROD_IDX_0 0x00001808 #define SNDBDI_IN_PROD_IDX_1 0x0000180c #define SNDBDI_IN_PROD_IDX_2 0x00001810 #define SNDBDI_IN_PROD_IDX_3 0x00001814 #define SNDBDI_IN_PROD_IDX_4 0x00001818 #define SNDBDI_IN_PROD_IDX_5 0x0000181c #define SNDBDI_IN_PROD_IDX_6 0x00001820 #define SNDBDI_IN_PROD_IDX_7 0x00001824 #define SNDBDI_IN_PROD_IDX_8 0x00001828 #define SNDBDI_IN_PROD_IDX_9 0x0000182c #define SNDBDI_IN_PROD_IDX_10 0x00001830 #define SNDBDI_IN_PROD_IDX_11 0x00001834 #define SNDBDI_IN_PROD_IDX_12 0x00001838 #define SNDBDI_IN_PROD_IDX_13 0x0000183c #define SNDBDI_IN_PROD_IDX_14 0x00001840 #define SNDBDI_IN_PROD_IDX_15 0x00001844 /* 0x1848 --> 0x1c00 unused */ /* Send BD completion control registers */ #define SNDBDC_MODE 0x00001c00 #define SNDBDC_MODE_RESET 0x00000001 #define SNDBDC_MODE_ENABLE 0x00000002 #define SNDBDC_MODE_ATTN_ENABLE 0x00000004 /* 0x1c04 --> 0x2000 unused */ /* Receive list placement control registers */ #define RCVLPC_MODE 0x00002000 #define RCVLPC_MODE_RESET 0x00000001 #define RCVLPC_MODE_ENABLE 0x00000002 #define RCVLPC_MODE_CLASS0_ATTN_ENAB 0x00000004 #define RCVLPC_MODE_MAPOOR_AATTN_ENAB 0x00000008 #define RCVLPC_MODE_STAT_OFLOW_ENAB 0x00000010 #define RCVLPC_STATUS 0x00002004 #define RCVLPC_STATUS_CLASS0 0x00000004 #define RCVLPC_STATUS_MAPOOR 0x00000008 #define RCVLPC_STATUS_STAT_OFLOW 0x00000010 #define RCVLPC_LOCK 0x00002008 #define RCVLPC_LOCK_REQ_MASK 0x0000ffff #define RCVLPC_LOCK_REQ_SHIFT 0 #define RCVLPC_LOCK_GRANT_MASK 0xffff0000 #define RCVLPC_LOCK_GRANT_SHIFT 16 #define RCVLPC_NON_EMPTY_BITS 0x0000200c #define RCVLPC_NON_EMPTY_BITS_MASK 0x0000ffff #define RCVLPC_CONFIG 0x00002010 #define RCVLPC_STATSCTRL 0x00002014 #define RCVLPC_STATSCTRL_ENABLE 0x00000001 #define RCVLPC_STATSCTRL_FASTUPD 0x00000002 #define RCVLPC_STATS_ENABLE 0x00002018 #define RCVLPC_STATSENAB_LNGBRST_RFIX 0x00400000 #define RCVLPC_STATS_INCMASK 0x0000201c /* 0x2020 --> 0x2100 unused */ #define RCVLPC_SELLST_BASE 0x00002100 /* 16 16-byte entries */ #define SELLST_TAIL 0x00000004 #define SELLST_CONT 0x00000008 #define SELLST_UNUSED 0x0000000c #define RCVLPC_COS_CNTL_BASE 0x00002200 /* 16 4-byte entries */ #define RCVLPC_DROP_FILTER_CNT 0x00002240 #define RCVLPC_DMA_WQ_FULL_CNT 0x00002244 #define RCVLPC_DMA_HIPRIO_WQ_FULL_CNT 0x00002248 #define RCVLPC_NO_RCV_BD_CNT 0x0000224c #define RCVLPC_IN_DISCARDS_CNT 0x00002250 #define RCVLPC_IN_ERRORS_CNT 0x00002254 #define RCVLPC_RCV_THRESH_HIT_CNT 0x00002258 /* 0x225c --> 0x2400 unused */ /* Receive Data and Receive BD Initiator Control */ #define RCVDBDI_MODE 0x00002400 #define RCVDBDI_MODE_RESET 0x00000001 #define RCVDBDI_MODE_ENABLE 0x00000002 #define RCVDBDI_MODE_JUMBOBD_NEEDED 0x00000004 #define RCVDBDI_MODE_FRM_TOO_BIG 0x00000008 #define RCVDBDI_MODE_INV_RING_SZ 0x00000010 #define RCVDBDI_STATUS 0x00002404 #define RCVDBDI_STATUS_JUMBOBD_NEEDED 0x00000004 #define RCVDBDI_STATUS_FRM_TOO_BIG 0x00000008 #define RCVDBDI_STATUS_INV_RING_SZ 0x00000010 #define RCVDBDI_SPLIT_FRAME_MINSZ 0x00002408 /* 0x240c --> 0x2440 unused */ #define RCVDBDI_JUMBO_BD 0x00002440 /* TG3_BDINFO_... */ #define RCVDBDI_STD_BD 0x00002450 /* TG3_BDINFO_... */ #define RCVDBDI_MINI_BD 0x00002460 /* TG3_BDINFO_... */ #define RCVDBDI_JUMBO_CON_IDX 0x00002470 #define RCVDBDI_STD_CON_IDX 0x00002474 #define RCVDBDI_MINI_CON_IDX 0x00002478 /* 0x247c --> 0x2480 unused */ #define RCVDBDI_BD_PROD_IDX_0 0x00002480 #define RCVDBDI_BD_PROD_IDX_1 0x00002484 #define RCVDBDI_BD_PROD_IDX_2 0x00002488 #define RCVDBDI_BD_PROD_IDX_3 0x0000248c #define RCVDBDI_BD_PROD_IDX_4 0x00002490 #define RCVDBDI_BD_PROD_IDX_5 0x00002494 #define RCVDBDI_BD_PROD_IDX_6 0x00002498 #define RCVDBDI_BD_PROD_IDX_7 0x0000249c #define RCVDBDI_BD_PROD_IDX_8 0x000024a0 #define RCVDBDI_BD_PROD_IDX_9 0x000024a4 #define RCVDBDI_BD_PROD_IDX_10 0x000024a8 #define RCVDBDI_BD_PROD_IDX_11 0x000024ac #define RCVDBDI_BD_PROD_IDX_12 0x000024b0 #define RCVDBDI_BD_PROD_IDX_13 0x000024b4 #define RCVDBDI_BD_PROD_IDX_14 0x000024b8 #define RCVDBDI_BD_PROD_IDX_15 0x000024bc #define RCVDBDI_HWDIAG 0x000024c0 /* 0x24c4 --> 0x2800 unused */ /* Receive Data Completion Control */ #define RCVDCC_MODE 0x00002800 #define RCVDCC_MODE_RESET 0x00000001 #define RCVDCC_MODE_ENABLE 0x00000002 #define RCVDCC_MODE_ATTN_ENABLE 0x00000004 /* 0x2804 --> 0x2c00 unused */ /* Receive BD Initiator Control Registers */ #define RCVBDI_MODE 0x00002c00 #define RCVBDI_MODE_RESET 0x00000001 #define RCVBDI_MODE_ENABLE 0x00000002 #define RCVBDI_MODE_RCB_ATTN_ENAB 0x00000004 #define RCVBDI_STATUS 0x00002c04 #define RCVBDI_STATUS_RCB_ATTN 0x00000004 #define RCVBDI_JUMBO_PROD_IDX 0x00002c08 #define RCVBDI_STD_PROD_IDX 0x00002c0c #define RCVBDI_MINI_PROD_IDX 0x00002c10 #define RCVBDI_MINI_THRESH 0x00002c14 #define RCVBDI_STD_THRESH 0x00002c18 #define RCVBDI_JUMBO_THRESH 0x00002c1c /* 0x2c20 --> 0x3000 unused */ /* Receive BD Completion Control Registers */ #define RCVCC_MODE 0x00003000 #define RCVCC_MODE_RESET 0x00000001 #define RCVCC_MODE_ENABLE 0x00000002 #define RCVCC_MODE_ATTN_ENABLE 0x00000004 #define RCVCC_STATUS 0x00003004 #define RCVCC_STATUS_ERROR_ATTN 0x00000004 #define RCVCC_JUMP_PROD_IDX 0x00003008 #define RCVCC_STD_PROD_IDX 0x0000300c #define RCVCC_MINI_PROD_IDX 0x00003010 /* 0x3014 --> 0x3400 unused */ /* Receive list selector control registers */ #define RCVLSC_MODE 0x00003400 #define RCVLSC_MODE_RESET 0x00000001 #define RCVLSC_MODE_ENABLE 0x00000002 #define RCVLSC_MODE_ATTN_ENABLE 0x00000004 #define RCVLSC_STATUS 0x00003404 #define RCVLSC_STATUS_ERROR_ATTN 0x00000004 /* 0x3408 --> 0x3800 unused */ /* Mbuf cluster free registers */ #define MBFREE_MODE 0x00003800 #define MBFREE_MODE_RESET 0x00000001 #define MBFREE_MODE_ENABLE 0x00000002 #define MBFREE_STATUS 0x00003804 /* 0x3808 --> 0x3c00 unused */ /* Host coalescing control registers */ #define HOSTCC_MODE 0x00003c00 #define HOSTCC_MODE_RESET 0x00000001 #define HOSTCC_MODE_ENABLE 0x00000002 #define HOSTCC_MODE_ATTN 0x00000004 #define HOSTCC_MODE_NOW 0x00000008 #define HOSTCC_MODE_FULL_STATUS 0x00000000 #define HOSTCC_MODE_64BYTE 0x00000080 #define HOSTCC_MODE_32BYTE 0x00000100 #define HOSTCC_MODE_CLRTICK_RXBD 0x00000200 #define HOSTCC_MODE_CLRTICK_TXBD 0x00000400 #define HOSTCC_MODE_NOINT_ON_NOW 0x00000800 #define HOSTCC_MODE_NOINT_ON_FORCE 0x00001000 #define HOSTCC_STATUS 0x00003c04 #define HOSTCC_STATUS_ERROR_ATTN 0x00000004 #define HOSTCC_RXCOL_TICKS 0x00003c08 #define LOW_RXCOL_TICKS 0x00000032 #define LOW_RXCOL_TICKS_CLRTCKS 0x00000014 #define DEFAULT_RXCOL_TICKS 0x00000048 #define HIGH_RXCOL_TICKS 0x00000096 #define MAX_RXCOL_TICKS 0x000003ff #define HOSTCC_TXCOL_TICKS 0x00003c0c #define LOW_TXCOL_TICKS 0x00000096 #define LOW_TXCOL_TICKS_CLRTCKS 0x00000048 #define DEFAULT_TXCOL_TICKS 0x0000012c #define HIGH_TXCOL_TICKS 0x00000145 #define MAX_TXCOL_TICKS 0x000003ff #define HOSTCC_RXMAX_FRAMES 0x00003c10 #define LOW_RXMAX_FRAMES 0x00000005 #define DEFAULT_RXMAX_FRAMES 0x00000008 #define HIGH_RXMAX_FRAMES 0x00000012 #define MAX_RXMAX_FRAMES 0x000000ff #define HOSTCC_TXMAX_FRAMES 0x00003c14 #define LOW_TXMAX_FRAMES 0x00000035 #define DEFAULT_TXMAX_FRAMES 0x0000004b #define HIGH_TXMAX_FRAMES 0x00000052 #define MAX_TXMAX_FRAMES 0x000000ff #define HOSTCC_RXCOAL_TICK_INT 0x00003c18 #define DEFAULT_RXCOAL_TICK_INT 0x00000019 #define DEFAULT_RXCOAL_TICK_INT_CLRTCKS 0x00000014 #define MAX_RXCOAL_TICK_INT 0x000003ff #define HOSTCC_TXCOAL_TICK_INT 0x00003c1c #define DEFAULT_TXCOAL_TICK_INT 0x00000019 #define DEFAULT_TXCOAL_TICK_INT_CLRTCKS 0x00000014 #define MAX_TXCOAL_TICK_INT 0x000003ff #define HOSTCC_RXCOAL_MAXF_INT 0x00003c20 #define DEFAULT_RXCOAL_MAXF_INT 0x00000005 #define MAX_RXCOAL_MAXF_INT 0x000000ff #define HOSTCC_TXCOAL_MAXF_INT 0x00003c24 #define DEFAULT_TXCOAL_MAXF_INT 0x00000005 #define MAX_TXCOAL_MAXF_INT 0x000000ff #define HOSTCC_STAT_COAL_TICKS 0x00003c28 #define DEFAULT_STAT_COAL_TICKS 0x000f4240 #define MAX_STAT_COAL_TICKS 0xd693d400 #define MIN_STAT_COAL_TICKS 0x00000064 /* 0x3c2c --> 0x3c30 unused */ #define HOSTCC_STATS_BLK_HOST_ADDR 0x00003c30 /* 64-bit */ #define HOSTCC_STATUS_BLK_HOST_ADDR 0x00003c38 /* 64-bit */ #define HOSTCC_STATS_BLK_NIC_ADDR 0x00003c40 #define HOSTCC_STATUS_BLK_NIC_ADDR 0x00003c44 #define HOSTCC_FLOW_ATTN 0x00003c48 /* 0x3c4c --> 0x3c50 unused */ #define HOSTCC_JUMBO_CON_IDX 0x00003c50 #define HOSTCC_STD_CON_IDX 0x00003c54 #define HOSTCC_MINI_CON_IDX 0x00003c58 /* 0x3c5c --> 0x3c80 unused */ #define HOSTCC_RET_PROD_IDX_0 0x00003c80 #define HOSTCC_RET_PROD_IDX_1 0x00003c84 #define HOSTCC_RET_PROD_IDX_2 0x00003c88 #define HOSTCC_RET_PROD_IDX_3 0x00003c8c #define HOSTCC_RET_PROD_IDX_4 0x00003c90 #define HOSTCC_RET_PROD_IDX_5 0x00003c94 #define HOSTCC_RET_PROD_IDX_6 0x00003c98 #define HOSTCC_RET_PROD_IDX_7 0x00003c9c #define HOSTCC_RET_PROD_IDX_8 0x00003ca0 #define HOSTCC_RET_PROD_IDX_9 0x00003ca4 #define HOSTCC_RET_PROD_IDX_10 0x00003ca8 #define HOSTCC_RET_PROD_IDX_11 0x00003cac #define HOSTCC_RET_PROD_IDX_12 0x00003cb0 #define HOSTCC_RET_PROD_IDX_13 0x00003cb4 #define HOSTCC_RET_PROD_IDX_14 0x00003cb8 #define HOSTCC_RET_PROD_IDX_15 0x00003cbc #define HOSTCC_SND_CON_IDX_0 0x00003cc0 #define HOSTCC_SND_CON_IDX_1 0x00003cc4 #define HOSTCC_SND_CON_IDX_2 0x00003cc8 #define HOSTCC_SND_CON_IDX_3 0x00003ccc #define HOSTCC_SND_CON_IDX_4 0x00003cd0 #define HOSTCC_SND_CON_IDX_5 0x00003cd4 #define HOSTCC_SND_CON_IDX_6 0x00003cd8 #define HOSTCC_SND_CON_IDX_7 0x00003cdc #define HOSTCC_SND_CON_IDX_8 0x00003ce0 #define HOSTCC_SND_CON_IDX_9 0x00003ce4 #define HOSTCC_SND_CON_IDX_10 0x00003ce8 #define HOSTCC_SND_CON_IDX_11 0x00003cec #define HOSTCC_SND_CON_IDX_12 0x00003cf0 #define HOSTCC_SND_CON_IDX_13 0x00003cf4 #define HOSTCC_SND_CON_IDX_14 0x00003cf8 #define HOSTCC_SND_CON_IDX_15 0x00003cfc /* 0x3d00 --> 0x4000 unused */ /* Memory arbiter control registers */ #define MEMARB_MODE 0x00004000 #define MEMARB_MODE_RESET 0x00000001 #define MEMARB_MODE_ENABLE 0x00000002 #define MEMARB_STATUS 0x00004004 #define MEMARB_TRAP_ADDR_LOW 0x00004008 #define MEMARB_TRAP_ADDR_HIGH 0x0000400c /* 0x4010 --> 0x4400 unused */ /* Buffer manager control registers */ #define BUFMGR_MODE 0x00004400 #define BUFMGR_MODE_RESET 0x00000001 #define BUFMGR_MODE_ENABLE 0x00000002 #define BUFMGR_MODE_ATTN_ENABLE 0x00000004 #define BUFMGR_MODE_BM_TEST 0x00000008 #define BUFMGR_MODE_MBLOW_ATTN_ENAB 0x00000010 #define BUFMGR_STATUS 0x00004404 #define BUFMGR_STATUS_ERROR 0x00000004 #define BUFMGR_STATUS_MBLOW 0x00000010 #define BUFMGR_MB_POOL_ADDR 0x00004408 #define BUFMGR_MB_POOL_SIZE 0x0000440c #define BUFMGR_MB_RDMA_LOW_WATER 0x00004410 #define DEFAULT_MB_RDMA_LOW_WATER 0x00000050 #define DEFAULT_MB_RDMA_LOW_WATER_5705 0x00000000 #define DEFAULT_MB_RDMA_LOW_WATER_JUMBO 0x00000130 #define DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780 0x00000000 #define BUFMGR_MB_MACRX_LOW_WATER 0x00004414 #define DEFAULT_MB_MACRX_LOW_WATER 0x00000020 #define DEFAULT_MB_MACRX_LOW_WATER_5705 0x00000010 #define DEFAULT_MB_MACRX_LOW_WATER_JUMBO 0x00000098 #define DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780 0x0000004b #define BUFMGR_MB_HIGH_WATER 0x00004418 #define DEFAULT_MB_HIGH_WATER 0x00000060 #define DEFAULT_MB_HIGH_WATER_5705 0x00000060 #define DEFAULT_MB_HIGH_WATER_JUMBO 0x0000017c #define DEFAULT_MB_HIGH_WATER_JUMBO_5780 0x00000096 #define BUFMGR_RX_MB_ALLOC_REQ 0x0000441c #define BUFMGR_MB_ALLOC_BIT 0x10000000 #define BUFMGR_RX_MB_ALLOC_RESP 0x00004420 #define BUFMGR_TX_MB_ALLOC_REQ 0x00004424 #define BUFMGR_TX_MB_ALLOC_RESP 0x00004428 #define BUFMGR_DMA_DESC_POOL_ADDR 0x0000442c #define BUFMGR_DMA_DESC_POOL_SIZE 0x00004430 #define BUFMGR_DMA_LOW_WATER 0x00004434 #define DEFAULT_DMA_LOW_WATER 0x00000005 #define BUFMGR_DMA_HIGH_WATER 0x00004438 #define DEFAULT_DMA_HIGH_WATER 0x0000000a #define BUFMGR_RX_DMA_ALLOC_REQ 0x0000443c #define BUFMGR_RX_DMA_ALLOC_RESP 0x00004440 #define BUFMGR_TX_DMA_ALLOC_REQ 0x00004444 #define BUFMGR_TX_DMA_ALLOC_RESP 0x00004448 #define BUFMGR_HWDIAG_0 0x0000444c #define BUFMGR_HWDIAG_1 0x00004450 #define BUFMGR_HWDIAG_2 0x00004454 /* 0x4458 --> 0x4800 unused */ /* Read DMA control registers */ #define RDMAC_MODE 0x00004800 #define RDMAC_MODE_RESET 0x00000001 #define RDMAC_MODE_ENABLE 0x00000002 #define RDMAC_MODE_TGTABORT_ENAB 0x00000004 #define RDMAC_MODE_MSTABORT_ENAB 0x00000008 #define RDMAC_MODE_PARITYERR_ENAB 0x00000010 #define RDMAC_MODE_ADDROFLOW_ENAB 0x00000020 #define RDMAC_MODE_FIFOOFLOW_ENAB 0x00000040 #define RDMAC_MODE_FIFOURUN_ENAB 0x00000080 #define RDMAC_MODE_FIFOOREAD_ENAB 0x00000100 #define RDMAC_MODE_LNGREAD_ENAB 0x00000200 #define RDMAC_MODE_SPLIT_ENABLE 0x00000800 #define RDMAC_MODE_SPLIT_RESET 0x00001000 #define RDMAC_MODE_FIFO_SIZE_128 0x00020000 #define RDMAC_MODE_FIFO_LONG_BURST 0x00030000 #define RDMAC_STATUS 0x00004804 #define RDMAC_STATUS_TGTABORT 0x00000004 #define RDMAC_STATUS_MSTABORT 0x00000008 #define RDMAC_STATUS_PARITYERR 0x00000010 #define RDMAC_STATUS_ADDROFLOW 0x00000020 #define RDMAC_STATUS_FIFOOFLOW 0x00000040 #define RDMAC_STATUS_FIFOURUN 0x00000080 #define RDMAC_STATUS_FIFOOREAD 0x00000100 #define RDMAC_STATUS_LNGREAD 0x00000200 /* 0x4808 --> 0x4c00 unused */ /* Write DMA control registers */ #define WDMAC_MODE 0x00004c00 #define WDMAC_MODE_RESET 0x00000001 #define WDMAC_MODE_ENABLE 0x00000002 #define WDMAC_MODE_TGTABORT_ENAB 0x00000004 #define WDMAC_MODE_MSTABORT_ENAB 0x00000008 #define WDMAC_MODE_PARITYERR_ENAB 0x00000010 #define WDMAC_MODE_ADDROFLOW_ENAB 0x00000020 #define WDMAC_MODE_FIFOOFLOW_ENAB 0x00000040 #define WDMAC_MODE_FIFOURUN_ENAB 0x00000080 #define WDMAC_MODE_FIFOOREAD_ENAB 0x00000100 #define WDMAC_MODE_LNGREAD_ENAB 0x00000200 #define WDMAC_MODE_RX_ACCEL 0x00000400 #define WDMAC_STATUS 0x00004c04 #define WDMAC_STATUS_TGTABORT 0x00000004 #define WDMAC_STATUS_MSTABORT 0x00000008 #define WDMAC_STATUS_PARITYERR 0x00000010 #define WDMAC_STATUS_ADDROFLOW 0x00000020 #define WDMAC_STATUS_FIFOOFLOW 0x00000040 #define WDMAC_STATUS_FIFOURUN 0x00000080 #define WDMAC_STATUS_FIFOOREAD 0x00000100 #define WDMAC_STATUS_LNGREAD 0x00000200 /* 0x4c08 --> 0x5000 unused */ /* Per-cpu register offsets (arm9) */ #define CPU_MODE 0x00000000 #define CPU_MODE_RESET 0x00000001 #define CPU_MODE_HALT 0x00000400 #define CPU_STATE 0x00000004 #define CPU_EVTMASK 0x00000008 /* 0xc --> 0x1c reserved */ #define CPU_PC 0x0000001c #define CPU_INSN 0x00000020 #define CPU_SPAD_UFLOW 0x00000024 #define CPU_WDOG_CLEAR 0x00000028 #define CPU_WDOG_VECTOR 0x0000002c #define CPU_WDOG_PC 0x00000030 #define CPU_HW_BP 0x00000034 /* 0x38 --> 0x44 unused */ #define CPU_WDOG_SAVED_STATE 0x00000044 #define CPU_LAST_BRANCH_ADDR 0x00000048 #define CPU_SPAD_UFLOW_SET 0x0000004c /* 0x50 --> 0x200 unused */ #define CPU_R0 0x00000200 #define CPU_R1 0x00000204 #define CPU_R2 0x00000208 #define CPU_R3 0x0000020c #define CPU_R4 0x00000210 #define CPU_R5 0x00000214 #define CPU_R6 0x00000218 #define CPU_R7 0x0000021c #define CPU_R8 0x00000220 #define CPU_R9 0x00000224 #define CPU_R10 0x00000228 #define CPU_R11 0x0000022c #define CPU_R12 0x00000230 #define CPU_R13 0x00000234 #define CPU_R14 0x00000238 #define CPU_R15 0x0000023c #define CPU_R16 0x00000240 #define CPU_R17 0x00000244 #define CPU_R18 0x00000248 #define CPU_R19 0x0000024c #define CPU_R20 0x00000250 #define CPU_R21 0x00000254 #define CPU_R22 0x00000258 #define CPU_R23 0x0000025c #define CPU_R24 0x00000260 #define CPU_R25 0x00000264 #define CPU_R26 0x00000268 #define CPU_R27 0x0000026c #define CPU_R28 0x00000270 #define CPU_R29 0x00000274 #define CPU_R30 0x00000278 #define CPU_R31 0x0000027c /* 0x280 --> 0x400 unused */ #define RX_CPU_BASE 0x00005000 #define RX_CPU_MODE 0x00005000 #define RX_CPU_STATE 0x00005004 #define RX_CPU_PGMCTR 0x0000501c #define RX_CPU_HWBKPT 0x00005034 #define TX_CPU_BASE 0x00005400 #define TX_CPU_MODE 0x00005400 #define TX_CPU_STATE 0x00005404 #define TX_CPU_PGMCTR 0x0000541c /* Mailboxes */ #define GRCMBOX_INTERRUPT_0 0x00005800 /* 64-bit */ #define GRCMBOX_INTERRUPT_1 0x00005808 /* 64-bit */ #define GRCMBOX_INTERRUPT_2 0x00005810 /* 64-bit */ #define GRCMBOX_INTERRUPT_3 0x00005818 /* 64-bit */ #define GRCMBOX_GENERAL_0 0x00005820 /* 64-bit */ #define GRCMBOX_GENERAL_1 0x00005828 /* 64-bit */ #define GRCMBOX_GENERAL_2 0x00005830 /* 64-bit */ #define GRCMBOX_GENERAL_3 0x00005838 /* 64-bit */ #define GRCMBOX_GENERAL_4 0x00005840 /* 64-bit */ #define GRCMBOX_GENERAL_5 0x00005848 /* 64-bit */ #define GRCMBOX_GENERAL_6 0x00005850 /* 64-bit */ #define GRCMBOX_GENERAL_7 0x00005858 /* 64-bit */ #define GRCMBOX_RELOAD_STAT 0x00005860 /* 64-bit */ #define GRCMBOX_RCVSTD_PROD_IDX 0x00005868 /* 64-bit */ #define GRCMBOX_RCVJUMBO_PROD_IDX 0x00005870 /* 64-bit */ #define GRCMBOX_RCVMINI_PROD_IDX 0x00005878 /* 64-bit */ #define GRCMBOX_RCVRET_CON_IDX_0 0x00005880 /* 64-bit */ #define GRCMBOX_RCVRET_CON_IDX_1 0x00005888 /* 64-bit */ #define GRCMBOX_RCVRET_CON_IDX_2 0x00005890 /* 64-bit */ #define GRCMBOX_RCVRET_CON_IDX_3 0x00005898 /* 64-bit */ #define GRCMBOX_RCVRET_CON_IDX_4 0x000058a0 /* 64-bit */ #define GRCMBOX_RCVRET_CON_IDX_5 0x000058a8 /* 64-bit */ #define GRCMBOX_RCVRET_CON_IDX_6 0x000058b0 /* 64-bit */ #define GRCMBOX_RCVRET_CON_IDX_7 0x000058b8 /* 64-bit */ #define GRCMBOX_RCVRET_CON_IDX_8 0x000058c0 /* 64-bit */ #define GRCMBOX_RCVRET_CON_IDX_9 0x000058c8 /* 64-bit */ #define GRCMBOX_RCVRET_CON_IDX_10 0x000058d0 /* 64-bit */ #define GRCMBOX_RCVRET_CON_IDX_11 0x000058d8 /* 64-bit */ #define GRCMBOX_RCVRET_CON_IDX_12 0x000058e0 /* 64-bit */ #define GRCMBOX_RCVRET_CON_IDX_13 0x000058e8 /* 64-bit */ #define GRCMBOX_RCVRET_CON_IDX_14 0x000058f0 /* 64-bit */ #define GRCMBOX_RCVRET_CON_IDX_15 0x000058f8 /* 64-bit */ #define GRCMBOX_SNDHOST_PROD_IDX_0 0x00005900 /* 64-bit */ #define GRCMBOX_SNDHOST_PROD_IDX_1 0x00005908 /* 64-bit */ #define GRCMBOX_SNDHOST_PROD_IDX_2 0x00005910 /* 64-bit */ #define GRCMBOX_SNDHOST_PROD_IDX_3 0x00005918 /* 64-bit */ #define GRCMBOX_SNDHOST_PROD_IDX_4 0x00005920 /* 64-bit */ #define GRCMBOX_SNDHOST_PROD_IDX_5 0x00005928 /* 64-bit */ #define GRCMBOX_SNDHOST_PROD_IDX_6 0x00005930 /* 64-bit */ #define GRCMBOX_SNDHOST_PROD_IDX_7 0x00005938 /* 64-bit */ #define GRCMBOX_SNDHOST_PROD_IDX_8 0x00005940 /* 64-bit */ #define GRCMBOX_SNDHOST_PROD_IDX_9 0x00005948 /* 64-bit */ #define GRCMBOX_SNDHOST_PROD_IDX_10 0x00005950 /* 64-bit */ #define GRCMBOX_SNDHOST_PROD_IDX_11 0x00005958 /* 64-bit */ #define GRCMBOX_SNDHOST_PROD_IDX_12 0x00005960 /* 64-bit */ #define GRCMBOX_SNDHOST_PROD_IDX_13 0x00005968 /* 64-bit */ #define GRCMBOX_SNDHOST_PROD_IDX_14 0x00005970 /* 64-bit */ #define GRCMBOX_SNDHOST_PROD_IDX_15 0x00005978 /* 64-bit */ #define GRCMBOX_SNDNIC_PROD_IDX_0 0x00005980 /* 64-bit */ #define GRCMBOX_SNDNIC_PROD_IDX_1 0x00005988 /* 64-bit */ #define GRCMBOX_SNDNIC_PROD_IDX_2 0x00005990 /* 64-bit */ #define GRCMBOX_SNDNIC_PROD_IDX_3 0x00005998 /* 64-bit */ #define GRCMBOX_SNDNIC_PROD_IDX_4 0x000059a0 /* 64-bit */ #define GRCMBOX_SNDNIC_PROD_IDX_5 0x000059a8 /* 64-bit */ #define GRCMBOX_SNDNIC_PROD_IDX_6 0x000059b0 /* 64-bit */ #define GRCMBOX_SNDNIC_PROD_IDX_7 0x000059b8 /* 64-bit */ #define GRCMBOX_SNDNIC_PROD_IDX_8 0x000059c0 /* 64-bit */ #define GRCMBOX_SNDNIC_PROD_IDX_9 0x000059c8 /* 64-bit */ #define GRCMBOX_SNDNIC_PROD_IDX_10 0x000059d0 /* 64-bit */ #define GRCMBOX_SNDNIC_PROD_IDX_11 0x000059d8 /* 64-bit */ #define GRCMBOX_SNDNIC_PROD_IDX_12 0x000059e0 /* 64-bit */ #define GRCMBOX_SNDNIC_PROD_IDX_13 0x000059e8 /* 64-bit */ #define GRCMBOX_SNDNIC_PROD_IDX_14 0x000059f0 /* 64-bit */ #define GRCMBOX_SNDNIC_PROD_IDX_15 0x000059f8 /* 64-bit */ #define GRCMBOX_HIGH_PRIO_EV_VECTOR 0x00005a00 #define GRCMBOX_HIGH_PRIO_EV_MASK 0x00005a04 #define GRCMBOX_LOW_PRIO_EV_VEC 0x00005a08 #define GRCMBOX_LOW_PRIO_EV_MASK 0x00005a0c /* 0x5a10 --> 0x5c00 */ /* Flow Through queues */ #define FTQ_RESET 0x00005c00 /* 0x5c04 --> 0x5c10 unused */ #define FTQ_DMA_NORM_READ_CTL 0x00005c10 #define FTQ_DMA_NORM_READ_FULL_CNT 0x00005c14 #define FTQ_DMA_NORM_READ_FIFO_ENQDEQ 0x00005c18 #define FTQ_DMA_NORM_READ_WRITE_PEEK 0x00005c1c #define FTQ_DMA_HIGH_READ_CTL 0x00005c20 #define FTQ_DMA_HIGH_READ_FULL_CNT 0x00005c24 #define FTQ_DMA_HIGH_READ_FIFO_ENQDEQ 0x00005c28 #define FTQ_DMA_HIGH_READ_WRITE_PEEK 0x00005c2c #define FTQ_DMA_COMP_DISC_CTL 0x00005c30 #define FTQ_DMA_COMP_DISC_FULL_CNT 0x00005c34 #define FTQ_DMA_COMP_DISC_FIFO_ENQDEQ 0x00005c38 #define FTQ_DMA_COMP_DISC_WRITE_PEEK 0x00005c3c #define FTQ_SEND_BD_COMP_CTL 0x00005c40 #define FTQ_SEND_BD_COMP_FULL_CNT 0x00005c44 #define FTQ_SEND_BD_COMP_FIFO_ENQDEQ 0x00005c48 #define FTQ_SEND_BD_COMP_WRITE_PEEK 0x00005c4c #define FTQ_SEND_DATA_INIT_CTL 0x00005c50 #define FTQ_SEND_DATA_INIT_FULL_CNT 0x00005c54 #define FTQ_SEND_DATA_INIT_FIFO_ENQDEQ 0x00005c58 #define FTQ_SEND_DATA_INIT_WRITE_PEEK 0x00005c5c #define FTQ_DMA_NORM_WRITE_CTL 0x00005c60 #define FTQ_DMA_NORM_WRITE_FULL_CNT 0x00005c64 #define FTQ_DMA_NORM_WRITE_FIFO_ENQDEQ 0x00005c68 #define FTQ_DMA_NORM_WRITE_WRITE_PEEK 0x00005c6c #define FTQ_DMA_HIGH_WRITE_CTL 0x00005c70 #define FTQ_DMA_HIGH_WRITE_FULL_CNT 0x00005c74 #define FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ 0x00005c78 #define FTQ_DMA_HIGH_WRITE_WRITE_PEEK 0x00005c7c #define FTQ_SWTYPE1_CTL 0x00005c80 #define FTQ_SWTYPE1_FULL_CNT 0x00005c84 #define FTQ_SWTYPE1_FIFO_ENQDEQ 0x00005c88 #define FTQ_SWTYPE1_WRITE_PEEK 0x00005c8c #define FTQ_SEND_DATA_COMP_CTL 0x00005c90 #define FTQ_SEND_DATA_COMP_FULL_CNT 0x00005c94 #define FTQ_SEND_DATA_COMP_FIFO_ENQDEQ 0x00005c98 #define FTQ_SEND_DATA_COMP_WRITE_PEEK 0x00005c9c #define FTQ_HOST_COAL_CTL 0x00005ca0 #define FTQ_HOST_COAL_FULL_CNT 0x00005ca4 #define FTQ_HOST_COAL_FIFO_ENQDEQ 0x00005ca8 #define FTQ_HOST_COAL_WRITE_PEEK 0x00005cac #define FTQ_MAC_TX_CTL 0x00005cb0 #define FTQ_MAC_TX_FULL_CNT 0x00005cb4 #define FTQ_MAC_TX_FIFO_ENQDEQ 0x00005cb8 #define FTQ_MAC_TX_WRITE_PEEK 0x00005cbc #define FTQ_MB_FREE_CTL 0x00005cc0 #define FTQ_MB_FREE_FULL_CNT 0x00005cc4 #define FTQ_MB_FREE_FIFO_ENQDEQ 0x00005cc8 #define FTQ_MB_FREE_WRITE_PEEK 0x00005ccc #define FTQ_RCVBD_COMP_CTL 0x00005cd0 #define FTQ_RCVBD_COMP_FULL_CNT 0x00005cd4 #define FTQ_RCVBD_COMP_FIFO_ENQDEQ 0x00005cd8 #define FTQ_RCVBD_COMP_WRITE_PEEK 0x00005cdc #define FTQ_RCVLST_PLMT_CTL 0x00005ce0 #define FTQ_RCVLST_PLMT_FULL_CNT 0x00005ce4 #define FTQ_RCVLST_PLMT_FIFO_ENQDEQ 0x00005ce8 #define FTQ_RCVLST_PLMT_WRITE_PEEK 0x00005cec #define FTQ_RCVDATA_INI_CTL 0x00005cf0 #define FTQ_RCVDATA_INI_FULL_CNT 0x00005cf4 #define FTQ_RCVDATA_INI_FIFO_ENQDEQ 0x00005cf8 #define FTQ_RCVDATA_INI_WRITE_PEEK 0x00005cfc #define FTQ_RCVDATA_COMP_CTL 0x00005d00 #define FTQ_RCVDATA_COMP_FULL_CNT 0x00005d04 #define FTQ_RCVDATA_COMP_FIFO_ENQDEQ 0x00005d08 #define FTQ_RCVDATA_COMP_WRITE_PEEK 0x00005d0c #define FTQ_SWTYPE2_CTL 0x00005d10 #define FTQ_SWTYPE2_FULL_CNT 0x00005d14 #define FTQ_SWTYPE2_FIFO_ENQDEQ 0x00005d18 #define FTQ_SWTYPE2_WRITE_PEEK 0x00005d1c /* 0x5d20 --> 0x6000 unused */ /* Message signaled interrupt registers */ #define MSGINT_MODE 0x00006000 #define MSGINT_MODE_RESET 0x00000001 #define MSGINT_MODE_ENABLE 0x00000002 #define MSGINT_STATUS 0x00006004 #define MSGINT_FIFO 0x00006008 /* 0x600c --> 0x6400 unused */ /* DMA completion registers */ #define DMAC_MODE 0x00006400 #define DMAC_MODE_RESET 0x00000001 #define DMAC_MODE_ENABLE 0x00000002 /* 0x6404 --> 0x6800 unused */ /* GRC registers */ #define GRC_MODE 0x00006800 #define GRC_MODE_UPD_ON_COAL 0x00000001 #define GRC_MODE_BSWAP_NONFRM_DATA 0x00000002 #define GRC_MODE_WSWAP_NONFRM_DATA 0x00000004 #define GRC_MODE_BSWAP_DATA 0x00000010 #define GRC_MODE_WSWAP_DATA 0x00000020 #define GRC_MODE_SPLITHDR 0x00000100 #define GRC_MODE_NOFRM_CRACKING 0x00000200 #define GRC_MODE_INCL_CRC 0x00000400 #define GRC_MODE_ALLOW_BAD_FRMS 0x00000800 #define GRC_MODE_NOIRQ_ON_SENDS 0x00002000 #define GRC_MODE_NOIRQ_ON_RCV 0x00004000 #define GRC_MODE_FORCE_PCI32BIT 0x00008000 #define GRC_MODE_HOST_STACKUP 0x00010000 #define GRC_MODE_HOST_SENDBDS 0x00020000 #define GRC_MODE_NO_TX_PHDR_CSUM 0x00100000 #define GRC_MODE_NVRAM_WR_ENABLE 0x00200000 #define GRC_MODE_NO_RX_PHDR_CSUM 0x00800000 #define GRC_MODE_IRQ_ON_TX_CPU_ATTN 0x01000000 #define GRC_MODE_IRQ_ON_RX_CPU_ATTN 0x02000000 #define GRC_MODE_IRQ_ON_MAC_ATTN 0x04000000 #define GRC_MODE_IRQ_ON_DMA_ATTN 0x08000000 #define GRC_MODE_IRQ_ON_FLOW_ATTN 0x10000000 #define GRC_MODE_4X_NIC_SEND_RINGS 0x20000000 #define GRC_MODE_MCAST_FRM_ENABLE 0x40000000 #define GRC_MISC_CFG 0x00006804 #define GRC_MISC_CFG_CORECLK_RESET 0x00000001 #define GRC_MISC_CFG_PRESCALAR_MASK 0x000000fe #define GRC_MISC_CFG_PRESCALAR_SHIFT 1 #define GRC_MISC_CFG_BOARD_ID_MASK 0x0001e000 #define GRC_MISC_CFG_BOARD_ID_5700 0x0001e000 #define GRC_MISC_CFG_BOARD_ID_5701 0x00000000 #define GRC_MISC_CFG_BOARD_ID_5702FE 0x00004000 #define GRC_MISC_CFG_BOARD_ID_5703 0x00000000 #define GRC_MISC_CFG_BOARD_ID_5703S 0x00002000 #define GRC_MISC_CFG_BOARD_ID_5704 0x00000000 #define GRC_MISC_CFG_BOARD_ID_5704CIOBE 0x00004000 #define GRC_MISC_CFG_BOARD_ID_5704_A2 0x00008000 #define GRC_MISC_CFG_BOARD_ID_5788 0x00010000 #define GRC_MISC_CFG_BOARD_ID_5788M 0x00018000 #define GRC_MISC_CFG_BOARD_ID_AC91002A1 0x00018000 #define GRC_MISC_CFG_KEEP_GPHY_POWER 0x04000000 #define GRC_LOCAL_CTRL 0x00006808 #define GRC_LCLCTRL_INT_ACTIVE 0x00000001 #define GRC_LCLCTRL_CLEARINT 0x00000002 #define GRC_LCLCTRL_SETINT 0x00000004 #define GRC_LCLCTRL_INT_ON_ATTN 0x00000008 #define GRC_LCLCTRL_GPIO_UART_SEL 0x00000010 /* 5755 only */ #define GRC_LCLCTRL_USE_SIG_DETECT 0x00000010 /* 5714/5780 only */ #define GRC_LCLCTRL_USE_EXT_SIG_DETECT 0x00000020 /* 5714/5780 only */ #define GRC_LCLCTRL_GPIO_INPUT3 0x00000020 #define GRC_LCLCTRL_GPIO_OE3 0x00000040 #define GRC_LCLCTRL_GPIO_OUTPUT3 0x00000080 #define GRC_LCLCTRL_GPIO_INPUT0 0x00000100 #define GRC_LCLCTRL_GPIO_INPUT1 0x00000200 #define GRC_LCLCTRL_GPIO_INPUT2 0x00000400 #define GRC_LCLCTRL_GPIO_OE0 0x00000800 #define GRC_LCLCTRL_GPIO_OE1 0x00001000 #define GRC_LCLCTRL_GPIO_OE2 0x00002000 #define GRC_LCLCTRL_GPIO_OUTPUT0 0x00004000 #define GRC_LCLCTRL_GPIO_OUTPUT1 0x00008000 #define GRC_LCLCTRL_GPIO_OUTPUT2 0x00010000 #define GRC_LCLCTRL_EXTMEM_ENABLE 0x00020000 #define GRC_LCLCTRL_MEMSZ_MASK 0x001c0000 #define GRC_LCLCTRL_MEMSZ_256K 0x00000000 #define GRC_LCLCTRL_MEMSZ_512K 0x00040000 #define GRC_LCLCTRL_MEMSZ_1M 0x00080000 #define GRC_LCLCTRL_MEMSZ_2M 0x000c0000 #define GRC_LCLCTRL_MEMSZ_4M 0x00100000 #define GRC_LCLCTRL_MEMSZ_8M 0x00140000 #define GRC_LCLCTRL_MEMSZ_16M 0x00180000 #define GRC_LCLCTRL_BANK_SELECT 0x00200000 #define GRC_LCLCTRL_SSRAM_TYPE 0x00400000 #define GRC_LCLCTRL_AUTO_SEEPROM 0x01000000 #define GRC_TIMER 0x0000680c #define GRC_RX_CPU_EVENT 0x00006810 #define GRC_RX_TIMER_REF 0x00006814 #define GRC_RX_CPU_SEM 0x00006818 #define GRC_REMOTE_RX_CPU_ATTN 0x0000681c #define GRC_TX_CPU_EVENT 0x00006820 #define GRC_TX_TIMER_REF 0x00006824 #define GRC_TX_CPU_SEM 0x00006828 #define GRC_REMOTE_TX_CPU_ATTN 0x0000682c #define GRC_MEM_POWER_UP 0x00006830 /* 64-bit */ #define GRC_EEPROM_ADDR 0x00006838 #define EEPROM_ADDR_WRITE 0x00000000 #define EEPROM_ADDR_READ 0x80000000 #define EEPROM_ADDR_COMPLETE 0x40000000 #define EEPROM_ADDR_FSM_RESET 0x20000000 #define EEPROM_ADDR_DEVID_MASK 0x1c000000 #define EEPROM_ADDR_DEVID_SHIFT 26 #define EEPROM_ADDR_START 0x02000000 #define EEPROM_ADDR_CLKPERD_SHIFT 16 #define EEPROM_ADDR_ADDR_MASK 0x0000ffff #define EEPROM_ADDR_ADDR_SHIFT 0 #define EEPROM_DEFAULT_CLOCK_PERIOD 0x60 #define EEPROM_CHIP_SIZE (64 * 1024) #define GRC_EEPROM_DATA 0x0000683c #define GRC_EEPROM_CTRL 0x00006840 #define GRC_MDI_CTRL 0x00006844 #define GRC_SEEPROM_DELAY 0x00006848 /* 0x684c --> 0x6c00 unused */ #define GRC_FASTBOOT_PC 0x00006894 /* 5752, 5755, 5787 */ /* 0x6c00 --> 0x7000 unused */ /* NVRAM Control registers */ #define NVRAM_CMD 0x00007000 #define NVRAM_CMD_RESET 0x00000001 #define NVRAM_CMD_DONE 0x00000008 #define NVRAM_CMD_GO 0x00000010 #define NVRAM_CMD_WR 0x00000020 #define NVRAM_CMD_RD 0x00000000 #define NVRAM_CMD_ERASE 0x00000040 #define NVRAM_CMD_FIRST 0x00000080 #define NVRAM_CMD_LAST 0x00000100 #define NVRAM_CMD_WREN 0x00010000 #define NVRAM_CMD_WRDI 0x00020000 #define NVRAM_STAT 0x00007004 #define NVRAM_WRDATA 0x00007008 #define NVRAM_ADDR 0x0000700c #define NVRAM_ADDR_MSK 0x00ffffff #define NVRAM_RDDATA 0x00007010 #define NVRAM_CFG1 0x00007014 #define NVRAM_CFG1_FLASHIF_ENAB 0x00000001 #define NVRAM_CFG1_BUFFERED_MODE 0x00000002 #define NVRAM_CFG1_PASS_THRU 0x00000004 #define NVRAM_CFG1_STATUS_BITS 0x00000070 #define NVRAM_CFG1_BIT_BANG 0x00000008 #define NVRAM_CFG1_FLASH_SIZE 0x02000000 #define NVRAM_CFG1_COMPAT_BYPASS 0x80000000 #define NVRAM_CFG1_VENDOR_MASK 0x03000003 #define FLASH_VENDOR_ATMEL_EEPROM 0x02000000 #define FLASH_VENDOR_ATMEL_FLASH_BUFFERED 0x02000003 #define FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED 0x00000003 #define FLASH_VENDOR_ST 0x03000001 #define FLASH_VENDOR_SAIFUN 0x01000003 #define FLASH_VENDOR_SST_SMALL 0x00000001 #define FLASH_VENDOR_SST_LARGE 0x02000001 #define NVRAM_CFG1_5752VENDOR_MASK 0x03c00003 #define FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ 0x00000000 #define FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ 0x02000000 #define FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED 0x02000003 #define FLASH_5752VENDOR_ST_M45PE10 0x02400000 #define FLASH_5752VENDOR_ST_M45PE20 0x02400002 #define FLASH_5752VENDOR_ST_M45PE40 0x02400001 #define FLASH_5755VENDOR_ATMEL_FLASH_1 0x03400001 #define FLASH_5755VENDOR_ATMEL_FLASH_2 0x03400002 #define FLASH_5755VENDOR_ATMEL_FLASH_3 0x03400000 #define FLASH_5755VENDOR_ATMEL_FLASH_4 0x00000003 #define FLASH_5755VENDOR_ATMEL_EEPROM_64KHZ 0x03c00003 #define FLASH_5755VENDOR_ATMEL_EEPROM_376KHZ 0x03c00002 #define FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ 0x03000003 #define FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ 0x03000002 #define FLASH_5787VENDOR_MICRO_EEPROM_64KHZ 0x03000000 #define FLASH_5787VENDOR_MICRO_EEPROM_376KHZ 0x02000000 #define NVRAM_CFG1_5752PAGE_SIZE_MASK 0x70000000 #define FLASH_5752PAGE_SIZE_256 0x00000000 #define FLASH_5752PAGE_SIZE_512 0x10000000 #define FLASH_5752PAGE_SIZE_1K 0x20000000 #define FLASH_5752PAGE_SIZE_2K 0x30000000 #define FLASH_5752PAGE_SIZE_4K 0x40000000 #define FLASH_5752PAGE_SIZE_264 0x50000000 #define NVRAM_CFG2 0x00007018 #define NVRAM_CFG3 0x0000701c #define NVRAM_SWARB 0x00007020 #define SWARB_REQ_SET0 0x00000001 #define SWARB_REQ_SET1 0x00000002 #define SWARB_REQ_SET2 0x00000004 #define SWARB_REQ_SET3 0x00000008 #define SWARB_REQ_CLR0 0x00000010 #define SWARB_REQ_CLR1 0x00000020 #define SWARB_REQ_CLR2 0x00000040 #define SWARB_REQ_CLR3 0x00000080 #define SWARB_GNT0 0x00000100 #define SWARB_GNT1 0x00000200 #define SWARB_GNT2 0x00000400 #define SWARB_GNT3 0x00000800 #define SWARB_REQ0 0x00001000 #define SWARB_REQ1 0x00002000 #define SWARB_REQ2 0x00004000 #define SWARB_REQ3 0x00008000 #define NVRAM_ACCESS 0x00007024 #define ACCESS_ENABLE 0x00000001 #define ACCESS_WR_ENABLE 0x00000002 #define NVRAM_WRITE1 0x00007028 /* 0x702c --> 0x7400 unused */ /* 0x7400 --> 0x8000 unused */ #define TG3_EEPROM_MAGIC 0x669955aa /* 32K Window into NIC internal memory */ #define NIC_SRAM_WIN_BASE 0x00008000 /* Offsets into first 32k of NIC internal memory. */ #define NIC_SRAM_PAGE_ZERO 0x00000000 #define NIC_SRAM_SEND_RCB 0x00000100 /* 16 * TG3_BDINFO_... */ #define NIC_SRAM_RCV_RET_RCB 0x00000200 /* 16 * TG3_BDINFO_... */ #define NIC_SRAM_STATS_BLK 0x00000300 #define NIC_SRAM_STATUS_BLK 0x00000b00 #define NIC_SRAM_FIRMWARE_MBOX 0x00000b50 #define NIC_SRAM_FIRMWARE_MBOX_MAGIC1 0x4B657654 #define NIC_SRAM_FIRMWARE_MBOX_MAGIC2 0x4861764b /* !dma on linkchg */ #define NIC_SRAM_DATA_SIG 0x00000b54 #define NIC_SRAM_DATA_SIG_MAGIC 0x4b657654 /* ascii for 'KevT' */ #define NIC_SRAM_DATA_CFG 0x00000b58 #define NIC_SRAM_DATA_CFG_LED_MODE_MASK 0x0000000c #define NIC_SRAM_DATA_CFG_LED_MODE_MAC 0x00000000 #define NIC_SRAM_DATA_CFG_LED_MODE_PHY_1 0x00000004 #define NIC_SRAM_DATA_CFG_LED_MODE_PHY_2 0x00000008 #define NIC_SRAM_DATA_CFG_PHY_TYPE_MASK 0x00000030 #define NIC_SRAM_DATA_CFG_PHY_TYPE_UNKNOWN 0x00000000 #define NIC_SRAM_DATA_CFG_PHY_TYPE_COPPER 0x00000010 #define NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER 0x00000020 #define NIC_SRAM_DATA_CFG_WOL_ENABLE 0x00000040 #define NIC_SRAM_DATA_CFG_ASF_ENABLE 0x00000080 #define NIC_SRAM_DATA_CFG_EEPROM_WP 0x00000100 #define NIC_SRAM_DATA_CFG_MINI_PCI 0x00001000 #define NIC_SRAM_DATA_CFG_FIBER_WOL 0x00004000 #define NIC_SRAM_DATA_CFG_NO_GPIO2 0x00100000 #define NIC_SRAM_DATA_VER 0x00000b5c #define NIC_SRAM_DATA_VER_SHIFT 16 #define NIC_SRAM_DATA_PHY_ID 0x00000b74 #define NIC_SRAM_DATA_PHY_ID1_MASK 0xffff0000 #define NIC_SRAM_DATA_PHY_ID2_MASK 0x0000ffff #define NIC_SRAM_FW_CMD_MBOX 0x00000b78 #define FWCMD_NICDRV_ALIVE 0x00000001 #define FWCMD_NICDRV_PAUSE_FW 0x00000002 #define FWCMD_NICDRV_IPV4ADDR_CHG 0x00000003 #define FWCMD_NICDRV_IPV6ADDR_CHG 0x00000004 #define FWCMD_NICDRV_FIX_DMAR 0x00000005 #define FWCMD_NICDRV_FIX_DMAW 0x00000006 #define FWCMD_NICDRV_ALIVE2 0x0000000d #define NIC_SRAM_FW_CMD_LEN_MBOX 0x00000b7c #define NIC_SRAM_FW_CMD_DATA_MBOX 0x00000b80 #define NIC_SRAM_FW_ASF_STATUS_MBOX 0x00000c00 #define NIC_SRAM_FW_DRV_STATE_MBOX 0x00000c04 #define DRV_STATE_START 0x00000001 #define DRV_STATE_START_DONE 0x80000001 #define DRV_STATE_UNLOAD 0x00000002 #define DRV_STATE_UNLOAD_DONE 0x80000002 #define DRV_STATE_WOL 0x00000003 #define DRV_STATE_SUSPEND 0x00000004 #define NIC_SRAM_FW_RESET_TYPE_MBOX 0x00000c08 #define NIC_SRAM_MAC_ADDR_HIGH_MBOX 0x00000c14 #define NIC_SRAM_MAC_ADDR_LOW_MBOX 0x00000c18 #define NIC_SRAM_WOL_MBOX 0x00000d30 #define WOL_SIGNATURE 0x474c0000 #define WOL_DRV_STATE_SHUTDOWN 0x00000001 #define WOL_DRV_WOL 0x00000002 #define WOL_SET_MAGIC_PKT 0x00000004 #define NIC_SRAM_DATA_CFG_2 0x00000d38 #define SHASTA_EXT_LED_MODE_MASK 0x00018000 #define SHASTA_EXT_LED_LEGACY 0x00000000 #define SHASTA_EXT_LED_SHARED 0x00008000 #define SHASTA_EXT_LED_MAC 0x00010000 #define SHASTA_EXT_LED_COMBO 0x00018000 #define NIC_SRAM_RX_MINI_BUFFER_DESC 0x00001000 #define NIC_SRAM_DMA_DESC_POOL_BASE 0x00002000 #define NIC_SRAM_DMA_DESC_POOL_SIZE 0x00002000 #define NIC_SRAM_TX_BUFFER_DESC 0x00004000 /* 512 entries */ #define NIC_SRAM_RX_BUFFER_DESC 0x00006000 /* 256 entries */ #define NIC_SRAM_RX_JUMBO_BUFFER_DESC 0x00007000 /* 256 entries */ #define NIC_SRAM_MBUF_POOL_BASE 0x00008000 #define NIC_SRAM_MBUF_POOL_SIZE96 0x00018000 #define NIC_SRAM_MBUF_POOL_SIZE64 0x00010000 #define NIC_SRAM_MBUF_POOL_BASE5705 0x00010000 #define NIC_SRAM_MBUF_POOL_SIZE5705 0x0000e000 /* Currently this is fixed. */ #define PHY_ADDR 0x01 /* Tigon3 specific PHY MII registers. */ #define TG3_BMCR_SPEED1000 0x0040 #define MII_TG3_CTRL 0x09 /* 1000-baseT control register */ #define MII_TG3_CTRL_ADV_1000_HALF 0x0100 #define MII_TG3_CTRL_ADV_1000_FULL 0x0200 #define MII_TG3_CTRL_AS_MASTER 0x0800 #define MII_TG3_CTRL_ENABLE_AS_MASTER 0x1000 #define MII_TG3_EXT_CTRL 0x10 /* Extended control register */ #define MII_TG3_EXT_CTRL_FIFO_ELASTIC 0x0001 #define MII_TG3_EXT_CTRL_LNK3_LED_MODE 0x0002 #define MII_TG3_EXT_CTRL_FORCE_LED_OFF 0x0008 #define MII_TG3_EXT_CTRL_TBI 0x8000 #define MII_TG3_EXT_STAT 0x11 /* Extended status register */ #define MII_TG3_EXT_STAT_LPASS 0x0100 #define MII_TG3_DSP_RW_PORT 0x15 /* DSP coefficient read/write port */ #define MII_TG3_DSP_ADDRESS 0x17 /* DSP address register */ #define MII_TG3_AUX_CTRL 0x18 /* auxilliary control register */ #define MII_TG3_AUX_STAT 0x19 /* auxilliary status register */ #define MII_TG3_AUX_STAT_LPASS 0x0004 #define MII_TG3_AUX_STAT_SPDMASK 0x0700 #define MII_TG3_AUX_STAT_10HALF 0x0100 #define MII_TG3_AUX_STAT_10FULL 0x0200 #define MII_TG3_AUX_STAT_100HALF 0x0300 #define MII_TG3_AUX_STAT_100_4 0x0400 #define MII_TG3_AUX_STAT_100FULL 0x0500 #define MII_TG3_AUX_STAT_1000HALF 0x0600 #define MII_TG3_AUX_STAT_1000FULL 0x0700 #define MII_TG3_ISTAT 0x1a /* IRQ status register */ #define MII_TG3_IMASK 0x1b /* IRQ mask register */ /* ISTAT/IMASK event bits */ #define MII_TG3_INT_LINKCHG 0x0002 #define MII_TG3_INT_SPEEDCHG 0x0004 #define MII_TG3_INT_DUPLEXCHG 0x0008 #define MII_TG3_INT_ANEG_PAGE_RX 0x0400 /* There are two ways to manage the TX descriptors on the tigon3. * Either the descriptors are in host DMA'able memory, or they * exist only in the cards on-chip SRAM. All 16 send bds are under * the same mode, they may not be configured individually. * * This driver always uses host memory TX descriptors. * * To use host memory TX descriptors: * 1) Set GRC_MODE_HOST_SENDBDS in GRC_MODE register. * Make sure GRC_MODE_4X_NIC_SEND_RINGS is clear. * 2) Allocate DMA'able memory. * 3) In NIC_SRAM_SEND_RCB (of desired index) of on-chip SRAM: * a) Set TG3_BDINFO_HOST_ADDR to DMA address of memory * obtained in step 2 * b) Set TG3_BDINFO_NIC_ADDR to NIC_SRAM_TX_BUFFER_DESC. * c) Set len field of TG3_BDINFO_MAXLEN_FLAGS to number * of TX descriptors. Leave flags field clear. * 4) Access TX descriptors via host memory. The chip * will refetch into local SRAM as needed when producer