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ted='selected'>pandaboard-litmus LITMUS^RT and MC^2 V0 support for the pandaboard.Christopher Joseph Kenna
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path: root/include/linux/ibmtr.h
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#ifndef __LINUX_IBMTR_H__
#define __LINUX_IBMTR_H__

/* Definitions for an IBM Token Ring card. */
/* This file is distributed under the GNU GPL   */

/* ported to the Alpha architecture 02/20/96 (just used the HZ macro) */

#define TR_RETRY_INTERVAL	(30*HZ)	/* 500 on PC = 5 s */
#define TR_RST_TIME		(msecs_to_jiffies(50))	/* 5 on PC = 50 ms */
#define TR_BUSY_INTERVAL	(msecs_to_jiffies(200))	/* 5 on PC = 200 ms */
#define TR_SPIN_INTERVAL	(3*HZ)	/* 3 seconds before init timeout */

#define TR_ISA 1
#define TR_MCA 2
#define TR_ISAPNP 3
#define NOTOK 0

#define IBMTR_SHARED_RAM_SIZE 0x10000
#define IBMTR_IO_EXTENT 4
#define IBMTR_MAX_ADAPTERS 4

#define CHANNEL_ID      0X1F30
#define AIP             0X1F00
#define AIPADAPTYPE     0X1FA0
#define AIPDATARATE     0X1FA2
#define AIPEARLYTOKEN   0X1FA4
#define AIPAVAILSHRAM   0X1FA6
#define AIPSHRAMPAGE    0X1FA8
#define AIP4MBDHB       0X1FAA
#define AIP16MBDHB      0X1FAC
#define AIPFID		0X1FBA

#define ADAPTRESET      0x1     /* Control Adapter reset (add to base) */
#define ADAPTRESETREL   0x2     /* Release Adapter from reset ( """)  */
#define ADAPTINTREL	0x3 	/* Adapter interrupt release */

#define GLOBAL_INT_ENABLE 0x02f0

/* MMIO bits 0-4 select register */
#define RRR_EVEN       0x00 /* Shared RAM relocation registers - even and odd */
/* Used to set the starting address of shared RAM  */
/* Bits 1 through 7 of this register map to bits 13 through 19 of the shared
   RAM address.*/
/* ie: 0x02 sets RAM address to ...ato!  issy su wazzoo !! GODZILLA!!! */
#define RRR_ODD         0x01
/* Bits 2 and 3 of this register can be read to determine shared RAM size */
/* 00 for 8k, 01 for 16k, 10 for 32k, 11 for 64k  */
#define WRBR_EVEN       0x02    /* Write region base registers - even and odd */
#define WRBR_ODD        0x03
#define WWOR_EVEN       0x04    /* Write window open registers - even and odd */
#define WWOR_ODD        0x05
#define WWCR_EVEN       0x06   /* Write window close registers - even and odd */
#define WWCR_ODD        0x07

/* Interrupt status registers - PC system  - even and odd */