/************************************************************************ * Linux driver for * * ICP vortex GmbH: GDT ISA/EISA/PCI Disk Array Controllers * * Intel Corporation: Storage RAID Controllers * * * * gdth.c * * Copyright (C) 1995-06 ICP vortex GmbH, Achim Leubner * * Copyright (C) 2002-04 Intel Corporation * * Copyright (C) 2003-06 Adaptec Inc. * * * * * * Additions/Fixes: * * Boji Tony Kannanthanam * * Johannes Dinner * * * * This program is free software; you can redistribute it and/or modify * * it under the terms of the GNU General Public License as published * * by the Free Software Foundation; either version 2 of the License, * * or (at your option) any later version. * * * * This program is distributed in the hope that it will be useful, * * but WITHOUT ANY WARRANTY; without even the implied warranty of * * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * * GNU General Public License for more details. * * * * You should have received a copy of the GNU General Public License * * along with this kernel; if not, write to the Free Software * * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. * * * * Linux kernel 2.6.x supported * * * ************************************************************************/ /* All GDT Disk Array Controllers are fully supported by this driver. * This includes the PCI/EISA/ISA SCSI Disk Array Controllers and the * PCI Fibre Channel Disk Array Controllers. See gdth.h for a complete * list of all controller types. * * If you have one or more GDT3000/3020 EISA controllers with * controller BIOS disabled, you have to set the IRQ values with the * command line option "gdth=irq1,irq2,...", where the irq1,irq2,... are * the IRQ values for the EISA controllers. * * After the optional list of IRQ values, other possible * command line options are: * disable:Y disable driver * disable:N enable driver * reserve_mode:0 reserve no drives for the raw service * reserve_mode:1 reserve all not init., removable drives * reserve_mode:2 reserve all not init. drives * reserve_list:h,b,t,l,h,b,t,l,... reserve particular drive(s) with * h- controller no., b- channel no., * t- target ID, l- LUN * reverse_scan:Y reverse scan order for PCI controllers * reverse_scan:N scan PCI controllers like BIOS * max_ids:x x - target ID count per channel (1..MAXID) * rescan:Y rescan all channels/IDs * rescan:N use all devices found until now * hdr_channel:x x - number of virtual bus for host drives * shared_access:Y disable driver reserve/release protocol to * access a shared resource from several nodes, * appropriate controller firmware required * shared_access:N enable driver reserve/release protocol * probe_eisa_isa:Y scan for EISA/ISA controllers * probe_eisa_isa:N do not scan for EISA/ISA controllers * force_dma32:Y use only 32 bit DMA mode * force_dma32:N use 64 bit DMA mode, if supported * * The default values are: "gdth=disable:N,reserve_mode:1,reverse_scan:N, * max_ids:127,rescan:N,hdr_channel:0, * shared_access:Y,probe_eisa_isa:N,force_dma32:N". * Here is another example: "gdth=reserve_list:0,1,2,0,0,1,3,0,rescan:Y". * * When loading the gdth driver as a module, the same options are available. * You can set the IRQs with "IRQ=...". However, the syntax to specify the * options changes slightly. You must replace all ',' between options * with ' ' and all ':' with '=' and you must use * '1' in place of 'Y' and '0' in place of 'N'. * * Default: "modprobe gdth disable=0 reserve_mode=1 reverse_scan=0 * max_ids=127 rescan=0 hdr_channel=0 shared_access=0 * probe_eisa_isa=0 force_dma32=0" * The other example: "modprobe gdth reserve_list=0,1,2,0,0,1,3,0 rescan=1". */ /* The meaning of the Scsi_Pointer members in this driver is as follows: * ptr: Chaining * this_residual: unused * buffer: unused * dma_handle: unused * buffers_residual: unused * Status: unused * Message: unused * have_data_in: unused * sent_command: unused * phase: unused */ /* interrupt coalescing */ /* #define INT_COAL */ /* statistics */ #define GDTH_STATISTICS #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #ifdef GDTH_RTC #include #endif #include #include #include #include #include #include #include #include "scsi.h" #include #include "gdth.h" static DEFINE_MUTEX(gdth_mutex); static void gdth_delay(int milliseconds); static void gdth_eval_mapping(u32 size, u32 *cyls, int *heads, int *secs); static irqreturn_t gdth_interrupt(int irq, void *dev_id); static irqreturn_t __gdth_interrupt(gdth_ha_str *ha, int gdth_from_wait, int* pIndex); static int gdth_sync_event(gdth_ha_str *ha, int service, u8 index, Scsi_Cmnd *scp); static int gdth_async_event(gdth_ha_str *ha); static void gdth_log_event(gdth_evt_data *dvr, char *buffer); static void gdth_putq(gdth_ha_str *ha, Scsi_Cmnd *scp, u8 priority); static void gdth_next(gdth_ha_str *ha); static int gdth_fill_raw_cmd(gdth_ha_str *ha, Scsi_Cmnd *scp, u8 b); static int gdth_special_cmd(gdth_ha_str *ha, Scsi_Cmnd *scp); static gdth_evt_str *gdth_store_event(gdth_ha_str *ha, u16 source, u16 idx, gdth_evt_data *evt); static int gdth_read_event(gdth_ha_str *ha, int handle, gdth_evt_str *estr); static void gdth_readapp_event(gdth_ha_str *ha, u8 application, gdth_evt_str *estr); static void gdth_clear_events(void); static void gdth_copy_internal_data(gdth_ha_str *ha, Scsi_Cmnd *scp, char *buffer, u16 count); static int gdth_internal_cache_cmd(gdth_ha_str *ha, Scsi_Cmnd *scp); static int gdth_fill_cache_cmd(gdth_ha_str *ha, Scsi_Cmnd *scp, u16 hdrive); static void gdth_enable_int(gdth_ha_str *ha); static int gdth_test_busy(gdth_ha_str *ha); static int gdth_get_cmd_index(gdth_ha_str *ha); static void gdth_release_event(gdth_ha_str *ha); static int gdth_wait(gdth_ha_str *ha, int index,u32 time); static int gdth_internal_cmd(gdth_ha_str *ha, u8 service, u16 opcode, u32 p1, u64 p2,u64 p3); static int gdth_search_drives(gdth_ha_str *ha); static int gdth_analyse_hdrive(gdth_ha_str *ha, u16 hdrive); static const char *gdth_ctr_name(gdth_ha_str *ha); static int gdth_open(struct inode *inode, struct file *filep); static int gdth_close(struct inode *inode, struct file *filep); static long gdth_unlocked_ioctl(struct file *filep, unsigned int cmd, unsigned long arg); static void gdth_flush(gdth_ha_str *ha); static int gdth_queuecommand(struct Scsi_Host *h, struct scsi_cmnd *cmd); static int __gdth_queuecommand(gdth_ha_str *ha, struct scsi_cmnd *scp, struct gdth_cmndinfo *cmndinfo); static void gdth_scsi_done(struct scsi_cmnd *scp); #ifdef DEBUG_GDTH static u8 DebugState = DEBUG_GDTH; #ifdef __SERIAL__ #define MAX_SERBUF 160 static void ser_init(void); static void ser_puts(char *str); static void ser_putc(char c); static int ser_printk(const char *fmt, ...); static char strbuf[MAX_SERBUF+1]; #ifdef __COM2__ #define COM_BASE 0x2f8 #else #define COM_BASE 0x3f8 #endif static void ser_init() { unsigned port=COM_BASE; outb(0x80,port+3); outb(0,port+1); /* 19200 Baud, if 9600: outb(12,port) */ outb(6, port); outb(3,port+3); outb(0,port+1); /* ser_putc('I'); ser_putc(' '); */ } static void ser_puts(char *str) { char *ptr; ser_init(); for (ptr=str;*ptr;++ptr) ser_putc(*ptr); } static void ser_putc(char c) { unsigned port=COM_BASE; while ((inb(port+5) & 0x20)==0); outb(c,port); if (c==0x0a) { while ((inb(port+5) & 0x20)==0); outb(0x0d,port); } } static int ser_printk(const char *fmt, ...) { va_list args; int i; va_start(args,fmt); i = vsprintf(strbuf,fmt,args); ser_puts(strbuf); va_end(args); return i; } #define TRACE(a) {if (DebugState==1) {ser_printk a;}} #define TRACE2(a) {if (DebugState==1 || DebugState==2) {ser_printk a;}} #define TRACE3(a) {if (DebugState!=0) {ser_printk a;}} #else /* !__SERIAL__ */ #define TRACE(a) {if (DebugState==1) {printk a;}} #define TRACE2(a) {if (DebugState==1 || DebugState==2) {printk a;}} #define TRACE3(a) {if (DebugState!=0) {printk a;}} #endif #else /* !DEBUG */ #define TRACE(a) #define TRACE2(a) #define TRACE3(a) #endif #ifdef GDTH_STATISTICS static u32 max_rq=0, max_index=0, max_sg=0; #ifdef INT_COAL static u32 max_int_coal=0; #endif static u32 act_ints=0, act_ios=0, act_stats=0, act_rq=0; static struct timer_list gdth_timer; #endif #define PTR2USHORT(a) (u16)(unsigned long)(a) #define GDTOFFSOF(a,b) (size_t)&(((a*)0)->b) #define INDEX_OK(i,t) ((i)(a)->virt_bus ? (b-1):(b)) #ifdef CONFIG_ISA static u8 gdth_drq_tab[4] = {5,6,7,7}; /* DRQ table */ #endif #if defined(CONFIG_EISA) || defined(CONFIG_ISA) static u8 gdth_irq_tab[6] = {0,10,11,12,14,0}; /* IRQ table */ #endif static u8 gdth_polling; /* polling if TRUE */ static int gdth_ctr_count = 0; /* controller count */ static LIST_HEAD(gdth_instances); /* controller list */ static u8 gdth_write_through = FALSE; /* write through */ static gdth_evt_str ebuffer[MAX_EVENTS]; /* event buffer */ static int elastidx; static int eoldidx; static int major; #define DIN 1 /* IN data direction */ #define DOU 2 /* OUT data direction */ #define DNO DIN /* no data transfer */ #define DUN DIN /* unknown data direction */ static u8 gdth_direction_tab[0x100] = { DNO,DNO,DIN,DIN,DOU,DIN,DIN,DOU,DIN,DUN,DOU,DOU,DUN,DUN,DUN,DIN, DNO,DIN,DIN,DOU,DIN,DOU,DNO,DNO,DOU,DNO,DIN,DNO,DIN,DOU,DNO,DUN, DIN,DUN,DIN,DUN,DOU,DIN,DUN,DUN,DIN,DIN,DOU,DNO,DUN,DIN,DOU,DOU, DOU,DOU,DOU,DNO,DIN,DNO,DNO,DIN,DOU,DOU,DOU,DOU,DIN,DOU,DIN,DOU, DOU,DOU,DIN,DIN,DIN,DNO,DUN,DNO,DNO,DNO,DUN,DNO,DOU,DIN,DUN,DUN, DUN,DUN,DUN,DUN,DUN,DOU,DUN,DUN,DUN,DUN,DIN,DUN,DUN,DUN,DUN,DUN, DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN, DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN, DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DIN,DUN,DOU,DUN,DUN,DUN,DUN,DUN, DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DIN,DUN, DUN,DUN,DUN,DUN,DUN,DNO,DNO,DUN,DIN,DNO,DOU,DUN,DNO,DUN,DOU,DOU, DOU,DOU,DOU,DNO,DUN,DIN,DOU,DIN,DIN,DUN,DUN,DUN,DUN,DUN,DUN,DUN, DUN,DUN,DOU,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN, DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN, DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DOU,DUN,DUN,DUN,DUN,DUN, DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN }; /* LILO and modprobe/insmod parameters */ /* IRQ list for GDT3000/3020 EISA controllers */ static int irq[MAXHA] __initdata = {0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff}; /* disable driver flag */ static int disable __initdata = 0; /* reserve flag */ static int reserve_mode = 1; /* reserve list */ static int reserve_list[MAX_RES_ARGS] = {0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff}; /* scan order for PCI controllers */ static int reverse_scan = 0; /* virtual channel for the host drives */ static int hdr_channel = 0; /* max. IDs per channel */ static int max_ids = MAXID; /* rescan all IDs */ static int rescan = 0; /* shared access */ static int shared_access = 1; /* enable support for EISA and ISA controllers */ static int probe_eisa_isa = 0; /* 64 bit DMA mode, support for drives > 2 TB, if force_dma32 = 0 */ static int force_dma32 = 0; /* parameters for modprobe/insmod */ module_param_array(irq, int, NULL, 0); module_param(disable, int, 0); module_param(reserve_mode, int, 0); module_param_array(reserve_list, int, NULL, 0); module_param(reverse_scan, int, 0); module_param(hdr_channel, int, 0); module_param(max_ids, int, 0); module_param(rescan, int, 0); module_param(shared_access, int, 0); module_param(probe_eisa_isa, int, 0); module_param(force_dma32, int, 0); MODULE_AUTHOR("Achim Leubner"); MODULE_LICENSE("GPL"); /* ioctl interface */ static const struct file_operations gdth_fops = { .unlocked_ioctl = gdth_unlocked_ioctl, .open = gdth_open, .release = gdth_close, .llseek = noop_llseek, }; #include "gdth_proc.h" #include "gdth_proc.c" static gdth_ha_str *gdth_find_ha(int hanum) { gdth_ha_str *ha; list_for_each_entry(ha, &gdth_instances, list) if (hanum == ha->hanum) return ha; return NULL; } static struct gdth_cmndinfo *gdth_get_cmndinfo(gdth_ha_str *ha) { struct gdth_cmndinfo *priv = NULL; unsigned long flags; int i; spin_lock_irqsave(&ha->smp_lock, flags); for (i=0; icmndinfo[i].index == 0) { priv = &ha->cmndinfo[i]; memset(priv, 0, sizeof(*priv)); priv->index = i+1; break; } } spin_unlock_irqrestore(&ha->smp_lock, flags); return priv; } static void gdth_put_cmndinfo(struct gdth_cmndinfo *priv) { BUG_ON(!priv); priv->index = 0; } static void gdth_delay(int milliseconds) { if (milliseconds == 0) { udelay(1); } else { mdelay(milliseconds); } } static void gdth_scsi_done(struct scsi_cmnd *scp) { struct gdth_cmndinfo *cmndinfo = gdth_cmnd_priv(scp); int internal_command = cmndinfo->internal_command; TRACE2(("gdth_scsi_done()\n")); gdth_put_cmndinfo(cmndinfo); scp->host_scribble = NULL; if (internal_command) complete((struct completion *)scp->request); else scp->scsi_done(scp); } int __gdth_execute(struct scsi_device *sdev, gdth_cmd_str *gdtcmd, char *cmnd, int timeout, u32 *info) { gdth_ha_str *ha = shost_priv(sdev->host); Scsi_Cmnd *scp; struct gdth_cmndinfo cmndinfo; DECLARE_COMPLETION_ONSTACK(wait); int rval; scp = kzalloc(sizeof(*scp), GFP_KERNEL); if (!scp) return -ENOMEM; scp->sense_buffer = kzalloc(SCSI_SENSE_BUFFERSIZE, GFP_KERNEL); if (!scp->sense_buffer) { kfree(scp); return -ENOMEM; } scp->device = sdev; memset(&cmndinfo, 0, sizeof(cmndinfo)); /* use request field to save the ptr. to completion struct. */ scp->request = (struct request *)&wait; scp->cmd_len = 12; scp->cmnd = cmnd; cmndinfo.priority = IOCTL_PRI; cmndinfo.internal_cmd_str = gdtcmd; cmndinfo.internal_command = 1; TRACE(("__gdth_execute() cmd 0x%x\n", scp->cmnd[0])); __gdth_queuecommand(ha, scp, &cmndinfo); wait_for_completion(&wait); rval = cmndinfo.status; if (info) *info = cmndinfo.info; kfree(scp->sense_buffer); kfree(scp); return rval; } int gdth_execute(struct Scsi_Host *shost, gdth_cmd_str *gdtcmd, char *cmnd, int timeout, u32 *info) { struct scsi_device *sdev = scsi_get_host_dev(shost); int rval = __gdth_execute(sdev, gdtcmd, cmnd, timeout, info); scsi_free_host_dev(sdev); return rval; } static void gdth_eval_mapping(u32 size, u32 *cyls, int *heads, int *secs) { *cyls = size /HEADS/SECS; if (*cyls <= MAXCYLS) { *heads = HEADS; *secs = SECS; } else { /* too high for 64*32 */ *cyls = size /MEDHEADS/MEDSECS; if (*cyls <= MAXCYLS) { *heads = MEDHEADS; *secs = MEDSECS; } else { /* too high for 127*63 */ *cyls = size /BIGHEADS/BIGSECS; *heads = BIGHEADS; *secs = BIGSECS; } } } /* controller search and initialization functions */ #ifdef CONFIG_EISA static int __init gdth_search_eisa(u16 eisa_adr) { u32 id; TRACE(("gdth_search_eisa() adr. %x\n",eisa_adr)); id = inl(eisa_adr+ID0REG); if (id == GDT3A_ID || id == GDT3B_ID) { /* GDT3000A or GDT3000B */ if ((inb(eisa_adr+EISAREG) & 8) == 0) return 0; /* not EISA configured */ return 1; } if (id == GDT3_ID) /* GDT3000 */ return 1; return 0; } #endif /* CONFIG_EISA */ #ifdef CONFIG_ISA static int __init gdth_search_isa(u32 bios_adr) { void __iomem *addr; u32 id; TRACE(("gdth_search_isa() bios adr. %x\n",bios_adr)); if ((addr = ioremap(bios_adr+BIOS_ID_OFFS, sizeof(u32))) != NULL) { id = readl(addr); iounmap(addr); if (id == GDT2_ID) /* GDT2000 */ return 1; } return 0; } #endif /* CONFIG_ISA */ #ifdef CONFIG_PCI static bool gdth_search_vortex(u16 device) { if (device <= PCI_DEVICE_ID_VORTEX_GDT6555) return true; if (device >= PCI_DEVICE_ID_VORTEX_GDT6x17RP && device <= PCI_DEVICE_ID_VORTEX_GDTMAXRP) return true; if (device == PCI_DEVICE_ID_VORTEX_GDTNEWRX || device == PCI_DEVICE_ID_VORTEX_GDTNEWRX2) return true; return false; } static int gdth_pci_probe_one(gdth_pci_str *pcistr, gdth_ha_str **ha_out); static int gdth_pci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent); static void gdth_pci_remove_one(struct pci_dev *pdev); static void gdth_remove_one(gdth_ha_str *ha); /* Vortex only makes RAID controllers. * We do not really want to specify all 550 ids here, so wildcard match. */ static const struct pci_device_id gdthtable[] = { { PCI_VDEVICE(VORTEX, PCI_ANY_ID) }, { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_SRC) }, { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_SRC_XSCALE) }, { } /* terminate list */ }; MODULE_DEVICE_TABLE(pci, gdthtable); static struct pci_driver gdth_pci_driver = { .name = "gdth", .id_table = gdthtable, .probe = gdth_pci_init_one, .remove = gdth_pci_remove_one, }; static void gdth_pci_remove_one(struct pci_dev *pdev) { gdth_ha_str *ha = pci_get_drvdata(pdev); list_del(&ha->list); gdth_remove_one(ha); pci_disable_device(pdev); } static int gdth_pci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) { u16 vendor = pdev->vendor; u16 device = pdev->device; unsigned long base0, base1, base2; int rc; gdth_pci_str gdth_pcistr; gdth_ha_str *ha = NULL; TRACE(("gdth_search_dev() cnt %d vendor %x device %x\n", gdth_ctr_count, vendor, device)); memset(&gdth_pcistr, 0, sizeof(gdth_pcistr)); if (vendor == PCI_VENDOR_ID_VORTEX && !gdth_search_vortex(device)) return -ENODEV; rc = pci_enable_device(pdev); if (rc) return rc; if (gdth_ctr_count >= MAXHA) return -EBUSY; /* GDT PCI controller found, resources are already in pdev */ gdth_pcistr.pdev = pdev; base0 = pci_resource_flags(pdev, 0); base1 = pci_resource_flags(pdev, 1); base2 = pci_resource_flags(pdev, 2); if (device <= PCI_DEVICE_ID_VORTEX_GDT6000B || /* GDT6000/B */ device >= PCI_DEVICE_ID_VORTEX_GDT6x17RP) { /* MPR */ if (!(base0 & IORESOURCE_MEM)) return -ENODEV; gdth_pcistr.dpmem = pci_resource_start(pdev, 0); } else { /* GDT6110, GDT6120, .. */ if (!(base0 & IORESOURCE_MEM) || !(base2 & IORESOURCE_MEM) || !(base1 & IORESOURCE_IO)) return -ENODEV; gdth_pcistr.dpmem = pci_resource_start(pdev, 2); gdth_pcistr.io = pci_resource_start(pdev, 1); } TRACE2(("Controller found at %d/%d, irq %d, dpmem 0x%lx\n", gdth_pcistr.pdev->bus->number, PCI_SLOT(gdth_pcistr.pdev->devfn), gdth_pcistr.irq, gdth_pcistr.dpmem)); rc = gdth_pci_probe_one(&gdth_pcistr, &ha); if (rc) return rc; return 0; } #endif /* CONFIG_PCI */ #ifdef CONFIG_EISA static int __init gdth_init_eisa(u16 eisa_adr,gdth_ha_str *ha) { u32 retries,id; u8 prot_ver,eisacf,i,irq_found; TRACE(("gdth_init_eisa() adr. %x\n",eisa_adr)); /* disable board interrupts, deinitialize services */ outb(0xff,eisa_adr+EDOORREG); outb(0x00,eisa_adr+EDENABREG); outb(0x00,eisa_adr+EINTENABREG); outb(0xff,eisa_adr+LDOORREG); retries = INIT_RETRIES; gdth_delay(20); while (inb(eisa_adr+EDOORREG) != 0xff) { if (--retries == 0) { printk("GDT-EISA: Initialization error (DEINIT failed)\n"); return 0; } gdth_delay(1); TRACE2(("wait for DEINIT: retries=%d\n",retries)); } prot_ver = inb(eisa_adr+MAILBOXREG); outb(0xff,eisa_adr+EDOORREG); if (prot_ver != PROTOCOL_VERSION) { printk("GDT-EISA: Illegal protocol version\n"); return 0; } ha->bmic = eisa_adr; ha->brd_phys = (u32)eisa_adr >> 12; outl(0,eisa_adr+MAILBOXREG); outl(0,eisa_adr+MAILBOXREG+4); outl(0,eisa_adr+MAILBOXREG+8); outl(0,eisa_adr+MAILBOXREG+12); /* detect IRQ */ if ((id = inl(eisa_adr+ID0REG)) == GDT3_ID) { ha->oem_id = OEM_ID_ICP; ha->type = GDT_EISA; ha->stype = id; outl(1,eisa_adr+MAILBOXREG+8); outb(0xfe,eisa_adr+LDOORREG); retries = INIT_RETRIES; gdth_delay(20); while (inb(eisa_adr+EDOORREG) != 0xfe) { if (--retries == 0) { printk("GDT-EISA: Initialization error (get IRQ failed)\n"); return 0; } gdth_delay(1); } ha->irq = inb(eisa_adr+MAILBOXREG); outb(0xff,eisa_adr+EDOORREG); TRACE2(("GDT3000/3020: IRQ=%d\n",ha->irq)); /* check the result */ if (ha->irq == 0) { TRACE2(("Unknown IRQ, use IRQ table from cmd line !\n")); for (i = 0, irq_found = FALSE; i < MAXHA && irq[i] != 0xff; ++i) { if (irq[i]==10 || irq[i]==11 || irq[i]==12 || irq[i]==14) { irq_found = TRUE; break; } } if (irq_found) { ha->irq = irq[i]; irq[i] = 0; printk("GDT-EISA: Can not detect controller IRQ,\n"); printk("Use IRQ setting from command line (IRQ = %d)\n", ha->irq); } else { printk("GDT-EISA: Initialization error (unknown IRQ), Enable\n"); printk("the controller BIOS or use command line parameters\n"); return 0; } } } else { eisacf = inb(eisa_adr+EISAREG) & 7; if (eisacf > 4) /* level triggered */ eisacf -= 4; ha->irq = gdth_irq_tab[eisacf]; ha->oem_id = OEM_ID_ICP; ha->type = GDT_EISA; ha->stype = id; } ha->dma64_support = 0; return 1; } #endif /* CONFIG_EISA */ #ifdef CONFIG_ISA static int __init gdth_init_isa(u32 bios_adr,gdth_ha_str *ha) { register gdt2_dpram_str __iomem *dp2_ptr; int i; u8 irq_drq,prot_ver; u32 retries; TRACE(("gdth_init_isa() bios adr. %x\n",bios_adr)); ha->brd = ioremap(bios_adr, sizeof(gdt2_dpram_str)); if (ha->brd == NULL) { printk("GDT-ISA: Initialization error (DPMEM remap error)\n"); return 0; } dp2_ptr = ha->brd; writeb(1, &dp2_ptr->io.memlock); /* switch off write protection */ /* reset interface area */ memset_io(&dp2_ptr->u, 0, sizeof(dp2_ptr->u)); if (readl(&dp2_ptr->u) != 0) { printk("GDT-ISA: Initialization error (DPMEM write error)\n"); iounmap(ha->brd); return 0; } /* disable board interrupts, read DRQ and IRQ */ writeb(0xff, &dp2_ptr->io.irqdel); writeb(0x00, &dp2_ptr->io.irqen); writeb(0x00, &dp2_ptr->u.ic.S_Status); writeb(0x00, &dp2_ptr->u.ic.Cmd_Index); irq_drq = readb(&dp2_ptr->io.rq); for (i=0; i<3; ++i) { if ((irq_drq & 1)==0) break; irq_drq >>= 1; } ha->drq = gdth_drq_tab[i]; irq_drq = readb(&dp2_ptr->io.rq) >> 3; for (i=1; i<5; ++i) { if ((irq_drq & 1)==0) break; irq_drq >>= 1; } ha->irq = gdth_irq_tab[i]; /* deinitialize services */ writel(bios_adr, &dp2_ptr->u.ic.S_Info[0]); writeb(0xff, &dp2_ptr->u.ic.S_Cmd_Indx); writeb(0, &dp2_ptr->io.event); retries = INIT_RETRIES; gdth_delay(20); while (readb(&dp2_ptr->u.ic.S_Status) != 0xff) { if (--retries == 0) { printk("GDT-ISA: Initialization error (DEINIT failed)\n"); iounmap(ha->brd); return 0; } gdth_delay(1); } prot_ver = (u8)readl(&dp2_ptr->u.ic.S_Info[0]); writeb(0, &dp2_ptr->u.ic.Status); writeb(0xff, &dp2_ptr->io.irqdel); if (prot_ver != PROTOCOL_VERSION) { printk("GDT-ISA: Illegal protocol version\n"); iounmap(ha->brd); return 0; } ha->oem_id = OEM_ID_ICP; ha->type = GDT_ISA; ha->ic_all_size = sizeof(dp2_ptr->u); ha->stype= GDT2_ID; ha->brd_phys = bios_adr >> 4; /* special request to controller BIOS */ writel(0x00, &dp2_ptr->u.ic.S_Info[0]); writel(0x00, &dp2_ptr->u.ic.S_Info[1]); writel(0x01, &dp2_ptr->u.ic.S_Info[2]); writel(0x00, &dp2_ptr->u.ic.S_Info[3]); writeb(0xfe, &dp2_ptr->u.ic.S_Cmd_Indx); writeb(0, &dp2_ptr->io.event); retries = INIT_RETRIES; gdth_delay(20); while (readb(&dp2_ptr->u.ic.S_Status) != 0xfe) { if (--retries == 0) { printk("GDT-ISA: Initialization error\n"); iounmap(ha->brd); return 0; } gdth_delay(1); } writeb(0, &dp2_ptr->u.ic.Status); writeb(0xff, &dp2_ptr->io.irqdel); ha->dma64_support = 0; return 1; } #endif /* CONFIG_ISA */ #ifdef CONFIG_PCI static int gdth_init_pci(struct pci_dev *pdev, gdth_pci_str *pcistr, gdth_ha_str *ha) { register gdt6_dpram_str __iomem *dp6_ptr; register gdt6c_dpram_str __iomem *dp6c_ptr; register gdt6m_dpram_str __iomem *dp6m_ptr; u32 retries; u8 prot_ver; u16 command; int i, found = FALSE; TRACE(("gdth_init_pci()\n")); if (pdev->vendor == PCI_VENDOR_ID_INTEL) ha->oem_id = OEM_ID_INTEL; else ha->oem_id = OEM_ID_ICP; ha->brd_phys = (pdev->bus->number << 8) | (pdev->devfn & 0xf8); ha->stype = (u32)pdev->device; ha->irq = pdev->irq; ha->pdev = pdev; if (ha->pdev->device <= PCI_DEVICE_ID_VORTEX_GDT6000B) { /* GDT6000/B */ TRACE2(("init_pci() dpmem %lx irq %d\n",pcistr->dpmem,ha->irq)); ha->brd = ioremap(pcistr->dpmem, sizeof(gdt6_dpram_str)); if (ha->brd == NULL) { printk("GDT-PCI: Initialization error (DPMEM remap error)\n"); return 0; } /* check and reset interface area */ dp6_ptr = ha->brd; writel(DPMEM_MAGIC, &dp6_ptr->u); if (readl(&dp6_ptr->u) != DPMEM_MAGIC) { printk("GDT-PCI: Cannot access DPMEM at 0x%lx (shadowed?)\n", pcistr->dpmem); found = FALSE; for (i = 0xC8000; i < 0xE8000; i += 0x4000) { iounmap(ha->brd); ha->brd = ioremap(i, sizeof(u16)); if (ha->brd == NULL) { printk("GDT-PCI: Initialization error (DPMEM remap error)\n"); return 0; } if (readw(ha->brd) != 0xffff) { TRACE2(("init_pci_old() address 0x%x busy\n", i)); continue; } iounmap(ha->brd); pci_write_config_dword(pdev, PCI_BASE_ADDRESS_0, i); ha->brd = ioremap(i, sizeof(gdt6_dpram_str)); if (ha->brd == NULL) { printk("GDT-PCI: Initialization error (DPMEM remap error)\n"); return 0; } dp6_ptr = ha->brd; writel(DPMEM_MAGIC, &dp6_ptr->u); if (readl(&dp6_ptr->u) == DPMEM_MAGIC) { printk("GDT-PCI: Use free address at 0x%x\n", i); found = TRUE; break; } } if (!found) { printk("GDT-PCI: No free address found!\n"); iounmap(ha->brd); return 0; } } memset_io(&dp6_ptr->u, 0, sizeof(dp6_ptr->u)); if (readl(&dp6_ptr->u) != 0) { printk("GDT-PCI: Initialization error (DPMEM write error)\n"); iounmap(ha->brd); return 0; } /* disable board interrupts, deinit services */ writeb(0xff, &dp6_ptr->io.irqdel); writeb(0x00, &dp6_ptr->io.irqen); writeb(0x00, &dp6_ptr->u.ic.S_Status); writeb(0x00, &dp6_ptr->u.ic.Cmd_Index); writel(pcistr->dpmem, &dp6_ptr->u.ic.S_Info[0]); writeb(0xff, &dp6_ptr->u.ic.S_Cmd_Indx); writeb(0, &dp6_ptr->io.event); retries = INIT_RETRIES; gdth_delay(20); while (readb(&dp6_ptr->u.ic.S_Status) != 0xff) { if (--retries == 0) { printk("GDT-PCI: Initialization error (DEINIT failed)\n"); iounmap(ha->brd); return 0; } gdth_delay(1); } prot_ver = (u8)readl(&dp6_ptr->u.ic.S_Info[0]); writeb(0, &dp6_ptr->u.ic.S_Status); writeb(0xff, &dp6_ptr->io.irqdel); if (prot_ver != PROTOCOL_VERSION) { printk("GDT-PCI: Illegal protocol version\n"); iounmap(ha->brd); return 0; } ha->type = GDT_PCI; ha->ic_all_size = sizeof(dp6_ptr->u); /* special command to controller BIOS */ writel(0x00, &dp6_ptr->u.ic.S_Info[0]); writel(0x00, &dp6_ptr->u.ic.S_Info[1]); writel(0x00, &dp6_ptr->u.ic.S_Info[2]); writel(0x00, &dp6_ptr->u.ic.S_Info[3]); writeb(0xfe, &dp6_ptr->u.ic.S_Cmd_Indx); writeb(0, &dp6_ptr->io.event); retries = INIT_RETRIES; gdth_delay(20); while (readb(&dp6_ptr->u.ic.S_Status) != 0xfe) { if (--retries == 0) { printk("GDT-PCI: Initialization error\n"); iounmap(ha->brd); return 0; } gdth_delay(1); } writeb(0, &dp6_ptr->u.ic.S_Status); writeb(0xff, &dp6_ptr->io.irqdel); ha->dma64_support = 0; } else if (ha->pdev->device <= PCI_DEVICE_ID_VORTEX_GDT6555) { /* GDT6110, ... */ ha->plx = (gdt6c_plx_regs *)pcistr->io; TRACE2(("init_pci_new() dpmem %lx irq %d\n", pcistr->dpmem,ha->irq)); ha->brd = ioremap(pcistr->dpmem, sizeof(gdt6c_dpram_str)); if (ha->brd == NULL) { printk("GDT-PCI: Initialization error (DPMEM remap error)\n"); iounmap(ha->brd); return 0; } /* check and reset interface area */ dp6c_ptr = ha->brd; writel(DPMEM_MAGIC, &dp6c_ptr->u); if (readl(&dp6c_ptr->u) != DPMEM_MAGIC) { printk("GDT-PCI: Cannot access DPMEM at 0x%lx (shadowed?)\n", pcistr->dpmem); found = FALSE; for (i = 0xC8000; i < 0xE8000; i += 0x4000) { iounmap(ha->brd); ha->brd = ioremap(i, sizeof(u16)); if (ha->brd == NULL) { printk("GDT-PCI: Initialization error (DPMEM remap error)\n"); return 0; } if (readw(ha->brd) != 0xffff) { TRACE2(("init_pci_plx() address 0x%x busy\n", i)); continue; } iounmap(ha->brd); pci_write_config_dword(pdev, PCI_BASE_ADDRESS_2, i); ha->brd = ioremap(i, sizeof(gdt6c_dpram_str)); if (ha->brd == NULL) { printk("GDT-PCI: Initialization error (DPMEM remap error)\n"); return 0; } dp6c_ptr = ha->brd; writel(DPMEM_MAGIC, &dp6c_ptr->u); if (readl(&dp6c_ptr->u) == DPMEM_MAGIC) { printk("GDT-PCI: Use free address at 0x%x\n", i); found = TRUE; break; } } if (!found) { printk("GDT-PCI: No free address found!\n"); iounmap(ha->brd); return 0; } } memset_io(&dp6c_ptr->u, 0, sizeof(dp6c_ptr->u)); if (readl(&dp6c_ptr->u) != 0) { printk("GDT-PCI: Initialization error (DPMEM write error)\n"); iounmap(ha->brd); return 0; } /* disable board interrupts, deinit services */ outb(0x00,PTR2USHORT(&ha->plx->control1)); outb(0xff,PTR2USHORT(&ha->plx->edoor_reg)); writeb(0x00, &dp6c_ptr->u.ic.S_Status); writeb(0x00, &dp6c_ptr->u.ic.Cmd_Index); writel(pcistr->dpmem, &dp6c_ptr->u.ic.S_Info[0]); writeb(0xff, &dp6c_ptr->u.ic.S_Cmd_Indx); outb(1,PTR2USHORT(&ha->plx->ldoor_reg)); retries = INIT_RETRIES; gdth_delay(20); while (readb(&dp6c_ptr->u.ic.S_Status) != 0xff) { if (--retries == 0) { printk("GDT-PCI: Initialization error (DEINIT failed)\n"); iounmap(ha->brd); return 0; } gdth_delay(1); } prot_ver = (u8)readl(&dp6c_ptr->u.ic.S_Info[0]); writeb(0, &dp6c_ptr->u.ic.Status); if (prot_ver != PROTOCOL_VERSION) { printk("GDT-PCI: Illegal protocol version\n"); iounmap(ha->brd); return 0; } ha->type = GDT_PCINEW; ha->ic_all_size = sizeof(dp6c_ptr->u); /* special command to controller BIOS */ writel(0x00, &dp6c_ptr->u.ic.S_Info[0]); writel(0x00, &dp6c_ptr->u.ic.S_Info[1]); writel(0x00, &dp6c_ptr->u.ic.S_Info[2]); writel(0x00, &dp6c_ptr->u.ic.S_Info[3]); writeb(0xfe, &dp6c_ptr->u.ic.S_Cmd_Indx); outb(1,PTR2USHORT(&ha->plx->ldoor_reg)); retries = INIT_RETRIES; gdth_delay(20); while (readb(&dp6c_ptr->u.ic.S_Status) != 0xfe) { if (--retries == 0) { printk("GDT-PCI: Initialization error\n"); iounmap(ha->brd); return 0; } gdth_delay(1); } writeb(0, &dp6c_ptr->u.ic.S_Status); ha->dma64_support = 0; } else { /* MPR */ TRACE2(("init_pci_mpr() dpmem %lx irq %d\n",pcistr->dpmem,ha->irq)); ha->brd = ioremap(pcistr->dpmem, sizeof(gdt6m_dpram_str)); if (ha->brd == NULL) { printk("GDT-PCI: Initialization error (DPMEM remap error)\n"); return 0; } /* manipulate config. space to enable DPMEM, start RP controller */ pci_read_config_word(pdev, PCI_COMMAND, &command); command |= 6; pci_write_config_word(pdev, PCI_COMMAND, command); gdth_delay(1); dp6m_ptr = ha->brd; /* Ensure that it is safe to access the non HW portions of DPMEM. * Aditional check needed for Xscale based RAID controllers */ while( ((int)readb(&dp6m_ptr->i960r.sema0_reg) ) & 3 ) gdth_delay(1); /* check and reset interface area */ writel(DPMEM_MAGIC, &dp6m_ptr->u); if (readl(&dp6m_ptr->u) != DPMEM_MAGIC) { printk("GDT-PCI: Cannot access DPMEM at 0x%lx (shadowed?)\n", pcistr->dpmem); found = FALSE; for (i = 0xC8000; i < 0xE8000; i += 0x4000) { iounmap(ha->brd); ha->brd = ioremap(i, sizeof(u16)); if (ha->brd == NULL) { printk("GDT-PCI: Initialization error (DPMEM remap error)\n"); return 0; } if (readw(ha->brd) != 0xffff) { TRACE2(("init_pci_mpr() address 0x%x busy\n", i)); continue; } iounmap(ha->brd); pci_write_config_dword(pdev, PCI_BASE_ADDRESS_0, i); ha->brd = ioremap(i, sizeof(gdt6m_dpram_str)); if (ha->brd == NULL) { printk("GDT-PCI: Initialization error (DPMEM remap error)\n"); return 0; } dp6m_ptr = ha->brd; writel(DPMEM_MAGIC, &dp6m_ptr->u); if (readl(&dp6m_ptr->u) == DPMEM_MAGIC) { printk("GDT-PCI: Use free address at 0x%x\n", i); found = TRUE; break; } } if (!found) { printk("GDT-PCI: No free address found!\n"); iounmap(ha->brd); return 0; } } memset_io(&dp6m_ptr->u, 0, sizeof(dp6m_ptr->u)); /* disable board interrupts, deinit services */ writeb(readb(&dp6m_ptr->i960r.edoor_en_reg) | 4, &dp6m_ptr->i960r.edoor_en_reg); writeb(0xff, &dp6m_ptr->i960r.edoor_reg); writeb(0x00, &dp6m_ptr->u.ic.S_Status); writeb(0x00, &dp6m_ptr->u.ic.Cmd_Index); writel(pcistr->dpmem, &dp6m_ptr->u.ic.S_Info[0]); writeb(0xff, &dp6m_ptr->u.ic.S_Cmd_Indx); writeb(1, &dp6m_ptr->i960r.ldoor_reg); retries = INIT_RETRIES; gdth_delay(20); while (readb(&dp6m_ptr->u.ic.S_Status) != 0xff) { if (--retries == 0) { printk("GDT-PCI: Initialization error (DEINIT failed)\n"); iounmap(ha->brd); return 0; } gdth_delay(1); } prot_ver = (u8)readl(&dp6m_ptr->u.ic.S_Info[0]); writeb(0, &dp6m_ptr->u.ic.S_Status); if (prot_ver != PROTOCOL_VERSION) { printk("GDT-PCI: Illegal protocol version\n"); iounmap(ha->brd); return 0; } ha->type = GDT_PCIMPR; ha->ic_all_size = sizeof(dp6m_ptr->u); /* special command to controller BIOS */ writel(0x00, &dp6m_ptr->u.ic.S_Info[0]); writel(0x00, &dp6m_ptr->u.ic.S_Info[1]); writel(0x00, &dp6m_ptr->u.ic.S_Info[2]); writel(0x00, &dp6m_ptr->u.ic.S_Info[3]); writeb(0xfe, &dp6m_ptr->u.ic.S_Cmd_Indx); writeb(1, &dp6m_ptr->i960r.ldoor_reg); retries = INIT_RETRIES; gdth_delay(20); while (readb(&dp6m_ptr->u.ic.S_Status) != 0xfe) { if (--retries == 0) { printk("GDT-PCI: Initialization error\n"); iounmap(ha->brd); return 0; } gdth_delay(1); } writeb(0, &dp6m_ptr->u.ic.S_Status); /* read FW version to detect 64-bit DMA support */ writeb(0xfd, &dp6m_ptr->u.ic.S_Cmd_Indx); writeb(1, &dp6m_ptr->i960r.ldoor_reg); retries = INIT_RETRIES; gdth_delay(20); while (readb(&dp6m_ptr->u.ic.S_Status) != 0xfd) { if (--retries == 0) { printk("GDT-PCI: Initialization error (DEINIT failed)\n"); iounmap(ha->brd); return 0; } gdth_delay(1); } prot_ver = (u8)(readl(&dp6m_ptr->u.ic.S_Info[0]) >> 16); writeb(0, &dp6m_ptr->u.ic.S_Status); if (prot_ver < 0x2b) /* FW < x.43: no 64-bit DMA support */ ha->dma64_support = 0; else ha->dma64_support = 1; } return 1; } #endif /* CONFIG_PCI */ /* controller protocol functions */ static void gdth_enable_int(gdth_ha_str *ha) { unsigned long flags; gdt2_dpram_str __iomem *dp2_ptr; gdt6_dpram_str __iomem *dp6_ptr; gdt6m_dpram_str __iomem *dp6m_ptr; TRACE(("gdth_enable_int() hanum %d\n",ha->hanum)); spin_lock_irqsave(&ha->smp_lock, flags); if (ha->type == GDT_EISA) { outb(0xff, ha->bmic + EDOORREG); outb(0xff, ha->bmic + EDENABREG); outb(0x01, ha->bmic + EINTENABREG); } else if (ha->type == GDT_ISA) { dp2_ptr = ha->brd; writeb(1, &dp2_ptr->io.irqdel); writeb(0, &dp2_ptr->u.ic.Cmd_Index); writeb(1, &dp2_ptr->io.irqen); } else if (ha->type == GDT_PCI) { dp6_ptr = ha->brd; writeb(1, &dp6_ptr->io.irqdel); writeb(0, &dp6_ptr->u.ic.Cmd_Index); writeb(1, &dp6_ptr->io.irqen); } else if (ha->type == GDT_PCINEW) { outb(0xff, PTR2USHORT(&ha->plx->edoor_reg)); outb(0x03, PTR2USHORT(&ha->plx->control1)); } else if (ha->type == GDT_PCIMPR) { dp6m_ptr = ha->brd; writeb(0xff, &dp6m_ptr->i960r.edoor_reg); writeb(readb(&dp6m_ptr->i960r.edoor_en_reg) & ~4, &dp6m_ptr->i960r.edoor_en_reg); } spin_unlock_irqrestore(&ha->smp_lock, flags); } /* return IStatus if interrupt was from this card else 0 */ static u8 gdth_get_status(gdth_ha_str *ha) { u8 IStatus = 0; TRACE(("gdth_get_status() irq %d ctr_count %d\n", ha->irq, gdth_ctr_count)); if (ha->type == GDT_EISA) IStatus = inb((u16)ha->bmic + EDOORREG); else if (ha->type == GDT_ISA) IStatus = readb(&((gdt2_dpram_str __iomem *)ha->brd)->u.ic.Cmd_Index); else if (ha->type == GDT_PCI) IStatus = readb(&((gdt6_dpram_str __iomem *)ha->brd)->u.ic.Cmd_Index); else if (ha->type == GDT_PCINEW) IStatus = inb(PTR2USHORT(&ha->plx->edoor_reg)); else if (ha->type == GDT_PCIMPR) IStatus = readb(&((gdt6m_dpram_str __iomem *)ha->brd)->i960r.edoor_reg); return IStatus; } static int gdth_test_busy(gdth_ha_str *ha) { register int gdtsema0 = 0; TRACE(("gdth_test_busy() hanum %d\n", ha->hanum)); if (ha->type == GDT_EISA) gdtsema0 = (int)inb(ha->bmic + SEMA0REG); else if (ha->type == GDT_ISA) gdtsema0 = (int)readb(&((gdt2_dpram_str __iomem *)ha->brd)->u.ic.Sema0); else if (ha->type == GDT_PCI) gdtsema0 = (int)readb(&((gdt6_dpram_str __iomem *)ha->brd)->u.ic.Sema0); else if (ha->type == GDT_PCINEW) gdtsema0 = (int)inb(PTR2USHORT(&ha->plx->sema0_reg)); else if (ha->type == GDT_PCIMPR) gdtsema0 = (int)readb(&((gdt6m_dpram_str __iomem *)ha->brd)->i960r.sema0_reg); return (gdtsema0 & 1); } static int gdth_get_cmd_index(gdth_ha_str *ha) { int i; TRACE(("gdth_get_cmd_index() hanum %d\n", ha->hanum)); for (i=0; icmd_tab[i].cmnd == UNUSED_CMND) { ha->cmd_tab[i].cmnd = ha->pccb->RequestBuffer; ha->cmd_tab[i].service = ha->pccb->Service; ha->pccb->CommandIndex = (u32)i+2; return (i+2); } } return 0; } static void gdth_set_sema0(gdth_ha_str *ha) { TRACE(("gdth_set_sema0() hanum %d\n", ha->hanum)); if (ha->type == GDT_EISA) { outb(1, ha->bmic + SEMA0REG); } else if (ha->type == GDT_ISA) { writeb(1, &((gdt2_dpram_str __iomem *)ha->brd)->u.ic.Sema0); } else if (ha->type == GDT_PCI) { writeb(1, &((gdt6_dpram_str __iomem *)ha->brd)->u.ic.Sema0); } else if (ha->type == GDT_PCINEW) { outb(1, PTR2USHORT(&ha->plx->sema0_reg)); } else if (ha->type == GDT_PCIMPR) { writeb(1, &((gdt6m_dpram_str __iomem *)ha->brd)->i960r.sema0_reg); } } static void gdth_copy_command(gdth_ha_str *ha) { register gdth_cmd_str *cmd_ptr; register gdt6m_dpram_str __iomem *dp6m_ptr; register gdt6c_dpram_str __iomem *dp6c_ptr; gdt6_dpram_str __iomem *dp6_ptr; gdt2_dpram_str __iomem *dp2_ptr; u16 cp_count,dp_offset,cmd_no; TRACE(("gdth_copy_command() hanum %d\n", ha->hanum)); cp_count = ha->cmd_len; dp_offset= ha->cmd_offs_dpmem; cmd_no = ha->cmd_cnt; cmd_ptr = ha->pccb; ++ha->cmd_cnt; if (ha->type == GDT_EISA) return; /* no DPMEM, no copy */ /* set cpcount dword aligned */ if (cp_count & 3) cp_count += (4 - (cp_count & 3)); ha->cmd_offs_dpmem += cp_count; /* set offset and service, copy command to DPMEM */ if (ha->type == GDT_ISA) { dp2_ptr = ha->brd; writew(dp_offset + DPMEM_COMMAND_OFFSET, &dp2_ptr->u.ic.comm_queue[cmd_no].offset); writew((u16)cmd_ptr->Service, &dp2_ptr->u.ic.comm_queue[cmd_no].serv_id); memcpy_toio(&dp2_ptr->u.ic.gdt_dpr_cmd[dp_offset],cmd_ptr,cp_count); } else if (ha->type == GDT_PCI) { dp6_ptr = ha->brd; writew(dp_offset + DPMEM_COMMAND_OFFSET, &dp6_ptr->u.ic.comm_queue[cmd_no].offset); writew((u16)cmd_ptr->Service, &dp6_ptr->u.ic.comm_queue[cmd_no].serv_id); memcpy_toio(&dp6_ptr->u.ic.gdt_dpr_cmd[dp_offset],cmd_ptr,cp_count); } else if (ha->type == GDT_PCINEW) { dp6c_ptr = ha->brd; writew(dp_offset + DPMEM_COMMAND_OFFSET, &dp6c_ptr->u.ic.comm_queue[cmd_no].offset); writew((u16)cmd_ptr->Service, &dp6c_ptr->u.ic.comm_queue[cmd_no].serv_id); memcpy_toio(&dp6c_ptr->u.ic.gdt_dpr_cmd[dp_offset],cmd_ptr,cp_count); } else if (ha->type == GDT_PCIMPR) { dp6m_ptr = ha->brd; writew(dp_offset + DPMEM_COMMAND_OFFSET, &dp6m_ptr->u.ic.comm_queue[cmd_no].offset); writew((u16)cmd_ptr->Service, &dp6m_ptr->u.ic.comm_queue[cmd_no].serv_id); memcpy_toio(&dp6m_ptr->u.ic.gdt_dpr_cmd[dp_offset],cmd_ptr,cp_count); } } static void gdth_release_event(gdth_ha_str *ha) { TRACE(("gdth_release_event() hanum %d\n", ha->hanum)); #ifdef GDTH_STATISTICS { u32 i,j; for (i=0,j=0; jcmd_tab[j].cmnd != UNUSED_CMND) ++i; } if (max_index < i) { max_index = i; TRACE3(("GDT: max_index = %d\n",(u16)i)); } } #endif if (ha->pccb->OpCode == GDT_INIT) ha->pccb->Service |= 0x80; if (ha->type == GDT_EISA) { if (ha->pccb->OpCode == GDT_INIT) /* store DMA buffer */ outl(ha->ccb_phys, ha->bmic + MAILBOXREG); outb(ha->pccb->Service, ha->bmic + LDOORREG); } else if (ha->type == GDT_ISA) { writeb(0, &((gdt2_dpram_str __iomem *)ha->brd)->io.event); } else if (ha->type == GDT_PCI) { writeb(0, &((gdt6_dpram_str __iomem *)ha->brd)->io.event); } else if (ha->type == GDT_PCINEW) { outb(1, PTR2USHORT(&ha->plx->ldoor_reg)); } else if (ha->type == GDT_PCIMPR) { writeb(1, &((gdt6m_dpram_str __iomem *)ha->brd)->i960r.ldoor_reg); } } static int gdth_wait(gdth_ha_str *ha, int index, u32 time) { int answer_found = FALSE; int wait_index = 0; TRACE(("gdth_wait() hanum %d index %d time %d\n", ha->hanum, index, time)); if (index == 0) return 1; /* no wait required */ do { __gdth_interrupt(ha, true, &wait_index); if (wait_index == index) { answer_found = TRUE; break; } gdth_delay(1); } while (--time); while (gdth_test_busy(ha)) gdth_delay(0); return (answer_found); } static int gdth_internal_cmd(gdth_ha_str *ha, u8 service, u16 opcode, u32 p1, u64 p2, u64 p3) { register gdth_cmd_str *cmd_ptr; int retries,index; TRACE2(("gdth_internal_cmd() service %d opcode %d\n",service,opcode)); cmd_ptr = ha->pccb; memset((char*)cmd_ptr,0,sizeof(gdth_cmd_str)); /* make command */ for (retries = INIT_RETRIES;;) { cmd_ptr->Service = service; cmd_ptr->RequestBuffer = INTERNAL_CMND; if (!(index=gdth_get_cmd_index(ha))) { TRACE(("GDT: No free command index found\n")); return 0; } gdth_set_sema0(ha); cmd_ptr->OpCode = opcode; cmd_ptr->BoardNode = LOCALBOARD; if (service == CACHESERVICE) { if (opcode == GDT_IOCTL) { cmd_ptr->u.ioctl.subfunc = p1; cmd_ptr->u.ioctl.channel = (u32)p2; cmd_ptr->u.ioctl.param_size = (u16)p3; cmd_ptr->u.ioctl.p_param = ha->scratch_phys; } else { if (ha->cache_feat & GDT_64BIT) { cmd_ptr->u.cache64.DeviceNo = (u16)p1; cmd_ptr->u.cache64.BlockNo = p2; } else { cmd_ptr->u.cache.DeviceNo = (u16)p1; cmd_ptr->u.cache.BlockNo = (u32)p2; } } } else if (service == SCSIRAWSERVICE) { if (ha->raw_feat & GDT_64BIT) { cmd_ptr->u.raw64.direction = p1; cmd_ptr->u.raw64.bus = (u8)p2; cmd_ptr->u.raw64.target = (u8)p3; cmd_ptr->u.raw64.lun = (u8)(p3 >> 8); } else { cmd_ptr->u.raw.direction = p1; cmd_ptr->u.raw.bus = (u8)p2; cmd_ptr->u.raw.target = (u8)p3; cmd_ptr->u.raw.lun = (u8)(p3 >> 8); } } else if (service == SCREENSERVICE) { if (opcode == GDT_REALTIME) { *(u32 *)&cmd_ptr->u.screen.su.data[0] = p1; *(u32 *)&cmd_ptr->u.screen.su.data[4] = (u32)p2; *(u32 *)&cmd_ptr->u.screen.su.data[8] = (u32)p3; } } ha->cmd_len = sizeof(gdth_cmd_str); ha->cmd_offs_dpmem = 0; ha->cmd_cnt = 0; gdth_copy_command(ha); gdth_release_event(ha); gdth_delay(20); if (!gdth_wait(ha, index, INIT_TIMEOUT)) { printk("GDT: Initialization error (timeout service %d)\n",service); return 0; } if (ha->status != S_BSY || --retries == 0) break; gdth_delay(1); } return (ha->status != S_OK ? 0:1); } /* search for devices */ static int gdth_search_drives(gdth_ha_str *ha) { u16 cdev_cnt, i; int ok; u32 bus_no, drv_cnt, drv_no, j; gdth_getch_str *chn; gdth_drlist_str *drl; gdth_iochan_str *ioc; gdth_raw_iochan_str *iocr; gdth_arcdl_str *alst; gdth_alist_str *alst2; gdth_oem_str_ioctl *oemstr; #ifdef INT_COAL gdth_perf_modes *pmod; #endif #ifdef GDTH_RTC u8 rtc[12]; unsigned long flags; #endif TRACE(("gdth_search_drives() hanum %d\n", ha->hanum)); ok = 0; /* initialize controller services, at first: screen service */ ha->screen_feat = 0; if (!force_dma32) { ok = gdth_internal_cmd(ha, SCREENSERVICE, GDT_X_INIT_SCR, 0, 0, 0); if (ok) ha->screen_feat = GDT_64BIT; } if (force_dma32 || (!ok && ha->status == (u16)S_NOFUNC)) ok = gdth_internal_cmd(ha, SCREENSERVICE, GDT_INIT, 0, 0, 0); if (!ok) { printk("GDT-HA %d: Initialization error screen service (code %d)\n", ha->hanum, ha->status); return 0; } TRACE2(("gdth_search_drives(): SCREENSERVICE initialized\n")); #ifdef GDTH_RTC /* read realtime clock info, send to controller */ /* 1. wait for the falling edge of update flag */ spin_lock_irqsave(&rtc_lock, flags); for (j = 0; j < 1000000; ++j) if (CMOS_READ(RTC_FREQ_SELECT) & RTC_UIP) break; for (j = 0; j < 1000000; ++j) if (!(CMOS_READ(RTC_FREQ_SELECT) & RTC_UIP)) break; /* 2. read info */ do { for (j = 0; j < 12; ++j) rtc[j] = CMOS_READ(j); } while (rtc[0] != CMOS_READ(0)); spin_unlock_irqrestore(&rtc_lock, flags); TRACE2(("gdth_search_drives(): RTC: %x/%x/%x\n",*(u32 *)&rtc[0], *(u32 *)&rtc[4], *(u32 *)&rtc[8])); /* 3. send to controller firmware */ gdth_internal_cmd(ha, SCREENSERVICE, GDT_REALTIME, *(u32 *)&rtc[0], *(u32 *)&rtc[4], *(u32 *)&rtc[8]); #endif /* unfreeze all IOs */ gdth_internal_cmd(ha, CACHESERVICE, GDT_UNFREEZE_IO, 0, 0, 0); /* initialize cache service */ ha->cache_feat = 0; if (!force_dma32) { ok = gdth_internal_cmd(ha, CACHESERVICE, GDT_X_INIT_HOST, LINUX_OS, 0, 0); if (ok) ha->cache_feat = GDT_64BIT; } if (force_dma32 || (!ok && ha->status == (u16)S_NOFUNC)) ok = gdth_internal_cmd(ha, CACHESERVICE, GDT_INIT, LINUX_OS, 0, 0); if (!ok) { printk("GDT-HA %d: Initialization error cache service (code %d)\n", ha->hanum, ha->status); return 0; } TRACE2(("gdth_search_drives(): CACHESERVICE initialized\n")); cdev_cnt = (u16)ha->info; ha->fw_vers = ha->service; #ifdef INT_COAL if (ha->type == GDT_PCIMPR) { /* set perf. modes */ pmod = (gdth_perf_modes *)ha->pscratch; pmod->version = 1; pmod->st_mode = 1; /* enable one status buffer */ *((u64 *)&pmod->st_buff_addr1) = ha->coal_stat_phys; pmod->st_buff_indx1 = COALINDEX; pmod->st_buff_addr2 = 0; pmod->st_buff_u_addr2 = 0; pmod->st_buff_indx2 = 0; pmod->st_buff_size = sizeof(gdth_coal_status) * MAXOFFSETS; pmod->cmd_mode = 0; // disable all cmd buffers pmod->cmd_buff_addr1 = 0; pmod->cmd_buff_u_addr1 = 0; pmod->cmd_buff_indx1 = 0; pmod->cmd_buff_addr2 = 0; pmod->cmd_buff_u_addr2 = 0; pmod->cmd_buff_indx2 = 0; pmod->cmd_buff_size = 0; pmod->reserved1 = 0; pmod->reserved2 = 0; if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL, SET_PERF_MODES, INVALID_CHANNEL,sizeof(gdth_perf_modes))) { printk("GDT-HA %d: Interrupt coalescing activated\n", ha->hanum); } } #endif /* detect number of buses - try new IOCTL */ iocr = (gdth_raw_iochan_str *)ha->pscratch; iocr->hdr.version = 0xffffffff; iocr->hdr.list_entries = MAXBUS; iocr->hdr.first_chan = 0; iocr->hdr.last_chan = MAXBUS-1; iocr->hdr.list_offset = GDTOFFSOF(gdth_raw_iochan_str, list[0]); if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL, IOCHAN_RAW_DESC, INVALID_CHANNEL,sizeof(gdth_raw_iochan_str))) { TRACE2(("IOCHAN_RAW_DESC supported!\n")); ha->bus_cnt = iocr->hdr.chan_count; for (bus_no = 0; bus_no < ha->bus_cnt; ++bus_no) { if (iocr->list[bus_no].proc_id < MAXID) ha->bus_id[bus_no] = iocr->list[bus_no].proc_id; else ha->bus_id[bus_no] = 0xff; } } else { /* old method */ chn = (gdth_getch_str *)ha->pscratch; for (bus_no = 0; bus_no < MAXBUS; ++bus_no) { chn->channel_no = bus_no; if (!gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL, SCSI_CHAN_CNT | L_CTRL_PATTERN, IO_CHANNEL | INVALID_CHANNEL, sizeof(gdth_getch_str))) { if (bus_no == 0) { printk("GDT-HA %d: Error detecting channel count (0x%x)\n", ha->hanum, ha->status); return 0; } break; } if (chn->siop_id < MAXID) ha->bus_id[bus_no] = chn->siop_id; else ha->bus_id[bus_no] = 0xff; } ha->bus_cnt = (u8)bus_no; } TRACE2(("gdth_search_drives() %d channels\n",ha->bus_cnt)); /* read cache configuration */ if (!gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL, CACHE_INFO, INVALID_CHANNEL,sizeof(gdth_cinfo_str))) { printk("GDT-HA %d: Initialization error cache service (code %d)\n", ha->hanum, ha->status); return 0; } ha->cpar = ((gdth_cinfo_str *)ha->pscratch)->cpar; TRACE2(("gdth_search_drives() cinfo: vs %x sta %d str %d dw %d b %d\n", ha->cpar.version,ha->cpar.state,ha->cpar.strategy, ha->cpar.write_back,ha->cpar.block_size)); /* read board info and features */ ha->more_proc = FALSE; if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL, BOARD_INFO, INVALID_CHANNEL,sizeof(gdth_binfo_str))) { memcpy(&ha->binfo, (gdth_binfo_str *)ha->pscratch, sizeof(gdth_binfo_str)); if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL, BOARD_FEATURES, INVALID_CHANNEL,sizeof(gdth_bfeat_str))) { TRACE2(("BOARD_INFO/BOARD_FEATURES supported\n")); ha->bfeat = *(gdth_bfeat_str *)ha->pscratch; ha->more_proc = TRUE; } } else { TRACE2(("BOARD_INFO requires firmware >= 1.10/2.08\n")); strcpy(ha->binfo.type_string, gdth_ctr_name(ha)); } TRACE2(("Controller name: %s\n",ha->binfo.type_string)); /* read more informations */ if (ha->more_proc) { /* physical drives, channel addresses */ ioc = (gdth_iochan_str *)ha->pscratch; ioc->hdr.version = 0xffffffff; ioc->hdr.list_entries = MAXBUS; ioc->hdr.first_chan = 0; ioc->hdr.last_chan = MAXBUS-1; ioc->hdr.list_offset = GDTOFFSOF(gdth_iochan_str, list[0]); if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL, IOCHAN_DESC, INVALID_CHANNEL,sizeof(gdth_iochan_str))) { for (bus_no = 0; bus_no < ha->bus_cnt; ++bus_no) { ha->raw[bus_no].address = ioc->list[bus_no].address; ha->raw[bus_no].local_no = ioc->list[bus_no].local_no; } } else { for (bus_no = 0; bus_no < ha->bus_cnt; ++bus_no) { ha->raw[bus_no].address = IO_CHANNEL; ha->raw[bus_no].local_no = bus_no; } } for (bus_no = 0; bus_no < ha->bus_cnt; ++bus_no) { chn = (gdth_getch_str *)ha->pscratch; chn->channel_no = ha->raw[bus_no].local_no; if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL, SCSI_CHAN_CNT | L_CTRL_PATTERN, ha->raw[bus_no].address | INVALID_CHANNEL, sizeof(gdth_getch_str))) { ha->raw[bus_no].pdev_cnt = chn->drive_cnt; TRACE2(("Channel %d: %d phys. drives\n", bus_no,chn->drive_cnt)); } if (ha->raw[bus_no].pdev_cnt > 0) { drl = (gdth_drlist_str *)ha->pscratch; drl->sc_no = ha->raw[bus_no].local_no; drl->sc_cnt = ha->raw[bus_no].pdev_cnt; if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL, SCSI_DR_LIST | L_CTRL_PATTERN, ha->raw[bus_no].address | INVALID_CHANNEL, sizeof(gdth_drlist_str))) { for (j = 0; j < ha->raw[bus_no].pdev_cnt; ++j) ha->raw[bus_no].id_list[j] = drl->sc_list[j]; } else { ha->raw[bus_no].pdev_cnt = 0; } } } /* logical drives */ if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL, CACHE_DRV_CNT, INVALID_CHANNEL,sizeof(u32))) { drv_cnt = *(u32 *)ha->pscratch; if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL, CACHE_DRV_LIST, INVALID_CHANNEL,drv_cnt * sizeof(u32))) { for (j = 0; j < drv_cnt; ++j) { drv_no = ((u32 *)ha->pscratch)[j]; if (drv_no < MAX_LDRIVES) { ha->hdr[drv_no].is_logdrv = TRUE; TRACE2(("Drive %d is log. drive\n",drv_no)); } } } alst = (gdth_arcdl_str *)ha->pscratch; alst->entries_avail = MAX_LDRIVES; alst->first_entry = 0; alst->list_offset = GDTOFFSOF(gdth_arcdl_str, list[0]); if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL, ARRAY_DRV_LIST2 | LA_CTRL_PATTERN, INVALID_CHANNEL, sizeof(gdth_arcdl_str) + (alst->entries_avail-1) * sizeof(gdth_alist_str))) { for (j = 0; j < alst->entries_init; ++j) { ha->hdr[j].is_arraydrv = alst->list[j].is_arrayd; ha->hdr[j].is_master = alst->list[j].is_master; ha->hdr[j].is_parity = alst->list[j].is_parity; ha->hdr[j].is_hotfix = alst->list[j].is_hotfix; ha->hdr[j].master_no = alst->list[j].cd_handle; } } else if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL, ARRAY_DRV_LIST | LA_CTRL_PATTERN, 0, 35 * sizeof(gdth_alist_str))) { for (j = 0; j < 35; ++j) { alst2 = &((gdth_alist_str *)ha->pscratch)[j]; ha->hdr[j].is_arraydrv = alst2->is_arrayd; ha->hdr[j].is_master = alst2->is_master; ha->hdr[j].is_parity = alst2->is_parity; ha->hdr[j].is_hotfix = alst2->is_hotfix; ha->hdr[j].master_no = alst2->cd_handle; } } } } /* initialize raw service */ ha->raw_feat = 0; if (!force_dma32) { ok = gdth_internal_cmd(ha, SCSIRAWSERVICE, GDT_X_INIT_RAW, 0, 0, 0); if (ok) ha->raw_feat = GDT_64BIT; } if (force_dma32 || (!ok && ha->status == (u16)S_NOFUNC)) ok = gdth_internal_cmd(ha, SCSIRAWSERVICE, GDT_INIT, 0, 0, 0); if (!ok) { printk("GDT-HA %d: Initialization error raw service (code %d)\n", ha-