/* Copyright (C) 2010 Willow Garage Copyright (C) 2010 Ivo van Doorn Copyright (C) 2009 Bartlomiej Zolnierkiewicz Copyright (C) 2009 Gertjan van Wingerde Based on the original rt2800pci.c and rt2800usb.c. Copyright (C) 2009 Alban Browaeys Copyright (C) 2009 Felix Fietkau Copyright (C) 2009 Luis Correia Copyright (C) 2009 Mattias Nissler Copyright (C) 2009 Mark Asselstine Copyright (C) 2009 Xose Vazquez Perez This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ /* Module: rt2800lib Abstract: rt2800 generic device routines. */ #include #include #include #include #include "rt2x00.h" #include "rt2800lib.h" #include "rt2800.h" /* * Register access. * All access to the CSR registers will go through the methods * rt2800_register_read and rt2800_register_write. * BBP and RF register require indirect register access, * and use the CSR registers BBPCSR and RFCSR to achieve this. * These indirect registers work with busy bits, * and we will try maximal REGISTER_BUSY_COUNT times to access * the register while taking a REGISTER_BUSY_DELAY us delay * between each attampt. When the busy bit is still set at that time, * the access attempt is considered to have failed, * and we will print an error. * The _lock versions must be used if you already hold the csr_mutex */ #define WAIT_FOR_BBP(__dev, __reg) \ rt2800_regbusy_read((__dev), BBP_CSR_CFG, BBP_CSR_CFG_BUSY, (__reg)) #define WAIT_FOR_RFCSR(__dev, __reg) \ rt2800_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY, (__reg)) #define WAIT_FOR_RF(__dev, __reg) \ rt2800_regbusy_read((__dev), RF_CSR_CFG0, RF_CSR_CFG0_BUSY, (__reg)) #define WAIT_FOR_MCU(__dev, __reg) \ rt2800_regbusy_read((__dev), H2M_MAILBOX_CSR, \ H2M_MAILBOX_CSR_OWNER, (__reg)) static inline bool rt2800_is_305x_soc(struct rt2x00_dev *rt2x00dev) { /* check for rt2872 on SoC */ if (!rt2x00_is_soc(rt2x00dev) || !rt2x00_rt(rt2x00dev, RT2872)) return false; /* we know for sure that these rf chipsets are used on rt305x boards */ if (rt2x00_rf(rt2x00dev, RF3020) || rt2x00_rf(rt2x00dev, RF3021) || rt2x00_rf(rt2x00dev, RF3022)) return true; rt2x00_warn(rt2x00dev, "Unknown RF chipset on rt305x\n"); return false; } static void rt2800_bbp_write(struct rt2x00_dev *rt2x00dev, const unsigned int word, const u8 value) { u32 reg; mutex_lock(&rt2x00dev->csr_mutex); /* * Wait until the BBP becomes available, afterwards we * can safely write the new data into the register. */ if (WAIT_FOR_BBP(rt2x00dev, ®)) { reg = 0; rt2x00_set_field32(®, BBP_CSR_CFG_VALUE, value); rt2x00_set_field32(®, BBP_CSR_CFG_REGNUM, word); rt2x00_set_field32(®, BBP_CSR_CFG_BUSY, 1); rt2x00_set_field32(®, BBP_CSR_CFG_READ_CONTROL, 0); rt2x00_set_field32(®, BBP_CSR_CFG_BBP_RW_MODE, 1); rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg); } mutex_unlock(&rt2x00dev->csr_mutex); } static void rt2800_bbp_read(struct rt2x00_dev *rt2x00dev, const unsigned int word, u8 *value) { u32 reg; mutex_lock(&rt2x00dev->csr_mutex); /* * Wait until the BBP becomes available, afterwards we * can safely write the read request into the register. * After the data has been written, we wait until hardware * returns the correct value, if at any time the register * doesn't become available in time, reg will be 0xffffffff * which means we return 0xff to the caller. */ if (WAIT_FOR_BBP(rt2x00dev, ®)) { reg = 0; rt2x00_set_field32(®, BBP_CSR_CFG_REGNUM, word); rt2x00_set_field32(®, BBP_CSR_CFG_BUSY, 1); rt2x00_set_field32(®, BBP_CSR_CFG_READ_CONTROL, 1); rt2x00_set_field32(®, BBP_CSR_CFG_BBP_RW_MODE, 1); rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg); WAIT_FOR_BBP(rt2x00dev, ®); } *value = rt2x00_get_field32(reg, BBP_CSR_CFG_VALUE); mutex_unlock(&rt2x00dev->csr_mutex); } static void rt2800_rfcsr_write(struct rt2x00_dev *rt2x00dev, const unsigned int word, const u8 value) { u32 reg; mutex_lock(&rt2x00dev->csr_mutex); /* * Wait until the RFCSR becomes available, afterwards we * can safely write the new data into the register. */ if (WAIT_FOR_RFCSR(rt2x00dev, ®)) { reg = 0; rt2x00_set_field32(®, RF_CSR_CFG_DATA, value); rt2x00_set_field32(®, RF_CSR_CFG_REGNUM, word); rt2x00_set_field32(®, RF_CSR_CFG_WRITE, 1); rt2x00_set_field32(®, RF_CSR_CFG_BUSY, 1); rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg); } mutex_unlock(&rt2x00dev->csr_mutex); } static void rt2800_rfcsr_read(struct rt2x00_dev *rt2x00dev, const unsigned int word, u8 *value) { u32 reg; mutex_lock(&rt2x00dev->csr_mutex); /* * Wait until the RFCSR becomes available, afterwards we * can safely write the read request into the register. * After the data has been written, we wait until hardware * returns the correct value, if at any time the register * doesn't become available in time, reg will be 0xffffffff * which means we return 0xff to the caller. */ if (WAIT_FOR_RFCSR(rt2x00dev, ®)) { reg = 0; rt2x00_set_field32(®, RF_CSR_CFG_REGNUM, word); rt2x00_set_field32(®, RF_CSR_CFG_WRITE, 0); rt2x00_set_field32(®, RF_CSR_CFG_BUSY, 1); rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg); WAIT_FOR_RFCSR(rt2x00dev, ®); } *value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA); mutex_unlock(&rt2x00dev->csr_mutex); } static void rt2800_rf_write(struct rt2x00_dev *rt2x00dev, const unsigned int word, const u32 value) { u32 reg; mutex_lock(&rt2x00dev->csr_mutex); /* * Wait until the RF becomes available, afterwards we * can safely write the new data into the register. */ if (WAIT_FOR_RF(rt2x00dev, ®)) { reg = 0; rt2x00_set_field32(®, RF_CSR_CFG0_REG_VALUE_BW, value); rt2x00_set_field32(®, RF_CSR_CFG0_STANDBYMODE, 0); rt2x00_set_field32(®, RF_CSR_CFG0_SEL, 0); rt2x00_set_field32(®, RF_CSR_CFG0_BUSY, 1); rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG0, reg); rt2x00_rf_write(rt2x00dev, word, value); } mutex_unlock(&rt2x00dev->csr_mutex); } static const unsigned int rt2800_eeprom_map[EEPROM_WORD_COUNT] = { [EEPROM_CHIP_ID] = 0x0000, [EEPROM_VERSION] = 0x0001, [EEPROM_MAC_ADDR_0] = 0x0002, [EEPROM_MAC_ADDR_1] = 0x0003, [EEPROM_MAC_ADDR_2] = 0x0004, [EEPROM_NIC_CONF0] = 0x001a, [EEPROM_NIC_CONF1] = 0x001b, [EEPROM_FREQ] = 0x001d, [EEPROM_LED_AG_CONF] = 0x001e, [EEPROM_LED_ACT_CONF] = 0x001f, [EEPROM_LED_POLARITY] = 0x0020, [EEPROM_NIC_CONF2] = 0x0021, [EEPROM_LNA] = 0x0022, [EEPROM_RSSI_BG] = 0x0023, [EEPROM_RSSI_BG2] = 0x0024, [EEPROM_TXMIXER_GAIN_BG] = 0x0024, /* overlaps with RSSI_BG2 */ [EEPROM_RSSI_A] = 0x0025, [EEPROM_RSSI_A2] = 0x0026, [EEPROM_TXMIXER_GAIN_A] = 0x0026, /* overlaps with RSSI_A2 */ [EEPROM_EIRP_MAX_TX_POWER] = 0x0027, [EEPROM_TXPOWER_DELTA] = 0x0028, [EEPROM_TXPOWER_BG1] = 0x0029, [EEPROM_TXPOWER_BG2] = 0x0030, [EEPROM_TSSI_BOUND_BG1] = 0x0037, [EEPROM_TSSI_BOUND_BG2] = 0x0038, [EEPROM_TSSI_BOUND_BG3] = 0x0039, [EEPROM_TSSI_BOUND_BG4] = 0x003a, [EEPROM_TSSI_BOUND_BG5] = 0x003b, [EEPROM_TXPOWER_A1] = 0x003c, [EEPROM_TXPOWER_A2] = 0x0053, [EEPROM_TSSI_BOUND_A1] = 0x006a, [EEPROM_TSSI_BOUND_A2] = 0x006b, [EEPROM_TSSI_BOUND_A3] = 0x006c, [EEPROM_TSSI_BOUND_A4] = 0x006d, [EEPROM_TSSI_BOUND_A5] = 0x006e, [EEPROM_TXPOWER_BYRATE] = 0x006f, [EEPROM_BBP_START] = 0x0078, }; static const unsigned int rt2800_eeprom_map_ext[EEPROM_WORD_COUNT] = { [EEPROM_CHIP_ID] = 0x0000, [EEPROM_VERSION] = 0x0001, [EEPROM_MAC_ADDR_0] = 0x0002, [EEPROM_MAC_ADDR_1] = 0x0003, [EEPROM_MAC_ADDR_2] = 0x0004, [EEPROM_NIC_CONF0] = 0x001a, [EEPROM_NIC_CONF1] = 0x001b, [EEPROM_NIC_CONF2] = 0x001c, [EEPROM_EIRP_MAX_TX_POWER] = 0x0020, [EEPROM_FREQ] = 0x0022, [EEPROM_LED_AG_CONF] = 0x0023, [EEPROM_LED_ACT_CONF] = 0x0024, [EEPROM_LED_POLARITY] = 0x0025, [EEPROM_LNA] = 0x0026, [EEPROM_EXT_LNA2] = 0x0027, [EEPROM_RSSI_BG] = 0x0028, [EEPROM_TXPOWER_DELTA] = 0x0028, /* Overlaps with RSSI_BG */ [EEPROM_RSSI_BG2] = 0x0029, [EEPROM_TXMIXER_GAIN_BG] = 0x0029, /* Overlaps with RSSI_BG2 */ [EEPROM_RSSI_A] = 0x002a, [EEPROM_RSSI_A2] = 0x002b, [EEPROM_TXMIXER_GAIN_A] = 0x002b, /* Overlaps with RSSI_A2 */ [EEPROM_TXPOWER_BG1] = 0x0030, [EEPROM_TXPOWER_BG2] = 0x0037, [EEPROM_EXT_TXPOWER_BG3] = 0x003e, [EEPROM_TSSI_BOUND_BG1] = 0x0045, [EEPROM_TSSI_BOUND_BG2] = 0x0046, [EEPROM_TSSI_BOUND_BG3] = 0x0047, [EEPROM_TSSI_BOUND_BG4] = 0x0048, [EEPROM_TSSI_BOUND_BG5] = 0x0049, [EEPROM_TXPOWER_A1] = 0x004b, [EEPROM_TXPOWER_A2] = 0x0065, [EEPROM_EXT_TXPOWER_A3] = 0x007f, [EEPROM_TSSI_BOUND_A1] = 0x009a, [EEPROM_TSSI_BOUND_A2] = 0x009b, [EEPROM_TSSI_BOUND_A3] = 0x009c, [EEPROM_TSSI_BOUND_A4] = 0x009d, [EEPROM_TSSI_BOUND_A5] = 0x009e, [EEPROM_TXPOWER_BYRATE] = 0x00a0, }; static unsigned int rt2800_eeprom_word_index(struct rt2x00_dev *rt2x00dev, const enum rt2800_eeprom_word word) { const unsigned int *map; unsigned int index; if (WARN_ONCE(word >= EEPROM_WORD_COUNT, "%s: invalid EEPROM word %d\n", wiphy_name(rt2x00dev->hw->wiphy), word)) return 0; if (rt2x00_rt(rt2x00dev, RT3593)) map = rt2800_eeprom_map_ext; else map = rt2800_eeprom_map; index = map[word]; /* Index 0 is valid only for EEPROM_CHIP_ID. * Otherwise it means that the offset of the * given word is not initialized in the map, * or that the field is not usable on the * actual chipset. */ WARN_ONCE(word != EEPROM_CHIP_ID && index == 0, "%s: invalid access of EEPROM word %d\n", wiphy_name(rt2x00dev->hw->wiphy), word); return index; } static void *rt2800_eeprom_addr(struct rt2x00_dev *rt2x00dev, const enum rt2800_eeprom_word word) { unsigned int index; index = rt2800_eeprom_word_index(rt2x00dev, word); return rt2x00_eeprom_addr(rt2x00dev, index); } static void rt2800_eeprom_read(struct rt2x00_dev *rt2x00dev, const enum rt2800_eeprom_word word, u16 *data) { unsigned int index; index = rt2800_eeprom_word_index(rt2x00dev, word); rt2x00_eeprom_read(rt2x00dev, index, data); } static void rt2800_eeprom_write(struct rt2x00_dev *rt2x00dev, const enum rt2800_eeprom_word word, u16 data) { unsigned int index; index = rt2800_eeprom_word_index(rt2x00dev, word); rt2x00_eeprom_write(rt2x00dev, index, data); } static void rt2800_eeprom_read_from_array(struct rt2x00_dev *rt2x00dev, const enum rt2800_eeprom_word array, unsigned int offset, u16 *data) { unsigned int index; index = rt2800_eeprom_word_index(rt2x00dev, array); rt2x00_eeprom_read(rt2x00dev, index + offset, data); } static int rt2800_enable_wlan_rt3290(struct rt2x00_dev *rt2x00dev) { u32 reg; int i, count; rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL, ®); if (rt2x00_get_field32(reg, WLAN_EN)) return 0; rt2x00_set_field32(®, WLAN_GPIO_OUT_OE_BIT_ALL, 0xff); rt2x00_set_field32(®, FRC_WL_ANT_SET, 1); rt2x00_set_field32(®, WLAN_CLK_EN, 0); rt2x00_set_field32(®, WLAN_EN, 1); rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg); udelay(REGISTER_BUSY_DELAY); count = 0; do { /* * Check PLL_LD & XTAL_RDY. */ for (i = 0; i < REGISTER_BUSY_COUNT; i++) { rt2800_register_read(rt2x00dev, CMB_CTRL, ®); if (rt2x00_get_field32(reg, PLL_LD) && rt2x00_get_field32(reg, XTAL_RDY)) break; udelay(REGISTER_BUSY_DELAY); } if (i >= REGISTER_BUSY_COUNT) { if (count >= 10) return -EIO; rt2800_register_write(rt2x00dev, 0x58, 0x018); udelay(REGISTER_BUSY_DELAY); rt2800_register_write(rt2x00dev, 0x58, 0x418); udelay(REGISTER_BUSY_DELAY); rt2800_register_write(rt2x00dev, 0x58, 0x618); udelay(REGISTER_BUSY_DELAY); count++; } else { count = 0; } rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL, ®); rt2x00_set_field32(®, PCIE_APP0_CLK_REQ, 0); rt2x00_set_field32(®, WLAN_CLK_EN, 1); rt2x00_set_field32(®, WLAN_RESET, 1); rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg); udelay(10); rt2x00_set_field32(®, WLAN_RESET, 0); rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg); udelay(10); rt2800_register_write(rt2x00dev, INT_SOURCE_CSR, 0x7fffffff); } while (count != 0); return 0; } void rt2800_mcu_request(struct rt2x00_dev *rt2x00dev, const u8 command, const u8 token, const u8 arg0, const u8 arg1) { u32 reg; /* * SOC devices don't support MCU requests. */ if (rt2x00_is_soc(rt2x00dev)) return; mutex_lock(&rt2x00dev->csr_mutex); /* * Wait until the MCU becomes available, afterwards we * can safely write the new data into the register. */ if (WAIT_FOR_MCU(rt2x00dev, ®)) { rt2x00_set_field32(®, H2M_MAILBOX_CSR_OWNER, 1); rt2x00_set_field32(®, H2M_MAILBOX_CSR_CMD_TOKEN, token); rt2x00_set_field32(®, H2M_MAILBOX_CSR_ARG0, arg0); rt2x00_set_field32(®, H2M_MAILBOX_CSR_ARG1, arg1); rt2800_register_write_lock(rt2x00dev, H2M_MAILBOX_CSR, reg); reg = 0; rt2x00_set_field32(®, HOST_CMD_CSR_HOST_COMMAND, command); rt2800_register_write_lock(rt2x00dev, HOST_CMD_CSR, reg); } mutex_unlock(&rt2x00dev->csr_mutex); } EXPORT_SYMBOL_GPL(rt2800_mcu_request); int rt2800_wait_csr_ready(struct rt2x00_dev *rt2x00dev) { unsigned int i = 0; u32 reg; for (i = 0; i < REGISTER_BUSY_COUNT; i++) { rt2800_register_read(rt2x00dev, MAC_CSR0, ®); if (reg && reg != ~0) return 0; msleep(1); } rt2x00_err(rt2x00dev, "Unstable hardware\n"); return -EBUSY; } EXPORT_SYMBOL_GPL(rt2800_wait_csr_ready); int rt2800_wait_wpdma_ready(struct rt2x00_dev *rt2x00dev) { unsigned int i; u32 reg; /* * Some devices are really slow to respond here. Wait a whole second * before timing out. */ for (i = 0; i < REGISTER_BUSY_COUNT; i++) { rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, ®); if (!rt2x00_get_field32(reg, WPDMA_GLO_CFG_TX_DMA_BUSY) && !rt2x00_get_field32(reg, WPDMA_GLO_CFG_RX_DMA_BUSY)) return 0; msleep(10); } rt2x00_err(rt2x00dev, "WPDMA TX/RX busy [0x%08x]\n", reg); return -EACCES; } EXPORT_SYMBOL_GPL(rt2800_wait_wpdma_ready); void rt2800_disable_wpdma(struct rt2x00_dev *rt2x00dev) { u32 reg; rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, ®); rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0); rt2x00_set_field32(®, WPDMA_GLO_CFG_TX_DMA_BUSY, 0); rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0); rt2x00_set_field32(®, WPDMA_GLO_CFG_RX_DMA_BUSY, 0); rt2x00_set_field32(®, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1); rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg); } EXPORT_SYMBOL_GPL(rt2800_disable_wpdma); void rt2800_get_txwi_rxwi_size(struct rt2x00_dev *rt2x00dev, unsigned short *txwi_size, unsigned short *rxwi_size) { switch (rt2x00dev->chip.rt) { case RT3593: *txwi_size = TXWI_DESC_SIZE_4WORDS; *rxwi_size = RXWI_DESC_SIZE_5WORDS; break; case RT5592: *txwi_size = TXWI_DESC_SIZE_5WORDS; *rxwi_size = RXWI_DESC_SIZE_6WORDS; break; default: *txwi_size = TXWI_DESC_SIZE_4WORDS; *rxwi_size = RXWI_DESC_SIZE_4WORDS; break; } } EXPORT_SYMBOL_GPL(rt2800_get_txwi_rxwi_size); static bool rt2800_check_firmware_crc(const u8 *data, const size_t len) { u16 fw_crc; u16 crc; /* * The last 2 bytes in the firmware array are the crc checksum itself, * this means that we should never pass those 2 bytes to the crc * algorithm. */ fw_crc = (data[len - 2] << 8 | data[len - 1]); /* * Use the crc ccitt algorithm. * This will return the same value as the legacy driver which * used bit ordering reversion on the both the firmware bytes * before input input as well as on the final output. * Obviously using crc ccitt directly is much more efficient. */ crc = crc_ccitt(~0, data, len - 2); /* * There is a small difference between the crc-itu-t + bitrev and * the crc-ccitt crc calculation. In the latter method the 2 bytes * will be swapped, use swab16 to convert the crc to the correct * value. */ crc = swab16(crc); return fw_crc == crc; } int rt2800_check_firmware(struct rt2x00_dev *rt2x00dev, const u8 *data, const size_t len) { size_t offset = 0; size_t fw_len; bool multiple; /* * PCI(e) & SOC devices require firmware with a length * of 8kb. USB devices require firmware files with a length * of 4kb. Certain USB chipsets however require different firmware, * which Ralink only provides attached to the original firmware * file. Thus for USB devices, firmware files have a length * which is a multiple of 4kb. The firmware for rt3290 chip also * have a length which is a multiple of 4kb. */ if (rt2x00_is_usb(rt2x00dev) || rt2x00_rt(rt2x00dev, RT3290)) fw_len = 4096; else fw_len = 8192; multiple = true; /* * Validate the firmware length */ if (len != fw_len && (!multiple || (len % fw_len) != 0)) return FW_BAD_LENGTH; /* * Check if the chipset requires one of the upper parts * of the firmware. */ if (rt2x00_is_usb(rt2x00dev) && !rt2x00_rt(rt2x00dev, RT2860) && !rt2x00_rt(rt2x00dev, RT2872) && !rt2x00_rt(rt2x00dev, RT3070) && ((len / fw_len) == 1)) return FW_BAD_VERSION; /* * 8kb firmware files must be checked as if it were * 2 separate firmware files. */ while (offset < len) { if (!rt2800_check_firmware_crc(data + offset, fw_len)) return FW_BAD_CRC; offset += fw_len; } return FW_OK; } EXPORT_SYMBOL_GPL(rt2800_check_firmware); int rt2800_load_firmware(struct rt2x00_dev *rt2x00dev, const u8 *data, const size_t len) { unsigned int i; u32 reg; int retval; if (rt2x00_rt(rt2x00dev, RT3290)) { retval = rt2800_enable_wlan_rt3290(rt2x00dev); if (retval) return -EBUSY; } /* * If driver doesn't wake up firmware here, * rt2800_load_firmware will hang forever when interface is up again. */ rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0x00000000); /* * Wait for stable hardware. */ if (rt2800_wait_csr_ready(rt2x00dev)) return -EBUSY; if (rt2x00_is_pci(rt2x00dev)) { if (rt2x00_rt(rt2x00dev, RT3290) || rt2x00_rt(rt2x00dev, RT3572) || rt2x00_rt(rt2x00dev, RT5390) || rt2x00_rt(rt2x00dev, RT5392)) { rt2800_register_read(rt2x00dev, AUX_CTRL, ®); rt2x00_set_field32(®, AUX_CTRL_FORCE_PCIE_CLK, 1); rt2x00_set_field32(®, AUX_CTRL_WAKE_PCIE_EN, 1); rt2800_register_write(rt2x00dev, AUX_CTRL, reg); } rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000002); } rt2800_disable_wpdma(rt2x00dev); /* * Write firmware to the device. */ rt2800_drv_write_firmware(rt2x00dev, data, len); /* * Wait for device to stabilize. */ for (i = 0; i < REGISTER_BUSY_COUNT; i++) { rt2800_register_read(rt2x00dev, PBF_SYS_CTRL, ®); if (rt2x00_get_field32(reg, PBF_SYS_CTRL_READY)) break; msleep(1); } if (i == REGISTER_BUSY_COUNT) { rt2x00_err(rt2x00dev, "PBF system register not ready\n"); return -EBUSY; } /* * Disable DMA, will be reenabled later when enabling * the radio. */ rt2800_disable_wpdma(rt2x00dev); /* * Initialize firmware. */ rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0); rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0); if (rt2x00_is_usb(rt2x00dev)) { rt2800_register_write(rt2x00dev, H2M_INT_SRC, 0); rt2800_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0, 0, 0); } msleep(1); return 0; } EXPORT_SYMBOL_GPL(rt2800_load_firmware); void rt2800_write_tx_data(struct queue_entry *entry, struct txentry_desc *txdesc) { __le32 *txwi = rt2800_drv_get_txwi(entry); u32 word; int i; /* * Initialize TX Info descriptor */ rt2x00_desc_read(txwi, 0, &word); rt2x00_set_field32(&word, TXWI_W0_FRAG, test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags)); rt2x00_set_field32(&word, TXWI_W0_MIMO_PS, test_bit(ENTRY_TXD_HT_MIMO_PS, &txdesc->flags)); rt2x00_set_field32(&word, TXWI_W0_CF_ACK, 0); rt2x00_set_field32(&word, TXWI_W0_TS, test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags)); rt2x00_set_field32(&word, TXWI_W0_AMPDU, test_bit(ENTRY_TXD_HT_AMPDU, &txdesc->flags)); rt2x00_set_field32(&word, TXWI_W0_MPDU_DENSITY, txdesc->u.ht.mpdu_density); rt2x00_set_field32(&word, TXWI_W0_TX_OP, txdesc->u.ht.txop); rt2x00_set_field32(&word, TXWI_W0_MCS, txdesc->u.ht.mcs); rt2x00_set_field32(&word, TXWI_W0_BW, test_bit(ENTRY_TXD_HT_BW_40, &txdesc->flags)); rt2x00_set_field32(&word, TXWI_W0_SHORT_GI, test_bit(ENTRY_TXD_HT_SHORT_GI, &txdesc->flags)); rt2x00_set_field32(&word, TXWI_W0_STBC, txdesc->u.ht.stbc); rt2x00_set_field32(&word, TXWI_W0_PHYMODE, txdesc->rate_mode); rt2x00_desc_write(txwi, 0, word); rt2x00_desc_read(txwi, 1, &word); rt2x00_set_field32(&word, TXWI_W1_ACK, test_bit(ENTRY_TXD_ACK, &txdesc->flags)); rt2x00_set_field32(&word, TXWI_W1_NSEQ, test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags)); rt2x00_set_field32(&word, TXWI_W1_BW_WIN_SIZE, txdesc->u.ht.ba_size); rt2x00_set_field32(&word, TXWI_W1_WIRELESS_CLI_ID, test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags) ? txdesc->key_idx : txdesc->u.ht.wcid); rt2x00_set_field32(&word, TXWI_W1_MPDU_TOTAL_BYTE_COUNT, txdesc->length); rt2x00_set_field32(&word, TXWI_W1_PACKETID_QUEUE, entry->queue->qid); rt2x00_set_field32(&word, TXWI_W1_PACKETID_ENTRY, (entry->entry_idx % 3) + 1); rt2x00_desc_write(txwi, 1, word); /* * Always write 0 to IV/EIV fields (word 2 and 3), hardware will insert * the IV from the IVEIV register when TXD_W3_WIV is set to 0. * When TXD_W3_WIV is set to 1 it will use the IV data * from the descriptor. The TXWI_W1_WIRELESS_CLI_ID indicates which * crypto entry in the registers should be used to encrypt the frame. * * Nulify all remaining words as well, we don't know how to program them. */ for (i = 2; i < entry->queue->winfo_size / sizeof(__le32); i++) _rt2x00_desc_write(txwi, i, 0); } EXPORT_SYMBOL_GPL(rt2800_write_tx_data); static int rt2800_agc_to_rssi(struct rt2x00_dev *rt2x00dev, u32 rxwi_w2) { s8 rssi0 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI0); s8 rssi1 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI1); s8 rssi2 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI2); u16 eeprom; u8 offset0; u8 offset1; u8 offset2; if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) { rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &eeprom); offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET0); offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET1); rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom); offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_OFFSET2); } else { rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &eeprom); offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET0); offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET1); rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom); offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_OFFSET2); } /* * Convert the value from the descriptor into the RSSI value * If the value in the descriptor is 0, it is considered invalid * and the default (extremely low) rssi value is assumed */ rssi0 = (rssi0) ? (-12 - offset0 - rt2x00dev->lna_gain - rssi0) : -128; rssi1 = (rssi1) ? (-12 - offset1 - rt2x00dev->lna_gain - rssi1) : -128; rssi2 = (rssi2) ? (-12 - offset2 - rt2x00dev->lna_gain - rssi2) : -128; /* * mac80211 only accepts a single RSSI value. Calculating the * average doesn't deliver a fair answer either since -60:-60 would * be considered equally good as -50:-70 while the second is the one * which gives less energy... */ rssi0 = max(rssi0, rssi1); return (int)max(rssi0, rssi2); } void rt2800_process_rxwi(struct queue_entry *entry, struct rxdone_entry_desc *rxdesc) { __le32 *rxwi = (__le32 *) entry->skb->data; u32 word; rt2x00_desc_read(rxwi, 0, &word); rxdesc->cipher = rt2x00_get_field32(word, RXWI_W0_UDF); rxdesc->size = rt2x00_get_field32(word, RXWI_W0_MPDU_TOTAL_BYTE_COUNT); rt2x00_desc_read(rxwi, 1, &word); if (rt2x00_get_field32(word, RXWI_W1_SHORT_GI)) rxdesc->flags |= RX_FLAG_SHORT_GI; if (rt2x00_get_field32(word, RXWI_W1_BW)) rxdesc->flags |= RX_FLAG_40MHZ; /* * Detect RX rate, always use MCS as signal type. */ rxdesc->dev_flags |= RXDONE_SIGNAL_MCS; rxdesc->signal = rt2x00_get_field32(word, RXWI_W1_MCS); rxdesc->rate_mode = rt2x00_get_field32(word, RXWI_W1_PHYMODE); /* * Mask of 0x8 bit to remove the short preamble flag. */ if (rxdesc->rate_mode == RATE_MODE_CCK) rxdesc->signal &= ~0x8; rt2x00_desc_read(rxwi, 2, &word); /* * Convert descriptor AGC value to RSSI value. */ rxdesc->rssi = rt2800_agc_to_rssi(entry->queue->rt2x00dev, word); /* * Remove RXWI descriptor from start of the buffer. */ skb_pull(entry->skb, entry->queue->winfo_size); } EXPORT_SYMBOL_GPL(rt2800_process_rxwi); void rt2800_txdone_entry(struct queue_entry *entry, u32 status, __le32 *txwi) { struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev; struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb); struct txdone_entry_desc txdesc; u32 word; u16 mcs, real_mcs; int aggr, ampdu; /* * Obtain the status about this packet. */ txdesc.flags = 0; rt2x00_desc_read(txwi, 0, &word); mcs = rt2x00_get_field32(word, TXWI_W0_MCS); ampdu = rt2x00_get_field32(word, TXWI_W0_AMPDU); real_mcs = rt2x00_get_field32(status, TX_STA_FIFO_MCS); aggr = rt2x00_get_field32(status, TX_STA_FIFO_TX_AGGRE); /* * If a frame was meant to be sent as a single non-aggregated MPDU * but ended up in an aggregate the used tx rate doesn't correlate * with the one specified in the TXWI as the whole aggregate is sent * with the same rate. * * For example: two frames are sent to rt2x00, the first one sets * AMPDU=1 and requests MCS7 whereas the second frame sets AMDPU=0 * and requests MCS15. If the hw aggregates both frames into one * AMDPU the tx status for both frames will contain MCS7 although * the frame was sent successfully. * * Hence, replace the requested rate with the real tx rate to not * confuse the rate control algortihm by providing clearly wrong * data. */ if (unlikely(aggr == 1 && ampdu == 0 && real_mcs != mcs)) { skbdesc->tx_rate_idx = real_mcs; mcs = real_mcs; } if (aggr == 1 || ampdu == 1) __set_bit(TXDONE_AMPDU, &txdesc.flags); /* * Ralink has a retry mechanism using a global fallback * table. We setup this fallback table to try the immediate * lower rate for all rates. In the TX_STA_FIFO, the MCS field * always contains the MCS used for the last transmission, be * it successful or not. */ if (rt2x00_get_field32(status, TX_STA_FIFO_TX_SUCCESS)) { /* * Transmission succeeded. The number of retries is * mcs - real_mcs */ __set_bit(TXDONE_SUCCESS, &txdesc.flags); txdesc.retry = ((mcs > real_mcs) ? mcs - real_mcs : 0); } else { /* * Transmission failed. The number of retries is * always 7 in this case (for a total number of 8 * frames sent). */ __set_bit(TXDONE_FAILURE, &txdesc.flags); txdesc.retry = rt2x00dev->long_retry; } /* * the frame was retried at least once * -> hw used fallback rates */ if (txdesc.retry) __set_bit(TXDONE_FALLBACK, &txdesc.flags); rt2x00lib_txdone(entry, &txdesc); } EXPORT_SYMBOL_GPL(rt2800_txdone_entry); static unsigned int rt2800_hw_beacon_base(struct rt2x00_dev *rt2x00dev, unsigned int index) { return HW_BEACON_BASE(index); } static inline u8 rt2800_get_beacon_offset(struct rt2x00_dev *rt2x00dev, unsigned int index) { return BEACON_BASE_TO_OFFSET(rt2800_hw_beacon_base(rt2x00dev, index)); } void rt2800_write_beacon(struct queue_entry *entry, struct txentry_desc *txdesc) { struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev; struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb); unsigned int beacon_base; unsigned int padding_len; u32 orig_reg, reg; const int txwi_desc_size = entry->queue->winfo_size; /* * Disable beaconing while we are reloading the beacon data, * otherwise we might be sending out invalid data. */ rt2800_register_read(rt2x00dev, BCN_TIME_CFG, ®); orig_reg = reg; rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_GEN, 0); rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg); /* * Add space for the TXWI in front of the skb. */ memset(skb_push(entry->skb, txwi_desc_size), 0, txwi_desc_size); /* * Register descriptor details in skb frame descriptor. */ skbdesc->flags |= SKBDESC_DESC_IN_SKB; skbdesc->desc = entry->skb->data; skbdesc->desc_len = txwi_desc_size; /* * Add the TXWI for the beacon to the skb. */ rt2800_write_tx_data(entry, txdesc); /* * Dump beacon to userspace through debugfs. */ rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry->skb); /* * Write entire beacon with TXWI and padding to register. */ padding_len = roundup(entry->skb->len, 4) - entry->skb->len; if (padding_len && skb_pad(entry->skb, padding_len)) { rt2x00_err(rt2x00dev, "Failure padding beacon, aborting\n"); /* skb freed by skb_pad() on failure */ entry->skb = NULL; rt2800_register_write(rt2x00dev, BCN_TIME_CFG, orig_reg); return; } beacon_base = rt2800_hw_beacon_base(rt2x00dev, entry->entry_idx); rt2800_register_multiwrite(rt2x00dev, beacon_base, entry->skb->data, entry->skb->len + padding_len); /* * Enable beaconing again. */ rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_GEN, 1); rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg); /* * Clean up beacon skb. */ dev_kfree_skb_any(entry->skb); entry->skb = NULL; } EXPORT_SYMBOL_GPL(rt2800_write_beacon); static inline void rt2800_clear_beacon_register(struct rt2x00_dev *rt2x00dev, unsigned int index) { int i; const int txwi_desc_size = rt2x00dev->bcn->winfo_size; unsigned int beacon_base; beacon_base = rt2800_hw_beacon_base(rt2x00dev, index); /* * For the Beacon base registers we only need to clear * the whole TXWI which (when set to 0) will invalidate * the entire beacon. */ for (i = 0; i < txwi_desc_size; i += sizeof(__le32)) rt2800_register_write(rt2x00dev, beacon_base + i, 0); } void rt2800_clear_beacon(struct queue_entry *entry) { struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev; u32 reg; /* * Disable beaconing while we are reloading the beacon data, * otherwise we might be sending out invalid data. */ rt2800_register_read(rt2x00dev, BCN_TIME_CFG, ®); rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_GEN, 0); rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg); /* * Clear beacon. */ rt2800_clear_beacon_register(rt2x00dev, entry->entry_idx); /* * Enabled beaconing again. */ rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_GEN, 1); rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg); } EXPORT_SYMBOL_GPL(rt2800_clear_beacon); #ifdef CONFIG_RT2X00_LIB_DEBUGFS const struct rt2x00debug rt2800_rt2x00debug = { .owner = THIS_MODULE, .csr = { .read = rt2800_register_read, .write = rt2800_register_write, .flags = RT2X00DEBUGFS_OFFSET, .word_base = CSR_REG_BASE, .word_size = sizeof(u32), .word_count = CSR_REG_SIZE / sizeof(u32), }, .eeprom = { /* NOTE: The local EEPROM access functions can't * be used here, use the generic versions instead. */ .read = rt2x00_eeprom_read, .write = rt2x00_eeprom_write, .word_base = EEPROM_BASE, .word_size = sizeof(u16), .word_count = EEPROM_SIZE / sizeof(u16), }, .bbp = { .read = rt2800_bbp_read, .write = rt2800_bbp_write, .word_base = BBP_BASE, .word_size = sizeof(u8), .word_count = BBP_SIZE / sizeof(u8), }, .rf = { .read = rt2x00_rf_read, .write = rt2800_rf_write, .word_base = RF_BASE, .word_size = sizeof(u32), .word_count = RF_SIZE / sizeof(u32), }, .rfcsr = { .read = rt2800_rfcsr_read, .write = rt2800_rfcsr_write, .word_base = RFCSR_BASE, .word_size = sizeof(u8), .word_count = RFCSR_SIZE / sizeof(u8), }, }; EXPORT_SYMBOL_GPL(rt2800_rt2x00debug); #endif /* CONFIG_RT2X00_LIB_DEBUGFS */ int rt2800_rfkill_poll(struct rt2x00_dev *rt2x00dev) { u32 reg; if (rt2x00_rt(rt2x00dev, RT3290)) { rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL, ®); return rt2x00_get_field32(reg, WLAN_GPIO_IN_BIT0); } else { rt2800_register_read(rt2x00dev, GPIO_CTRL, ®); return rt2x00_get_field32(reg, GPIO_CTRL_VAL2); } } EXPORT_SYMBOL_GPL(rt2800_rfkill_poll); #ifdef CONFIG_RT2X00_LIB_LEDS static void rt2800_brightness_set(struct led_classdev *led_cdev, enum led_brightness brightness) { struct rt2x00_led *led = container_of(led_cdev, struct rt2x00_led, led_dev); unsigned int enabled = brightness != LED_OFF; unsigned int bg_mode = (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ); unsigned int polarity = rt2x00_get_field16(led->rt2x00dev->led_mcu_reg, EEPROM_FREQ_LED_POLARITY); unsigned int ledmode = rt2x00_get_field16(led->rt2x00dev->led_mcu_reg, EEPROM_FREQ_LED_MODE); u32 reg; /* Check for SoC (SOC devices don't support MCU requests) */ if (rt2x00_is_soc(led->rt2x00dev)) { rt2800_register_read(led->rt2x00dev, LED_CFG, ®); /* Set LED Polarity */ rt2x00_set_field32(®, LED_CFG_LED_POLAR, polarity); /* Set LED Mode */ if (led->type == LED_TYPE_RADIO) { rt2x00_set_field32(®, LED_CFG_G_LED_MODE, enabled ? 3 : 0); } else if (led->type == LED_TYPE_ASSOC) { rt2x00_set_field32(®, LED_CFG_Y_LED_MODE, enabled ? 3 : 0); } else if (led->type == LED_TYPE_QUALITY) { rt2x00_set_field32(®, LED_CFG_R_LED_MODE, enabled ? 3 : 0); } rt2800_register_write(led->rt2x00dev, LED_CFG, reg); } else { if (led->type == LED_TYPE_RADIO) { rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode, enabled ? 0x20 : 0); } else if (led->type == LED_TYPE_ASSOC) { rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode, enabled ? (bg_mode ? 0x60 : 0xa0) : 0x20); } else if (led->type == LED_TYPE_QUALITY) { /* * The brightness is divided into 6 levels (0 - 5), * The specs tell us the following levels: * 0, 1 ,3, 7, 15, 31 * to determine the level in a simple way we can simply * work with bitshifting: * (1 << level) - 1 */ rt2800_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff, (1 << brightness / (LED_FULL / 6)) - 1, polarity); } } } static void rt2800_init_led(struct rt2x00_dev *rt2x00dev, struct rt2x00_led *led, enum led_type type) { led->rt2x00dev = rt2x00dev; led->type = type; led->led_dev.brightness_set = rt2800_brightness_set; led->flags = LED_INITIALIZED; } #endif /* CONFIG_RT2X00_LIB_LEDS */ /* * Configuration handlers. */ static void rt2800_config_wcid(struct rt2x00_dev *rt2x00dev, const u8 *address, int wcid) { struct mac_wcid_entry wcid_entry; u32 offset; offset = MAC_WCID_ENTRY(wcid); memset(&wcid_entry, 0xff, sizeof(wcid_entry)); if (address) memcpy(wcid_entry.mac, address, ETH_ALEN); rt2800_register_multiwrite(rt2x00dev, offset, &wcid_entry, sizeof(wcid_entry)); } static void rt2800_delete_wcid_attr(struct rt2x00_dev *rt2x00dev, int wcid) { u32 offset; offset = MAC_WCID_ATTR_ENTRY(wcid); rt2800_register_write(rt2x00dev, offset, 0); } static void rt2800_config_wcid_attr_bssidx(struct rt2x00_dev *rt2x00dev, int wcid, u32 bssidx) { u32 offset = MAC_WCID_ATTR_ENTRY(wcid); u32 reg; /* * The BSS Idx numbers is split in a main value of 3 bits, * and a extended field for adding one additional bit to the value. */ rt2800_register_read(rt2x00dev, offset, ®); rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_BSS_IDX, (bssidx & 0x7)); rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_BSS_IDX_EXT, (bssidx & 0x8) >> 3); rt2800_register_write(rt2x00dev, offset, reg); } static void rt2800_config_wcid_attr_cipher(struct rt2x00_dev *rt2x00dev, struct rt2x00lib_crypto *crypto, struct ieee80211_key_conf *key) { struct mac_iveiv_entry iveiv_entry; u32 offset; u32 reg; offset = MAC_WCID_ATTR_ENTRY(key->hw_key_idx); if (crypto->cmd == SET_KEY) { rt2800_register_read(rt2x00dev, offset, ®); rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_KEYTAB, !!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)); /* * Both the cipher as the BSS Idx numbers are split in a main * value of 3 bits, and a extended field for adding one additional * bit to the value. */ rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_CIPHER, (crypto->cipher & 0x7)); rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_CIPHER_EXT, (crypto->cipher & 0x8) >> 3); rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_RX_WIUDF, crypto->cipher); rt2800_register_write(rt2x00dev, offset, reg); } else { /* Delete the cipher without touching the bssidx */ rt2800_register_read(rt2x00dev, offset, ®); rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_KEYTAB, 0); rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_CIPHER, 0); rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_CIPHER_EXT, 0); rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_RX_WIUDF, 0); rt2800_register_write(rt2x00dev, offset, reg); } offset = MAC_IVEIV_ENTRY(key->hw_key_idx); memset(&iveiv_entry, 0, sizeof(iveiv_entry)); if ((crypto->cipher == CIPHER_TKIP) || (crypto->cipher == CIPHER_TKIP_NO_MIC) || (crypto->cipher == CIPHER_AES)) iveiv_entry.iv[3] |= 0x20; iveiv_entry.iv[3] |= key->keyidx << 6; rt2800_register_multiwrite(rt2x00dev, offset, &iveiv_entry, sizeof(iveiv_entry)); } int rt2800_config_shared_key(struct rt2x00_dev *rt2x00dev, struct rt2x00lib_crypto *crypto, struct ieee80211_key_conf *key) { struct hw_key_entry key_entry; struct rt2x00_field32 field; u32 offset; u32 reg; if (crypto->cmd == SET_KEY) { key->hw_key_idx = (4 * crypto->bssidx) + key->keyidx; memcpy(key_entry.key, crypto->key, sizeof(key_entry.key)); memcpy(key_entry.tx_mic, crypto->tx_mic, sizeof(key_entry.tx_mic)); memcpy(key_entry.rx_mic, crypto->rx_mic, sizeof(key_entry.rx_mic)); offset = SHARED_KEY_ENTRY(key->hw_key_idx); rt2800_register_multiwrite(rt2x00dev, offset, &key_entry, sizeof(key_entry)); } /* * The cipher types are stored over multiple registers * starting with SHARED_KEY_MODE_BASE each word will have * 32 bits and contains the cipher types for 2 bssidx each. * Using the correct defines correctly will cause overhead, * so just calculate the correct offset. */ field.bit_offset = 4 * (key->hw_key_idx % 8); field.bit_mask = 0x7 << field.bit_offset; offset = SHARED_KEY_MODE_ENTRY(key->hw_key_idx / 8); rt2800_register_read(rt2x00dev, offset, ®); rt2x00_set_field32(®, field, (crypto->cmd == SET_KEY) * crypto->cipher); rt2800_register_write(rt2x00dev, offset, reg); /* * Update WCID information */ rt2800_config_wcid(rt2x00dev, crypto->address, key->hw_key_idx); rt2800_config_wcid_attr_bssidx(rt2x00dev, key->hw_key_idx, crypto->bssidx); rt2800_config_wcid_attr_cipher(rt2x00dev, crypto, key); return 0; } EXPORT_SYMBOL_GPL(rt2800_config_shared_key); static inline int rt2800_find_wcid(struct rt2x00_dev *rt2x00dev) { struct mac_wcid_entry wcid_entry; int idx; u32 offset; /* * Search for the first free WCID entry and return the corresponding * index. * * Make sure the WCID starts _after_ the last possible shared key * entry (>32). * * Since parts of the pairwise key table might be shared with * the beacon frame buffers 6 & 7 we should only write into the * first 222 entries. */ for (idx = 33; idx <= 222; idx++) { offset = MAC_WCID_ENTRY(idx); rt2800_register_multiread(rt2x00dev, offset, &wcid_entry, sizeof(wcid_entry)); if (is_broadcast_ether_addr(wcid_entry.mac)) return idx; } /* * Use -1 to indicate that we don't have any more space in the WCID * table. */ return -1; } int rt2800_config_pairwise_key(struct rt2x00_dev *rt2x00dev, struct rt2x00lib_crypto *crypto, struct ieee80211_key_conf *key) { struct hw_key_entry key_entry; u32 offset; if (crypto->cmd == SET_KEY) { /* * Allow key configuration only for STAs that are * known by the hw. */ if (crypto->wcid < 0) return -ENOSPC; key->hw_key_idx = crypto->wcid; memcpy(key_entry.key, crypto->key, sizeof(key_entry.key)); memcpy(key_entry.tx_mic, crypto->tx_mic, sizeof(key_entry.tx_mic)); memcpy(key_entry.rx_mic, crypto->rx_mic, sizeof(key_entry.rx_mic)); offset = PAIRWISE_KEY_ENTRY(key->hw_key_idx); rt2800_register_multiwrite(rt2x00dev, offset, &key_entry, sizeof(key_entry)); } /* * Update WCID information */ rt2800_config_wcid_attr_cipher(rt2x00dev, crypto, key); return 0; } EXPORT_SYMBOL_GPL(rt2800_config_pairwise_key); int rt2800_sta_add(struct rt2x00_dev *rt2x00dev, struct ieee80211_vif *vif, struct ieee80211_sta *sta) { int wcid; struct rt2x00_sta *sta_priv = sta_to_rt2x00_sta(sta); /* * Find next free WCID. */ wcid = rt2800_find_wcid(rt2x00dev); /* * Store selected wcid even if it is invalid so that we can * later decide if the STA is uploaded into the hw. */ sta_priv->wcid = wcid; /* * No space left in the device, however, we can still communicate * with the STA -> No error. */ if (wcid < 0) return 0; /* * Clean up WCID attributes and write STA address to the device. */ rt2800_delete_wcid_attr(rt2x00dev, wcid); rt2800_config_wcid(rt2x00dev, sta->addr, wcid); rt2800_config_wcid_attr_bssidx(rt2x00dev, wcid, rt2x00lib_get_bssidx(rt2x00dev, vif)); return 0; } EXPORT_SYMBOL_GPL(rt2800_sta_add); int rt2800_sta_remove(struct rt2x00_dev *rt2x00dev, int wcid) { /* * Remove WCID entry, no need to clean the attributes as they will * get renewed when the WCID is reused. */ rt2800_config_wcid(rt2x00dev, NULL, wcid); return 0; } EXPORT_SYMBOL_GPL(rt2800_sta_remove); void rt2800_config_filter(struct rt2x00_dev *rt2x00dev, const unsigned int filter_flags) { u32 reg; /* * Start configuration steps. * Note that the version error will always be dropped * and broadcast frames will always be accepted since * there is no filter for it at this time. */ rt2800_register_read(rt2x00dev, RX_FILTER_CFG, ®); rt2x00_set_field32(®, RX_FILTER_CFG_DROP_CRC_ERROR, !(filter_flags & FIF_FCSFAIL)); rt2x00_set_field32(®, RX_FILTER_CFG_DROP_PHY_ERROR, !(filter_flags & FIF_PLCPFAIL)); rt2x00_set_field32(®, RX_FILTER_CFG_DROP_NOT_TO_ME, !(filter_flags & FIF_PROMISC_IN_BSS)); rt2x00_set_field32(®, RX_FILTER_CFG_DROP_NOT_MY_BSSD, 0); rt2x00_set_field32(®, RX_FILTER_CFG_DROP_VER_ERROR, 1); rt2x00_set_field32(®, RX_FILTER_CFG_DROP_MULTICAST, !(filter_flags & FIF_ALLMULTI)); rt2x00_set_field32(®, RX_FILTER_CFG_DROP_BROADCAST, 0); rt2x00_set_field32(®, RX_FILTER_CFG_DROP_DUPLICATE, 1); rt2x00_set_field32(®, RX_FILTER_CFG_DROP_CF_END_ACK, !(filter_flags & FIF_CONTROL)); rt2x00_set_field32(®, RX_FILTER_CFG_DROP_CF_END, !(filter_flags & FIF_CONTROL)); rt2x00_set_field32(®, RX_FILTER_CFG_DROP_ACK, !(filter_flags & FIF_CONTROL)); rt2x00_set_field32(®, RX_FILTER_CFG_DROP_CTS, !(filter_flags & FIF_CONTROL)); rt2x00_set_field32(®, RX_FILTER_CFG_DROP_RTS, !(filter_flags & FIF_CONTROL)); rt2x00_set_field32(®, RX_FILTER_CFG_DROP_PSPOLL, !(filter_flags & FIF_PSPOLL)); rt2x00_set_field32(®, RX_FILTER_CFG_DROP_BA, 0); rt2x00_set_field32(®, RX_FILTER_CFG_DROP_BAR, !(filter_flags & FIF_CONTROL)); rt2x00_set_field32(®, RX_FILTER_CFG_DROP_CNTL, !(filter_flags & FIF_CONTROL)); rt2800_register_write(rt2x00dev, RX_FILTER_CFG, reg); } EXPORT_SYMBOL_GPL(rt2800_config_filter); void rt2800_config_intf(struct rt2x00_dev *rt2x00dev, struct rt2x00_intf *intf, struct rt2x00intf_conf *conf, const unsigned int flags) { u32 reg; bool update_bssid = false; if (flags & CONFIG_UPDATE_TYPE) { /* * Enable synchronisation. */ rt2800_register_read(rt2x00dev, BCN_TIME_CFG, ®); rt2x00_set_field32(®, BCN_TIME_CFG_TSF_SYNC, conf->sync); rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg); if (conf->sync == TSF_SYNC_AP_NONE) { /* * Tune beacon queue transmit parameters for AP mode */ rt2800_register_read(rt2x00dev, TBTT_SYNC_CFG, ®); rt2x00_set_field32(®, TBTT_SYNC_CFG_BCN_CWMIN, 0); rt2x00_set_field32(®, TBTT_SYNC_CFG_BCN_AIFSN, 1); rt2x00_set_field32(®, TBTT_SYNC_CFG_BCN_EXP_WIN, 32); rt2x00_set_field32(®, TBTT_SYNC_CFG_TBTT_ADJUST, 0); rt2800_register_write(rt2x00dev, TBTT_SYNC_CFG, reg); } else { rt2800_register_read(rt2x00dev, TBTT_SYNC_CFG, ®); rt2x00_set_field32(®, TBTT_SYNC_CFG_BCN_CWMIN, 4); rt2x00_set_field32(®, TBTT_SYNC_CFG_BCN_AIFSN, 2); rt2x00_set_field32(®, TBTT_SYNC_CFG_BCN_EXP_WIN, 32); rt2x00_set_field32(®, TBTT_SYNC_CFG_TBTT_ADJUST, 16); rt2800_register_write(rt2x00dev, TBTT_SYNC_CFG, reg); } } if (flags & CONFIG_UPDATE_MAC) { if (flags & CONFIG_UPDATE_TYPE && conf->sync == TSF_SYNC_AP_NONE) { /* * The BSSID register has to be set to our own mac * address in AP mode. */ memcpy(conf->bssid, conf->mac, sizeof(conf->mac)); update_bssid = true; } if (!is_zero_ether_addr((const u8 *)conf->mac)) { reg = le32_to_cpu(conf->mac[1]); rt2x00_set_field32(®, MAC_ADDR_DW1_UNICAST_TO_ME_MASK, 0xff); conf->mac[1] = cpu_to_le32(reg); } rt2800_register_multiwrite(rt2x00dev, MAC_ADDR_DW0, conf->mac, sizeof(conf->mac)); } if ((flags & CONFIG_UPDATE_BSSID) || update_bssid) { if (!is_zero_ether_addr((const u8 *)conf->bssid)) { reg = le32_to_cpu(conf->bssid[1]); rt2x00_set_field32(®, MAC_BSSID_DW1_BSS_ID_MASK, 3); rt2x00_set_field32(®, MAC_BSSID_DW1_BSS_BCN_NUM, 7); conf->bssid[1] = cpu_to_le32(reg); } rt2800_register_multiwrite(rt2x00dev, MAC_BSSID_DW0, conf->bssid, sizeof(conf->bssid)); } } EXPORT_SYMBOL_GPL(rt2800_config_intf); static void rt2800_config_ht_opmode(struct rt2x00_dev *rt2x00dev, struct rt2x00lib_erp *erp) { bool any_sta_nongf = !!(erp->ht_opmode & IEEE80211_HT_OP_MODE_NON_GF_STA_PRSNT); u8 protection = erp->ht_opmode & IEEE80211_HT_OP_MODE_PROTECTION; u8 mm20_mode, mm40_mode, gf20_mode, gf40_mode; u16 mm20_rate, mm40_rate, gf20_rate, gf40_rate; u32 reg; /* default protection rate for HT20: OFDM 24M */ mm20_rate = gf20_rate = 0x4004; /* default protection rate for HT40: duplicate OFDM 24M */ mm40_rate = gf40_rate = 0x4084; switch (protection) { case IEEE80211_HT_OP_MODE_PROTECTION_NONE: /* * All STAs in this BSS are HT20/40 but there might be * STAs not supporting greenfield mode. * => Disable protection for HT transmissions. */ mm20_mode = mm40_mode = gf20_mode = gf40_mode = 0; break; case IEEE80211_HT_OP_MODE_PROTECTION_20MHZ: /* * All STAs in this BSS are HT20 or HT20/40 but there * might be STAs not supporting greenfield mode. * => Protect all HT40 transmissions. */ mm20_mode = gf20_mode = 0; mm40_mode = gf40_mode = 2; break; case IEEE80211_HT_OP_MODE_PROTECTION_NONMEMBER: /* * Nonmember protection: * According to 802.11n we _should_ protect all * HT transmissions (but we don't have to). * * But if cts_protection is enabled we _shall_ protect * all HT transmissions using a CCK rate. * * And if any station is non GF we _shall_ protect * GF transmissions. * * We decide to protect everything * -> fall through to mixed mode. */ case IEEE80211_HT_OP_MODE_PROTECTION_NONHT_MIXED: /* * Legacy STAs are present * => Protect all HT transmissions. */ mm20_mode = mm40_mode = gf20_mode = gf40_mode = 2; /* * If erp protection is needed we have to protect HT * transmissions with CCK 11M long preamble. */ if (erp->cts_protection) { /* don't duplicate RTS/CTS in CCK mode */ mm20_rate = mm40_rate = 0x0003; gf20_rate = gf40_rate = 0x0003; } break; } /* check for STAs not supporting greenfield mode */ if (any_sta_nongf) gf20_mode = gf40_mode = 2; /* Update HT protection config */ rt2800_register_read(rt2x00dev, MM20_PROT_CFG, ®); rt2x00_set_field32(®, MM20_PROT_CFG_PROTECT_RATE, mm20_rate); rt2x00_set_field32(®, MM20_PROT_CFG_PROTECT_CTRL, mm20_mode); rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg); rt2800_register_read(rt2x00dev, MM40_PROT_CFG, ®); rt2x00_set_field32(®, MM40_PROT_CFG_PROTECT_RATE, mm40_rate); rt2x00_set_field32(®, MM40_PROT_CFG_PROTECT_CTRL, mm40_mode); rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg); rt2800_register_read(rt2x00dev, GF20_PROT_CFG, ®); rt2x00_set_field32(®, GF20_PROT_CFG_PROTECT_RATE, gf20_rate); rt2x00_set_field32(®, GF20_PROT_CFG_PROTECT_CTRL, gf20_mode); rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg); rt2800_register_read(rt2x00dev, GF40_PROT_CFG, ®); rt2x00_set_field32(®, GF40_PROT_CFG_PROTECT_RATE, gf40_rate); rt2x00_set_field32(®, GF40_PROT_CFG_PROTECT_CTRL, gf40_mode); rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg); } void rt2800_config_erp(struct rt2x00_dev *rt2x00dev, struct rt2x00lib_erp *erp, u32 changed) { u32 reg; if (changed & BSS_CHANGED_ERP_PREAMBLE) { rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, ®); rt2x00_set_field32(®, AUTO_RSP_CFG_BAC_ACK_POLICY, !!erp->short_preamble); rt2x00_set_field32(®, AUTO_RSP_CFG_AR_PREAMBLE, !!erp->short_preamble); rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg); } if (changed & BSS_CHANGED_ERP_CTS_PROT) { rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, ®); rt2x00_set_field32(®, OFDM_PROT_CFG_PROTECT_CTRL, erp->cts_protection ? 2 : 0); rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg); } if (changed & BSS_CHANGED_BASIC_RATES) { rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE, erp->basic_rates); rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003); } if (changed & BSS_CHANGED_ERP_SLOT) { rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, ®); rt2x00_set_field32(®, BKOFF_SLOT_CFG_SLOT_TIME, erp->slot_time); rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg); rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, ®); rt2x00_set_field32(®, XIFS_TIME_CFG_EIFS, erp->eifs); rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg); } if (changed & BSS_CHANGED_BEACON_INT) { rt2800_register_read(rt2x00dev, BCN_TIME_CFG, ®); rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_INTERVAL, erp->beacon_int * 16); rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg); } if (changed & BSS_CHANGED_HT) rt2800_config_ht_opmode(rt2x00dev, erp); } EXPORT_SYMBOL_GPL(rt2800_config_erp); static void rt2800_config_3572bt_ant(struct rt2x00_dev *rt2x00dev) { u32 reg; u16 eeprom; u8 led_ctrl, led_g_mode, led_r_mode; rt2800_register_read(rt2x00dev, GPIO_SWITCH, ®); if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) { rt2x00_set_field32(®, GPIO_SWITCH_0, 1); rt2x00_set_field32(®, GPIO_SWITCH_1, 1); } else { rt2x00_set_field32(®, GPIO_SWITCH_0, 0); rt2x00_set_field32(®, GPIO_SWITCH_1, 0); } rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg); rt2800_register_read(rt2x00dev, LED_CFG, ®); led_g_mode = rt2x00_get_field32(reg, LED_CFG_LED_POLAR) ? 3 : 0; led_r_mode = rt2x00_get_field32(reg, LED_CFG_LED_POLAR) ? 0 : 3; if (led_g_mode != rt2x00_get_field32(reg, LED_CFG_G_LED_MODE) || led_r_mode != rt2x00_get_field32(reg, LED_CFG_R_LED_MODE)) { rt2800_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom); led_ctrl = rt2x00_get_field16(eeprom, EEPROM_FREQ_LED_MODE); if (led_ctrl == 0 || led_ctrl > 0x40) { rt2x00_set_field32(®, LED_CFG_G_LED_MODE, led_g_mode); rt2x00_set_field32(®, LED_CFG_R_LED_MODE, led_r_mode); rt2800_register_write(rt2x00dev, LED_CFG, reg); } else { rt2800_mcu_request(rt2x00dev, MCU_BAND_SELECT, 0xff, (led_g_mode << 2) | led_r_mode, 1); } } } static void rt2800_set_ant_diversity(struct rt2x00_dev *rt2x00dev, enum antenna ant) { u32 reg; u8 eesk_pin = (ant == ANTENNA_A) ? 1 : 0; u8 gpio_bit3 = (ant == ANTENNA_A) ? 0 : 1; if (rt2x00_is_pci(rt2x00dev)) { rt2800_register_read(rt2x00dev, E2PROM_CSR, ®); rt2x00_set_field32(®, E2PROM_CSR_DATA_CLOCK, eesk_pin); rt2800_register_write(rt2x00dev, E2PROM_CSR, reg); } else if (rt2x00_is_usb(rt2x00dev)) rt2800_mcu_request(rt2x00dev, MCU_ANT_SELECT, 0xff, eesk_pin, 0); rt2800_register_read(rt2x00dev, GPIO_CTRL, ®); rt2x00_set_field32(®, GPIO_CTRL_DIR3, 0); rt2x00_set_field32(®, GPIO_CTRL_VAL3, gpio_bit3); rt2800_register_write(rt2x00dev, GPIO_CTRL, reg); } void rt2800_config_ant(struct rt2x00_dev *rt2x00dev, struct antenna_setup *ant) { u8 r1; u8 r3; u16 eeprom; rt2800_bbp_read(rt2x00dev, 1, &r1); rt2800_bbp_read(rt2x00dev, 3, &r3); if (rt2x00_rt(rt2x00dev, RT3572) && test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags)) rt2800_config_3572bt_ant(rt2x00dev); /* * Configure the TX antenna. */ switch (ant->tx_chain_num) { case 1: rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0); break; case 2: if (rt2x00_rt(rt2x00dev, RT3572) && test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags)) rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 1); else rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2); break; case 3: rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2); break; } /* * Configure the RX antenna. */ switch (ant->rx_chain_num) { case 1: if (rt2x00_rt(rt2x00dev, RT3070) || rt2x00_rt(rt2x00dev, RT3090) || rt2x00_rt(rt2x00dev, RT3352) || rt2x00_rt(rt2x00dev, RT3390)) { rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom); if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_ANT_DIVERSITY)) rt2800_set_ant_diversity(rt2x00dev, rt2x00dev->default_ant.rx); } rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0); break; case 2: if (rt2x00_rt(rt2x00dev, RT3572) && test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags)) { rt2x00_set_field8(&r3, BBP3_RX_ADC, 1); rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, rt2x00dev->curr_band == IEEE80211_BAND_5GHZ); rt2800_set_ant_diversity(rt2x00dev, ANTENNA_B); } else { rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 1); } break; case 3: rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 2); break; } rt2800_bbp_write(rt2x00dev, 3, r3); rt2800_bbp_write(rt2x00dev, 1, r1); if (rt2x00_rt(rt2x00dev, RT3593)) { if (ant->rx_chain_num == 1) rt2800_bbp_write(rt2x00dev, 86, 0x00); else rt2800_bbp_write(rt2x00dev, 86, 0x46); } } EXPORT_SYMBOL_GPL(rt2800_config_ant); static void rt2800_config_lna_gain(struct rt2x00_dev *rt2x00dev, struct rt2x00lib_conf *libconf) { u16 eeprom; short lna_gain; if (libconf->rf.channel <= 14) { rt2800_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom); lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_BG); } else if (libconf->rf.channel <= 64) { rt2800_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom); lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_A0); } else if (libconf->rf.channel <= 128) { if (rt2x00_rt(rt2x00dev, RT3593)) { rt2800_eeprom_read(rt2x00dev, EEPROM_EXT_LNA2, &eeprom); lna_gain = rt2x00_get_field16(eeprom, EEPROM_EXT_LNA2_A1); } else { rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom); lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_LNA_A1); } } else { if (rt2x00_rt(rt2x00dev, RT3593)) { rt2800_eeprom_read(rt2x00dev, EEPROM_EXT_LNA2, &eeprom); lna_gain = rt2x00_get_field16(eeprom, EEPROM_EXT_LNA2_A2); } else { rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom); lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_LNA_A2); } } rt2x00dev->lna_gain = lna_gain; } #define FREQ_OFFSET_BOUND 0x5f static void rt2800_adjust_freq_offset(struct rt2x00_dev *rt2x00dev) { u8 freq_offset, prev_freq_offset; u8 rfcsr, prev_rfcsr; freq_offset = rt2x00_get_field8(rt2x00dev->freq_offset, RFCSR17_CODE); freq_offset = min_t(u8, freq_offset, FREQ_OFFSET_BOUND); rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr); prev_rfcsr = rfcsr; rt2x00_set_field8(&rfcsr, RFCSR17_CODE, freq_offset); if (rfcsr == prev_rfcsr) return; if (rt2x00_is_usb(rt2x00dev)) { rt2800_mcu_request(rt2x00dev, MCU_FREQ_OFFSET, 0xff, freq_offset, prev_rfcsr); return; } prev_freq_offset = rt2x00_get_field8(prev_rfcsr, RFCSR17_CODE); while (prev_freq_offset != freq_offset) { if (prev_freq_offset < freq_offset) prev_freq_offset++; else prev_freq_offset--; rt2x00_set_field8(&rfcsr, RFCSR17_CODE, prev_freq_offset); rt2800_rfcsr_write(rt2x00dev, 17, rfcsr); usleep_range(1000, 1500); } } static void rt2800_config_channel_rf2xxx(struct rt2x00_dev *rt2x00dev, struct ieee80211_conf *conf, struct rf_channel *rf, struct channel_info *info) { rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset); if (rt2x00dev->default_ant.tx_chain_num == 1) rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_TX1, 1); if (rt2x00dev->default_ant.rx_chain_num == 1) { rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX1, 1); rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1); } else if (rt2x00dev->default_ant.rx_chain_num == 2) rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1); if (rf->channel > 14) { /* * When TX power is below 0, we should increase it by 7 to * make it a positive value (Minimum value is -7). * However this means that values between 0 and 7 have * double meaning, and we should set a 7DBm boost flag. */ rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A_7DBM_BOOST, (info->default_power1 >= 0)); if (info->default_power1 < 0) info->default_power1 += 7; rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A, info->default_power1); rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A_7DBM_BOOST, (info->default_power2 >= 0)); if (info->default_power2 < 0) info->default_power2 += 7; rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A, info->default_power2); } else { rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_G, info->default_power1); rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_G, info->default_power2); } rt2x00_set_field32(&rf->rf4, RF4_HT40, conf_is_ht40(conf)); rt2800_rf_write(rt2x00dev, 1, rf->rf1); rt2800_rf_write(rt2x00dev, 2, rf->rf2); rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004); rt2800_rf_write(rt2x00dev, 4, rf->rf4); udelay(200); rt2800_rf_write(rt2x00dev, 1, rf->rf1); rt2800_rf_write(rt2x00dev, 2, rf->rf2); rt2800_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004); rt2800_rf_write(rt2x00dev, 4, rf->rf4); udelay(200); rt2800_rf_write(rt2x00dev, 1, rf->rf1); rt2800_rf_write(rt2x00dev, 2, rf->rf2); rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004); rt2800_rf_write(rt2x00dev, 4, rf->rf4); } static void rt2800_config_channel_rf3xxx(struct rt2x00_dev *rt2x00dev, struct ieee80211_conf *conf, struct rf_channel *rf, struct channel_info *info) { struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; u8 rfcsr, calib_tx, calib_rx; rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1); rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr); rt2x00_set_field8(&rfcsr, RFCSR3_K, rf->rf3); rt2800_rfcsr_write(rt2x00dev, 3, rfcsr); rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr); rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2); rt2800_rfcsr_write(rt2x00dev, 6, rfcsr); rt2800_rfcsr_read(rt2x00dev, 12, &rfcsr); rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER, info->default_power1); rt2800_rfcsr_write(rt2x00dev, 12, rfcsr); rt2800_rfcsr_read(rt2x00dev, 13, &rfcsr); rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER, info->default_power2); rt2800_rfcsr_write(rt2x00dev, 13, rfcsr); rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr); rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0); rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, rt2x00dev->default_ant.rx_chain_num <= 1); rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, rt2x00dev->default_ant.rx_chain_num <= 2); rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0); rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, rt2x00dev->default_ant.tx_chain_num <= 1); rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, rt2x00dev->default_ant.tx_chain_num <= 2); rt2800_rfcsr_write(rt2x00dev, 1, rfcsr); rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr); rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1); rt2800_rfcsr_write(rt2x00dev, 30, rfcsr); msleep(1); rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0); rt2800_rfcsr_write(rt2x00dev, 30, rfcsr); rt2800_rfcsr_read(rt2x00dev, 23, &rfcsr); rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset); rt2800_rfcsr_write(rt2x00dev, 23, rfcsr); if (rt2x00_rt(rt2x00dev, RT3390)) { calib_tx = conf_is_ht40(conf) ? 0x68 : 0x4f; calib_rx = conf_is_ht40(conf) ? 0x6f : 0x4f; } else { if (conf_is_ht40(conf)) { calib_tx = drv_data->calibration_bw40; calib_rx = drv_data->calibration_bw40; } else { calib_tx = drv_data->calibration_bw20; calib_rx = drv_data->calibration_bw20; } } rt2800_rfcsr_read(rt2x00dev, 24, &rfcsr); rt2x00_set_field8(&rfcsr, RFCSR24_TX_CALIB, calib_tx); rt2800_rfcsr_write(rt2x00dev, 24, rfcsr); rt2800_rfcsr_read(rt2x00dev, 31, &rfcsr); rt2x00_set_field8(&rfcsr, RFCSR31_RX_CALIB, calib_rx); rt2800_rfcsr_write(rt2x00dev, 31, rfcsr); rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr); rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1); rt2800_rfcsr_write(rt2x00dev, 7, rfcsr); rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr); rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1); rt2800_rfcsr_write(rt2x00dev, 30, rfcsr); msleep(1); rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0); rt2800_rfcsr_write(rt2x00dev, 30, rfcsr); } static void rt2800_config_channel_rf3052(struct rt2x00_dev *rt2x00dev, struct ieee80211_conf *conf, struct rf_channel *rf, struct channel_info *info) { struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; u8 rfcsr; u32 reg; if (rf->channel <= 14) { rt2800_bbp_write(rt2x00dev, 25, drv_data->bbp25); rt2800_bbp_write(rt2x00dev, 26, drv_data->bbp26); } else { rt2800_bbp_write(rt2x00dev, 25, 0x09); rt2800_bbp_write(rt2x00dev, 26, 0xff); } rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1); rt2800_rfcsr_write(rt2x00dev, 3, rf->rf3); rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr); rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2); if (rf->channel <= 14) rt2x00_set_field8(&rfcsr, RFCSR6_TXDIV, 2); else rt2x00_set_field8(&rfcsr, RFCSR6_TXDIV, 1); rt2800_rfcsr_write(rt2x00dev, 6, rfcsr); rt2800_rfcsr_read(rt2x00dev, 5, &rfcsr); if (rf->channel <= 14) rt2x00_set_field8(&rfcsr, RFCSR5_R1, 1); else rt2x00_set_field8(&rfcsr, RFCSR5_R1, 2); rt2800_rfcsr_write(rt2x00dev, 5, rfcsr); rt2800_rfcsr_read(rt2x00dev, 12, &rfcsr); if (rf->channel <= 14) { rt2x00_set_field8(&rfcsr, RFCSR12_DR0, 3); rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER, info->default_power1); } else { rt2x00_set_field8(&rfcsr, RFCSR12_DR0, 7); rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER, (info->default_power1 & 0x3) | ((info->default_power1 & 0xC) << 1)); } rt2800_rfcsr_write(rt2x00dev, 12, rfcsr); rt2800_rfcsr_read(rt2x00dev, 13, &rfcsr); if (rf->channel <= 14) { rt2x00_set_field8(&rfcsr, RFCSR13_DR0, 3); rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER, info->default_power2); } else { rt2x00_set_field8(&rfcsr, RFCSR13_DR0, 7); rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER, (info->default_power2 & 0x3) | ((info->default_power2 & 0xC) << 1)); } rt2800_rfcsr_write(rt2x00dev, 13, rfcsr); rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr); rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0); rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0); rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0); rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0); rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0); rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0); if (test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags)) { if (rf->channel <= 14) { rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1); rt2x00_set