/* * Device Tree Include file for Marvell Armada 1500 (Berlin BG2) SoC * * Sebastian Hesselbarth * * based on GPL'ed 2.6 kernel sources * (c) Marvell International Ltd. * * This file is licensed under the terms of the GNU General Public * License version 2. This program is licensed "as is" without any * warranty of any kind, whether express or implied. */ #include "skeleton.dtsi" #include #include / { model = "Marvell Armada 1500 (BG2) SoC"; compatible = "marvell,berlin2", "marvell,berlin"; cpus { #address-cells = <1>; #size-cells = <0>; cpu@0 { compatible = "marvell,pj4b"; device_type = "cpu"; next-level-cache = <&l2>; reg = <0>; }; cpu@1 { compatible = "marvell,pj4b"; device_type = "cpu"; next-level-cache = <&l2>; reg = <1>; }; }; refclk: oscillator { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <25000000>; }; soc { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; interrupt-parent = <&gic>; ranges = <0 0xf7000000 0x1000000>; l2: l2-cache-controller@ac0000 { compatible = "marvell,tauros3-cache", "arm,pl310-cache"; reg = <0xac0000 0x1000>; cache-unified; cache-level = <2>; }; scu: snoop-control-unit@ad0000 { compatible = "arm,cortex-a9-scu"; reg = <0xad0000 0x58>; }; gic: interrupt-controller@ad1000 { compatible = "arm,cortex-a9-gic"; reg = <0xad1000 0x1000>, <0xad0100 0x0100>; interrupt-controller; #interrupt-cells = <3>; }; local-timer@ad0600 { compatible = "arm,cortex-a9-twd-timer"; reg = <0xad0600 0x20>; interrupts = ; clocks = <&chip CLKID_TWD>; }; apb@e80000 { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges = <0 0xe80000 0x10000>; interrupt-parent = <&aic>; gpio0: gpio@0400 { compatible = "snps,dw-apb-gpio"; reg = <0x0400 0x400>; #address-cells = <1>; #size-cells = <0>; porta: gpio-port@0 { compatible = "snps,dw-apb-gpio-port"; gpio-controller; #gpio-cells = <2>; snps,nr-gpios = <8>; reg = <0>; interrupt-controller; #interrupt-cells = <2>; interrupts = <0>; }; }; gpio1: gpio@0800 { compatible = "snps,dw-apb-gpio"; reg = <0x0800 0x400>; #address-cells = <1>; #size-cells = <0>; portb: gpio-port@1 { compatible = "snps,dw-apb-gpio-port"; gpio-controller; #gpio-cells = <2>; snps,nr-gpios = <8>; reg = <0>; interrupt-controller; #interrupt-cells = <2>; interrupts = <1>; }; }; gpio2: gpio@0c00 { compatible = "snps,dw-apb-gpio"; reg = <0x0c00 0x400>; #address-cells = <1>; #size-cells = <0>; portc: gpio-port@2 { compatible = "snps,dw-apb-gpio-port"; gpio-controller; #gpio-cells = <2>; snps,nr-gpios = <8>; reg = <0>; interrupt-controller; #interrupt-cells = <2>; interrupts = <2>; }; }; gpio3: gpio@1000 { compatible = "snps,dw-apb-gpio"; reg = <0x1000 0x400>; #address-cells = <1>; #size-cells = <0>; portd: gpio-port@3 { compatible = "snps,dw-apb-gpio-port"; gpio-controller; #gpio-cells = <2>; snps,nr-gpios = <8>; reg = <0>; interrupt-controller; #interrupt-cells = <2>; interrupts = <3>; }; }; timer0: timer@2c00 { compatible = "snps,dw-apb-timer"; reg = <0x2c00 0x14>; interrupts = <8>; clocks = <&chip CLKID_CFG>; clock-names = "timer"; status = "okay"; }; timer1: timer@2c14 { compatible = "snps,dw-apb-timer"; reg = <0x2c14 0x14>; interrupts = <9>; clocks = <&chip CLKID_CFG>; clock-names = "timer"; status = "okay"; }; timer2: timer@2c28 { compatible = "snps,dw-apb-timer"; reg = <0x2c28 0x14>; interrupts = <10>; clocks = <&chip CLKID_CFG>; clock-names = "timer"; status = "disabled"; }; timer3: timer@2c3c { compatible = "snps,dw-apb-timer"; reg = <0x2c3c 0x14>; interrupts = <11>; clocks = <&chip CLKID_CFG>; clock-names = "timer"; status = "disabled"; }; timer4: timer@2c50 { compatible = "snps,dw-apb-timer"; reg = <0x2c50 0x14>; interrupts = <12>; clocks = <&chip CLKID_CFG>; clock-names = "timer"; status = "disabled"; }; timer5: timer@2c64 { compatible = "snps,dw-apb-timer"; reg = <0x2c64 0x14>; interrupts = <13>; clocks = <&chip CLKID_CFG>; clock-names = "timer"; status = "disabled"; }; timer6: timer@2c78 { compatible = "snps,dw-apb-timer"; reg = <0x2c78 0x14>; interrupts = <14>; clocks = <&chip CLKID_CFG>; clock-names = "timer"; status = "disabled"; }; timer7: timer@2c8c { compatible = "snps,dw-apb-timer"; reg = <0x2c8c 0x14>; interrupts = <15>; clocks = <&chip CLKID_CFG>; clock-names = "timer"; status = "disabled"; }; aic: interrupt-controller@3000 { compatible = "snps,dw-apb-ictl"; reg = <0x3000 0xc00>; interrupt-controller; #interrupt-cells = <1>; interrupt-parent = <&gic>; interrupts = ; }; }; chip: chip-control@ea0000 { compatible = "marvell,berlin2-chip-ctrl"; #clock-cells = <1>; reg = <0xea0000 0x400>; clocks = <&refclk>; clock-names = "refclk"; }; apb@fc0000 { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges = <0 0xfc0000 0x10000>; interrupt-parent = <&sic>; sm_gpio1: gpio@5000 { compatible = "snps,dw-apb-gpio"; reg = <0x5000 0x400>; #address-cells = <1>; #size-cells = <0>; portf: gpio-port@5 { compatible = "snps,dw-apb-gpio-port"; gpio-controller; #gpio-cells = <2>; snps,nr-gpios = <8>; reg = <0>; }; }; sm_gpio0: gpio@c000 { compatible = "snps,dw-apb-gpio"; reg = <0xc000 0x400>; #address-cells = <1>; #size-cells = <0>; porte: gpio-port@4 { compatible = "snps,dw-apb-gpio-port"; gpio-controller; #gpio-cells = <2>; snps,nr-gpios = <8>; reg = <0>; interrupt-controller; #interrupt-cells = <2>; interrupts = <11>; }; }; uart0: serial@9000 { compatible = "snps,dw-apb-uart"; reg = <0x9000 0x100>; reg-shift = <2>; reg-io-width = <1>; interrupts = <8>; clocks = <&refclk>; status = "disabled"; }; uart1: serial@a000 { compatible = "snps,dw-apb-uart"; reg = <0xa000 0x100>; reg-shift = <2>; reg-io-width = <1>; interrupts = <9>; clocks = <&refclk>; status = "disabled"; }; uart2: serial@b000 { compatible = "snps,dw-apb-uart"; reg = <0xb000 0x100>; reg-shift = <2>; reg-io-width = <1>; interrupts = <10>; clocks = <&refclk>; status = "disabled"; }; sic: interrupt-controller@e000 { compatible = "snps,dw-apb-ictl"; reg = <0xe000 0x400>; interrupt-controller; #interrupt-cells = <1>; interrupt-parent = <&gic>; interrupts = ; }; }; }; };