From 6f4bc952c60b26ecfcb013fb9a7e9474023e046e Mon Sep 17 00:00:00 2001 From: "Arnaud Patard (Rtp)" Date: Thu, 21 Oct 2010 19:40:02 +0200 Subject: ASoC: add support for alc562[123] codecs This patch is adding support for alc562[123] codecs. It's based on the source code available in HP source code and other places. Signed-off-by: Arnaud Patard Acked-by: Liam Girdwood Signed-off-by: Mark Brown --- sound/soc/codecs/Kconfig | 5 + sound/soc/codecs/Makefile | 2 + sound/soc/codecs/alc5623.c | 1118 ++++++++++++++++++++++++++++++++++++++++++++ sound/soc/codecs/alc5623.h | 161 +++++++ 4 files changed, 1286 insertions(+) create mode 100644 sound/soc/codecs/alc5623.c create mode 100644 sound/soc/codecs/alc5623.h (limited to 'sound/soc/codecs') diff --git a/sound/soc/codecs/Kconfig b/sound/soc/codecs/Kconfig index 94a9d06b9027..658cbe07fb72 100644 --- a/sound/soc/codecs/Kconfig +++ b/sound/soc/codecs/Kconfig @@ -22,6 +22,7 @@ config SND_SOC_ALL_CODECS select SND_SOC_AK4535 if I2C select SND_SOC_AK4642 if I2C select SND_SOC_AK4671 if I2C + select SND_SOC_ALC562 if I2C select SND_SOC_CQ0093VC if MFD_DAVINCI_VOICECODEC select SND_SOC_CS42L51 if I2C select SND_SOC_CS4270 if I2C @@ -129,6 +130,9 @@ config SND_SOC_AK4642 config SND_SOC_AK4671 tristate +config SND_SOC_ALC5623 + tristate + config SND_SOC_CQ0093VC tristate @@ -317,3 +321,4 @@ config SND_SOC_WM2000 config SND_SOC_WM9090 tristate + diff --git a/sound/soc/codecs/Makefile b/sound/soc/codecs/Makefile index f67a2d6f7a46..0dcaed3e73f3 100644 --- a/sound/soc/codecs/Makefile +++ b/sound/soc/codecs/Makefile @@ -17,6 +17,7 @@ snd-soc-da7210-objs := da7210.o snd-soc-l3-objs := l3.o snd-soc-max98088-objs := max98088.o snd-soc-pcm3008-objs := pcm3008.o +snd-soc-alc5623-objs := alc5623.o snd-soc-spdif-objs := spdif_transciever.o snd-soc-ssm2602-objs := ssm2602.o snd-soc-stac9766-objs := stac9766.o @@ -92,6 +93,7 @@ obj-$(CONFIG_SND_SOC_L3) += snd-soc-l3.o obj-$(CONFIG_SND_SOC_JZ4740_CODEC) += snd-soc-jz4740-codec.o obj-$(CONFIG_SND_SOC_MAX98088) += snd-soc-max98088.o obj-$(CONFIG_SND_SOC_PCM3008) += snd-soc-pcm3008.o +obj-$(CONFIG_SND_SOC_ALC5623) += snd-soc-alc5623.o obj-$(CONFIG_SND_SOC_SPDIF) += snd-soc-spdif.o obj-$(CONFIG_SND_SOC_SSM2602) += snd-soc-ssm2602.o obj-$(CONFIG_SND_SOC_STAC9766) += snd-soc-stac9766.o diff --git a/sound/soc/codecs/alc5623.c b/sound/soc/codecs/alc5623.c new file mode 100644 index 000000000000..fac61744f8c7 --- /dev/null +++ b/sound/soc/codecs/alc5623.c @@ -0,0 +1,1118 @@ +/* + * alc5623.c -- alc562[123] ALSA Soc Audio driver + * + * Copyright 2008 Realtek Microelectronics + * Author: flove Ethan + * + * Copyright 2010 Arnaud Patard + * + * + * Based on WM8753.c + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "alc5623.h" + +static int caps_charge = 2000; +module_param(caps_charge, int, 0); +MODULE_PARM_DESC(caps_charge, "ALC5623 cap charge time (msecs)"); + +/* codec private data */ +struct alc5623_priv { + enum snd_soc_control_type control_type; + void *control_data; + struct mutex mutex; + u8 id; + unsigned int sysclk; + u16 reg_cache[ALC5623_VENDOR_ID2+2]; + unsigned int add_ctrl; + unsigned int jack_det_ctrl; +}; + +static void alc5623_fill_cache(struct snd_soc_codec *codec) +{ + int i, step = codec->driver->reg_cache_step; + u16 *cache = codec->reg_cache; + + /* not really efficient ... */ + for (i = 0 ; i < codec->driver->reg_cache_size ; i += step) + cache[i] = codec->hw_read(codec, i); +} + +static inline int alc5623_reset(struct snd_soc_codec *codec) +{ + return snd_soc_write(codec, ALC5623_RESET, 0); +} + +static int amp_mixer_event(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, int event) +{ + /* to power-on/off class-d amp generators/speaker */ + /* need to write to 'index-46h' register : */ + /* so write index num (here 0x46) to reg 0x6a */ + /* and then 0xffff/0 to reg 0x6c */ + snd_soc_write(w->codec, ALC5623_HID_CTRL_INDEX, 0x46); + + switch (event) { + case SND_SOC_DAPM_PRE_PMU: + snd_soc_write(w->codec, ALC5623_HID_CTRL_DATA, 0xFFFF); + break; + case SND_SOC_DAPM_POST_PMD: + snd_soc_write(w->codec, ALC5623_HID_CTRL_DATA, 0); + break; + } + + return 0; +} + +/* + * ALC5623 Controls + */ + +static const DECLARE_TLV_DB_SCALE(vol_tlv, -3450, 150, 0); +static const DECLARE_TLV_DB_SCALE(hp_tlv, -4650, 150, 0); +static const DECLARE_TLV_DB_SCALE(adc_rec_tlv, -1650, 150, 0); +static const unsigned int boost_tlv[] = { + TLV_DB_RANGE_HEAD(3), + 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0), + 1, 1, TLV_DB_SCALE_ITEM(2000, 0, 0), + 2, 2, TLV_DB_SCALE_ITEM(3000, 0, 0), +}; +static const DECLARE_TLV_DB_SCALE(dig_tlv, 0, 600, 0); + +static const struct snd_kcontrol_new rt5621_vol_snd_controls[] = { + SOC_DOUBLE_TLV("Speaker Playback Volume", + ALC5623_SPK_OUT_VOL, 8, 0, 31, 1, hp_tlv), + SOC_DOUBLE("Speaker Playback Switch", + ALC5623_SPK_OUT_VOL, 15, 7, 1, 1), + SOC_DOUBLE_TLV("Headphone Playback Volume", + ALC5623_HP_OUT_VOL, 8, 0, 31, 1, hp_tlv), + SOC_DOUBLE("Headphone Playback Switch", + ALC5623_HP_OUT_VOL, 15, 7, 1, 1), +}; + +static const struct snd_kcontrol_new rt5622_vol_snd_controls[] = { + SOC_DOUBLE_TLV("Speaker Playback Volume", + ALC5623_SPK_OUT_VOL, 8, 0, 31, 1, hp_tlv), + SOC_DOUBLE("Speaker Playback Switch", + ALC5623_SPK_OUT_VOL, 15, 7, 1, 1), + SOC_DOUBLE_TLV("Line Playback Volume", + ALC5623_HP_OUT_VOL, 8, 0, 31, 1, hp_tlv), + SOC_DOUBLE("Line Playback Switch", + ALC5623_HP_OUT_VOL, 15, 7, 1, 1), +}; + +static const struct snd_kcontrol_new alc5623_vol_snd_controls[] = { + SOC_DOUBLE_TLV("Line Playback Volume", + ALC5623_SPK_OUT_VOL, 8, 0, 31, 1, hp_tlv), + SOC_DOUBLE("Line Playback Switch", + ALC5623_SPK_OUT_VOL, 15, 7, 1, 1), + SOC_DOUBLE_TLV("Headphone Playback Volume", + ALC5623_HP_OUT_VOL, 8, 0, 31, 1, hp_tlv), + SOC_DOUBLE("Headphone Playback Switch", + ALC5623_HP_OUT_VOL, 15, 7, 1, 1), +}; + +static const struct snd_kcontrol_new alc5623_snd_controls[] = { + SOC_DOUBLE_TLV("Auxout Playback Volume", + ALC5623_MONO_AUX_OUT_VOL, 8, 0, 31, 1, hp_tlv), + SOC_DOUBLE("Auxout Playback Switch", + ALC5623_MONO_AUX_OUT_VOL, 15, 7, 1, 1), + SOC_DOUBLE_TLV("PCM Playback Volume", + ALC5623_STEREO_DAC_VOL, 8, 0, 31, 1, vol_tlv), + SOC_DOUBLE_TLV("AuxI Capture Volume", + ALC5623_AUXIN_VOL, 8, 0, 31, 1, vol_tlv), + SOC_DOUBLE_TLV("LineIn Capture Volume", + ALC5623_LINE_IN_VOL, 8, 0, 31, 1, vol_tlv), + SOC_SINGLE_TLV("Mic1 Capture Volume", + ALC5623_MIC_VOL, 8, 31, 1, vol_tlv), + SOC_SINGLE_TLV("Mic2 Capture Volume", + ALC5623_MIC_VOL, 0, 31, 1, vol_tlv), + SOC_DOUBLE_TLV("Rec Capture Volume", + ALC5623_ADC_REC_GAIN, 7, 0, 31, 0, adc_rec_tlv), + SOC_SINGLE_TLV("Mic 1 Boost Volume", + ALC5623_MIC_CTRL, 10, 2, 0, boost_tlv), + SOC_SINGLE_TLV("Mic 2 Boost Volume", + ALC5623_MIC_CTRL, 8, 2, 0, boost_tlv), + SOC_SINGLE_TLV("Digital Boost Volume", + ALC5623_ADD_CTRL_REG, 4, 3, 0, dig_tlv), +}; + +/* + * DAPM Controls + */ +static const struct snd_kcontrol_new alc5623_hp_mixer_controls[] = { +SOC_DAPM_SINGLE("LI2HP Playback Switch", ALC5623_LINE_IN_VOL, 15, 1, 1), +SOC_DAPM_SINGLE("AUXI2HP Playback Switch", ALC5623_AUXIN_VOL, 15, 1, 1), +SOC_DAPM_SINGLE("MIC12HP Playback Switch", ALC5623_MIC_ROUTING_CTRL, 15, 1, 1), +SOC_DAPM_SINGLE("MIC22HP Playback Switch", ALC5623_MIC_ROUTING_CTRL, 7, 1, 1), +SOC_DAPM_SINGLE("DAC2HP Playback Switch", ALC5623_STEREO_DAC_VOL, 15, 1, 1), +}; + +static const struct snd_kcontrol_new alc5623_hpl_mixer_controls[] = { +SOC_DAPM_SINGLE("ADC2HP_L Playback Switch", ALC5623_ADC_REC_GAIN, 15, 1, 1), +}; + +static const struct snd_kcontrol_new alc5623_hpr_mixer_controls[] = { +SOC_DAPM_SINGLE("ADC2HP_R Playback Switch", ALC5623_ADC_REC_GAIN, 14, 1, 1), +}; + +static const struct snd_kcontrol_new alc5623_mono_mixer_controls[] = { +SOC_DAPM_SINGLE("ADC2MONO_L Playback Switch", ALC5623_ADC_REC_GAIN, 13, 1, 1), +SOC_DAPM_SINGLE("ADC2MONO_R Playback Switch", ALC5623_ADC_REC_GAIN, 12, 1, 1), +SOC_DAPM_SINGLE("LI2MONO Playback Switch", ALC5623_LINE_IN_VOL, 13, 1, 1), +SOC_DAPM_SINGLE("AUXI2MONO Playback Switch", ALC5623_AUXIN_VOL, 13, 1, 1), +SOC_DAPM_SINGLE("MIC12MONO Playback Switch", ALC5623_MIC_ROUTING_CTRL, 13, 1, 1), +SOC_DAPM_SINGLE("MIC22MONO Playback Switch", ALC5623_MIC_ROUTING_CTRL, 5, 1, 1), +SOC_DAPM_SINGLE("DAC2MONO Playback Switch", ALC5623_STEREO_DAC_VOL, 13, 1, 1), +}; + +static const struct snd_kcontrol_new alc5623_speaker_mixer_controls[] = { +SOC_DAPM_SINGLE("LI2SPK Playback Switch", ALC5623_LINE_IN_VOL, 14, 1, 1), +SOC_DAPM_SINGLE("AUXI2SPK Playback Switch", ALC5623_AUXIN_VOL, 14, 1, 1), +SOC_DAPM_SINGLE("MIC12SPK Playback Switch", ALC5623_MIC_ROUTING_CTRL, 14, 1, 1), +SOC_DAPM_SINGLE("MIC22SPK Playback Switch", ALC5623_MIC_ROUTING_CTRL, 6, 1, 1), +SOC_DAPM_SINGLE("DAC2SPK Playback Switch", ALC5623_STEREO_DAC_VOL, 14, 1, 1), +}; + +/* Left Record Mixer */ +static const struct snd_kcontrol_new alc5623_captureL_mixer_controls[] = { +SOC_DAPM_SINGLE("Mic1 Capture Switch", ALC5623_ADC_REC_MIXER, 14, 1, 1), +SOC_DAPM_SINGLE("Mic2 Capture Switch", ALC5623_ADC_REC_MIXER, 13, 1, 1), +SOC_DAPM_SINGLE("LineInL Capture Switch", ALC5623_ADC_REC_MIXER, 12, 1, 1), +SOC_DAPM_SINGLE("Left AuxI Capture Switch", ALC5623_ADC_REC_MIXER, 11, 1, 1), +SOC_DAPM_SINGLE("HPMixerL Capture Switch", ALC5623_ADC_REC_MIXER, 10, 1, 1), +SOC_DAPM_SINGLE("SPKMixer Capture Switch", ALC5623_ADC_REC_MIXER, 9, 1, 1), +SOC_DAPM_SINGLE("MonoMixer Capture Switch", ALC5623_ADC_REC_MIXER, 8, 1, 1), +}; + +/* Right Record Mixer */ +static const struct snd_kcontrol_new alc5623_captureR_mixer_controls[] = { +SOC_DAPM_SINGLE("Mic1 Capture Switch", ALC5623_ADC_REC_MIXER, 6, 1, 1), +SOC_DAPM_SINGLE("Mic2 Capture Switch", ALC5623_ADC_REC_MIXER, 5, 1, 1), +SOC_DAPM_SINGLE("LineInR Capture Switch", ALC5623_ADC_REC_MIXER, 4, 1, 1), +SOC_DAPM_SINGLE("Right AuxI Capture Switch", ALC5623_ADC_REC_MIXER, 3, 1, 1), +SOC_DAPM_SINGLE("HPMixerR Capture Switch", ALC5623_ADC_REC_MIXER, 2, 1, 1), +SOC_DAPM_SINGLE("SPKMixer Capture Switch", ALC5623_ADC_REC_MIXER, 1, 1, 1), +SOC_DAPM_SINGLE("MonoMixer Capture Switch", ALC5623_ADC_REC_MIXER, 0, 1, 1), +}; + +static const char *alc5623_spk_n_sour_sel[] = { + "RN/-R", "RP/+R", "LN/-R", "Vmid" }; +static const char *alc5623_hpl_out_input_sel[] = { + "Vmid", "HP Left Mix"}; +static const char *alc5623_hpr_out_input_sel[] = { + "Vmid", "HP Right Mix"}; +static const char *alc5623_spkout_input_sel[] = { + "Vmid", "HPOut Mix", "Speaker Mix", "Mono Mix"}; +static const char *alc5623_aux_out_input_sel[] = { + "Vmid", "HPOut Mix", "Speaker Mix", "Mono Mix"}; + +/* auxout output mux */ +static const struct soc_enum alc5623_aux_out_input_enum = +SOC_ENUM_SINGLE(ALC5623_OUTPUT_MIXER_CTRL, 6, 4, alc5623_aux_out_input_sel); +static const struct snd_kcontrol_new alc5623_auxout_mux_controls = +SOC_DAPM_ENUM("Route", alc5623_aux_out_input_enum); + +/* speaker output mux */ +static const struct soc_enum alc5623_spkout_input_enum = +SOC_ENUM_SINGLE(ALC5623_OUTPUT_MIXER_CTRL, 10, 4, alc5623_spkout_input_sel); +static const struct snd_kcontrol_new alc5623_spkout_mux_controls = +SOC_DAPM_ENUM("Route", alc5623_spkout_input_enum); + +/* headphone left output mux */ +static const struct soc_enum alc5623_hpl_out_input_enum = +SOC_ENUM_SINGLE(ALC5623_OUTPUT_MIXER_CTRL, 9, 2, alc5623_hpl_out_input_sel); +static const struct snd_kcontrol_new alc5623_hpl_out_mux_controls = +SOC_DAPM_ENUM("Route", alc5623_hpl_out_input_enum); + +/* headphone right output mux */ +static const struct soc_enum alc5623_hpr_out_input_enum = +SOC_ENUM_SINGLE(ALC5623_OUTPUT_MIXER_CTRL, 8, 2, alc5623_hpr_out_input_sel); +static const struct snd_kcontrol_new alc5623_hpr_out_mux_controls = +SOC_DAPM_ENUM("Route", alc5623_hpr_out_input_enum); + +/* speaker output N select */ +static const struct soc_enum alc5623_spk_n_sour_enum = +SOC_ENUM_SINGLE(ALC5623_OUTPUT_MIXER_CTRL, 14, 4, alc5623_spk_n_sour_sel); +static const struct snd_kcontrol_new alc5623_spkoutn_mux_controls = +SOC_DAPM_ENUM("Route", alc5623_spk_n_sour_enum); + +static const struct snd_soc_dapm_widget alc5623_dapm_widgets[] = { +/* Muxes */ +SND_SOC_DAPM_MUX("AuxOut Mux", SND_SOC_NOPM, 0, 0, + &alc5623_auxout_mux_controls), +SND_SOC_DAPM_MUX("SpeakerOut Mux", SND_SOC_NOPM, 0, 0, + &alc5623_spkout_mux_controls), +SND_SOC_DAPM_MUX("Left Headphone Mux", SND_SOC_NOPM, 0, 0, + &alc5623_hpl_out_mux_controls), +SND_SOC_DAPM_MUX("Right Headphone Mux", SND_SOC_NOPM, 0, 0, + &alc5623_hpr_out_mux_controls), +SND_SOC_DAPM_MUX("SpeakerOut N Mux", SND_SOC_NOPM, 0, 0, + &alc5623_spkoutn_mux_controls), + +/* output mixers */ +SND_SOC_DAPM_MIXER("HP Mix", SND_SOC_NOPM, 0, 0, + &alc5623_hp_mixer_controls[0], + ARRAY_SIZE(alc5623_hp_mixer_controls)), +SND_SOC_DAPM_MIXER("HPR Mix", ALC5623_PWR_MANAG_ADD2, 4, 0, + &alc5623_hpr_mixer_controls[0], + ARRAY_SIZE(alc5623_hpr_mixer_controls)), +SND_SOC_DAPM_MIXER("HPL Mix", ALC5623_PWR_MANAG_ADD2, 5, 0, + &alc5623_hpl_mixer_controls[0], + ARRAY_SIZE(alc5623_hpl_mixer_controls)), +SND_SOC_DAPM_MIXER("HPOut Mix", SND_SOC_NOPM, 0, 0, NULL, 0), +SND_SOC_DAPM_MIXER("Mono Mix", ALC5623_PWR_MANAG_ADD2, 2, 0, + &alc5623_mono_mixer_controls[0], + ARRAY_SIZE(alc5623_mono_mixer_controls)), +SND_SOC_DAPM_MIXER("Speaker Mix", ALC5623_PWR_MANAG_ADD2, 3, 0, + &alc5623_speaker_mixer_controls[0], + ARRAY_SIZE(alc5623_speaker_mixer_controls)), + +/* input mixers */ +SND_SOC_DAPM_MIXER("Left Capture Mix", ALC5623_PWR_MANAG_ADD2, 1, 0, + &alc5623_captureL_mixer_controls[0], + ARRAY_SIZE(alc5623_captureL_mixer_controls)), +SND_SOC_DAPM_MIXER("Right Capture Mix", ALC5623_PWR_MANAG_ADD2, 0, 0, + &alc5623_captureR_mixer_controls[0], + ARRAY_SIZE(alc5623_captureR_mixer_controls)), + +SND_SOC_DAPM_DAC("Left DAC", "Left HiFi Playback", + ALC5623_PWR_MANAG_ADD2, 9, 0), +SND_SOC_DAPM_DAC("Right DAC", "Right HiFi Playback", + ALC5623_PWR_MANAG_ADD2, 8, 0), +SND_SOC_DAPM_MIXER("I2S Mix", ALC5623_PWR_MANAG_ADD1, 15, 0, NULL, 0), +SND_SOC_DAPM_MIXER("AuxI Mix", SND_SOC_NOPM, 0, 0, NULL, 0), +SND_SOC_DAPM_MIXER("Line Mix", SND_SOC_NOPM, 0, 0, NULL, 0), +SND_SOC_DAPM_ADC("Left ADC", "Left HiFi Capture", + ALC5623_PWR_MANAG_ADD2, 7, 0), +SND_SOC_DAPM_ADC("Right ADC", "Right HiFi Capture", + ALC5623_PWR_MANAG_ADD2, 6, 0), +SND_SOC_DAPM_PGA("Left Headphone", ALC5623_PWR_MANAG_ADD3, 10, 0, NULL, 0), +SND_SOC_DAPM_PGA("Right Headphone", ALC5623_PWR_MANAG_ADD3, 9, 0, NULL, 0), +SND_SOC_DAPM_PGA("SpeakerOut", ALC5623_PWR_MANAG_ADD3, 12, 0, NULL, 0), +SND_SOC_DAPM_PGA("Left AuxOut", ALC5623_PWR_MANAG_ADD3, 14, 0, NULL, 0), +SND_SOC_DAPM_PGA("Right AuxOut", ALC5623_PWR_MANAG_ADD3, 13, 0, NULL, 0), +SND_SOC_DAPM_PGA("Left LineIn", ALC5623_PWR_MANAG_ADD3, 7, 0, NULL, 0), +SND_SOC_DAPM_PGA("Right LineIn", ALC5623_PWR_MANAG_ADD3, 6, 0, NULL, 0), +SND_SOC_DAPM_PGA("Left AuxI", ALC5623_PWR_MANAG_ADD3, 5, 0, NULL, 0), +SND_SOC_DAPM_PGA("Right AuxI", ALC5623_PWR_MANAG_ADD3, 4, 0, NULL, 0), +SND_SOC_DAPM_PGA("MIC1 PGA", ALC5623_PWR_MANAG_ADD3, 3, 0, NULL, 0), +SND_SOC_DAPM_PGA("MIC2 PGA", ALC5623_PWR_MANAG_ADD3, 2, 0, NULL, 0), +SND_SOC_DAPM_PGA("MIC1 Pre Amp", ALC5623_PWR_MANAG_ADD3, 1, 0, NULL, 0), +SND_SOC_DAPM_PGA("MIC2 Pre Amp", ALC5623_PWR_MANAG_ADD3, 0, 0, NULL, 0), +SND_SOC_DAPM_MICBIAS("Mic Bias1", ALC5623_PWR_MANAG_ADD1, 11, 0), + +SND_SOC_DAPM_OUTPUT("AUXOUTL"), +SND_SOC_DAPM_OUTPUT("AUXOUTR"), +SND_SOC_DAPM_OUTPUT("HPL"), +SND_SOC_DAPM_OUTPUT("HPR"), +SND_SOC_DAPM_OUTPUT("SPKOUT"), +SND_SOC_DAPM_OUTPUT("SPKOUTN"), +SND_SOC_DAPM_INPUT("LINEINL"), +SND_SOC_DAPM_INPUT("LINEINR"), +SND_SOC_DAPM_INPUT("AUXINL"), +SND_SOC_DAPM_INPUT("AUXINR"), +SND_SOC_DAPM_INPUT("MIC1"), +SND_SOC_DAPM_INPUT("MIC2"), +SND_SOC_DAPM_VMID("Vmid"), +}; + +static const char *alc5623_amp_names[] = {"AB Amp", "D Amp"}; +static const struct soc_enum alc5623_amp_enum = + SOC_ENUM_SINGLE(ALC5623_OUTPUT_MIXER_CTRL, 13, 2, alc5623_amp_names); +static const struct snd_kcontrol_new alc5623_amp_mux_controls = + SOC_DAPM_ENUM("Route", alc5623_amp_enum); + +static const struct snd_soc_dapm_widget alc5623_dapm_amp_widgets[] = { +SND_SOC_DAPM_PGA_E("D Amp", ALC5623_PWR_MANAG_ADD2, 14, 0, NULL, 0, + amp_mixer_event, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), +SND_SOC_DAPM_PGA("AB Amp", ALC5623_PWR_MANAG_ADD2, 15, 0, NULL, 0), +SND_SOC_DAPM_MUX("AB-D Amp Mux", SND_SOC_NOPM, 0, 0, + &alc5623_amp_mux_controls), +}; + +static const struct snd_soc_dapm_route intercon[] = { + /* virtual mixer - mixes left & right channels */ + {"I2S Mix", NULL, "Left DAC"}, + {"I2S Mix", NULL, "Right DAC"}, + {"Line Mix", NULL, "Right LineIn"}, + {"Line Mix", NULL, "Left LineIn"}, + {"AuxI Mix", NULL, "Left AuxI"}, + {"AuxI Mix", NULL, "Right AuxI"}, + {"AUXOUTL", NULL, "Left AuxOut"}, + {"AUXOUTR", NULL, "Right AuxOut"}, + + /* HP mixer */ + {"HPL Mix", "ADC2HP_L Playback Switch", "Left Capture Mix"}, + {"HPL Mix", NULL, "HP Mix"}, + {"HPR Mix", "ADC2HP_R Playback Switch", "Right Capture Mix"}, + {"HPR Mix", NULL, "HP Mix"}, + {"HP Mix", "LI2HP Playback Switch", "Line Mix"}, + {"HP Mix", "AUXI2HP Playback Switch", "AuxI Mix"}, + {"HP Mix", "MIC12HP Playback Switch", "MIC1 PGA"}, + {"HP Mix", "MIC22HP Playback Switch", "MIC2 PGA"}, + {"HP Mix", "DAC2HP Playback Switch", "I2S Mix"}, + + /* speaker mixer */ + {"Speaker Mix", "LI2SPK Playback Switch", "Line Mix"}, + {"Speaker Mix", "AUXI2SPK Playback Switch", "AuxI Mix"}, + {"Speaker Mix", "MIC12SPK Playback Switch", "MIC1 PGA"}, + {"Speaker Mix", "MIC22SPK Playback Switch", "MIC2 PGA"}, + {"Speaker Mix", "DAC2SPK Playback Switch", "I2S Mix"}, + + /* mono mixer */ + {"Mono Mix", "ADC2MONO_L Playback Switch", "Left Capture Mix"}, + {"Mono Mix", "ADC2MONO_R Playback Switch", "Right Capture Mix"}, + {"Mono Mix", "LI2MONO Playback Switch", "Line Mix"}, + {"Mono Mix", "AUXI2MONO Playback Switch", "AuxI Mix"}, + {"Mono Mix", "MIC12MONO Playback Switch", "MIC1 PGA"}, + {"Mono Mix", "MIC22MONO Playback Switch", "MIC2 PGA"}, + {"Mono Mix", "DAC2MONO Playback Switch", "I2S Mix"}, + + /* Left record mixer */ + {"Left Capture Mix", "LineInL Capture Switch", "LINEINL"}, + {"Left Capture Mix", "Left AuxI Capture Switch", "AUXINL"}, + {"Left Capture Mix", "Mic1 Capture Switch", "MIC1 Pre Amp"}, + {"Left Capture Mix", "Mic2 Capture Switch", "MIC2 Pre Amp"}, + {"Left Capture Mix", "HPMixerL Capture Switch", "HPL Mix"}, + {"Left Capture Mix", "SPKMixer Capture Switch", "Speaker Mix"}, + {"Left Capture Mix", "MonoMixer Capture Switch", "Mono Mix"}, + + /*Right record mixer */ + {"Right Capture Mix", "LineInR Capture Switch", "LINEINR"}, + {"Right Capture Mix", "Right AuxI Capture Switch", "AUXINR"}, + {"Right Capture Mix", "Mic1 Capture Switch", "MIC1 Pre Amp"}, + {"Right Capture Mix", "Mic2 Capture Switch", "MIC2 Pre Amp"}, + {"Right Capture Mix", "HPMixerR Capture Switch", "HPR Mix"}, + {"Right Capture Mix", "SPKMixer Capture Switch", "Speaker Mix"}, + {"Right Capture Mix", "MonoMixer Capture Switch", "Mono Mix"}, + + /* headphone left mux */ + {"Left Headphone Mux", "HP Left Mix", "HPL Mix"}, + {"Left Headphone Mux", "Vmid", "Vmid"}, + + /* headphone right mux */ + {"Right Headphone Mux", "HP Right Mix", "HPR Mix"}, + {"Right Headphone Mux", "Vmid", "Vmid"}, + + /* speaker out mux */ + {"SpeakerOut Mux", "Vmid", "Vmid"}, + {"SpeakerOut Mux", "HPOut Mix", "HPOut Mix"}, + {"SpeakerOut Mux", "Speaker Mix", "Speaker Mix"}, + {"SpeakerOut Mux", "Mono Mix", "Mono Mix"}, + + /* Mono/Aux Out mux */ + {"AuxOut Mux", "Vmid", "Vmid"}, + {"AuxOut Mux", "HPOut Mix", "HPOut Mix"}, + {"AuxOut Mux", "Speaker Mix", "Speaker Mix"}, + {"AuxOut Mux", "Mono Mix", "Mono Mix"}, + + /* output pga */ + {"HPL", NULL, "Left Headphone"}, + {"Left Headphone", NULL, "Left Headphone Mux"}, + {"HPR", NULL, "Right Headphone"}, + {"Right Headphone", NULL, "Right Headphone Mux"}, + {"Left AuxOut", NULL, "AuxOut Mux"}, + {"Right AuxOut", NULL, "AuxOut Mux"}, + + /* input pga */ + {"Left LineIn", NULL, "LINEINL"}, + {"Right LineIn", NULL, "LINEINR"}, + {"Left AuxI", NULL, "AUXINL"}, + {"Right AuxI", NULL, "AUXINR"}, + {"MIC1 Pre Amp", NULL, "MIC1"}, + {"MIC2 Pre Amp", NULL, "MIC2"}, + {"MIC1 PGA", NULL, "MIC1 Pre Amp"}, + {"MIC2 PGA", NULL, "MIC2 Pre Amp"}, + + /* left ADC */ + {"Left ADC", NULL, "Left Capture Mix"}, + + /* right ADC */ + {"Right ADC", NULL, "Right Capture Mix"}, + + {"SpeakerOut N Mux", "RN/-R", "SpeakerOut"}, + {"SpeakerOut N Mux", "RP/+R", "SpeakerOut"}, + {"SpeakerOut N Mux", "LN/-R", "SpeakerOut"}, + {"SpeakerOut N Mux", "Vmid", "Vmid"}, + + {"SPKOUT", NULL, "SpeakerOut"}, + {"SPKOUTN", NULL, "SpeakerOut N Mux"}, +}; + +static const struct snd_soc_dapm_route intercon_spk[] = { + {"SpeakerOut", NULL, "SpeakerOut Mux"}, +}; + +static const struct snd_soc_dapm_route intercon_amp_spk[] = { + {"AB Amp", NULL, "SpeakerOut Mux"}, + {"D Amp", NULL, "SpeakerOut Mux"}, + {"AB-D Amp Mux", "AB Amp", "AB Amp"}, + {"AB-D Amp Mux", "D Amp", "D Amp"}, + {"SpeakerOut", NULL, "AB-D Amp Mux"}, +}; + +/* PLL divisors */ +struct _pll_div { + u32 pll_in; + u32 pll_out; + u16 regvalue; +}; + +/* Note : pll code from original alc5623 driver. Not sure of how good it is */ +/* usefull only for master mode */ +static const struct _pll_div codec_master_pll_div[] = { + + { 2048000, 8192000, 0x0ea0}, + { 3686400, 8192000, 0x4e27}, + { 12000000, 8192000, 0x456b}, + { 13000000, 8192000, 0x495f}, + { 13100000, 8192000, 0x0320}, + { 2048000, 11289600, 0xf637}, + { 3686400, 11289600, 0x2f22}, + { 12000000, 11289600, 0x3e2f}, + { 13000000, 11289600, 0x4d5b}, + { 13100000, 11289600, 0x363b}, + { 2048000, 16384000, 0x1ea0}, + { 3686400, 16384000, 0x9e27}, + { 12000000, 16384000, 0x452b}, + { 13000000, 16384000, 0x542f}, + { 13100000, 16384000, 0x03a0}, + { 2048000, 16934400, 0xe625}, + { 3686400, 16934400, 0x9126}, + { 12000000, 16934400, 0x4d2c}, + { 13000000, 16934400, 0x742f}, + { 13100000, 16934400, 0x3c27}, + { 2048000, 22579200, 0x2aa0}, + { 3686400, 22579200, 0x2f20}, + { 12000000, 22579200, 0x7e2f}, + { 13000000, 22579200, 0x742f}, + { 13100000, 22579200, 0x3c27}, + { 2048000, 24576000, 0x2ea0}, + { 3686400, 24576000, 0xee27}, + { 12000000, 24576000, 0x2915}, + { 13000000, 24576000, 0x772e}, + { 13100000, 24576000, 0x0d20}, +}; + +static const struct _pll_div codec_slave_pll_div[] = { + + { 1024000, 16384000, 0x3ea0}, + { 1411200, 22579200, 0x3ea0}, + { 1536000, 24576000, 0x3ea0}, + { 2048000, 16384000, 0x1ea0}, + { 2822400, 22579200, 0x1ea0}, + { 3072000, 24576000, 0x1ea0}, + +}; + +static int alc5623_set_dai_pll(struct snd_soc_dai *codec_dai, int pll_id, + int source, unsigned int freq_in, unsigned int freq_out) +{ + int i; + struct snd_soc_codec *codec = codec_dai->codec; + int gbl_clk = 0, pll_div = 0; + u16 reg; + + if (pll_id < ALC5623_PLL_FR_MCLK || pll_id > ALC5623_PLL_FR_BCK) + return -ENODEV; + + /* Disable PLL power */ + snd_soc_update_bits(codec, ALC5623_PWR_MANAG_ADD2, + ALC5623_PWR_ADD2_PLL, + 0); + + /* pll is not used in slave mode */ + reg = snd_soc_read(codec, ALC5623_DAI_CONTROL); + if (reg & ALC5623_DAI_SDP_SLAVE_MODE) + return 0; + + if (!freq_in || !freq_out) + return 0; + + switch (pll_id) { + case ALC5623_PLL_FR_MCLK: + for (i = 0; i < ARRAY_SIZE(codec_master_pll_div); i++) { + if (codec_master_pll_div[i].pll_in == freq_in + && codec_master_pll_div[i].pll_out == freq_out) { + /* PLL source from MCLK */ + pll_div = codec_master_pll_div[i].regvalue; + break; + } + } + break; + case ALC5623_PLL_FR_BCK: + for (i = 0; i < ARRAY_SIZE(codec_slave_pll_div); i++) { + if (codec_slave_pll_div[i].pll_in == freq_in + && codec_slave_pll_div[i].pll_out == freq_out) { + /* PLL source from Bitclk */ + gbl_clk = ALC5623_GBL_CLK_PLL_SOUR_SEL_BITCLK; + pll_div = codec_slave_pll_div[i].regvalue; + break; + } + } + break; + default: + return -EINVAL; + } + + if (!pll_div) + return -EINVAL; + + snd_soc_write(codec, ALC5623_GLOBAL_CLK_CTRL_REG, gbl_clk); + snd_soc_write(codec, ALC5623_PLL_CTRL, pll_div); + snd_soc_update_bits(codec, ALC5623_PWR_MANAG_ADD2, + ALC5623_PWR_ADD2_PLL, + ALC5623_PWR_ADD2_PLL); + gbl_clk |= ALC5623_GBL_CLK_SYS_SOUR_SEL_PLL; + snd_soc_write(codec, ALC5623_GLOBAL_CLK_CTRL_REG, gbl_clk); + + return 0; +} + +struct _coeff_div { + u16 fs; + u16 regvalue; +}; + +/* codec hifi mclk (after PLL) clock divider coefficients */ +/* values inspired from column BCLK=32Fs of Appendix A table */ +static const struct _coeff_div coeff_div[] = { + {256*8, 0x3a69}, + {384*8, 0x3c6b}, + {256*4, 0x2a69}, + {384*4, 0x2c6b}, + {256*2, 0x1a69}, + {384*2, 0x1c6b}, + {256*1, 0x0a69}, + {384*1, 0x0c6b}, +}; + +static int get_coeff(struct snd_soc_codec *codec, int rate) +{ + struct alc5623_priv *alc5623 = snd_soc_codec_get_drvdata(codec); + int i; + + for (i = 0; i < ARRAY_SIZE(coeff_div); i++) { + if (coeff_div[i].fs * rate == alc5623->sysclk) + return i; + } + return -EINVAL; +} + +/* + * Clock after PLL and dividers + */ +static int alc5623_set_dai_sysclk(struct snd_soc_dai *codec_dai, + int clk_id, unsigned int freq, int dir) +{ + struct snd_soc_codec *codec = codec_dai->codec; + struct alc5623_priv *alc5623 = snd_soc_codec_get_drvdata(codec); + + switch (freq) { + case 8192000: + case 11289600: + case 12288000: + case 16384000: + case 16934400: + case 18432000: + case 22579200: + case 24576000: + alc5623->sysclk = freq; + return 0; + } + return -EINVAL; +} + +static int alc5623_set_dai_fmt(struct snd_soc_dai *codec_dai, + unsigned int fmt) +{ + struct snd_soc_codec *codec = codec_dai->codec; + u16 iface = 0; + + /* set master/slave audio interface */ + switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { + case SND_SOC_DAIFMT_CBM_CFM: + iface = ALC5623_DAI_SDP_MASTER_MODE; + break; + case SND_SOC_DAIFMT_CBS_CFS: + iface = ALC5623_DAI_SDP_SLAVE_MODE; + break; + default: + return -EINVAL; + } + + /* interface format */ + switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { + case SND_SOC_DAIFMT_I2S: + iface |= ALC5623_DAI_I2S_DF_I2S; + break; + case SND_SOC_DAIFMT_RIGHT_J: + iface |= ALC5623_DAI_I2S_DF_RIGHT; + break; + case SND_SOC_DAIFMT_LEFT_J: + iface |= ALC5623_DAI_I2S_DF_LEFT; + break; + case SND_SOC_DAIFMT_DSP_A: + iface |= ALC5623_DAI_I2S_DF_PCM; + break; + case SND_SOC_DAIFMT_DSP_B: + iface |= ALC5623_DAI_I2S_DF_PCM | ALC5623_DAI_I2S_PCM_MODE; + break; + default: + return -EINVAL; + } + + /* clock inversion */ + switch (fmt & SND_SOC_DAIFMT_INV_MASK) { + case SND_SOC_DAIFMT_NB_NF: + break; + case SND_SOC_DAIFMT_IB_IF: + iface |= ALC5623_DAI_MAIN_I2S_BCLK_POL_CTRL; + break; + case SND_SOC_DAIFMT_IB_NF: + iface |= ALC5623_DAI_MAIN_I2S_BCLK_POL_CTRL; + break; + case SND_SOC_DAIFMT_NB_IF: + break; + default: + return -EINVAL; + } + + return snd_soc_write(codec, ALC5623_DAI_CONTROL, iface); +} + +static int alc5623_pcm_hw_params(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) +{ + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct snd_soc_codec *codec = rtd->codec; + struct alc5623_priv *alc5623 = snd_soc_codec_get_drvdata(codec); + int coeff, rate; + u16 iface; + + iface = snd_soc_read(codec, ALC5623_DAI_CONTROL); + iface &= ~ALC5623_DAI_I2S_DL_MASK; + + /* bit size */ + switch (params_format(params)) { + case SNDRV_PCM_FORMAT_S16_LE: + iface |= ALC5623_DAI_I2S_DL_16; + break; + case SNDRV_PCM_FORMAT_S20_3LE: + iface |= ALC5623_DAI_I2S_DL_20; + break; + case SNDRV_PCM_FORMAT_S24_LE: + iface |= ALC5623_DAI_I2S_DL_24; + break; + case SNDRV_PCM_FORMAT_S32_LE: + iface |= ALC5623_DAI_I2S_DL_32; + break; + default: + return -EINVAL; + } + + /* set iface & srate */ + snd_soc_write(codec, ALC5623_DAI_CONTROL, iface); + rate = params_rate(params); + coeff = get_coeff(codec, rate); + if (coeff < 0) + return -EINVAL; + + coeff = coeff_div[coeff].regvalue; + dev_dbg(codec->dev, "%s: sysclk=%d,rate=%d,coeff=0x%04x\n", + __func__, alc5623->sysclk, rate, coeff); + snd_soc_write(codec, ALC5623_STEREO_AD_DA_CLK_CTRL, coeff); + + return 0; +} + +static int alc5623_mute(struct snd_soc_dai *dai, int mute) +{ + struct snd_soc_codec *codec = dai->codec; + u16 hp_mute = ALC5623_MISC_M_DAC_L_INPUT | ALC5623_MISC_M_DAC_R_INPUT; + u16 mute_reg = snd_soc_read(codec, ALC5623_MISC_CTRL) & ~hp_mute; + + if (mute) + mute_reg |= hp_mute; + + return snd_soc_write(codec, ALC5623_MISC_CTRL, mute_reg); +} + +#define ALC5623_ADD2_POWER_EN (ALC5623_PWR_ADD2_VREF \ + | ALC5623_PWR_ADD2_DAC_REF_CIR) + +#define ALC5623_ADD3_POWER_EN (ALC5623_PWR_ADD3_MAIN_BIAS \ + | ALC5623_PWR_ADD3_MIC1_BOOST_AD) + +#define ALC5623_ADD1_POWER_EN \ + (ALC5623_PWR_ADD1_SHORT_CURR_DET_EN | ALC5623_PWR_ADD1_SOFTGEN_EN \ + | ALC5623_PWR_ADD1_DEPOP_BUF_HP | ALC5623_PWR_ADD1_HP_OUT_AMP \ + | ALC5623_PWR_ADD1_HP_OUT_ENH_AMP) + +#define ALC5623_ADD1_POWER_EN_5622 \ + (ALC5623_PWR_ADD1_SHORT_CURR_DET_EN \ + | ALC5623_PWR_ADD1_HP_OUT_AMP) + +static void enable_power_depop(struct snd_soc_codec *codec) +{ + struct alc5623_priv *alc5623 = snd_soc_codec_get_drvdata(codec); + + snd_soc_update_bits(codec, ALC5623_PWR_MANAG_ADD1, + ALC5623_PWR_ADD1_SOFTGEN_EN, + ALC5623_PWR_ADD1_SOFTGEN_EN); + + snd_soc_write(codec, ALC5623_PWR_MANAG_ADD3, ALC5623_ADD3_POWER_EN); + + snd_soc_update_bits(codec, ALC5623_MISC_CTRL, + ALC5623_MISC_HP_DEPOP_MODE2_EN, + ALC5623_MISC_HP_DEPOP_MODE2_EN); + + msleep(500); + + snd_soc_write(codec, ALC5623_PWR_MANAG_ADD2, ALC5623_ADD2_POWER_EN); + + /* avoid writing '1' into 5622 reserved bits */ + if (alc5623->id == 0x22) + snd_soc_write(codec, ALC5623_PWR_MANAG_ADD1, + ALC5623_ADD1_POWER_EN_5622); + else + snd_soc_write(codec, ALC5623_PWR_MANAG_ADD1, + ALC5623_ADD1_POWER_EN); + + /* disable HP Depop2 */ + snd_soc_update_bits(codec, ALC5623_MISC_CTRL, + ALC5623_MISC_HP_DEPOP_MODE2_EN, + 0); + +} + +static int alc5623_set_bias_level(struct snd_soc_codec *codec, + enum snd_soc_bias_level level) +{ + switch (level) { + case SND_SOC_BIAS_ON: + enable_power_depop(codec); + break; + case SND_SOC_BIAS_PREPARE: + break; + case SND_SOC_BIAS_STANDBY: + /* everything off except vref/vmid, */ + snd_soc_write(codec, ALC5623_PWR_MANAG_ADD2, + ALC5623_PWR_ADD2_VREF); + snd_soc_write(codec, ALC5623_PWR_MANAG_ADD3, + ALC5623_PWR_ADD3_MAIN_BIAS); + break; + case SND_SOC_BIAS_OFF: + /* everything off, dac mute, inactive */ + snd_soc_write(codec, ALC5623_PWR_MANAG_ADD2, 0); + snd_soc_write(codec, ALC5623_PWR_MANAG_ADD3, 0); + snd_soc_write(codec, ALC5623_PWR_MANAG_ADD1, 0); + break; + } + codec->bias_level = level; + return 0; +} + +#define ALC5623_FORMATS (SNDRV_PCM_FMTBIT_S16_LE \ + | SNDRV_PCM_FMTBIT_S24_LE \ + | SNDRV_PCM_FMTBIT_S32_LE) + +static struct snd_soc_dai_ops alc5623_dai_ops = { + .hw_params = alc5623_pcm_hw_params, + .digital_mute = alc5623_mute, + .set_fmt = alc5623_set_dai_fmt, + .set_sysclk = alc5623_set_dai_sysclk, + .set_pll = alc5623_set_dai_pll, +}; + +static struct snd_soc_dai_driver alc5623_dai = { + .name = "alc5623-hifi", + .playback = { + .stream_name = "Playback", + .channels_min = 1, + .channels_max = 2, + .rate_min = 8000, + .rate_max = 48000, + .rates = SNDRV_PCM_RATE_8000_48000, + .formats = ALC5623_FORMATS,}, + .capture = { + .stream_name = "Capture", + .channels_min = 1, + .channels_max = 2, + .rate_min = 8000, + .rate_max = 48000, + .rates = SNDRV_PCM_RATE_8000_48000, + .formats = ALC5623_FORMATS,}, + + .ops = &alc5623_dai_ops, +}; + +static int alc5623_suspend(struct snd_soc_codec *codec, pm_message_t mesg) +{ + alc5623_set_bias_level(codec, SND_SOC_BIAS_OFF); + return 0; +} + +static int alc5623_resume(struct snd_soc_codec *codec) +{ + int i, step = codec->driver->reg_cache_step; + u16 *cache = codec->reg_cache; + + /* Sync reg_cache with the hardware */ + for (i = 2 ; i < codec->driver->reg_cache_size ; i += step) + snd_soc_write(codec, i, cache[i]); + + alc5623_set_bias_level(codec, SND_SOC_BIAS_STANDBY); + + /* charge alc5623 caps */ + if (codec->suspend_bias_level == SND_SOC_BIAS_ON) { + alc5623_set_bias_level(codec, SND_SOC_BIAS_STANDBY); + codec->bias_level = SND_SOC_BIAS_ON; + alc5623_set_bias_level(codec, codec->bias_level); + } + + return 0; +} + +static int alc5623_probe(struct snd_soc_codec *codec) +{ + struct alc5623_priv *alc5623 = snd_soc_codec_get_drvdata(codec); + int ret; + + ret = snd_soc_codec_set_cache_io(codec, 8, 16, alc5623->control_type); + if (ret < 0) { + dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret); + return ret; + } + + alc5623_reset(codec); + alc5623_fill_cache(codec); + + /* power on device */ + alc5623_set_bias_level(codec, SND_SOC_BIAS_STANDBY); + + if (alc5623->add_ctrl) { + snd_soc_write(codec, ALC5623_ADD_CTRL_REG, + alc5623->add_ctrl); + } + + if (alc5623->jack_det_ctrl) { + snd_soc_write(codec, ALC5623_JACK_DET_CTRL, + alc5623->jack_det_ctrl); + } + + switch (alc5623->id) { + default: + case 0x21: + snd_soc_add_controls(codec, rt5621_vol_snd_controls, + ARRAY_SIZE(rt5621_vol_snd_controls)); + break; + case 0x22: + snd_soc_add_controls(codec, rt5622_vol_snd_controls, + ARRAY_SIZE(rt5622_vol_snd_controls)); + break; + case 0x23: + snd_soc_add_controls(codec, alc5623_vol_snd_controls, + ARRAY_SIZE(alc5623_vol_snd_controls)); + break; + } + + snd_soc_add_controls(codec, alc5623_snd_controls, + ARRAY_SIZE(alc5623_snd_controls)); + + snd_soc_dapm_new_controls(codec, alc5623_dapm_widgets, + ARRAY_SIZE(alc5623_dapm_widgets)); + + /* set up audio path interconnects */ + snd_soc_dapm_add_routes(codec, intercon, ARRAY_SIZE(intercon)); + + switch (alc5623->id) { + default: + case 0x21: + case 0x22: + snd_soc_dapm_new_controls(codec, alc5623_dapm_amp_widgets, + ARRAY_SIZE(alc5623_dapm_amp_widgets)); + snd_soc_dapm_add_routes(codec, intercon_amp_spk, + ARRAY_SIZE(intercon_amp_spk)); + break; + case 0x23: + snd_soc_dapm_add_routes(codec, intercon_spk, + ARRAY_SIZE(intercon_spk)); + break; + } + + return ret; +} + +/* power down chip */ +static int alc5623_remove(struct snd_soc_codec *codec) +{ + alc5623_set_bias_level(codec, SND_SOC_BIAS_OFF); + return 0; +} + +static struct snd_soc_codec_driver soc_codec_device_alc5623 = { + .probe = alc5623_probe, + .remove = alc5623_remove, + .suspend = alc5623_suspend, + .resume = alc5623_resume, + .set_bias_level = alc5623_set_bias_level, + .reg_cache_size = ALC5623_VENDOR_ID2+2, + .reg_word_size = sizeof(u16), + .reg_cache_step = 2, +}; + +/* + * ALC5623 2 wire address is determined by A1 pin + * state during powerup. + * low = 0x1a + * high = 0x1b + */ +static int alc5623_i2c_probe(struct i2c_client *client, + const struct i2c_device_id *id) +{ + struct alc5623_platform_data *pdata; + struct alc5623_priv *alc5623; + int ret, vid1, vid2; + + vid1 = i2c_smbus_read_word_data(client, ALC5623_VENDOR_ID1); + if (vid1 < 0) { + dev_err(&client->dev, "failed to read I2C\n"); + return -EIO; + } + vid1 = ((vid1 & 0xff) << 8) | (vid1 >> 8); + + vid2 = i2c_smbus_read_byte_data(client, ALC5623_VENDOR_ID2); + if (vid2 < 0) { + dev_err(&client->dev, "failed to read I2C\n"); + return -EIO; + } + + if ((vid1 != 0x10ec) || (vid2 != id->driver_data)) { + dev_err(&client->dev, "unknown or wrong codec\n"); + dev_err(&client->dev, "Expected %x:%lx, got %x:%x\n", + 0x10ec, id->driver_data, + vid1, vid2); + return -ENODEV; + } + + dev_dbg(&client->dev, "Found codec id : alc56%02x\n", vid2); + + alc5623 = kzalloc(sizeof(struct alc5623_priv), GFP_KERNEL); + if (alc5623 == NULL) { + ret = -ENOMEM; + goto err; + } + + pdata = client->dev.platform_data; + if (pdata) { + alc5623->add_ctrl = pdata->add_ctrl; + alc5623->jack_det_ctrl = pdata->jack_det_ctrl; + } + + alc5623->id = vid2; + switch (alc5623->id) { + case 0x21: + alc5623_dai.name = "alc5621-hifi"; + break; + case 0x22: + alc5623_dai.name = "alc5622-hifi"; + break; + default: + case 0x23: + alc5623_dai.name = "alc5623-hifi"; + break; + } + + i2c_set_clientdata(client, alc5623); + alc5623->control_data = client; + alc5623->control_type = SND_SOC_I2C; + mutex_init(&alc5623->mutex); + + ret = snd_soc_register_codec(&client->dev, + &soc_codec_device_alc5623, &alc5623_dai, 1); + if (ret != 0) { + dev_err(&client->dev, "Failed to register codec: %d\n", ret); + goto err; + } + + return 0; + +err: + return ret; +} + +static int alc5623_i2c_remove(struct i2c_client *client) +{ + struct alc5623_priv *alc5623 = i2c_get_clientdata(client); + + snd_soc_unregister_codec(&client->dev); + kfree(alc5623); + return 0; +} + +static const struct i2c_device_id alc5623_i2c_table[] = { + {"alc5621", 0x21}, + {"alc5622", 0x22}, + {"alc5623", 0x23}, + {} +}; +MODULE_DEVICE_TABLE(i2c, alc5623_i2c_table); + +/* i2c codec control layer */ +static struct i2c_driver alc5623_i2c_driver = { + .driver = { + .name = "alc562x-codec", + .owner = THIS_MODULE, + }, + .probe = alc5623_i2c_probe, + .remove = __devexit_p(alc5623_i2c_remove), + .id_table = alc5623_i2c_table, +}; + +static int __init alc5623_modinit(void) +{ + int ret; + + ret = i2c_add_driver(&alc5623_i2c_driver); + if (ret != 0) { + printk(KERN_ERR "%s: can't add i2c driver", __func__); + return ret; + } + + return ret; +} +module_init(alc5623_modinit); + +static void __exit alc5623_modexit(void) +{ + i2c_del_driver(&alc5623_i2c_driver); +} +module_exit(alc5623_modexit); + +MODULE_DESCRIPTION("ASoC alc5621/2/3 driver"); +MODULE_AUTHOR("Arnaud Patard "); +MODULE_LICENSE("GPL"); diff --git a/sound/soc/codecs/alc5623.h b/sound/soc/codecs/alc5623.h new file mode 100644 index 000000000000..f3d68260d425 --- /dev/null +++ b/sound/soc/codecs/alc5623.h @@ -0,0 +1,161 @@ +/* + * alc5623.h -- alc562[123] ALSA Soc Audio driver + * + * Copyright 2008 Realtek Microelectronics + * Copyright 2010 Arnaud Patard + * + * Author: flove + * Arnaud Patard + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#ifndef _ALC5623_H +#define _ALC5623_H + +#define ALC5623_RESET 0x00 +/* 5621 5622 5623 */ +/* speaker output vol 2 2 */ +/* line output vol 4 2 */ +/* HP output vol 4 0 4 */ +#define ALC5623_SPK_OUT_VOL 0x02 +#define ALC5623_HP_OUT_VOL 0x04 +#define ALC5623_MONO_AUX_OUT_VOL 0x06 +#define ALC5623_AUXIN_VOL 0x08 +#define ALC5623_LINE_IN_VOL 0x0A +#define ALC5623_STEREO_DAC_VOL 0x0C +#define ALC5623_MIC_VOL 0x0E +#define ALC5623_MIC_ROUTING_CTRL 0x10 +#define ALC5623_ADC_REC_GAIN 0x12 +#define ALC5623_ADC_REC_MIXER 0x14 +#define ALC5623_SOFT_VOL_CTRL_TIME 0x16 +/* ALC5623_OUTPUT_MIXER_CTRL : */ +/* same remark as for reg 2 line vs speaker */ +#define ALC5623_OUTPUT_MIXER_CTRL 0x1C +#define ALC5623_MIC_CTRL 0x22 + +#define ALC5623_DAI_CONTROL 0x34 +#define ALC5623_DAI_SDP_MASTER_MODE (0 << 15) +#define ALC5623_DAI_SDP_SLAVE_MODE (1 << 15) +#define ALC5623_DAI_I2S_PCM_MODE (1 << 14) +#define ALC5623_DAI_MAIN_I2S_BCLK_POL_CTRL (1 << 7) +#define ALC5623_DAI_ADC_DATA_L_R_SWAP (1 << 5) +#define ALC5623_DAI_DAC_DATA_L_R_SWAP (1 << 4) +#define ALC5623_DAI_I2S_DL_MASK (3 << 2) +#define ALC5623_DAI_I2S_DL_32 (3 << 2) +#define ALC5623_DAI_I2S_DL_24 (2 << 2) +#define ALC5623_DAI_I2S_DL_20 (1 << 2) +#define ALC5623_DAI_I2S_DL_16 (0 << 2) +#define ALC5623_DAI_I2S_DF_PCM (3 << 0) +#define ALC5623_DAI_I2S_DF_LEFT (2 << 0) +#define ALC5623_DAI_I2S_DF_RIGHT (1 << 0) +#define ALC5623_DAI_I2S_DF_I2S (0 << 0) + +#define ALC5623_STEREO_AD_DA_CLK_CTRL 0x36 +#define ALC5623_COMPANDING_CTRL 0x38 + +#define ALC5623_PWR_MANAG_ADD1 0x3A +#define ALC5623_PWR_ADD1_MAIN_I2S_EN (1 << 15) +#define ALC5623_PWR_ADD1_ZC_DET_PD_EN (1 << 14) +#define ALC5623_PWR_ADD1_MIC1_BIAS_EN (1 << 11) +#define ALC5623_PWR_ADD1_SHORT_CURR_DET_EN (1 << 10) +#define ALC5623_PWR_ADD1_SOFTGEN_EN (1 << 8) /* rsvd on 5622 */ +#define ALC5623_PWR_ADD1_DEPOP_BUF_HP (1 << 6) /* rsvd on 5622 */ +#define ALC5623_PWR_ADD1_HP_OUT_AMP (1 << 5) +#define ALC5623_PWR_ADD1_HP_OUT_ENH_AMP (1 << 4) /* rsvd on 5622 */ +#define ALC5623_PWR_ADD1_DEPOP_BUF_AUX (1 << 2) +#define ALC5623_PWR_ADD1_AUX_OUT_AMP (1 << 1) +#define ALC5623_PWR_ADD1_AUX_OUT_ENH_AMP (1 << 0) /* rsvd on 5622 */ + +#define ALC5623_PWR_MANAG_ADD2 0x3C +#define ALC5623_PWR_ADD2_LINEOUT (1 << 15) /* rt5623 */ +#define ALC5623_PWR_ADD2_CLASS_AB (1 << 15) /* rt5621 */ +#define ALC5623_PWR_ADD2_CLASS_D (1 << 14) /* rt5621 */ +#define ALC5623_PWR_ADD2_VREF (1 << 13) +#define ALC5623_PWR_ADD2_PLL (1 << 12) +#define ALC5623_PWR_ADD2_DAC_REF_CIR (1 << 10) +#define ALC5623_PWR_ADD2_L_DAC_CLK (1 << 9) +#define ALC5623_PWR_ADD2_R_DAC_CLK (1 << 8) +#define ALC5623_PWR_ADD2_L_ADC_CLK_GAIN (1 << 7) +#define ALC5623_PWR_ADD2_R_ADC_CLK_GAIN (1 << 6) +#define ALC5623_PWR_ADD2_L_HP_MIXER (1 << 5) +#define ALC5623_PWR_ADD2_R_HP_MIXER (1 << 4) +#define ALC5623_PWR_ADD2_SPK_MIXER (1 << 3) +#define ALC5623_PWR_ADD2_MONO_MIXER (1 << 2) +#define ALC5623_PWR_ADD2_L_ADC_REC_MIXER (1 << 1) +#define ALC5623_PWR_ADD2_R_ADC_REC_MIXER (1 << 0) + +#define ALC5623_PWR_MANAG_ADD3 0x3E +#define ALC5623_PWR_ADD3_MAIN_BIAS (1 << 15) +#define ALC5623_PWR_ADD3_AUXOUT_L_VOL_AMP (1 << 14) +#define ALC5623_PWR_ADD3_AUXOUT_R_VOL_AMP (1 << 13) +#define ALC5623_PWR_ADD3_SPK_OUT (1 << 12) +#define ALC5623_PWR_ADD3_HP_L_OUT_VOL (1 << 10) +#define ALC5623_PWR_ADD3_HP_R_OUT_VOL (1 << 9) +#define ALC5623_PWR_ADD3_LINEIN_L_VOL (1 << 7) +#define ALC5623_PWR_ADD3_LINEIN_R_VOL (1 << 6) +#define ALC5623_PWR_ADD3_AUXIN_L_VOL (1 << 5) +#define ALC5623_PWR_ADD3_AUXIN_R_VOL (1 << 4) +#define ALC5623_PWR_ADD3_MIC1_FUN_CTRL (1 << 3) +#define ALC5623_PWR_ADD3_MIC2_FUN_CTRL (1 << 2) +#define ALC5623_PWR_ADD3_MIC1_BOOST_AD (1 << 1) +#define ALC5623_PWR_ADD3_MIC2_BOOST_AD (1 << 0) + +#define ALC5623_ADD_CTRL_REG 0x40 + +#define ALC5623_GLOBAL_CLK_CTRL_REG 0x42 +#define ALC5623_GBL_CLK_SYS_SOUR_SEL_PLL (1 << 15) +#define ALC5623_GBL_CLK_SYS_SOUR_SEL_MCLK (0 << 15) +#define ALC5623_GBL_CLK_PLL_SOUR_SEL_BITCLK (1 << 14) +#define ALC5623_GBL_CLK_PLL_SOUR_SEL_MCLK (0 << 14) +#define ALC5623_GBL_CLK_PLL_DIV_RATIO_DIV8 (3 << 1) +#define ALC5623_GBL_CLK_PLL_DIV_RATIO_DIV4 (2 << 1) +#define ALC5623_GBL_CLK_PLL_DIV_RATIO_DIV2 (1 << 1) +#define ALC5623_GBL_CLK_PLL_DIV_RATIO_DIV1 (0 << 1) +#define ALC5623_GBL_CLK_PLL_PRE_DIV2 (1 << 0) +#define ALC5623_GBL_CLK_PLL_PRE_DIV1 (0 << 0) + +#define ALC5623_PLL_CTRL 0x44 +#define ALC5623_PLL_CTRL_N_VAL(n) (((n)&0xff) << 8) +#define ALC5623_PLL_CTRL_K_VAL(k) (((k)&0x7) << 4) +#define ALC5623_PLL_CTRL_M_VAL(m) ((m)&0xf) + +#define ALC5623_GPIO_OUTPUT_PIN_CTRL 0x4A +#define ALC5623_GPIO_PIN_CONFIG 0x4C +#define ALC5623_GPIO_PIN_POLARITY 0x4E +#define ALC5623_GPIO_PIN_STICKY 0x50 +#define ALC5623_GPIO_PIN_WAKEUP 0x52 +#define ALC5623_GPIO_PIN_STATUS 0x54 +#define ALC5623_GPIO_PIN_SHARING 0x56 +#define ALC5623_OVER_CURR_STATUS 0x58 +#define ALC5623_JACK_DET_CTRL 0x5A + +#define ALC5623_MISC_CTRL 0x5E +#define ALC5623_MISC_DISABLE_FAST_VREG (1 << 15) +#define ALC5623_MISC_SPK_CLASS_AB_OC_PD (1 << 13) /* 5621 */ +#define ALC5623_MISC_SPK_CLASS_AB_OC_DET (1 << 12) /* 5621 */ +#define ALC5623_MISC_HP_DEPOP_MODE3_EN (1 << 10) +#define ALC5623_MISC_HP_DEPOP_MODE2_EN (1 << 9) +#define ALC5623_MISC_HP_DEPOP_MODE1_EN (1 << 8) +#define ALC5623_MISC_AUXOUT_DEPOP_MODE3_EN (1 << 6) +#define ALC5623_MISC_AUXOUT_DEPOP_MODE2_EN (1 << 5) +#define ALC5623_MISC_AUXOUT_DEPOP_MODE1_EN (1 << 4) +#define ALC5623_MISC_M_DAC_L_INPUT (1 << 3) +#define ALC5623_MISC_M_DAC_R_INPUT (1 << 2) +#define ALC5623_MISC_IRQOUT_INV_CTRL (1 << 0) + +#define ALC5623_PSEDUEO_SPATIAL_CTRL 0x60 +#define ALC5623_EQ_CTRL 0x62 +#define ALC5623_EQ_MODE_ENABLE 0x66 +#define ALC5623_AVC_CTRL 0x68 +#define ALC5623_HID_CTRL_INDEX 0x6A +#define ALC5623_HID_CTRL_DATA 0x6C +#define ALC5623_VENDOR_ID1 0x7C +#define ALC5623_VENDOR_ID2 0x7E + +#define ALC5623_PLL_FR_MCLK 0 +#define ALC5623_PLL_FR_BCK 1 +#endif -- cgit v1.2.2 From 7e6120c57cf92f005f72c6345c0961415099881e Mon Sep 17 00:00:00 2001 From: Peter Ujfalusi Date: Mon, 25 Oct 2010 11:34:23 +0300 Subject: ASoC: TWL4030: Use usleep_range when appropriate Change the busy loop delays with usleep_range or msleep calls. Signed-off-by: Peter Ujfalusi Acked-by: Mark Brown Signed-off-by: Liam Girdwood --- sound/soc/codecs/twl4030.c | 31 +++++++++++++++++++++++-------- 1 file changed, 23 insertions(+), 8 deletions(-) (limited to 'sound/soc/codecs') diff --git a/sound/soc/codecs/twl4030.c b/sound/soc/codecs/twl4030.c index cbebec6ba1ba..a6ceddb0bb7d 100644 --- a/sound/soc/codecs/twl4030.c +++ b/sound/soc/codecs/twl4030.c @@ -233,6 +233,16 @@ static int twl4030_write(struct snd_soc_codec *codec, return 0; } +static inline void twl4030_wait_ms(int time) +{ + if (time < 60) { + time *= 1000; + usleep_range(time, time + 500); + } else { + msleep(time); + } +} + static void twl4030_codec_enable(struct snd_soc_codec *codec, int enable) { struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec); @@ -338,10 +348,14 @@ static void twl4030_init_chip(struct snd_soc_codec *codec) twl4030_write(codec, TWL4030_REG_ANAMICL, reg | TWL4030_CNCL_OFFSET_START); - /* wait for offset cancellation to complete */ + /* + * Wait for offset cancellation to complete. + * Since this takes a while, do not slam the i2c. + * Start polling the status after ~20ms. + */ + msleep(20); do { - /* this takes a little while, so don't slam i2c */ - udelay(2000); + usleep_range(1000, 2000); twl_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &byte, TWL4030_REG_ANAMICL); } while ((i++ < 100) && @@ -725,9 +739,12 @@ static void headset_ramp(struct snd_soc_codec *codec, int ramp) /* Base values for ramp delay calculation: 2^19 - 2^26 */ unsigned int ramp_base[] = {524288, 1048576, 2097152, 4194304, 8388608, 16777216, 33554432, 67108864}; + unsigned int delay; hs_gain = twl4030_read_reg_cache(codec, TWL4030_REG_HS_GAIN_SET); hs_pop = twl4030_read_reg_cache(codec, TWL4030_REG_HS_POPN_SET); + delay = (ramp_base[(hs_pop & TWL4030_RAMP_DELAY) >> 2] / + twl4030->sysclk) + 1; /* Enable external mute control, this dramatically reduces * the pop-noise */ @@ -751,16 +768,14 @@ static void headset_ramp(struct snd_soc_codec *codec, int ramp) hs_pop |= TWL4030_RAMP_EN; twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop); /* Wait ramp delay time + 1, so the VMID can settle */ - mdelay((ramp_base[(hs_pop & TWL4030_RAMP_DELAY) >> 2] / - twl4030->sysclk) + 1); + twl4030_wait_ms(delay); } else { /* Headset ramp-down _not_ according to * the TRM, but in a way that it is working */ hs_pop &= ~TWL4030_RAMP_EN; twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop); /* Wait ramp delay time + 1, so the VMID can settle */ - mdelay((ramp_base[(hs_pop & TWL4030_RAMP_DELAY) >> 2] / - twl4030->sysclk) + 1); + twl4030_wait_ms(delay); /* Bypass the reg_cache to mute the headset */ twl_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, hs_gain & (~0x0f), @@ -835,7 +850,7 @@ static int digimic_event(struct snd_soc_dapm_widget *w, struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(w->codec); if (twl4030->digimic_delay) - mdelay(twl4030->digimic_delay); + twl4030_wait_ms(twl4030->digimic_delay); return 0; } -- cgit v1.2.2 From fec6dd833e733b5d9588a1f1e4d81118b79b5774 Mon Sep 17 00:00:00 2001 From: Mark Brown Date: Wed, 27 Oct 2010 13:48:36 -0700 Subject: ASoC: Store DC offset correction for wm_hubs devices in class W mode Providing the analogue configuration of the output path remains the same the DC offset corrected by the DC servo will remain identical so we can skip the callibration, reducing the startup time for the headphone output. Implement this for the wm_hubs devices as has been done for several other CODECs. Don't do this if we have any analogue paths enabled since offsets may be being introduced by the analogue paths which could vary outside the control of the driver. Signed-off-by: Mark Brown Acked-by: Liam Girdwood --- sound/soc/codecs/wm8993.c | 2 ++ sound/soc/codecs/wm8994.c | 3 ++ sound/soc/codecs/wm_hubs.c | 69 ++++++++++++++++++++++++++++++---------------- sound/soc/codecs/wm_hubs.h | 3 ++ 4 files changed, 54 insertions(+), 23 deletions(-) (limited to 'sound/soc/codecs') diff --git a/sound/soc/codecs/wm8993.c b/sound/soc/codecs/wm8993.c index 589e3fa24734..67fe5ccc6082 100644 --- a/sound/soc/codecs/wm8993.c +++ b/sound/soc/codecs/wm8993.c @@ -735,6 +735,7 @@ static int class_w_put(struct snd_kcontrol *kcontrol, 0); } wm8993->class_w_users++; + wm8993->hubs_data.class_w = true; } /* Implement the change */ @@ -751,6 +752,7 @@ static int class_w_put(struct snd_kcontrol *kcontrol, WM8993_CP_DYN_V); } wm8993->class_w_users--; + wm8993->hubs_data.class_w = false; } dev_dbg(codec->dev, "Indirect DAC use count now %d\n", diff --git a/sound/soc/codecs/wm8994.c b/sound/soc/codecs/wm8994.c index 0db59c3aa5d4..3f70dee048b0 100644 --- a/sound/soc/codecs/wm8994.c +++ b/sound/soc/codecs/wm8994.c @@ -2228,6 +2228,7 @@ static int clk_sys_event(struct snd_soc_dapm_widget *w, static void wm8994_update_class_w(struct snd_soc_codec *codec) { + struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); int enable = 1; int source = 0; /* GCC flow analysis can't track enable */ int reg, reg_r; @@ -2278,11 +2279,13 @@ static void wm8994_update_class_w(struct snd_soc_codec *codec) WM8994_CP_DYN_PWR | WM8994_CP_DYN_SRC_SEL_MASK, source | WM8994_CP_DYN_PWR); + wm8994->hubs.class_w = true; } else { dev_dbg(codec->dev, "Class W disabled\n"); snd_soc_update_bits(codec, WM8994_CLASS_W_1, WM8994_CP_DYN_PWR, 0); + wm8994->hubs.class_w = false; } } diff --git a/sound/soc/codecs/wm_hubs.c b/sound/soc/codecs/wm_hubs.c index 2cb81538cd91..31c2a5724d85 100644 --- a/sound/soc/codecs/wm_hubs.c +++ b/sound/soc/codecs/wm_hubs.c @@ -94,6 +94,18 @@ static void calibrate_dc_servo(struct snd_soc_codec *codec) struct wm_hubs_data *hubs = snd_soc_codec_get_drvdata(codec); u16 reg, reg_l, reg_r, dcs_cfg; + /* If we're using a digital only path and have a previously + * callibrated DC servo offset stored then use that. */ + if (hubs->class_w && hubs->class_w_dcs) { + dev_dbg(codec->dev, "Using cached DC servo offset %x\n", + hubs->class_w_dcs); + snd_soc_write(codec, WM8993_DC_SERVO_3, hubs->class_w_dcs); + wait_for_dc_servo(codec, + WM8993_DCS_TRIG_DAC_WR_0 | + WM8993_DCS_TRIG_DAC_WR_1); + return; + } + /* Set for 32 series updates */ snd_soc_update_bits(codec, WM8993_DC_SERVO_1, WM8993_DCS_SERIES_NO_01_MASK, @@ -101,34 +113,34 @@ static void calibrate_dc_servo(struct snd_soc_codec *codec) wait_for_dc_servo(codec, WM8993_DCS_TRIG_SERIES_0 | WM8993_DCS_TRIG_SERIES_1); + /* Different chips in the family support different readback + * methods. + */ + switch (hubs->dcs_readback_mode) { + case 0: + reg_l = snd_soc_read(codec, WM8993_DC_SERVO_READBACK_1) + & WM8993_DCS_INTEG_CHAN_0_MASK;; + reg_r = snd_soc_read(codec, WM8993_DC_SERVO_READBACK_2) + & WM8993_DCS_INTEG_CHAN_1_MASK; + break; + case 1: + reg = snd_soc_read(codec, WM8993_DC_SERVO_3); + reg_l = (reg & WM8993_DCS_DAC_WR_VAL_1_MASK) + >> WM8993_DCS_DAC_WR_VAL_1_SHIFT; + reg_r = reg & WM8993_DCS_DAC_WR_VAL_0_MASK; + break; + default: + WARN(1, "Unknown DCS readback method"); + break; + } + + dev_dbg(codec->dev, "DCS input: %x %x\n", reg_l, reg_r); + /* Apply correction to DC servo result */ if (hubs->dcs_codes) { dev_dbg(codec->dev, "Applying %d code DC servo correction\n", hubs->dcs_codes); - /* Different chips in the family support different - * readback methods. - */ - switch (hubs->dcs_readback_mode) { - case 0: - reg_l = snd_soc_read(codec, WM8993_DC_SERVO_READBACK_1) - & WM8993_DCS_INTEG_CHAN_0_MASK;; - reg_r = snd_soc_read(codec, WM8993_DC_SERVO_READBACK_2) - & WM8993_DCS_INTEG_CHAN_1_MASK; - break; - case 1: - reg = snd_soc_read(codec, WM8993_DC_SERVO_3); - reg_l = (reg & WM8993_DCS_DAC_WR_VAL_1_MASK) - >> WM8993_DCS_DAC_WR_VAL_1_SHIFT; - reg_r = reg & WM8993_DCS_DAC_WR_VAL_0_MASK; - break; - default: - WARN(1, "Unknown DCS readback method"); - break; - } - - dev_dbg(codec->dev, "DCS input: %x %x\n", reg_l, reg_r); - /* HPOUT1L */ if (reg_l + hubs->dcs_codes > 0 && reg_l + hubs->dcs_codes < 0xff) @@ -148,7 +160,15 @@ static void calibrate_dc_servo(struct snd_soc_codec *codec) wait_for_dc_servo(codec, WM8993_DCS_TRIG_DAC_WR_0 | WM8993_DCS_TRIG_DAC_WR_1); + } else { + dcs_cfg = reg_l << WM8993_DCS_DAC_WR_VAL_1_SHIFT; + dcs_cfg |= reg_r; } + + /* Save the callibrated offset if we're in class W mode and + * therefore don't have any analogue signal mixed in. */ + if (hubs->class_w) + hubs->class_w_dcs = dcs_cfg; } /* @@ -163,6 +183,9 @@ static int wm8993_put_dc_servo(struct snd_kcontrol *kcontrol, ret = snd_soc_put_volsw_2r(kcontrol, ucontrol); + /* Updating the analogue gains invalidates the DC servo cache */ + hubs->class_w_dcs = 0; + /* If we're applying an offset correction then updating the * callibration would be likely to introduce further offsets. */ if (hubs->dcs_codes) diff --git a/sound/soc/codecs/wm_hubs.h b/sound/soc/codecs/wm_hubs.h index e51c16683589..f8a5e976b5e6 100644 --- a/sound/soc/codecs/wm_hubs.h +++ b/sound/soc/codecs/wm_hubs.h @@ -23,6 +23,9 @@ struct wm_hubs_data { int dcs_codes; int dcs_readback_mode; int hp_startup_mode; + + bool class_w; + u16 class_w_dcs; }; extern int wm_hubs_add_analogue_controls(struct snd_soc_codec *); -- cgit v1.2.2 From 473f89fff76568a9f30c53b458e6323d48b0ab95 Mon Sep 17 00:00:00 2001 From: Jarkko Nikula Date: Fri, 29 Oct 2010 16:47:44 +0300 Subject: ASoC: Fix SND_SOC_ALL_CODECS typo for alc5623 Include alc5623.c in SND_SOC_ALL_CODECS when dependencies are met. Signed-off-by: Jarkko Nikula Acked-by: Liam Girdwood Signed-off-by: Mark Brown --- sound/soc/codecs/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'sound/soc/codecs') diff --git a/sound/soc/codecs/Kconfig b/sound/soc/codecs/Kconfig index 8d11fbd1b1aa..e61fbab48aa2 100644 --- a/sound/soc/codecs/Kconfig +++ b/sound/soc/codecs/Kconfig @@ -22,7 +22,7 @@ config SND_SOC_ALL_CODECS select SND_SOC_AK4535 if I2C select SND_SOC_AK4642 if I2C select SND_SOC_AK4671 if I2C - select SND_SOC_ALC562 if I2C + select SND_SOC_ALC5623 if I2C select SND_SOC_CQ0093VC if MFD_DAVINCI_VOICECODEC select SND_SOC_CS42L51 if I2C select SND_SOC_CS4270 if I2C -- cgit v1.2.2 From 79ee820d2aa24ac2577ca4e89ecc49c26d099707 Mon Sep 17 00:00:00 2001 From: Jarkko Nikula Date: Mon, 1 Nov 2010 14:03:55 +0200 Subject: ASoC: tlv320aic3x: Use gpio_is_valid in checking for valid gpio_reset I promised to convert this at some point. Signed-off-by: Jarkko Nikula Acked-by: Mark Brown Signed-off-by: Liam Girdwood --- sound/soc/codecs/tlv320aic3x.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) (limited to 'sound/soc/codecs') diff --git a/sound/soc/codecs/tlv320aic3x.c b/sound/soc/codecs/tlv320aic3x.c index fc687790188b..157b534585f4 100644 --- a/sound/soc/codecs/tlv320aic3x.c +++ b/sound/soc/codecs/tlv320aic3x.c @@ -1075,7 +1075,7 @@ static int aic3x_regulator_event(struct notifier_block *nb, * Put codec to reset and require cache sync as at least one * of the supplies was disabled */ - if (aic3x->gpio_reset >= 0) + if (gpio_is_valid(aic3x->gpio_reset)) gpio_set_value(aic3x->gpio_reset, 0); aic3x->codec->cache_sync = 1; } @@ -1102,7 +1102,7 @@ static int aic3x_set_power(struct snd_soc_codec *codec, int power) if (!codec->cache_sync) goto out; - if (aic3x->gpio_reset >= 0) { + if (gpio_is_valid(aic3x->gpio_reset)) { udelay(1); gpio_set_value(aic3x->gpio_reset, 1); } @@ -1359,7 +1359,7 @@ static int aic3x_probe(struct snd_soc_codec *codec) return ret; } - if (aic3x->gpio_reset >= 0) { + if (gpio_is_valid(aic3x->gpio_reset)) { ret = gpio_request(aic3x->gpio_reset, "tlv320aic3x reset"); if (ret != 0) goto err_gpio; @@ -1414,7 +1414,7 @@ err_notif: &aic3x->disable_nb[i].nb); regulator_bulk_free(ARRAY_SIZE(aic3x->supplies), aic3x->supplies); err_get: - if (aic3x->gpio_reset >= 0) + if (gpio_is_valid(aic3x->gpio_reset)) gpio_free(aic3x->gpio_reset); err_gpio: kfree(aic3x); @@ -1427,7 +1427,7 @@ static int aic3x_remove(struct snd_soc_codec *codec) int i; aic3x_set_bias_level(codec, SND_SOC_BIAS_OFF); - if (aic3x->gpio_reset >= 0) { + if (gpio_is_valid(aic3x->gpio_reset)) { gpio_set_value(aic3x->gpio_reset, 0); gpio_free(aic3x->gpio_reset); } -- cgit v1.2.2 From 414c73abfd0e565950f3b02336cf516147f0e104 Mon Sep 17 00:00:00 2001 From: Jarkko Nikula Date: Mon, 1 Nov 2010 14:03:56 +0200 Subject: ASoC: tlv320aic3x: Add support to shared common reset line This is aimed to configurations where multiple aic3x codecs share the same reset line and are powered from same supply voltages. Currently aic3x_probe will fail if trying to request already requested gpio_reset and passing -1 to another aic3x instances cause that those instances cannot release reset in aic3x_set_power. That is, another instances can work only if primary aic3x instance is powered and reset is released. Solve this by implementing a list of probed instances that is used for checking if other instance shares the same gpio_reset number. If a shared reset line exists, then only first instance tries to request and configure it and the last instance releases it. Runtime modifications are not needed since aic3x_regulator_event with help of regulator framework takes already care that reset is pulled down only when some or all supplies are disabled meaning that all instances using them are idle. Signed-off-by: Jarkko Nikula Acked-by: Mark Brown Signed-off-by: Liam Girdwood --- sound/soc/codecs/tlv320aic3x.c | 28 +++++++++++++++++++++++++--- 1 file changed, 25 insertions(+), 3 deletions(-) (limited to 'sound/soc/codecs') diff --git a/sound/soc/codecs/tlv320aic3x.c b/sound/soc/codecs/tlv320aic3x.c index 157b534585f4..684ca3a57caa 100644 --- a/sound/soc/codecs/tlv320aic3x.c +++ b/sound/soc/codecs/tlv320aic3x.c @@ -61,6 +61,8 @@ static const char *aic3x_supply_names[AIC3X_NUM_SUPPLIES] = { "DRVDD", /* ADC Analog and Output Driver Voltage */ }; +static LIST_HEAD(reset_list); + struct aic3x_priv; struct aic3x_disable_nb { @@ -77,6 +79,7 @@ struct aic3x_priv { struct aic3x_setup_data *setup; void *control_data; unsigned int sysclk; + struct list_head list; int master; int gpio_reset; int power; @@ -1344,11 +1347,25 @@ static int aic3x_init(struct snd_soc_codec *codec) return 0; } +static bool aic3x_is_shared_reset(struct aic3x_priv *aic3x) +{ + struct aic3x_priv *a; + + list_for_each_entry(a, &reset_list, list) { + if (gpio_is_valid(aic3x->gpio_reset) && + aic3x->gpio_reset == a->gpio_reset) + return true; + } + + return false; +} + static int aic3x_probe(struct snd_soc_codec *codec) { struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec); int ret, i; + INIT_LIST_HEAD(&aic3x->list); codec->control_data = aic3x->control_data; aic3x->codec = codec; codec->idle_bias_off = 1; @@ -1359,7 +1376,8 @@ static int aic3x_probe(struct snd_soc_codec *codec) return ret; } - if (gpio_is_valid(aic3x->gpio_reset)) { + if (gpio_is_valid(aic3x->gpio_reset) && + !aic3x_is_shared_reset(aic3x)) { ret = gpio_request(aic3x->gpio_reset, "tlv320aic3x reset"); if (ret != 0) goto err_gpio; @@ -1405,6 +1423,7 @@ static int aic3x_probe(struct snd_soc_codec *codec) snd_soc_add_controls(codec, &aic3x_classd_amp_gain_ctrl, 1); aic3x_add_widgets(codec); + list_add(&aic3x->list, &reset_list); return 0; @@ -1414,7 +1433,8 @@ err_notif: &aic3x->disable_nb[i].nb); regulator_bulk_free(ARRAY_SIZE(aic3x->supplies), aic3x->supplies); err_get: - if (gpio_is_valid(aic3x->gpio_reset)) + if (gpio_is_valid(aic3x->gpio_reset) && + !aic3x_is_shared_reset(aic3x)) gpio_free(aic3x->gpio_reset); err_gpio: kfree(aic3x); @@ -1427,7 +1447,9 @@ static int aic3x_remove(struct snd_soc_codec *codec) int i; aic3x_set_bias_level(codec, SND_SOC_BIAS_OFF); - if (gpio_is_valid(aic3x->gpio_reset)) { + list_del(&aic3x->list); + if (gpio_is_valid(aic3x->gpio_reset) && + !aic3x_is_shared_reset(aic3x)) { gpio_set_value(aic3x->gpio_reset, 0); gpio_free(aic3x->gpio_reset); } -- cgit v1.2.2 From 7b0f42b59a01a2cc563c5f8670133b819e5c9895 Mon Sep 17 00:00:00 2001 From: Mark Brown Date: Wed, 3 Nov 2010 13:48:04 -0400 Subject: ASoC: Remove register write trace from WM8994 We now have trace in the ASoC core so we don't need to our own trace in the driver. Signed-off-by: Mark Brown Acked-by: Liam Girdwood --- sound/soc/codecs/wm8994.c | 2 -- 1 file changed, 2 deletions(-) (limited to 'sound/soc/codecs') diff --git a/sound/soc/codecs/wm8994.c b/sound/soc/codecs/wm8994.c index 3f70dee048b0..d81cac5b93b4 100644 --- a/sound/soc/codecs/wm8994.c +++ b/sound/soc/codecs/wm8994.c @@ -1730,8 +1730,6 @@ static int wm8994_write(struct snd_soc_codec *codec, unsigned int reg, if (!wm8994_volatile(reg)) wm8994->reg_cache[reg] = value; - dev_dbg(codec->dev, "0x%x = 0x%x\n", reg, value); - return wm8994_reg_write(codec->control_data, reg, value); } -- cgit v1.2.2 From 11e16eb365f4f6979cfcb2a2d379338b383590d9 Mon Sep 17 00:00:00 2001 From: Mark Brown Date: Wed, 3 Nov 2010 14:45:07 -0400 Subject: ASoC: Use pm_wakeup_event() in WM8962 jack detection Ensure that the system does not suspend while we process a WM8962 jack event by using pm_wakeup_event() to block the suspend while we're waiting for the jack to settle. Use a slightly longer timeout than the jack waits to allow for other stuff to take over and delays in scheduling. Signed-off-by: Mark Brown Acked-by: Liam Girdwood --- sound/soc/codecs/wm8962.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'sound/soc/codecs') diff --git a/sound/soc/codecs/wm8962.c b/sound/soc/codecs/wm8962.c index 894d0cd3aa9b..2eaf9bb36b57 100644 --- a/sound/soc/codecs/wm8962.c +++ b/sound/soc/codecs/wm8962.c @@ -3353,6 +3353,8 @@ static irqreturn_t wm8962_irq(int irq, void *data) if (active & (WM8962_MICSCD_EINT | WM8962_MICD_EINT)) { dev_dbg(codec->dev, "Microphone event detected\n"); + pm_wakeup_event(codec->dev, 300); + schedule_delayed_work(&wm8962->mic_work, msecs_to_jiffies(250)); } -- cgit v1.2.2 From ce6120cca2589ede530200c7cfe11ac9f144333c Mon Sep 17 00:00:00 2001 From: Liam Girdwood Date: Fri, 5 Nov 2010 15:53:46 +0200 Subject: ASoC: Decouple DAPM from CODECs Decoupling Dynamic Audio Power Management (DAPM) from codec devices is required when developing ASoC further. Such as for other ASoC components to have DAPM widgets or when extending DAPM to handle cross-device paths. This patch decouples DAPM related variables from struct snd_soc_codec and moves them to new struct snd_soc_dapm_context that is used to encapsulate DAPM context of a device. ASoC core and API of DAPM functions are modified to use DAPM context instead of codec. This patch does not change current functionality and a large part of changes come because of structure and internal API changes. Core implementation is from Liam Girdwood with some minor core changes, codecs and machine driver conversions from Jarkko Nikula . Signed-off-by: Liam Girdwood Signed-off-by: Jarkko Nikula Cc: Nicolas Ferre Cc: Manuel Lauss Cc: Mike Frysinger Cc: Cliff Cai Cc: Kevin Hilman Cc: Ryan Mallon Cc: Timur Tabi Cc: Sascha Hauer Cc: Lars-Peter Clausen Cc: Arnaud Patard (Rtp) Cc: Wan ZongShun Cc: Eric Miao Cc: Jassi Brar Cc: Daniel Gloeckner Cc: Kuninori Morimoto Signed-off-by: Mark Brown --- sound/soc/codecs/88pm860x-codec.c | 9 +++++---- sound/soc/codecs/ad1836.c | 5 +++-- sound/soc/codecs/ad193x.c | 5 +++-- sound/soc/codecs/ak4535.c | 9 +++++---- sound/soc/codecs/ak4642.c | 2 +- sound/soc/codecs/ak4671.c | 9 +++++---- sound/soc/codecs/alc5623.c | 23 ++++++++++++----------- sound/soc/codecs/cq93vc.c | 2 +- sound/soc/codecs/cs42l51.c | 5 +++-- sound/soc/codecs/cx20442.c | 15 ++++++++------- sound/soc/codecs/da7210.c | 2 +- sound/soc/codecs/jz4740.c | 10 ++++++---- sound/soc/codecs/max98088.c | 12 +++++++----- sound/soc/codecs/ssm2602.c | 9 +++++---- sound/soc/codecs/stac9766.c | 3 ++- sound/soc/codecs/tlv320aic23.c | 9 +++++---- sound/soc/codecs/tlv320aic3x.c | 22 ++++++++++++---------- sound/soc/codecs/tlv320dac33.c | 15 ++++++++------- sound/soc/codecs/tpa6130a2.c | 5 +++-- sound/soc/codecs/twl4030.c | 13 +++++++------ sound/soc/codecs/twl6040.c | 12 ++++++------ sound/soc/codecs/uda134x.c | 2 +- sound/soc/codecs/uda1380.c | 13 +++++++------ sound/soc/codecs/wm2000.c | 5 +++-- sound/soc/codecs/wm8350.c | 28 +++++++++++++++------------- sound/soc/codecs/wm8400.c | 11 ++++++----- sound/soc/codecs/wm8510.c | 11 ++++++----- sound/soc/codecs/wm8523.c | 11 ++++++----- sound/soc/codecs/wm8580.c | 11 ++++++----- sound/soc/codecs/wm8711.c | 9 +++++---- sound/soc/codecs/wm8728.c | 11 ++++++----- sound/soc/codecs/wm8731.c | 13 +++++++------ sound/soc/codecs/wm8741.c | 7 ++++--- sound/soc/codecs/wm8750.c | 11 ++++++----- sound/soc/codecs/wm8753.c | 29 ++++++++++++++++------------- sound/soc/codecs/wm8776.c | 9 +++++---- sound/soc/codecs/wm8804.c | 6 +++--- sound/soc/codecs/wm8900.c | 11 ++++++----- sound/soc/codecs/wm8903.c | 11 ++++++----- sound/soc/codecs/wm8904.c | 33 +++++++++++++++++---------------- sound/soc/codecs/wm8940.c | 5 +++-- sound/soc/codecs/wm8955.c | 11 ++++++----- sound/soc/codecs/wm8960.c | 25 +++++++++++++------------ sound/soc/codecs/wm8961.c | 11 ++++++----- sound/soc/codecs/wm8962.c | 30 ++++++++++++++++-------------- sound/soc/codecs/wm8971.c | 29 ++++++++++++++++------------- sound/soc/codecs/wm8974.c | 11 ++++++----- sound/soc/codecs/wm8978.c | 11 ++++++----- sound/soc/codecs/wm8985.c | 11 ++++++----- sound/soc/codecs/wm8988.c | 9 +++++---- sound/soc/codecs/wm8990.c | 11 ++++++----- sound/soc/codecs/wm8993.c | 9 +++++---- sound/soc/codecs/wm8994.c | 13 +++++++------ sound/soc/codecs/wm9081.c | 9 +++++---- sound/soc/codecs/wm9090.c | 17 +++++++++-------- sound/soc/codecs/wm9705.c | 6 ++++-- sound/soc/codecs/wm9712.c | 9 +++++---- sound/soc/codecs/wm9713.c | 8 +++++--- sound/soc/codecs/wm_hubs.c | 18 +++++++++++------- 59 files changed, 379 insertions(+), 312 deletions(-) (limited to 'sound/soc/codecs') diff --git a/sound/soc/codecs/88pm860x-codec.c b/sound/soc/codecs/88pm860x-codec.c index 01d19e9f53f9..a15a3e974f0d 100644 --- a/sound/soc/codecs/88pm860x-codec.c +++ b/sound/soc/codecs/88pm860x-codec.c @@ -1172,7 +1172,7 @@ static int pm860x_set_bias_level(struct snd_soc_codec *codec, break; case SND_SOC_BIAS_STANDBY: - if (codec->bias_level == SND_SOC_BIAS_OFF) { + if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) { /* Enable Audio PLL & Audio section */ data = AUDIO_PLL | AUDIO_SECTION_RESET | AUDIO_SECTION_ON; @@ -1185,7 +1185,7 @@ static int pm860x_set_bias_level(struct snd_soc_codec *codec, pm860x_set_bits(codec->control_data, REG_MISC2, data, 0); break; } - codec->bias_level = level; + codec->dapm.bias_level = level; return 0; } @@ -1346,6 +1346,7 @@ EXPORT_SYMBOL_GPL(pm860x_mic_jack_detect); static int pm860x_probe(struct snd_soc_codec *codec) { struct pm860x_priv *pm860x = snd_soc_codec_get_drvdata(codec); + struct snd_soc_dapm_context *dapm = &codec->dapm; int i, ret; pm860x->codec = codec; @@ -1374,9 +1375,9 @@ static int pm860x_probe(struct snd_soc_codec *codec) snd_soc_add_controls(codec, pm860x_snd_controls, ARRAY_SIZE(pm860x_snd_controls)); - snd_soc_dapm_new_controls(codec, pm860x_dapm_widgets, + snd_soc_dapm_new_controls(dapm, pm860x_dapm_widgets, ARRAY_SIZE(pm860x_dapm_widgets)); - snd_soc_dapm_add_routes(codec, audio_map, ARRAY_SIZE(audio_map)); + snd_soc_dapm_add_routes(dapm, audio_map, ARRAY_SIZE(audio_map)); return 0; out_codec: diff --git a/sound/soc/codecs/ad1836.c b/sound/soc/codecs/ad1836.c index d272534c8f84..c71b05ddd752 100644 --- a/sound/soc/codecs/ad1836.c +++ b/sound/soc/codecs/ad1836.c @@ -220,6 +220,7 @@ static struct snd_soc_dai_driver ad1836_dai = { static int ad1836_probe(struct snd_soc_codec *codec) { struct ad1836_priv *ad1836 = snd_soc_codec_get_drvdata(codec); + struct snd_soc_dapm_context *dapm = &codec->dapm; int ret = 0; codec->control_data = ad1836->control_data; @@ -252,9 +253,9 @@ static int ad1836_probe(struct snd_soc_codec *codec) snd_soc_add_controls(codec, ad1836_snd_controls, ARRAY_SIZE(ad1836_snd_controls)); - snd_soc_dapm_new_controls(codec, ad1836_dapm_widgets, + snd_soc_dapm_new_controls(dapm, ad1836_dapm_widgets, ARRAY_SIZE(ad1836_dapm_widgets)); - snd_soc_dapm_add_routes(codec, audio_paths, ARRAY_SIZE(audio_paths)); + snd_soc_dapm_add_routes(dapm, audio_paths, ARRAY_SIZE(audio_paths)); return ret; } diff --git a/sound/soc/codecs/ad193x.c b/sound/soc/codecs/ad193x.c index fa2834c91b9f..dc105d8aaa0f 100644 --- a/sound/soc/codecs/ad193x.c +++ b/sound/soc/codecs/ad193x.c @@ -353,6 +353,7 @@ static struct snd_soc_dai_driver ad193x_dai = { static int ad193x_probe(struct snd_soc_codec *codec) { struct ad193x_priv *ad193x = snd_soc_codec_get_drvdata(codec); + struct snd_soc_dapm_context *dapm = &codec->dapm; int ret; codec->control_data = ad193x->control_data; @@ -385,9 +386,9 @@ static int ad193x_probe(struct snd_soc_codec *codec) snd_soc_add_controls(codec, ad193x_snd_controls, ARRAY_SIZE(ad193x_snd_controls)); - snd_soc_dapm_new_controls(codec, ad193x_dapm_widgets, + snd_soc_dapm_new_controls(dapm, ad193x_dapm_widgets, ARRAY_SIZE(ad193x_dapm_widgets)); - snd_soc_dapm_add_routes(codec, audio_paths, ARRAY_SIZE(audio_paths)); + snd_soc_dapm_add_routes(dapm, audio_paths, ARRAY_SIZE(audio_paths)); return ret; } diff --git a/sound/soc/codecs/ak4535.c b/sound/soc/codecs/ak4535.c index cd88c8f32a38..52abb93a7dce 100644 --- a/sound/soc/codecs/ak4535.c +++ b/sound/soc/codecs/ak4535.c @@ -290,10 +290,11 @@ static const struct snd_soc_dapm_route audio_map[] = { static int ak4535_add_widgets(struct snd_soc_codec *codec) { - snd_soc_dapm_new_controls(codec, ak4535_dapm_widgets, - ARRAY_SIZE(ak4535_dapm_widgets)); + struct snd_soc_dapm_context *dapm = &codec->dapm; - snd_soc_dapm_add_routes(codec, audio_map, ARRAY_SIZE(audio_map)); + snd_soc_dapm_new_controls(dapm, ak4535_dapm_widgets, + ARRAY_SIZE(ak4535_dapm_widgets)); + snd_soc_dapm_add_routes(dapm, audio_map, ARRAY_SIZE(audio_map)); return 0; } @@ -399,7 +400,7 @@ static int ak4535_set_bias_level(struct snd_soc_codec *codec, ak4535_write(codec, AK4535_PM1, i & (~0x80)); break; } - codec->bias_level = level; + codec->dapm.bias_level = level; return 0; } diff --git a/sound/soc/codecs/ak4642.c b/sound/soc/codecs/ak4642.c index 90c90b7f4a2e..f00eba313dfd 100644 --- a/sound/soc/codecs/ak4642.c +++ b/sound/soc/codecs/ak4642.c @@ -26,7 +26,7 @@ #include #include #include -#include +#include #include #include diff --git a/sound/soc/codecs/ak4671.c b/sound/soc/codecs/ak4671.c index 24f5f49bb9d2..1d6573c38af4 100644 --- a/sound/soc/codecs/ak4671.c +++ b/sound/soc/codecs/ak4671.c @@ -437,10 +437,11 @@ static const struct snd_soc_dapm_route intercon[] = { static int ak4671_add_widgets(struct snd_soc_codec *codec) { - snd_soc_dapm_new_controls(codec, ak4671_dapm_widgets, - ARRAY_SIZE(ak4671_dapm_widgets)); + struct snd_soc_dapm_context *dapm = &codec->dapm; - snd_soc_dapm_add_routes(codec, intercon, ARRAY_SIZE(intercon)); + snd_soc_dapm_new_controls(dapm, ak4671_dapm_widgets, + ARRAY_SIZE(ak4671_dapm_widgets)); + snd_soc_dapm_add_routes(dapm, intercon, ARRAY_SIZE(intercon)); return 0; } @@ -602,7 +603,7 @@ static int ak4671_set_bias_level(struct snd_soc_codec *codec, snd_soc_write(codec, AK4671_AD_DA_POWER_MANAGEMENT, 0x00); break; } - codec->bias_level = level; + codec->dapm.bias_level = level; return 0; } diff --git a/sound/soc/codecs/alc5623.c b/sound/soc/codecs/alc5623.c index fac61744f8c7..5a45067b43ba 100644 --- a/sound/soc/codecs/alc5623.c +++ b/sound/soc/codecs/alc5623.c @@ -832,7 +832,7 @@ static int alc5623_set_bias_level(struct snd_soc_codec *codec, snd_soc_write(codec, ALC5623_PWR_MANAG_ADD1, 0); break; } - codec->bias_level = level; + codec->dapm.bias_level = level; return 0; } @@ -888,10 +888,10 @@ static int alc5623_resume(struct snd_soc_codec *codec) alc5623_set_bias_level(codec, SND_SOC_BIAS_STANDBY); /* charge alc5623 caps */ - if (codec->suspend_bias_level == SND_SOC_BIAS_ON) { + if (codec->dapm.suspend_bias_level == SND_SOC_BIAS_ON) { alc5623_set_bias_level(codec, SND_SOC_BIAS_STANDBY); - codec->bias_level = SND_SOC_BIAS_ON; - alc5623_set_bias_level(codec, codec->bias_level); + codec->dapm.bias_level = SND_SOC_BIAS_ON; + alc5623_set_bias_level(codec, codec->dapm.bias_level); } return 0; @@ -900,6 +900,7 @@ static int alc5623_resume(struct snd_soc_codec *codec) static int alc5623_probe(struct snd_soc_codec *codec) { struct alc5623_priv *alc5623 = snd_soc_codec_get_drvdata(codec); + struct snd_soc_dapm_context *dapm = &codec->dapm; int ret; ret = snd_soc_codec_set_cache_io(codec, 8, 16, alc5623->control_type); @@ -943,24 +944,24 @@ static int alc5623_probe(struct snd_soc_codec *codec) snd_soc_add_controls(codec, alc5623_snd_controls, ARRAY_SIZE(alc5623_snd_controls)); - snd_soc_dapm_new_controls(codec, alc5623_dapm_widgets, + snd_soc_dapm_new_controls(dapm, alc5623_dapm_widgets, ARRAY_SIZE(alc5623_dapm_widgets)); /* set up audio path interconnects */ - snd_soc_dapm_add_routes(codec, intercon, ARRAY_SIZE(intercon)); + snd_soc_dapm_add_routes(dapm, intercon, ARRAY_SIZE(intercon)); switch (alc5623->id) { default: case 0x21: case 0x22: - snd_soc_dapm_new_controls(codec, alc5623_dapm_amp_widgets, + snd_soc_dapm_new_controls(dapm, alc5623_dapm_amp_widgets, ARRAY_SIZE(alc5623_dapm_amp_widgets)); - snd_soc_dapm_add_routes(codec, intercon_amp_spk, - ARRAY_SIZE(intercon_amp_spk)); + snd_soc_dapm_add_routes(dapm, intercon_amp_spk, + ARRAY_SIZE(intercon_amp_spk)); break; case 0x23: - snd_soc_dapm_add_routes(codec, intercon_spk, - ARRAY_SIZE(intercon_spk)); + snd_soc_dapm_add_routes(dapm, intercon_spk, + ARRAY_SIZE(intercon_spk)); break; } diff --git a/sound/soc/codecs/cq93vc.c b/sound/soc/codecs/cq93vc.c index 823643932dde..98b9e5294cbe 100644 --- a/sound/soc/codecs/cq93vc.c +++ b/sound/soc/codecs/cq93vc.c @@ -116,7 +116,7 @@ static int cq93vc_set_bias_level(struct snd_soc_codec *codec, DAVINCI_VC_REG12_POWER_ALL_OFF); break; } - codec->bias_level = level; + codec->dapm.bias_level = level; return 0; } diff --git a/sound/soc/codecs/cs42l51.c b/sound/soc/codecs/cs42l51.c index cb086eaf4e07..a7fdca36b490 100644 --- a/sound/soc/codecs/cs42l51.c +++ b/sound/soc/codecs/cs42l51.c @@ -519,6 +519,7 @@ static struct snd_soc_dai_driver cs42l51_dai = { static int cs42l51_probe(struct snd_soc_codec *codec) { struct cs42l51_private *cs42l51 = snd_soc_codec_get_drvdata(codec); + struct snd_soc_dapm_context *dapm = &codec->dapm; int ret, reg; codec->control_data = cs42l51->control_data; @@ -550,9 +551,9 @@ static int cs42l51_probe(struct snd_soc_codec *codec) snd_soc_add_controls(codec, cs42l51_snd_controls, ARRAY_SIZE(cs42l51_snd_controls)); - snd_soc_dapm_new_controls(codec, cs42l51_dapm_widgets, + snd_soc_dapm_new_controls(dapm, cs42l51_dapm_widgets, ARRAY_SIZE(cs42l51_dapm_widgets)); - snd_soc_dapm_add_routes(codec, cs42l51_routes, + snd_soc_dapm_add_routes(dapm, cs42l51_routes, ARRAY_SIZE(cs42l51_routes)); return 0; diff --git a/sound/soc/codecs/cx20442.c b/sound/soc/codecs/cx20442.c index e8d27c8f9ba3..11beb1a77c4e 100644 --- a/sound/soc/codecs/cx20442.c +++ b/sound/soc/codecs/cx20442.c @@ -18,7 +18,7 @@ #include #include -#include +#include #include "cx20442.h" @@ -89,10 +89,11 @@ static const struct snd_soc_dapm_route cx20442_audio_map[] = { static int cx20442_add_widgets(struct snd_soc_codec *codec) { - snd_soc_dapm_new_controls(codec, cx20442_dapm_widgets, - ARRAY_SIZE(cx20442_dapm_widgets)); + struct snd_soc_dapm_context *dapm = &codec->dapm; - snd_soc_dapm_add_routes(codec, cx20442_audio_map, + snd_soc_dapm_new_controls(dapm, cx20442_dapm_widgets, + ARRAY_SIZE(cx20442_dapm_widgets)); + snd_soc_dapm_add_routes(dapm, cx20442_audio_map, ARRAY_SIZE(cx20442_audio_map)); return 0; @@ -263,7 +264,7 @@ static void v253_close(struct tty_struct *tty) /* Prevent the codec driver from further accessing the modem */ codec->hw_write = NULL; cx20442->control_data = NULL; - codec->pop_time = 0; + codec->dapm.pop_time = 0; } /* Line discipline .hangup() */ @@ -291,7 +292,7 @@ static void v253_receive(struct tty_struct *tty, /* Set up codec driver access to modem controls */ cx20442->control_data = tty; codec->hw_write = (hw_write_t)tty->ops->write; - codec->pop_time = 1; + codec->dapm.pop_time = 1; } } @@ -348,7 +349,7 @@ static int cx20442_codec_probe(struct snd_soc_codec *codec) cx20442->control_data = NULL; codec->hw_write = NULL; - codec->pop_time = 0; + codec->dapm.pop_time = 0; return 0; } diff --git a/sound/soc/codecs/da7210.c b/sound/soc/codecs/da7210.c index 58bb9b994811..92fd9d7a9221 100644 --- a/sound/soc/codecs/da7210.c +++ b/sound/soc/codecs/da7210.c @@ -21,7 +21,7 @@ #include #include #include -#include +#include #include #include diff --git a/sound/soc/codecs/jz4740.c b/sound/soc/codecs/jz4740.c index 16253ec9b022..8a45562a96d4 100644 --- a/sound/soc/codecs/jz4740.c +++ b/sound/soc/codecs/jz4740.c @@ -266,7 +266,7 @@ static int jz4740_codec_set_bias_level(struct snd_soc_codec *codec, break; case SND_SOC_BIAS_STANDBY: /* The only way to clear the suspend flag is to reset the codec */ - if (codec->bias_level == SND_SOC_BIAS_OFF) + if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) jz4740_codec_wakeup(codec); mask = JZ4740_CODEC_1_VREF_DISABLE | @@ -288,23 +288,25 @@ static int jz4740_codec_set_bias_level(struct snd_soc_codec *codec, break; } - codec->bias_level = level; + codec->dapm.bias_level = level; return 0; } static int jz4740_codec_dev_probe(struct snd_soc_codec *codec) { + struct snd_soc_dapm_context *dapm = &codec->dapm; + snd_soc_update_bits(codec, JZ4740_REG_CODEC_1, JZ4740_CODEC_1_SW2_ENABLE, JZ4740_CODEC_1_SW2_ENABLE); snd_soc_add_controls(codec, jz4740_codec_controls, ARRAY_SIZE(jz4740_codec_controls)); - snd_soc_dapm_new_controls(codec, jz4740_codec_dapm_widgets, + snd_soc_dapm_new_controls(dapm, jz4740_codec_dapm_widgets, ARRAY_SIZE(jz4740_codec_dapm_widgets)); - snd_soc_dapm_add_routes(codec, jz4740_codec_dapm_routes, + snd_soc_dapm_add_routes(dapm, jz4740_codec_dapm_routes, ARRAY_SIZE(jz4740_codec_dapm_routes)); snd_soc_dapm_new_widgets(codec); diff --git a/sound/soc/codecs/max98088.c b/sound/soc/codecs/max98088.c index bc22ee93a75d..ef06007d8895 100644 --- a/sound/soc/codecs/max98088.c +++ b/sound/soc/codecs/max98088.c @@ -1224,15 +1224,17 @@ static const struct snd_soc_dapm_route audio_map[] = { static int max98088_add_widgets(struct snd_soc_codec *codec) { - snd_soc_dapm_new_controls(codec, max98088_dapm_widgets, + struct snd_soc_dapm_context *dapm = &codec->dapm; + + snd_soc_dapm_new_controls(dapm, max98088_dapm_widgets, ARRAY_SIZE(max98088_dapm_widgets)); - snd_soc_dapm_add_routes(codec, audio_map, ARRAY_SIZE(audio_map)); + snd_soc_dapm_add_routes(dapm, audio_map, ARRAY_SIZE(audio_map)); snd_soc_add_controls(codec, max98088_snd_controls, ARRAY_SIZE(max98088_snd_controls)); - snd_soc_dapm_new_widgets(codec); + snd_soc_dapm_new_widgets(dapm); return 0; } @@ -1617,7 +1619,7 @@ static int max98088_set_bias_level(struct snd_soc_codec *codec, break; case SND_SOC_BIAS_STANDBY: - if (codec->bias_level == SND_SOC_BIAS_OFF) + if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) max98088_sync_cache(codec); snd_soc_update_bits(codec, M98088_REG_4C_PWR_EN_IN, @@ -1630,7 +1632,7 @@ static int max98088_set_bias_level(struct snd_soc_codec *codec, codec->cache_sync = 1; break; } - codec->bias_level = level; + codec->dapm.bias_level = level; return 0; } diff --git a/sound/soc/codecs/ssm2602.c b/sound/soc/codecs/ssm2602.c index 6f38d619bf8a..adbc3e8dafc8 100644 --- a/sound/soc/codecs/ssm2602.c +++ b/sound/soc/codecs/ssm2602.c @@ -207,10 +207,11 @@ static const struct snd_soc_dapm_route audio_conn[] = { static int ssm2602_add_widgets(struct snd_soc_codec *codec) { - snd_soc_dapm_new_controls(codec, ssm2602_dapm_widgets, - ARRAY_SIZE(ssm2602_dapm_widgets)); + struct snd_soc_dapm_context *dapm = &codec->dapm; - snd_soc_dapm_add_routes(codec, audio_conn, ARRAY_SIZE(audio_conn)); + snd_soc_dapm_new_controls(dapm, ssm2602_dapm_widgets, + ARRAY_SIZE(ssm2602_dapm_widgets)); + snd_soc_dapm_add_routes(dapm, audio_conn, ARRAY_SIZE(audio_conn)); return 0; } @@ -493,7 +494,7 @@ static int ssm2602_set_bias_level(struct snd_soc_codec *codec, break; } - codec->bias_level = level; + codec->dapm.bias_level = level; return 0; } diff --git a/sound/soc/codecs/stac9766.c b/sound/soc/codecs/stac9766.c index 00d67cc8e206..8aad3a2c4f3d 100644 --- a/sound/soc/codecs/stac9766.c +++ b/sound/soc/codecs/stac9766.c @@ -24,6 +24,7 @@ #include #include #include +#include #include #include "stac9766.h" @@ -236,7 +237,7 @@ static int stac9766_set_bias_level(struct snd_soc_codec *codec, stac9766_ac97_write(codec, AC97_POWERDOWN, 0xffff); break; } - codec->bias_level = level; + codec->dapm.bias_level = level; return 0; } diff --git a/sound/soc/codecs/tlv320aic23.c b/sound/soc/codecs/tlv320aic23.c index e8652b1ae326..d9d8e844d63f 100644 --- a/sound/soc/codecs/tlv320aic23.c +++ b/sound/soc/codecs/tlv320aic23.c @@ -391,11 +391,12 @@ static int set_sample_rate_control(struct snd_soc_codec *codec, int mclk, static int tlv320aic23_add_widgets(struct snd_soc_codec *codec) { - snd_soc_dapm_new_controls(codec, tlv320aic23_dapm_widgets, - ARRAY_SIZE(tlv320aic23_dapm_widgets)); + struct snd_soc_dapm_context *dapm = &codec->dapm; + snd_soc_dapm_new_controls(dapm, tlv320aic23_dapm_widgets, + ARRAY_SIZE(tlv320aic23_dapm_widgets)); /* set up audio path interconnects */ - snd_soc_dapm_add_routes(codec, intercon, ARRAY_SIZE(intercon)); + snd_soc_dapm_add_routes(dapm, intercon, ARRAY_SIZE(intercon)); return 0; } @@ -574,7 +575,7 @@ static int tlv320aic23_set_bias_level(struct snd_soc_codec *codec, tlv320aic23_write(codec, TLV320AIC23_PWR, 0xffff); break; } - codec->bias_level = level; + codec->dapm.bias_level = level; return 0; } diff --git a/sound/soc/codecs/tlv320aic3x.c b/sound/soc/codecs/tlv320aic3x.c index fc687790188b..6173c2b4c364 100644 --- a/sound/soc/codecs/tlv320aic3x.c +++ b/sound/soc/codecs/tlv320aic3x.c @@ -183,7 +183,7 @@ static int snd_soc_dapm_put_volsw_aic3x(struct snd_kcontrol *kcontrol, if (snd_soc_test_bits(widget->codec, reg, val_mask, val)) { /* find dapm widget path assoc with kcontrol */ - list_for_each_entry(path, &widget->codec->dapm_paths, list) { + list_for_each_entry(path, &widget->dapm->paths, list) { if (path->kcontrol != kcontrol) continue; @@ -199,7 +199,7 @@ static int snd_soc_dapm_put_volsw_aic3x(struct snd_kcontrol *kcontrol, } if (found) - snd_soc_dapm_sync(widget->codec); + snd_soc_dapm_sync(widget->dapm); } ret = snd_soc_update_bits(widget->codec, reg, val_mask, val); @@ -788,17 +788,19 @@ static const struct snd_soc_dapm_route intercon_3007[] = { static int aic3x_add_widgets(struct snd_soc_codec *codec) { struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec); + struct snd_soc_dapm_context *dapm = &codec->dapm; - snd_soc_dapm_new_controls(codec, aic3x_dapm_widgets, + snd_soc_dapm_new_controls(dapm, aic3x_dapm_widgets, ARRAY_SIZE(aic3x_dapm_widgets)); /* set up audio path interconnects */ - snd_soc_dapm_add_routes(codec, intercon, ARRAY_SIZE(intercon)); + snd_soc_dapm_add_routes(dapm, intercon, ARRAY_SIZE(intercon)); if (aic3x->model == AIC3X_MODEL_3007) { - snd_soc_dapm_new_controls(codec, aic3007_dapm_widgets, + snd_soc_dapm_new_controls(dapm, aic3007_dapm_widgets, ARRAY_SIZE(aic3007_dapm_widgets)); - snd_soc_dapm_add_routes(codec, intercon_3007, ARRAY_SIZE(intercon_3007)); + snd_soc_dapm_add_routes(dapm, intercon_3007, + ARRAY_SIZE(intercon_3007)); } return 0; @@ -1135,7 +1137,7 @@ static int aic3x_set_bias_level(struct snd_soc_codec *codec, case SND_SOC_BIAS_ON: break; case SND_SOC_BIAS_PREPARE: - if (codec->bias_level == SND_SOC_BIAS_STANDBY && + if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY && aic3x->master) { /* enable pll */ reg = snd_soc_read(codec, AIC3X_PLL_PROGA_REG); @@ -1146,7 +1148,7 @@ static int aic3x_set_bias_level(struct snd_soc_codec *codec, case SND_SOC_BIAS_STANDBY: if (!aic3x->power) aic3x_set_power(codec, 1); - if (codec->bias_level == SND_SOC_BIAS_PREPARE && + if (codec->dapm.bias_level == SND_SOC_BIAS_PREPARE && aic3x->master) { /* disable pll */ reg = snd_soc_read(codec, AIC3X_PLL_PROGA_REG); @@ -1159,7 +1161,7 @@ static int aic3x_set_bias_level(struct snd_soc_codec *codec, aic3x_set_power(codec, 0); break; } - codec->bias_level = level; + codec->dapm.bias_level = level; return 0; } @@ -1351,7 +1353,7 @@ static int aic3x_probe(struct snd_soc_codec *codec) codec->control_data = aic3x->control_data; aic3x->codec = codec; - codec->idle_bias_off = 1; + codec->dapm.idle_bias_off = 1; ret = snd_soc_codec_set_cache_io(codec, 8, 8, aic3x->control_type); if (ret != 0) { diff --git a/sound/soc/codecs/tlv320dac33.c b/sound/soc/codecs/tlv320dac33.c index c5ab8c805771..7149c14b289e 100644 --- a/sound/soc/codecs/tlv320dac33.c +++ b/sound/soc/codecs/tlv320dac33.c @@ -628,11 +628,12 @@ static const struct snd_soc_dapm_route audio_map[] = { static int dac33_add_widgets(struct snd_soc_codec *codec) { - snd_soc_dapm_new_controls(codec, dac33_dapm_widgets, - ARRAY_SIZE(dac33_dapm_widgets)); + struct snd_soc_dapm_context *dapm = &codec->dapm; + snd_soc_dapm_new_controls(dapm, dac33_dapm_widgets, + ARRAY_SIZE(dac33_dapm_widgets)); /* set up audio path interconnects */ - snd_soc_dapm_add_routes(codec, audio_map, ARRAY_SIZE(audio_map)); + snd_soc_dapm_add_routes(dapm, audio_map, ARRAY_SIZE(audio_map)); return 0; } @@ -649,7 +650,7 @@ static int dac33_set_bias_level(struct snd_soc_codec *codec, case SND_SOC_BIAS_PREPARE: break; case SND_SOC_BIAS_STANDBY: - if (codec->bias_level == SND_SOC_BIAS_OFF) { + if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) { /* Coming from OFF, switch on the codec */ ret = dac33_hard_power(codec, 1); if (ret != 0) @@ -660,14 +661,14 @@ static int dac33_set_bias_level(struct snd_soc_codec *codec, break; case SND_SOC_BIAS_OFF: /* Do not power off, when the codec is already off */ - if (codec->bias_level == SND_SOC_BIAS_OFF) + if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) return 0; ret = dac33_hard_power(codec, 0); if (ret != 0) return ret; break; } - codec->bias_level = level; + codec->dapm.bias_level = level; return 0; } @@ -1415,7 +1416,7 @@ static int dac33_soc_probe(struct snd_soc_codec *codec) codec->control_data = dac33->control_data; codec->hw_write = (hw_write_t) i2c_master_send; - codec->idle_bias_off = 1; + codec->dapm.idle_bias_off = 1; dac33->codec = codec; /* Read the tlv320dac33 ID registers */ diff --git a/sound/soc/codecs/tpa6130a2.c b/sound/soc/codecs/tpa6130a2.c index ee4fb201de60..f9a92ea6b50a 100644 --- a/sound/soc/codecs/tpa6130a2.c +++ b/sound/soc/codecs/tpa6130a2.c @@ -388,16 +388,17 @@ static const struct snd_soc_dapm_route audio_map[] = { int tpa6130a2_add_controls(struct snd_soc_codec *codec) { struct tpa6130a2_data *data; + struct snd_soc_dapm_context *dapm = &codec->dapm; if (tpa6130a2_client == NULL) return -ENODEV; data = i2c_get_clientdata(tpa6130a2_client); - snd_soc_dapm_new_controls(codec, tpa6130a2_dapm_widgets, + snd_soc_dapm_new_controls(dapm, tpa6130a2_dapm_widgets, ARRAY_SIZE(tpa6130a2_dapm_widgets)); - snd_soc_dapm_add_routes(codec, audio_map, ARRAY_SIZE(audio_map)); + snd_soc_dapm_add_routes(dapm, audio_map, ARRAY_SIZE(audio_map)); if (data->id == TPA6140A2) return snd_soc_add_controls(codec, tpa6140a2_controls, diff --git a/sound/soc/codecs/twl4030.c b/sound/soc/codecs/twl4030.c index cbebec6ba1ba..f4602e8b67cc 100644 --- a/sound/soc/codecs/twl4030.c +++ b/sound/soc/codecs/twl4030.c @@ -1621,10 +1621,11 @@ static const struct snd_soc_dapm_route intercon[] = { static int twl4030_add_widgets(struct snd_soc_codec *codec) { - snd_soc_dapm_new_controls(codec, twl4030_dapm_widgets, - ARRAY_SIZE(twl4030_dapm_widgets)); + struct snd_soc_dapm_context *dapm = &codec->dapm; - snd_soc_dapm_add_routes(codec, intercon, ARRAY_SIZE(intercon)); + snd_soc_dapm_new_controls(dapm, twl4030_dapm_widgets, + ARRAY_SIZE(twl4030_dapm_widgets)); + snd_soc_dapm_add_routes(dapm, intercon, ARRAY_SIZE(intercon)); return 0; } @@ -1638,14 +1639,14 @@ static int twl4030_set_bias_level(struct snd_soc_codec *codec, case SND_SOC_BIAS_PREPARE: break; case SND_SOC_BIAS_STANDBY: - if (codec->bias_level == SND_SOC_BIAS_OFF) + if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) twl4030_codec_enable(codec, 1); break; case SND_SOC_BIAS_OFF: twl4030_codec_enable(codec, 0); break; } - codec->bias_level = level; + codec->dapm.bias_level = level; return 0; } @@ -2245,7 +2246,7 @@ static int twl4030_soc_probe(struct snd_soc_codec *codec) snd_soc_codec_set_drvdata(codec, twl4030); /* Set the defaults, and power up the codec */ twl4030->sysclk = twl4030_codec_get_mclk() / 1000; - codec->idle_bias_off = 1; + codec->dapm.idle_bias_off = 1; twl4030_init_chip(codec); diff --git a/sound/soc/codecs/twl6040.c b/sound/soc/codecs/twl6040.c index 10f6e5214511..0dd2d5397264 100644 --- a/sound/soc/codecs/twl6040.c +++ b/sound/soc/codecs/twl6040.c @@ -641,12 +641,12 @@ static const struct snd_soc_dapm_route intercon[] = { static int twl6040_add_widgets(struct snd_soc_codec *codec) { - snd_soc_dapm_new_controls(codec, twl6040_dapm_widgets, - ARRAY_SIZE(twl6040_dapm_widgets)); - - snd_soc_dapm_add_routes(codec, intercon, ARRAY_SIZE(intercon)); + struct snd_soc_dapm_context *dapm = &codec->dapm; - snd_soc_dapm_new_widgets(codec); + snd_soc_dapm_new_controls(dapm, twl6040_dapm_widgets, + ARRAY_SIZE(twl6040_dapm_widgets)); + snd_soc_dapm_add_routes(dapm, intercon, ARRAY_SIZE(intercon)); + snd_soc_dapm_new_widgets(dapm); return 0; } @@ -739,7 +739,7 @@ static int twl6040_set_bias_level(struct snd_soc_codec *codec, break; } - codec->bias_level = level; + codec->dapm.bias_level = level; return 0; } diff --git a/sound/soc/codecs/uda134x.c b/sound/soc/codecs/uda134x.c index 7540a509a6f5..8ea81d48124a 100644 --- a/sound/soc/codecs/uda134x.c +++ b/sound/soc/codecs/uda134x.c @@ -389,7 +389,7 @@ static int uda134x_set_bias_level(struct snd_soc_codec *codec, pd->power(0); break; } - codec->bias_level = level; + codec->dapm.bias_level = level; return 0; } diff --git a/sound/soc/codecs/uda1380.c b/sound/soc/codecs/uda1380.c index 0c6c725736c6..cd6dd19fa1aa 100644 --- a/sound/soc/codecs/uda1380.c +++ b/sound/soc/codecs/uda1380.c @@ -414,10 +414,11 @@ static const struct snd_soc_dapm_route audio_map[] = { static int uda1380_add_widgets(struct snd_soc_codec *codec) { - snd_soc_dapm_new_controls(codec, uda1380_dapm_widgets, - ARRAY_SIZE(uda1380_dapm_widgets)); + struct snd_soc_dapm_context *dapm = &codec->dapm; - snd_soc_dapm_add_routes(codec, audio_map, ARRAY_SIZE(audio_map)); + snd_soc_dapm_new_controls(dapm, uda1380_dapm_widgets, + ARRAY_SIZE(uda1380_dapm_widgets)); + snd_soc_dapm_add_routes(dapm, audio_map, ARRAY_SIZE(audio_map)); return 0; } @@ -603,7 +604,7 @@ static int uda1380_set_bias_level(struct snd_soc_codec *codec, int reg; struct uda1380_platform_data *pdata = codec->dev->platform_data; - if (codec->bias_level == level) + if (codec->dapm.bias_level == level) return 0; switch (level) { @@ -613,7 +614,7 @@ static int uda1380_set_bias_level(struct snd_soc_codec *codec, uda1380_write(codec, UDA1380_PM, R02_PON_BIAS | pm); break; case SND_SOC_BIAS_STANDBY: - if (codec->bias_level == SND_SOC_BIAS_OFF) { + if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) { if (gpio_is_valid(pdata->gpio_power)) { gpio_set_value(pdata->gpio_power, 1); mdelay(1); @@ -636,7 +637,7 @@ static int uda1380_set_bias_level(struct snd_soc_codec *codec, for (reg = UDA1380_MVOL; reg < UDA1380_CACHEREGNUM; reg++) set_bit(reg - 0x10, &uda1380_cache_dirty); } - codec->bias_level = level; + codec->dapm.bias_level = level; return 0; } diff --git a/sound/soc/codecs/wm2000.c b/sound/soc/codecs/wm2000.c index 4bcd168794e1..9277d8d7474e 100644 --- a/sound/soc/codecs/wm2000.c +++ b/sound/soc/codecs/wm2000.c @@ -705,6 +705,7 @@ static const struct snd_soc_dapm_route audio_map[] = { /* Called from the machine driver */ int wm2000_add_controls(struct snd_soc_codec *codec) { + struct snd_soc_dapm_context *dapm = &codec->dapm; int ret; if (!wm2000_i2c) { @@ -712,12 +713,12 @@ int wm2000_add_controls(struct snd_soc_codec *codec) return -ENODEV; } - ret = snd_soc_dapm_new_controls(codec, wm2000_dapm_widgets, + ret = snd_soc_dapm_new_controls(dapm, wm2000_dapm_widgets, ARRAY_SIZE(wm2000_dapm_widgets)); if (ret < 0) return ret; - ret = snd_soc_dapm_add_routes(codec, audio_map, ARRAY_SIZE(audio_map)); + ret = snd_soc_dapm_add_routes(dapm, audio_map, ARRAY_SIZE(audio_map)); if (ret < 0) return ret; diff --git a/sound/soc/codecs/wm8350.c b/sound/soc/codecs/wm8350.c index f4f1fba38eb9..4c6c81e11544 100644 --- a/sound/soc/codecs/wm8350.c +++ b/sound/soc/codecs/wm8350.c @@ -230,8 +230,9 @@ static inline int wm8350_out2_ramp_step(struct snd_soc_codec *codec) */ static void wm8350_pga_work(struct work_struct *work) { - struct snd_soc_codec *codec = - container_of(work, struct snd_soc_codec, delayed_work.work); + struct snd_soc_dapm_context *dapm = + container_of(work, struct snd_soc_dapm_context, delayed_work.work); + struct snd_soc_codec *codec = dapm->codec; struct wm8350_data *wm8350_data = snd_soc_codec_get_drvdata(codec); struct wm8350_output *out1 = &wm8350_data->out1, *out2 = &wm8350_data->out2; @@ -302,8 +303,8 @@ static int pga_event(struct snd_soc_dapm_widget *w, out->ramp = WM8350_RAMP_UP; out->active = 1; - if (!delayed_work_pending(&codec->delayed_work)) - schedule_delayed_work(&codec->delayed_work, + if (!delayed_work_pending(&codec->dapm.delayed_work)) + schedule_delayed_work(&codec->dapm.delayed_work, msecs_to_jiffies(1)); break; @@ -311,8 +312,8 @@ static int pga_event(struct snd_soc_dapm_widget *w, out->ramp = WM8350_RAMP_DOWN; out->active = 0; - if (!delayed_work_pending(&codec->delayed_work)) - schedule_delayed_work(&codec->delayed_work, + if (!delayed_work_pending(&codec->dapm.delayed_work)) + schedule_delayed_work(&codec->dapm.delayed_work, msecs_to_jiffies(1)); break; } @@ -786,9 +787,10 @@ static const struct snd_soc_dapm_route audio_map[] = { static int wm8350_add_widgets(struct snd_soc_codec *codec) { + struct snd_soc_dapm_context *dapm = &codec->dapm; int ret; - ret = snd_soc_dapm_new_controls(codec, + ret = snd_soc_dapm_new_controls(dapm, wm8350_dapm_widgets, ARRAY_SIZE(wm8350_dapm_widgets)); if (ret != 0) { @@ -797,7 +799,7 @@ static int wm8350_add_widgets(struct snd_soc_codec *codec) } /* set up audio paths */ - ret = snd_soc_dapm_add_routes(codec, audio_map, ARRAY_SIZE(audio_map)); + ret = snd_soc_dapm_add_routes(dapm, audio_map, ARRAY_SIZE(audio_map)); if (ret != 0) { dev_err(codec->dev, "DAPM route register failed\n"); return ret; @@ -1184,7 +1186,7 @@ static int wm8350_set_bias_level(struct snd_soc_codec *codec, break; case SND_SOC_BIAS_STANDBY: - if (codec->bias_level == SND_SOC_BIAS_OFF) { + if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) { ret = regulator_bulk_enable(ARRAY_SIZE(priv->supplies), priv->supplies); if (ret != 0) @@ -1317,7 +1319,7 @@ static int wm8350_set_bias_level(struct snd_soc_codec *codec, priv->supplies); break; } - codec->bias_level = level; + codec->dapm.bias_level = level; return 0; } @@ -1550,7 +1552,7 @@ static int wm8350_codec_probe(struct snd_soc_codec *codec) /* Put the codec into reset if it wasn't already */ wm8350_clear_bits(wm8350, WM8350_POWER_MGMT_5, WM8350_CODEC_ENA); - INIT_DELAYED_WORK(&codec->delayed_work, wm8350_pga_work); + INIT_DELAYED_WORK(&codec->dapm.delayed_work, wm8350_pga_work); /* Enable the codec */ wm8350_set_bits(wm8350, WM8350_POWER_MGMT_5, WM8350_CODEC_ENA); @@ -1635,12 +1637,12 @@ static int wm8350_codec_remove(struct snd_soc_codec *codec) priv->mic.jack = NULL; /* cancel any work waiting to be queued. */ - ret = cancel_delayed_work(&codec->delayed_work); + ret = cancel_delayed_work(&codec->dapm.delayed_work); /* if there was any work waiting then we run it now and * wait for its completion */ if (ret) { - schedule_delayed_work(&codec->delayed_work, 0); + schedule_delayed_work(&codec->dapm.delayed_work, 0); flush_scheduled_work(); } diff --git a/sound/soc/codecs/wm8400.c b/sound/soc/codecs/wm8400.c index 850299786e02..96927a457a34 100644 --- a/sound/soc/codecs/wm8400.c +++ b/sound/soc/codecs/wm8400.c @@ -911,10 +911,11 @@ static const struct snd_soc_dapm_route audio_map[] = { static int wm8400_add_widgets(struct snd_soc_codec *codec) { - snd_soc_dapm_new_controls(codec, wm8400_dapm_widgets, - ARRAY_SIZE(wm8400_dapm_widgets)); + struct snd_soc_dapm_context *dapm = &codec->dapm; - snd_soc_dapm_add_routes(codec, audio_map, ARRAY_SIZE(audio_map)); + snd_soc_dapm_new_controls(dapm, wm8400_dapm_widgets, + ARRAY_SIZE(wm8400_dapm_widgets)); + snd_soc_dapm_add_routes(dapm, audio_map, ARRAY_SIZE(audio_map)); return 0; } @@ -1219,7 +1220,7 @@ static int wm8400_set_bias_level(struct snd_soc_codec *codec, break; case SND_SOC_BIAS_STANDBY: - if (codec->bias_level == SND_SOC_BIAS_OFF) { + if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) { ret = regulator_bulk_enable(ARRAY_SIZE(power), &power[0]); if (ret != 0) { @@ -1306,7 +1307,7 @@ static int wm8400_set_bias_level(struct snd_soc_codec *codec, break; } - codec->bias_level = level; + codec->dapm.bias_level = level; return 0; } diff --git a/sound/soc/codecs/wm8510.c b/sound/soc/codecs/wm8510.c index 8f107095760e..6b3833c7bdf3 100644 --- a/sound/soc/codecs/wm8510.c +++ b/sound/soc/codecs/wm8510.c @@ -216,10 +216,11 @@ static const struct snd_soc_dapm_route audio_map[] = { static int wm8510_add_widgets(struct snd_soc_codec *codec) { - snd_soc_dapm_new_controls(codec, wm8510_dapm_widgets, - ARRAY_SIZE(wm8510_dapm_widgets)); + struct snd_soc_dapm_context *dapm = &codec->dapm; - snd_soc_dapm_add_routes(codec, audio_map, ARRAY_SIZE(audio_map)); + snd_soc_dapm_new_controls(dapm, wm8510_dapm_widgets, + ARRAY_SIZE(wm8510_dapm_widgets)); + snd_soc_dapm_add_routes(dapm, audio_map, ARRAY_SIZE(audio_map)); return 0; } @@ -478,7 +479,7 @@ static int wm8510_set_bias_level(struct snd_soc_codec *codec, case SND_SOC_BIAS_STANDBY: power1 |= WM8510_POWER1_BIASEN | WM8510_POWER1_BUFIOEN; - if (codec->bias_level == SND_SOC_BIAS_OFF) { + if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) { /* Initial cap charge at VMID 5k */ snd_soc_write(codec, WM8510_POWER1, power1 | 0x3); mdelay(100); @@ -495,7 +496,7 @@ static int wm8510_set_bias_level(struct snd_soc_codec *codec, break; } - codec->bias_level = level; + codec->dapm.bias_level = level; return 0; } diff --git a/sound/soc/codecs/wm8523.c b/sound/soc/codecs/wm8523.c index 712ef7c76f90..d3318886f43e 100644 --- a/sound/soc/codecs/wm8523.c +++ b/sound/soc/codecs/wm8523.c @@ -110,10 +110,11 @@ static const struct snd_soc_dapm_route intercon[] = { static int wm8523_add_widgets(struct snd_soc_codec *codec) { - snd_soc_dapm_new_controls(codec, wm8523_dapm_widgets, - ARRAY_SIZE(wm8523_dapm_widgets)); + struct snd_soc_dapm_context *dapm = &codec->dapm; - snd_soc_dapm_add_routes(codec, intercon, ARRAY_SIZE(intercon)); + snd_soc_dapm_new_controls(dapm, wm8523_dapm_widgets, + ARRAY_SIZE(wm8523_dapm_widgets)); + snd_soc_dapm_add_routes(dapm, intercon, ARRAY_SIZE(intercon)); return 0; } @@ -328,7 +329,7 @@ static int wm8523_set_bias_level(struct snd_soc_codec *codec, break; case SND_SOC_BIAS_STANDBY: - if (codec->bias_level == SND_SOC_BIAS_OFF) { + if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) { ret = regulator_bulk_enable(ARRAY_SIZE(wm8523->supplies), wm8523->supplies); if (ret != 0) { @@ -367,7 +368,7 @@ static int wm8523_set_bias_level(struct snd_soc_codec *codec, wm8523->supplies); break; } - codec->bias_level = level; + codec->dapm.bias_level = level; return 0; } diff --git a/sound/soc/codecs/wm8580.c b/sound/soc/codecs/wm8580.c index a2e0ed59b376..dfd1dbd71f1d 100644 --- a/sound/soc/codecs/wm8580.c +++ b/sound/soc/codecs/wm8580.c @@ -302,10 +302,11 @@ static const struct snd_soc_dapm_route audio_map[] = { static int wm8580_add_widgets(struct snd_soc_codec *codec) { - snd_soc_dapm_new_controls(codec, wm8580_dapm_widgets, - ARRAY_SIZE(wm8580_dapm_widgets)); + struct snd_soc_dapm_context *dapm = &codec->dapm; - snd_soc_dapm_add_routes(codec, audio_map, ARRAY_SIZE(audio_map)); + snd_soc_dapm_new_controls(dapm, wm8580_dapm_widgets, + ARRAY_SIZE(wm8580_dapm_widgets)); + snd_soc_dapm_add_routes(dapm, audio_map, ARRAY_SIZE(audio_map)); return 0; } @@ -767,7 +768,7 @@ static int wm8580_set_bias_level(struct snd_soc_codec *codec, break; case SND_SOC_BIAS_STANDBY: - if (codec->bias_level == SND_SOC_BIAS_OFF) { + if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) { /* Power up and get individual control of the DACs */ reg = snd_soc_read(codec, WM8580_PWRDN1); reg &= ~(WM8580_PWRDN1_PWDN | WM8580_PWRDN1_ALLDACPD); @@ -785,7 +786,7 @@ static int wm8580_set_bias_level(struct snd_soc_codec *codec, snd_soc_write(codec, WM8580_PWRDN1, reg | WM8580_PWRDN1_PWDN); break; } - codec->bias_level = level; + codec->dapm.bias_level = level; return 0; } diff --git a/sound/soc/codecs/wm8711.c b/sound/soc/codecs/wm8711.c index 54fbd76c8bca..ea2daf4da57c 100644 --- a/sound/soc/codecs/wm8711.c +++ b/sound/soc/codecs/wm8711.c @@ -93,10 +93,11 @@ static const struct snd_soc_dapm_route intercon[] = { static int wm8711_add_widgets(struct snd_soc_codec *codec) { - snd_soc_dapm_new_controls(codec, wm8711_dapm_widgets, - ARRAY_SIZE(wm8711_dapm_widgets)); + struct snd_soc_dapm_context *dapm = &codec->dapm; - snd_soc_dapm_add_routes(codec, intercon, ARRAY_SIZE(intercon)); + snd_soc_dapm_new_controls(dapm, wm8711_dapm_widgets, + ARRAY_SIZE(wm8711_dapm_widgets)); + snd_soc_dapm_add_routes(dapm, intercon, ARRAY_SIZE(intercon)); return 0; } @@ -318,7 +319,7 @@ static int wm8711_set_bias_level(struct snd_soc_codec *codec, snd_soc_write(codec, WM8711_PWR, 0xffff); break; } - codec->bias_level = level; + codec->dapm.bias_level = level; return 0; } diff --git a/sound/soc/codecs/wm8728.c b/sound/soc/codecs/wm8728.c index 075f35e4f4cb..23939976c3cc 100644 --- a/sound/soc/codecs/wm8728.c +++ b/sound/soc/codecs/wm8728.c @@ -73,10 +73,11 @@ static const struct snd_soc_dapm_route intercon[] = { static int wm8728_add_widgets(struct snd_soc_codec *codec) { - snd_soc_dapm_new_controls(codec, wm8728_dapm_widgets, - ARRAY_SIZE(wm8728_dapm_widgets)); + struct snd_soc_dapm_context *dapm = &codec->dapm; - snd_soc_dapm_add_routes(codec, intercon, ARRAY_SIZE(intercon)); + snd_soc_dapm_new_controls(dapm, wm8728_dapm_widgets, + ARRAY_SIZE(wm8728_dapm_widgets)); + snd_soc_dapm_add_routes(dapm, intercon, ARRAY_SIZE(intercon)); return 0; } @@ -180,7 +181,7 @@ static int wm8728_set_bias_level(struct snd_soc_codec *codec, case SND_SOC_BIAS_ON: case SND_SOC_BIAS_PREPARE: case SND_SOC_BIAS_STANDBY: - if (codec->bias_level == SND_SOC_BIAS_OFF) { + if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) { /* Power everything up... */ reg = snd_soc_read(codec, WM8728_DACCTL); snd_soc_write(codec, WM8728_DACCTL, reg & ~0x4); @@ -197,7 +198,7 @@ static int wm8728_set_bias_level(struct snd_soc_codec *codec, snd_soc_write(codec, WM8728_DACCTL, reg | 0x4); break; } - codec->bias_level = level; + codec->dapm.bias_level = level; return 0; } diff --git a/sound/soc/codecs/wm8731.c b/sound/soc/codecs/wm8731.c index 631385802eb4..95ade3245056 100644 --- a/sound/soc/codecs/wm8731.c +++ b/sound/soc/codecs/wm8731.c @@ -165,10 +165,11 @@ static const struct snd_soc_dapm_route intercon[] = { static int wm8731_add_widgets(struct snd_soc_codec *codec) { - snd_soc_dapm_new_controls(codec, wm8731_dapm_widgets, - ARRAY_SIZE(wm8731_dapm_widgets)); + struct snd_soc_dapm_context *dapm = &codec->dapm; - snd_soc_dapm_add_routes(codec, intercon, ARRAY_SIZE(intercon)); + snd_soc_dapm_new_controls(dapm, wm8731_dapm_widgets, + ARRAY_SIZE(wm8731_dapm_widgets)); + snd_soc_dapm_add_routes(dapm, intercon, ARRAY_SIZE(intercon)); return 0; } @@ -319,7 +320,7 @@ static int wm8731_set_dai_sysclk(struct snd_soc_dai *codec_dai, return -EINVAL; } - snd_soc_dapm_sync(codec); + snd_soc_dapm_sync(&codec->dapm); return 0; } @@ -399,7 +400,7 @@ static int wm8731_set_bias_level(struct snd_soc_codec *codec, case SND_SOC_BIAS_PREPARE: break; case SND_SOC_BIAS_STANDBY: - if (codec->bias_level == SND_SOC_BIAS_OFF) { + if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) { ret = regulator_bulk_enable(ARRAY_SIZE(wm8731->supplies), wm8731->supplies); if (ret != 0) @@ -428,7 +429,7 @@ static int wm8731_set_bias_level(struct snd_soc_codec *codec, wm8731->supplies); break; } - codec->bias_level = level; + codec->dapm.bias_level = level; return 0; } diff --git a/sound/soc/codecs/wm8741.c b/sound/soc/codecs/wm8741.c index 90e31e9aa6f7..43c49dfc9928 100644 --- a/sound/soc/codecs/wm8741.c +++ b/sound/soc/codecs/wm8741.c @@ -95,10 +95,11 @@ static const struct snd_soc_dapm_route intercon[] = { static int wm8741_add_widgets(struct snd_soc_codec *codec) { - snd_soc_dapm_new_controls(codec, wm8741_dapm_widgets, - ARRAY_SIZE(wm8741_dapm_widgets)); + struct snd_soc_dapm_context *dapm = &codec->dapm; - snd_soc_dapm_add_routes(codec, intercon, ARRAY_SIZE(intercon)); + snd_soc_dapm_new_controls(dapm, wm8741_dapm_widgets, + ARRAY_SIZE(wm8741_dapm_widgets)); + snd_soc_dapm_add_routes(dapm, intercon, ARRAY_SIZE(intercon)); return 0; } diff --git a/sound/soc/codecs/wm8750.c b/sound/soc/codecs/wm8750.c index 6c924cd2cfd4..178b967af73f 100644 --- a/sound/soc/codecs/wm8750.c +++ b/sound/soc/codecs/wm8750.c @@ -399,10 +399,11 @@ static const struct snd_soc_dapm_route audio_map[] = { static int wm8750_add_widgets(struct snd_soc_codec *codec) { - snd_soc_dapm_new_controls(codec, wm8750_dapm_widgets, - ARRAY_SIZE(wm8750_dapm_widgets)); + struct snd_soc_dapm_context *dapm = &codec->dapm; - snd_soc_dapm_add_routes(codec, audio_map, ARRAY_SIZE(audio_map)); + snd_soc_dapm_new_controls(dapm, wm8750_dapm_widgets, + ARRAY_SIZE(wm8750_dapm_widgets)); + snd_soc_dapm_add_routes(dapm, audio_map, ARRAY_SIZE(audio_map)); return 0; } @@ -615,7 +616,7 @@ static int wm8750_set_bias_level(struct snd_soc_codec *codec, case SND_SOC_BIAS_PREPARE: break; case SND_SOC_BIAS_STANDBY: - if (codec->bias_level == SND_SOC_BIAS_OFF) { + if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) { /* Set VMID to 5k */ snd_soc_write(codec, WM8750_PWR1, pwr_reg | 0x01c1); @@ -630,7 +631,7 @@ static int wm8750_set_bias_level(struct snd_soc_codec *codec, snd_soc_write(codec, WM8750_PWR1, 0x0001); break; } - codec->bias_level = level; + codec->dapm.bias_level = level; return 0; } diff --git a/sound/soc/codecs/wm8753.c b/sound/soc/codecs/wm8753.c index 8f679a13f2bc..26096b47a493 100644 --- a/sound/soc/codecs/wm8753.c +++ b/sound/soc/codecs/wm8753.c @@ -670,10 +670,11 @@ static const struct snd_soc_dapm_route audio_map[] = { static int wm8753_add_widgets(struct snd_soc_codec *codec) { - snd_soc_dapm_new_controls(codec, wm8753_dapm_widgets, - ARRAY_SIZE(wm8753_dapm_widgets)); + struct snd_soc_dapm_context *dapm = &codec->dapm; - snd_soc_dapm_add_routes(codec, audio_map, ARRAY_SIZE(audio_map)); + snd_soc_dapm_new_controls(dapm, wm8753_dapm_widgets, + ARRAY_SIZE(wm8753_dapm_widgets)); + snd_soc_dapm_add_routes(dapm, audio_map, ARRAY_SIZE(audio_map)); return 0; } @@ -1292,7 +1293,7 @@ static int wm8753_set_bias_level(struct snd_soc_codec *codec, wm8753_write(codec, WM8753_PWR1, 0x0001); break; } - codec->bias_level = level; + codec->dapm.bias_level = level; return 0; } @@ -1482,9 +1483,11 @@ static void wm8753_set_dai_mode(struct snd_soc_codec *codec, static void wm8753_work(struct work_struct *work) { - struct snd_soc_codec *codec = - container_of(work, struct snd_soc_codec, delayed_work.work); - wm8753_set_bias_level(codec, codec->bias_level); + struct snd_soc_dapm_context *dapm = + container_of(work, struct snd_soc_dapm_context, + delayed_work.work); + struct snd_soc_codec *codec = dapm->codec; + wm8753_set_bias_level(codec, dapm->bias_level); } static int wm8753_suspend(struct snd_soc_codec *codec, pm_message_t state) @@ -1516,10 +1519,10 @@ static int wm8753_resume(struct snd_soc_codec *codec) wm8753_set_bias_level(codec, SND_SOC_BIAS_STANDBY); /* charge wm8753 caps */ - if (codec->suspend_bias_level == SND_SOC_BIAS_ON) { + if (codec->dapm.suspend_bias_level == SND_SOC_BIAS_ON) { wm8753_set_bias_level(codec, SND_SOC_BIAS_PREPARE); - codec->bias_level = SND_SOC_BIAS_ON; - schedule_delayed_work(&codec->delayed_work, + codec->dapm.bias_level = SND_SOC_BIAS_ON; + schedule_delayed_work(&codec->dapm.delayed_work, msecs_to_jiffies(caps_charge)); } @@ -1550,7 +1553,7 @@ static int wm8753_probe(struct snd_soc_codec *codec) struct wm8753_priv *wm8753 = snd_soc_codec_get_drvdata(codec); int ret = 0, reg; - INIT_DELAYED_WORK(&codec->delayed_work, wm8753_work); + INIT_DELAYED_WORK(&codec->dapm.delayed_work, wm8753_work); ret = snd_soc_codec_set_cache_io(codec, 7, 9, wm8753->control_type); if (ret < 0) { @@ -1569,7 +1572,7 @@ static int wm8753_probe(struct snd_soc_codec *codec) /* charge output caps */ wm8753_set_bias_level(codec, SND_SOC_BIAS_PREPARE); - schedule_delayed_work(&codec->delayed_work, + schedule_delayed_work(&codec->dapm.delayed_work, msecs_to_jiffies(caps_charge)); /* set the update bits */ @@ -1604,7 +1607,7 @@ static int wm8753_probe(struct snd_soc_codec *codec) /* power down chip */ static int wm8753_remove(struct snd_soc_codec *codec) { - run_delayed_work(&codec->delayed_work); + run_delayed_work(&codec->dapm.delayed_work); wm8753_set_bias_level(codec, SND_SOC_BIAS_OFF); return 0; diff --git a/sound/soc/codecs/wm8776.c b/sound/soc/codecs/wm8776.c index 04182c464e35..96474a40da8d 100644 --- a/sound/soc/codecs/wm8776.c +++ b/sound/soc/codecs/wm8776.c @@ -307,7 +307,7 @@ static int wm8776_set_bias_level(struct snd_soc_codec *codec, case SND_SOC_BIAS_PREPARE: break; case SND_SOC_BIAS_STANDBY: - if (codec->bias_level == SND_SOC_BIAS_OFF) { + if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) { /* Disable the global powerdown; DAPM does the rest */ snd_soc_update_bits(codec, WM8776_PWRDOWN, 1, 0); } @@ -318,7 +318,7 @@ static int wm8776_set_bias_level(struct snd_soc_codec *codec, break; } - codec->bias_level = level; + codec->dapm.bias_level = level; return 0; } @@ -405,6 +405,7 @@ static int wm8776_resume(struct snd_soc_codec *codec) static int wm8776_probe(struct snd_soc_codec *codec) { struct wm8776_priv *wm8776 = snd_soc_codec_get_drvdata(codec); + struct snd_soc_dapm_context *dapm = &codec->dapm; int ret = 0; ret = snd_soc_codec_set_cache_io(codec, 7, 9, wm8776->control_type); @@ -428,9 +429,9 @@ static int wm8776_probe(struct snd_soc_codec *codec) snd_soc_add_controls(codec, wm8776_snd_controls, ARRAY_SIZE(wm8776_snd_controls)); - snd_soc_dapm_new_controls(codec, wm8776_dapm_widgets, + snd_soc_dapm_new_controls(dapm, wm8776_dapm_widgets, ARRAY_SIZE(wm8776_dapm_widgets)); - snd_soc_dapm_add_routes(codec, routes, ARRAY_SIZE(routes)); + snd_soc_dapm_add_routes(dapm, routes, ARRAY_SIZE(routes)); return ret; } diff --git a/sound/soc/codecs/wm8804.c b/sound/soc/codecs/wm8804.c index 4599e8e95aa2..031a0d421108 100644 --- a/sound/soc/codecs/wm8804.c +++ b/sound/soc/codecs/wm8804.c @@ -515,7 +515,7 @@ static int wm8804_set_bias_level(struct snd_soc_codec *codec, snd_soc_update_bits(codec, WM8804_PWRDN, 0x9, 0); break; case SND_SOC_BIAS_STANDBY: - if (codec->bias_level == SND_SOC_BIAS_OFF) { + if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) { ret = regulator_bulk_enable(ARRAY_SIZE(wm8804->supplies), wm8804->supplies); if (ret) { @@ -537,7 +537,7 @@ static int wm8804_set_bias_level(struct snd_soc_codec *codec, break; } - codec->bias_level = level; + codec->dapm.bias_level = level; return 0; } @@ -581,7 +581,7 @@ static int wm8804_probe(struct snd_soc_codec *codec) wm8804 = snd_soc_codec_get_drvdata(codec); wm8804->codec = codec; - codec->idle_bias_off = 1; + codec->dapm.idle_bias_off = 1; ret = snd_soc_codec_set_cache_io(codec, 8, 8, wm8804->control_type); if (ret < 0) { diff --git a/sound/soc/codecs/wm8900.c b/sound/soc/codecs/wm8900.c index aca4b1ea10bb..06ea9c0f863b 100644 --- a/sound/soc/codecs/wm8900.c +++ b/sound/soc/codecs/wm8900.c @@ -611,10 +611,11 @@ static const struct snd_soc_dapm_route audio_map[] = { static int wm8900_add_widgets(struct snd_soc_codec *codec) { - snd_soc_dapm_new_controls(codec, wm8900_dapm_widgets, - ARRAY_SIZE(wm8900_dapm_widgets)); + struct snd_soc_dapm_context *dapm = &codec->dapm; - snd_soc_dapm_add_routes(codec, audio_map, ARRAY_SIZE(audio_map)); + snd_soc_dapm_new_controls(dapm, wm8900_dapm_widgets, + ARRAY_SIZE(wm8900_dapm_widgets)); + snd_soc_dapm_add_routes(dapm, audio_map, ARRAY_SIZE(audio_map)); return 0; } @@ -1051,7 +1052,7 @@ static int wm8900_set_bias_level(struct snd_soc_codec *codec, case SND_SOC_BIAS_STANDBY: /* Charge capacitors if initial power up */ - if (codec->bias_level == SND_SOC_BIAS_OFF) { + if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) { /* STARTUP_BIAS_ENA on */ snd_soc_write(codec, WM8900_REG_POWER1, WM8900_REG_POWER1_STARTUP_BIAS_ENA); @@ -1119,7 +1120,7 @@ static int wm8900_set_bias_level(struct snd_soc_codec *codec, WM8900_REG_POWER2_SYSCLK_ENA); break; } - codec->bias_level = level; + codec->dapm.bias_level = level; return 0; } diff --git a/sound/soc/codecs/wm8903.c b/sound/soc/codecs/wm8903.c index 622b60238a82..4a6df4b69a04 100644 --- a/sound/soc/codecs/wm8903.c +++ b/sound/soc/codecs/wm8903.c @@ -923,10 +923,11 @@ static const struct snd_soc_dapm_route intercon[] = { static int wm8903_add_widgets(struct snd_soc_codec *codec) { - snd_soc_dapm_new_controls(codec, wm8903_dapm_widgets, - ARRAY_SIZE(wm8903_dapm_widgets)); + struct snd_soc_dapm_context *dapm = &codec->dapm; - snd_soc_dapm_add_routes(codec, intercon, ARRAY_SIZE(intercon)); + snd_soc_dapm_new_controls(dapm, wm8903_dapm_widgets, + ARRAY_SIZE(wm8903_dapm_widgets)); + snd_soc_dapm_add_routes(dapm, intercon, ARRAY_SIZE(intercon)); return 0; } @@ -946,7 +947,7 @@ static int wm8903_set_bias_level(struct snd_soc_codec *codec, break; case SND_SOC_BIAS_STANDBY: - if (codec->bias_level == SND_SOC_BIAS_OFF) { + if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) { snd_soc_write(codec, WM8903_CLOCK_RATES_2, WM8903_CLK_SYS_ENA); @@ -991,7 +992,7 @@ static int wm8903_set_bias_level(struct snd_soc_codec *codec, break; } - codec->bias_level = level; + codec->dapm.bias_level = level; return 0; } diff --git a/sound/soc/codecs/wm8904.c b/sound/soc/codecs/wm8904.c index 33be84e506ea..be90399c1cb4 100644 --- a/sound/soc/codecs/wm8904.c +++ b/sound/soc/codecs/wm8904.c @@ -1428,10 +1428,11 @@ static const struct snd_soc_dapm_route wm8912_intercon[] = { static int wm8904_add_widgets(struct snd_soc_codec *codec) { struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec); + struct snd_soc_dapm_context *dapm = &codec->dapm; - snd_soc_dapm_new_controls(codec, wm8904_core_dapm_widgets, + snd_soc_dapm_new_controls(dapm, wm8904_core_dapm_widgets, ARRAY_SIZE(wm8904_core_dapm_widgets)); - snd_soc_dapm_add_routes(codec, core_intercon, + snd_soc_dapm_add_routes(dapm, core_intercon, ARRAY_SIZE(core_intercon)); switch (wm8904->devtype) { @@ -1443,20 +1444,20 @@ static int wm8904_add_widgets(struct snd_soc_codec *codec) snd_soc_add_controls(codec, wm8904_snd_controls, ARRAY_SIZE(wm8904_snd_controls)); - snd_soc_dapm_new_controls(codec, wm8904_adc_dapm_widgets, + snd_soc_dapm_new_controls(dapm, wm8904_adc_dapm_widgets, ARRAY_SIZE(wm8904_adc_dapm_widgets)); - snd_soc_dapm_new_controls(codec, wm8904_dac_dapm_widgets, + snd_soc_dapm_new_controls(dapm, wm8904_dac_dapm_widgets, ARRAY_SIZE(wm8904_dac_dapm_widgets)); - snd_soc_dapm_new_controls(codec, wm8904_dapm_widgets, + snd_soc_dapm_new_controls(dapm, wm8904_dapm_widgets, ARRAY_SIZE(wm8904_dapm_widgets)); - snd_soc_dapm_add_routes(codec, core_intercon, + snd_soc_dapm_add_routes(dapm, core_intercon, ARRAY_SIZE(core_intercon)); - snd_soc_dapm_add_routes(codec, adc_intercon, + snd_soc_dapm_add_routes(dapm, adc_intercon, ARRAY_SIZE(adc_intercon)); - snd_soc_dapm_add_routes(codec, dac_intercon, + snd_soc_dapm_add_routes(dapm, dac_intercon, ARRAY_SIZE(dac_intercon)); - snd_soc_dapm_add_routes(codec, wm8904_intercon, + snd_soc_dapm_add_routes(dapm, wm8904_intercon, ARRAY_SIZE(wm8904_intercon)); break; @@ -1464,17 +1465,17 @@ static int wm8904_add_widgets(struct snd_soc_codec *codec) snd_soc_add_controls(codec, wm8904_dac_snd_controls, ARRAY_SIZE(wm8904_dac_snd_controls)); - snd_soc_dapm_new_controls(codec, wm8904_dac_dapm_widgets, + snd_soc_dapm_new_controls(dapm, wm8904_dac_dapm_widgets, ARRAY_SIZE(wm8904_dac_dapm_widgets)); - snd_soc_dapm_add_routes(codec, dac_intercon, + snd_soc_dapm_add_routes(dapm, dac_intercon, ARRAY_SIZE(dac_intercon)); - snd_soc_dapm_add_routes(codec, wm8912_intercon, + snd_soc_dapm_add_routes(dapm, wm8912_intercon, ARRAY_SIZE(wm8912_intercon)); break; } - snd_soc_dapm_new_widgets(codec); + snd_soc_dapm_new_widgets(dapm); return 0; } @@ -2139,7 +2140,7 @@ static int wm8904_set_bias_level(struct snd_soc_codec *codec, break; case SND_SOC_BIAS_STANDBY: - if (codec->bias_level == SND_SOC_BIAS_OFF) { + if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) { ret = regulator_bulk_enable(ARRAY_SIZE(wm8904->supplies), wm8904->supplies); if (ret != 0) { @@ -2198,7 +2199,7 @@ static int wm8904_set_bias_level(struct snd_soc_codec *codec, wm8904->supplies); break; } - codec->bias_level = level; + codec->dapm.bias_level = level; return 0; } @@ -2373,7 +2374,7 @@ static int wm8904_probe(struct snd_soc_codec *codec) int ret, i; codec->cache_sync = 1; - codec->idle_bias_off = 1; + codec->dapm.idle_bias_off = 1; switch (wm8904->devtype) { case WM8904: diff --git a/sound/soc/codecs/wm8940.c b/sound/soc/codecs/wm8940.c index 2cb16f895c46..c2def1b01ae0 100644 --- a/sound/soc/codecs/wm8940.c +++ b/sound/soc/codecs/wm8940.c @@ -291,13 +291,14 @@ static const struct snd_soc_dapm_route audio_map[] = { static int wm8940_add_widgets(struct snd_soc_codec *codec) { + struct snd_soc_dapm_context *dapm = &codec->dapm; int ret; - ret = snd_soc_dapm_new_controls(codec, wm8940_dapm_widgets, + ret = snd_soc_dapm_new_controls(dapm, wm8940_dapm_widgets, ARRAY_SIZE(wm8940_dapm_widgets)); if (ret) goto error_ret; - ret = snd_soc_dapm_add_routes(codec, audio_map, ARRAY_SIZE(audio_map)); + ret = snd_soc_dapm_add_routes(dapm, audio_map, ARRAY_SIZE(audio_map)); if (ret) goto error_ret; diff --git a/sound/soc/codecs/wm8955.c b/sound/soc/codecs/wm8955.c index f89ad6c9a80b..df1940fdbf69 100644 --- a/sound/soc/codecs/wm8955.c +++ b/sound/soc/codecs/wm8955.c @@ -577,13 +577,14 @@ static const struct snd_soc_dapm_route wm8955_intercon[] = { static int wm8955_add_widgets(struct snd_soc_codec *codec) { + struct snd_soc_dapm_context *dapm = &codec->dapm; + snd_soc_add_controls(codec, wm8955_snd_controls, ARRAY_SIZE(wm8955_snd_controls)); - snd_soc_dapm_new_controls(codec, wm8955_dapm_widgets, + snd_soc_dapm_new_controls(dapm, wm8955_dapm_widgets, ARRAY_SIZE(wm8955_dapm_widgets)); - - snd_soc_dapm_add_routes(codec, wm8955_intercon, + snd_soc_dapm_add_routes(dapm, wm8955_intercon, ARRAY_SIZE(wm8955_intercon)); return 0; @@ -786,7 +787,7 @@ static int wm8955_set_bias_level(struct snd_soc_codec *codec, break; case SND_SOC_BIAS_STANDBY: - if (codec->bias_level == SND_SOC_BIAS_OFF) { + if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) { ret = regulator_bulk_enable(ARRAY_SIZE(wm8955->supplies), wm8955->supplies); if (ret != 0) { @@ -850,7 +851,7 @@ static int wm8955_set_bias_level(struct snd_soc_codec *codec, wm8955->supplies); break; } - codec->bias_level = level; + codec->dapm.bias_level = level; return 0; } diff --git a/sound/soc/codecs/wm8960.c b/sound/soc/codecs/wm8960.c index 8d5efb333c33..0ea578815003 100644 --- a/sound/soc/codecs/wm8960.c +++ b/sound/soc/codecs/wm8960.c @@ -388,27 +388,28 @@ static int wm8960_add_widgets(struct snd_soc_codec *codec) { struct wm8960_data *pdata = codec->dev->platform_data; struct wm8960_priv *wm8960 = snd_soc_codec_get_drvdata(codec); + struct snd_soc_dapm_context *dapm = &codec->dapm; struct snd_soc_dapm_widget *w; - snd_soc_dapm_new_controls(codec, wm8960_dapm_widgets, + snd_soc_dapm_new_controls(dapm, wm8960_dapm_widgets, ARRAY_SIZE(wm8960_dapm_widgets)); - snd_soc_dapm_add_routes(codec, audio_paths, ARRAY_SIZE(audio_paths)); + snd_soc_dapm_add_routes(dapm, audio_paths, ARRAY_SIZE(audio_paths)); /* In capless mode OUT3 is used to provide VMID for the * headphone outputs, otherwise it is used as a mono mixer. */ if (pdata && pdata->capless) { - snd_soc_dapm_new_controls(codec, wm8960_dapm_widgets_capless, + snd_soc_dapm_new_controls(dapm, wm8960_dapm_widgets_capless, ARRAY_SIZE(wm8960_dapm_widgets_capless)); - snd_soc_dapm_add_routes(codec, audio_paths_capless, + snd_soc_dapm_add_routes(dapm, audio_paths_capless, ARRAY_SIZE(audio_paths_capless)); } else { - snd_soc_dapm_new_controls(codec, wm8960_dapm_widgets_out3, + snd_soc_dapm_new_controls(dapm, wm8960_dapm_widgets_out3, ARRAY_SIZE(wm8960_dapm_widgets_out3)); - snd_soc_dapm_add_routes(codec, audio_paths_out3, + snd_soc_dapm_add_routes(dapm, audio_paths_out3, ARRAY_SIZE(audio_paths_out3)); } @@ -417,7 +418,7 @@ static int wm8960_add_widgets(struct snd_soc_codec *codec) * list each time to find the desired power state do so now * and save the result. */ - list_for_each_entry(w, &codec->dapm_widgets, list) { + list_for_each_entry(w, &codec->dapm.widgets, list) { if (strcmp(w->name, "LOUT1 PGA") == 0) wm8960->lout1 = w; if (strcmp(w->name, "ROUT1 PGA") == 0) @@ -572,7 +573,7 @@ static int wm8960_set_bias_level_out3(struct snd_soc_codec *codec, break; case SND_SOC_BIAS_STANDBY: - if (codec->bias_level == SND_SOC_BIAS_OFF) { + if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) { /* Enable anti-pop features */ snd_soc_write(codec, WM8960_APOP1, WM8960_POBCTRL | WM8960_SOFT_ST | @@ -610,7 +611,7 @@ static int wm8960_set_bias_level_out3(struct snd_soc_codec *codec, break; } - codec->bias_level = level; + codec->dapm.bias_level = level; return 0; } @@ -626,7 +627,7 @@ static int wm8960_set_bias_level_capless(struct snd_soc_codec *codec, break; case SND_SOC_BIAS_PREPARE: - switch (codec->bias_level) { + switch (codec->dapm.bias_level) { case SND_SOC_BIAS_STANDBY: /* Enable anti pop mode */ snd_soc_update_bits(codec, WM8960_APOP1, @@ -681,7 +682,7 @@ static int wm8960_set_bias_level_capless(struct snd_soc_codec *codec, break; case SND_SOC_BIAS_STANDBY: - switch (codec->bias_level) { + switch (codec->dapm.bias_level) { case SND_SOC_BIAS_PREPARE: /* Disable HP discharge */ snd_soc_update_bits(codec, WM8960_APOP2, @@ -705,7 +706,7 @@ static int wm8960_set_bias_level_capless(struct snd_soc_codec *codec, break; } - codec->bias_level = level; + codec->dapm.bias_level = level; return 0; } diff --git a/sound/soc/codecs/wm8961.c b/sound/soc/codecs/wm8961.c index 4f326f604104..79b650945bb2 100644 --- a/sound/soc/codecs/wm8961.c +++ b/sound/soc/codecs/wm8961.c @@ -882,7 +882,7 @@ static int wm8961_set_bias_level(struct snd_soc_codec *codec, break; case SND_SOC_BIAS_PREPARE: - if (codec->bias_level == SND_SOC_BIAS_STANDBY) { + if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY) { /* Enable bias generation */ reg = snd_soc_read(codec, WM8961_ANTI_POP); reg |= WM8961_BUFIOEN | WM8961_BUFDCOPEN; @@ -897,7 +897,7 @@ static int wm8961_set_bias_level(struct snd_soc_codec *codec, break; case SND_SOC_BIAS_STANDBY: - if (codec->bias_level == SND_SOC_BIAS_PREPARE) { + if (codec->dapm.bias_level == SND_SOC_BIAS_PREPARE) { /* VREF off */ reg = snd_soc_read(codec, WM8961_PWR_MGMT_1); reg &= ~WM8961_VREF; @@ -919,7 +919,7 @@ static int wm8961_set_bias_level(struct snd_soc_codec *codec, break; } - codec->bias_level = level; + codec->dapm.bias_level = level; return 0; } @@ -959,6 +959,7 @@ static struct snd_soc_dai_driver wm8961_dai = { static int wm8961_probe(struct snd_soc_codec *codec) { + struct snd_soc_dapm_context *dapm = &codec->dapm; int ret = 0; u16 reg; @@ -1024,9 +1025,9 @@ static int wm8961_probe(struct snd_soc_codec *codec) snd_soc_add_controls(codec, wm8961_snd_controls, ARRAY_SIZE(wm8961_snd_controls)); - snd_soc_dapm_new_controls(codec, wm8961_dapm_widgets, + snd_soc_dapm_new_controls(dapm, wm8961_dapm_widgets, ARRAY_SIZE(wm8961_dapm_widgets)); - snd_soc_dapm_add_routes(codec, audio_paths, ARRAY_SIZE(audio_paths)); + snd_soc_dapm_add_routes(dapm, audio_paths, ARRAY_SIZE(audio_paths)); return 0; } diff --git a/sound/soc/codecs/wm8962.c b/sound/soc/codecs/wm8962.c index 3fc63b43c6a1..80986105f52e 100644 --- a/sound/soc/codecs/wm8962.c +++ b/sound/soc/codecs/wm8962.c @@ -2682,6 +2682,7 @@ static const struct snd_soc_dapm_route wm8962_spk_stereo_intercon[] = { static int wm8962_add_widgets(struct snd_soc_codec *codec) { struct wm8962_pdata *pdata = dev_get_platdata(codec->dev); + struct snd_soc_dapm_context *dapm = &codec->dapm; snd_soc_add_controls(codec, wm8962_snd_controls, ARRAY_SIZE(wm8962_snd_controls)); @@ -2693,26 +2694,26 @@ static int wm8962_add_widgets(struct snd_soc_codec *codec) ARRAY_SIZE(wm8962_spk_stereo_controls)); - snd_soc_dapm_new_controls(codec, wm8962_dapm_widgets, + snd_soc_dapm_new_controls(dapm, wm8962_dapm_widgets, ARRAY_SIZE(wm8962_dapm_widgets)); if (pdata && pdata->spk_mono) - snd_soc_dapm_new_controls(codec, wm8962_dapm_spk_mono_widgets, + snd_soc_dapm_new_controls(dapm, wm8962_dapm_spk_mono_widgets, ARRAY_SIZE(wm8962_dapm_spk_mono_widgets)); else - snd_soc_dapm_new_controls(codec, wm8962_dapm_spk_stereo_widgets, + snd_soc_dapm_new_controls(dapm, wm8962_dapm_spk_stereo_widgets, ARRAY_SIZE(wm8962_dapm_spk_stereo_widgets)); - snd_soc_dapm_add_routes(codec, wm8962_intercon, + snd_soc_dapm_add_routes(dapm, wm8962_intercon, ARRAY_SIZE(wm8962_intercon)); if (pdata && pdata->spk_mono) - snd_soc_dapm_add_routes(codec, wm8962_spk_mono_intercon, + snd_soc_dapm_add_routes(dapm, wm8962_spk_mono_intercon, ARRAY_SIZE(wm8962_spk_mono_intercon)); else - snd_soc_dapm_add_routes(codec, wm8962_spk_stereo_intercon, + snd_soc_dapm_add_routes(dapm, wm8962_spk_stereo_intercon, ARRAY_SIZE(wm8962_spk_stereo_intercon)); - snd_soc_dapm_disable_pin(codec, "Beep"); + snd_soc_dapm_disable_pin(dapm, "Beep"); return 0; } @@ -2819,7 +2820,7 @@ static int wm8962_set_bias_level(struct snd_soc_codec *codec, struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec); int ret; - if (level == codec->bias_level) + if (level == codec->dapm.bias_level) return 0; switch (level) { @@ -2833,7 +2834,7 @@ static int wm8962_set_bias_level(struct snd_soc_codec *codec, break; case SND_SOC_BIAS_STANDBY: - if (codec->bias_level == SND_SOC_BIAS_OFF) { + if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) { ret = regulator_bulk_enable(ARRAY_SIZE(wm8962->supplies), wm8962->supplies); if (ret != 0) { @@ -2883,7 +2884,7 @@ static int wm8962_set_bias_level(struct snd_soc_codec *codec, wm8962->supplies); break; } - codec->bias_level = level; + codec->dapm.bias_level = level; return 0; } @@ -3441,6 +3442,7 @@ static void wm8962_beep_work(struct work_struct *work) struct wm8962_priv *wm8962 = container_of(work, struct wm8962_priv, beep_work); struct snd_soc_codec *codec = wm8962->codec; + struct snd_soc_dapm_context *dapm = &codec->dapm; int i; int reg = 0; int best = 0; @@ -3457,16 +3459,16 @@ static void wm8962_beep_work(struct work_struct *work) reg = WM8962_BEEP_ENA | (best << WM8962_BEEP_RATE_SHIFT); - snd_soc_dapm_enable_pin(codec, "Beep"); + snd_soc_dapm_enable_pin(dapm, "Beep"); } else { dev_dbg(codec->dev, "Disabling beep\n"); - snd_soc_dapm_disable_pin(codec, "Beep"); + snd_soc_dapm_disable_pin(dapm, "Beep"); } snd_soc_update_bits(codec, WM8962_BEEP_GENERATOR_1, WM8962_BEEP_ENA | WM8962_BEEP_RATE_MASK, reg); - snd_soc_dapm_sync(codec); + snd_soc_dapm_sync(dapm); } /* For usability define a way of injecting beep events for the device - @@ -3713,7 +3715,7 @@ static int wm8962_probe(struct snd_soc_codec *codec) INIT_DELAYED_WORK(&wm8962->mic_work, wm8962_mic_work); codec->cache_sync = 1; - codec->idle_bias_off = 1; + codec->dapm.idle_bias_off = 1; ret = snd_soc_codec_set_cache_io(codec, 16, 16, SND_SOC_I2C); if (ret != 0) { diff --git a/sound/soc/codecs/wm8971.c b/sound/soc/codecs/wm8971.c index 63f6dbf5d070..84b2dcb18aea 100644 --- a/sound/soc/codecs/wm8971.c +++ b/sound/soc/codecs/wm8971.c @@ -333,10 +333,11 @@ static const struct snd_soc_dapm_route audio_map[] = { static int wm8971_add_widgets(struct snd_soc_codec *codec) { - snd_soc_dapm_new_controls(codec, wm8971_dapm_widgets, - ARRAY_SIZE(wm8971_dapm_widgets)); + struct snd_soc_dapm_context *dapm = &codec->dapm; - snd_soc_dapm_add_routes(codec, audio_map, ARRAY_SIZE(audio_map)); + snd_soc_dapm_new_controls(dapm, wm8971_dapm_widgets, + ARRAY_SIZE(wm8971_dapm_widgets)); + snd_soc_dapm_add_routes(dapm, audio_map, ARRAY_SIZE(audio_map)); return 0; } @@ -553,7 +554,7 @@ static int wm8971_set_bias_level(struct snd_soc_codec *codec, snd_soc_write(codec, WM8971_PWR1, 0x0001); break; } - codec->bias_level = level; + codec->dapm.bias_level = level; return 0; } @@ -590,9 +591,11 @@ static struct snd_soc_dai_driver wm8971_dai = { static void wm8971_work(struct work_struct *work) { - struct snd_soc_codec *codec = - container_of(work, struct snd_soc_codec, delayed_work.work); - wm8971_set_bias_level(codec, codec->bias_level); + struct snd_soc_dapm_context *dapm = + container_of(work, struct snd_soc_dapm_context, + delayed_work.work); + struct snd_soc_codec *codec = dapm->codec; + wm8971_set_bias_level(codec, codec->dapm.bias_level); } static int wm8971_suspend(struct snd_soc_codec *codec, pm_message_t state) @@ -620,11 +623,11 @@ static int wm8971_resume(struct snd_soc_codec *codec) wm8971_set_bias_level(codec, SND_SOC_BIAS_STANDBY); /* charge wm8971 caps */ - if (codec->suspend_bias_level == SND_SOC_BIAS_ON) { + if (codec->dapm.suspend_bias_level == SND_SOC_BIAS_ON) { reg = snd_soc_read(codec, WM8971_PWR1) & 0xfe3e; snd_soc_write(codec, WM8971_PWR1, reg | 0x01c0); - codec->bias_level = SND_SOC_BIAS_ON; - queue_delayed_work(wm8971_workq, &codec->delayed_work, + codec->dapm.bias_level = SND_SOC_BIAS_ON; + queue_delayed_work(wm8971_workq, &codec->dapm.delayed_work, msecs_to_jiffies(1000)); } @@ -643,7 +646,7 @@ static int wm8971_probe(struct snd_soc_codec *codec) return ret; } - INIT_DELAYED_WORK(&codec->delayed_work, wm8971_work); + INIT_DELAYED_WORK(&codec->dapm.delayed_work, wm8971_work); wm8971_workq = create_workqueue("wm8971"); if (wm8971_workq == NULL) return -ENOMEM; @@ -653,8 +656,8 @@ static int wm8971_probe(struct snd_soc_codec *codec) /* charge output caps - set vmid to 5k for quick power up */ reg = snd_soc_read(codec, WM8971_PWR1) & 0xfe3e; snd_soc_write(codec, WM8971_PWR1, reg | 0x01c0); - codec->bias_level = SND_SOC_BIAS_STANDBY; - queue_delayed_work(wm8971_workq, &codec->delayed_work, + codec->dapm.bias_level = SND_SOC_BIAS_STANDBY; + queue_delayed_work(wm8971_workq, &codec->dapm.delayed_work, msecs_to_jiffies(1000)); /* set the update bits */ diff --git a/sound/soc/codecs/wm8974.c b/sound/soc/codecs/wm8974.c index b4363f6d19b3..d19bb14842d4 100644 --- a/sound/soc/codecs/wm8974.c +++ b/sound/soc/codecs/wm8974.c @@ -274,10 +274,11 @@ static const struct snd_soc_dapm_route audio_map[] = { static int wm8974_add_widgets(struct snd_soc_codec *codec) { - snd_soc_dapm_new_controls(codec, wm8974_dapm_widgets, - ARRAY_SIZE(wm8974_dapm_widgets)); + struct snd_soc_dapm_context *dapm = &codec->dapm; - snd_soc_dapm_add_routes(codec, audio_map, ARRAY_SIZE(audio_map)); + snd_soc_dapm_new_controls(dapm, wm8974_dapm_widgets, + ARRAY_SIZE(wm8974_dapm_widgets)); + snd_soc_dapm_add_routes(dapm, audio_map, ARRAY_SIZE(audio_map)); return 0; } @@ -530,7 +531,7 @@ static int wm8974_set_bias_level(struct snd_soc_codec *codec, case SND_SOC_BIAS_STANDBY: power1 |= WM8974_POWER1_BIASEN | WM8974_POWER1_BUFIOEN; - if (codec->bias_level == SND_SOC_BIAS_OFF) { + if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) { /* Initial cap charge at VMID 5k */ snd_soc_write(codec, WM8974_POWER1, power1 | 0x3); mdelay(100); @@ -547,7 +548,7 @@ static int wm8974_set_bias_level(struct snd_soc_codec *codec, break; } - codec->bias_level = level; + codec->dapm.bias_level = level; return 0; } diff --git a/sound/soc/codecs/wm8978.c b/sound/soc/codecs/wm8978.c index 13b979a71a7c..ac43b6088e2e 100644 --- a/sound/soc/codecs/wm8978.c +++ b/sound/soc/codecs/wm8978.c @@ -355,11 +355,12 @@ static const struct snd_soc_dapm_route audio_map[] = { static int wm8978_add_widgets(struct snd_soc_codec *codec) { - snd_soc_dapm_new_controls(codec, wm8978_dapm_widgets, - ARRAY_SIZE(wm8978_dapm_widgets)); + struct snd_soc_dapm_context *dapm = &codec->dapm; + snd_soc_dapm_new_controls(dapm, wm8978_dapm_widgets, + ARRAY_SIZE(wm8978_dapm_widgets)); /* set up the WM8978 audio map */ - snd_soc_dapm_add_routes(codec, audio_map, ARRAY_SIZE(audio_map)); + snd_soc_dapm_add_routes(dapm, audio_map, ARRAY_SIZE(audio_map)); return 0; } @@ -837,7 +838,7 @@ static int wm8978_set_bias_level(struct snd_soc_codec *codec, /* bit 3: enable bias, bit 2: enable I/O tie off buffer */ power1 |= 0xc; - if (codec->bias_level == SND_SOC_BIAS_OFF) { + if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) { /* Initial cap charge at VMID 5k */ snd_soc_write(codec, WM8978_POWER_MANAGEMENT_1, power1 | 0x3); @@ -857,7 +858,7 @@ static int wm8978_set_bias_level(struct snd_soc_codec *codec, dev_dbg(codec->dev, "%s: %d, %x\n", __func__, level, power1); - codec->bias_level = level; + codec->dapm.bias_level = level; return 0; } diff --git a/sound/soc/codecs/wm8985.c b/sound/soc/codecs/wm8985.c index fd2e7cca1228..c3c8fd23d503 100644 --- a/sound/soc/codecs/wm8985.c +++ b/sound/soc/codecs/wm8985.c @@ -533,10 +533,11 @@ static int eqmode_put(struct snd_kcontrol *kcontrol, static int wm8985_add_widgets(struct snd_soc_codec *codec) { - snd_soc_dapm_new_controls(codec, wm8985_dapm_widgets, - ARRAY_SIZE(wm8985_dapm_widgets)); + struct snd_soc_dapm_context *dapm = &codec->dapm; - snd_soc_dapm_add_routes(codec, audio_map, + snd_soc_dapm_new_controls(dapm, wm8985_dapm_widgets, + ARRAY_SIZE(wm8985_dapm_widgets)); + snd_soc_dapm_add_routes(dapm, audio_map, ARRAY_SIZE(audio_map)); return 0; } @@ -879,7 +880,7 @@ static int wm8985_set_bias_level(struct snd_soc_codec *codec, 1 << WM8985_VMIDSEL_SHIFT); break; case SND_SOC_BIAS_STANDBY: - if (codec->bias_level == SND_SOC_BIAS_OFF) { + if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) { ret = regulator_bulk_enable(ARRAY_SIZE(wm8985->supplies), wm8985->supplies); if (ret) { @@ -939,7 +940,7 @@ static int wm8985_set_bias_level(struct snd_soc_codec *codec, break; } - codec->bias_level = level; + codec->dapm.bias_level = level; return 0; } diff --git a/sound/soc/codecs/wm8988.c b/sound/soc/codecs/wm8988.c index d7f259711970..0bc2eb530c7a 100644 --- a/sound/soc/codecs/wm8988.c +++ b/sound/soc/codecs/wm8988.c @@ -677,7 +677,7 @@ static int wm8988_set_bias_level(struct snd_soc_codec *codec, break; case SND_SOC_BIAS_STANDBY: - if (codec->bias_level == SND_SOC_BIAS_OFF) { + if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) { /* VREF, VMID=2x5k */ snd_soc_write(codec, WM8988_PWR1, pwr_reg | 0x1c1); @@ -693,7 +693,7 @@ static int wm8988_set_bias_level(struct snd_soc_codec *codec, snd_soc_write(codec, WM8988_PWR1, 0x0000); break; } - codec->bias_level = level; + codec->dapm.bias_level = level; return 0; } @@ -759,6 +759,7 @@ static int wm8988_resume(struct snd_soc_codec *codec) static int wm8988_probe(struct snd_soc_codec *codec) { struct wm8988_priv *wm8988 = snd_soc_codec_get_drvdata(codec); + struct snd_soc_dapm_context *dapm = &codec->dapm; int ret = 0; u16 reg; @@ -790,9 +791,9 @@ static int wm8988_probe(struct snd_soc_codec *codec) snd_soc_add_controls(codec, wm8988_snd_controls, ARRAY_SIZE(wm8988_snd_controls)); - snd_soc_dapm_new_controls(codec, wm8988_dapm_widgets, + snd_soc_dapm_new_controls(dapm, wm8988_dapm_widgets, ARRAY_SIZE(wm8988_dapm_widgets)); - snd_soc_dapm_add_routes(codec, audio_map, ARRAY_SIZE(audio_map)); + snd_soc_dapm_add_routes(dapm, audio_map, ARRAY_SIZE(audio_map)); return 0; } diff --git a/sound/soc/codecs/wm8990.c b/sound/soc/codecs/wm8990.c index 264828e4e67c..309664ea7dc3 100644 --- a/sound/soc/codecs/wm8990.c +++ b/sound/soc/codecs/wm8990.c @@ -914,11 +914,12 @@ static const struct snd_soc_dapm_route audio_map[] = { static int wm8990_add_widgets(struct snd_soc_codec *codec) { - snd_soc_dapm_new_controls(codec, wm8990_dapm_widgets, - ARRAY_SIZE(wm8990_dapm_widgets)); + struct snd_soc_dapm_context *dapm = &codec->dapm; + snd_soc_dapm_new_controls(dapm, wm8990_dapm_widgets, + ARRAY_SIZE(wm8990_dapm_widgets)); /* set up the WM8990 audio map */ - snd_soc_dapm_add_routes(codec, audio_map, ARRAY_SIZE(audio_map)); + snd_soc_dapm_add_routes(dapm, audio_map, ARRAY_SIZE(audio_map)); return 0; } @@ -1170,7 +1171,7 @@ static int wm8990_set_bias_level(struct snd_soc_codec *codec, break; case SND_SOC_BIAS_STANDBY: - if (codec->bias_level == SND_SOC_BIAS_OFF) { + if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) { /* Enable all output discharge bits */ snd_soc_write(codec, WM8990_ANTIPOP1, WM8990_DIS_LLINE | WM8990_DIS_RLINE | WM8990_DIS_OUT3 | @@ -1266,7 +1267,7 @@ static int wm8990_set_bias_level(struct snd_soc_codec *codec, break; } - codec->bias_level = level; + codec->dapm.bias_level = level; return 0; } diff --git a/sound/soc/codecs/wm8993.c b/sound/soc/codecs/wm8993.c index 67fe5ccc6082..bcc54be572ce 100644 --- a/sound/soc/codecs/wm8993.c +++ b/sound/soc/codecs/wm8993.c @@ -970,7 +970,7 @@ static int wm8993_set_bias_level(struct snd_soc_codec *codec, break; case SND_SOC_BIAS_STANDBY: - if (codec->bias_level == SND_SOC_BIAS_OFF) { + if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) { ret = regulator_bulk_enable(ARRAY_SIZE(wm8993->supplies), wm8993->supplies); if (ret != 0) @@ -1045,7 +1045,7 @@ static int wm8993_set_bias_level(struct snd_soc_codec *codec, break; } - codec->bias_level = level; + codec->dapm.bias_level = level; return 0; } @@ -1424,6 +1424,7 @@ static struct snd_soc_dai_driver wm8993_dai = { static int wm8993_probe(struct snd_soc_codec *codec) { struct wm8993_priv *wm8993 = snd_soc_codec_get_drvdata(codec); + struct snd_soc_dapm_context *dapm = &codec->dapm; int ret, i, val; wm8993->hubs_data.hp_startup_mode = 1; @@ -1505,11 +1506,11 @@ static int wm8993_probe(struct snd_soc_codec *codec) ARRAY_SIZE(wm8993_eq_controls)); } - snd_soc_dapm_new_controls(codec, wm8993_dapm_widgets, + snd_soc_dapm_new_controls(dapm, wm8993_dapm_widgets, ARRAY_SIZE(wm8993_dapm_widgets)); wm_hubs_add_analogue_controls(codec); - snd_soc_dapm_add_routes(codec, routes, ARRAY_SIZE(routes)); + snd_soc_dapm_add_routes(dapm, routes, ARRAY_SIZE(routes)); wm_hubs_add_analogue_routes(codec, wm8993->pdata.lineout1_diff, wm8993->pdata.lineout2_diff); diff --git a/sound/soc/codecs/wm8994.c b/sound/soc/codecs/wm8994.c index d81cac5b93b4..f7dea3d34a3e 100644 --- a/sound/soc/codecs/wm8994.c +++ b/sound/soc/codecs/wm8994.c @@ -1835,7 +1835,7 @@ static int configure_clock(struct snd_soc_codec *codec) snd_soc_update_bits(codec, WM8994_CLOCKING_1, WM8994_SYSCLK_SRC, new); - snd_soc_dapm_sync(codec); + snd_soc_dapm_sync(&codec->dapm); return 0; } @@ -3108,7 +3108,7 @@ static int wm8994_set_bias_level(struct snd_soc_codec *codec, break; case SND_SOC_BIAS_STANDBY: - if (codec->bias_level == SND_SOC_BIAS_OFF) { + if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) { /* Tweak DC servo and DSP configuration for * improved performance. */ if (wm8994->revision < 4) { @@ -3152,7 +3152,7 @@ static int wm8994_set_bias_level(struct snd_soc_codec *codec, break; case SND_SOC_BIAS_OFF: - if (codec->bias_level == SND_SOC_BIAS_STANDBY) { + if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY) { /* Switch over to startup biases */ snd_soc_update_bits(codec, WM8994_ANTIPOP_2, WM8994_BIAS_SRC | @@ -3187,7 +3187,7 @@ static int wm8994_set_bias_level(struct snd_soc_codec *codec, } break; } - codec->bias_level = level; + codec->dapm.bias_level = level; return 0; } @@ -3895,6 +3895,7 @@ static irqreturn_t wm8994_mic_irq(int irq, void *data) static int wm8994_codec_probe(struct snd_soc_codec *codec) { struct wm8994_priv *wm8994; + struct snd_soc_dapm_context *dapm = &codec->dapm; int ret, i; codec->control_data = dev_get_drvdata(codec->dev->parent); @@ -4033,10 +4034,10 @@ static int wm8994_codec_probe(struct snd_soc_codec *codec) wm_hubs_add_analogue_controls(codec); snd_soc_add_controls(codec, wm8994_snd_controls, ARRAY_SIZE(wm8994_snd_controls)); - snd_soc_dapm_new_controls(codec, wm8994_dapm_widgets, + snd_soc_dapm_new_controls(dapm, wm8994_dapm_widgets, ARRAY_SIZE(wm8994_dapm_widgets)); wm_hubs_add_analogue_routes(codec, 0, 0); - snd_soc_dapm_add_routes(codec, intercon, ARRAY_SIZE(intercon)); + snd_soc_dapm_add_routes(dapm, intercon, ARRAY_SIZE(intercon)); return 0; diff --git a/sound/soc/codecs/wm9081.c b/sound/soc/codecs/wm9081.c index ecc7c37180c7..c03e2c3e24e1 100644 --- a/sound/soc/codecs/wm9081.c +++ b/sound/soc/codecs/wm9081.c @@ -805,7 +805,7 @@ static int wm9081_set_bias_level(struct snd_soc_codec *codec, case SND_SOC_BIAS_STANDBY: /* Initial cold start */ - if (codec->bias_level == SND_SOC_BIAS_OFF) { + if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) { /* Disable LINEOUT discharge */ reg = snd_soc_read(codec, WM9081_ANTI_POP_CONTROL); reg &= ~WM9081_LINEOUT_DISCH; @@ -865,7 +865,7 @@ static int wm9081_set_bias_level(struct snd_soc_codec *codec, break; } - codec->bias_level = level; + codec->dapm.bias_level = level; return 0; } @@ -1228,6 +1228,7 @@ static struct snd_soc_dai_driver wm9081_dai = { static int wm9081_probe(struct snd_soc_codec *codec) { struct wm9081_priv *wm9081 = snd_soc_codec_get_drvdata(codec); + struct snd_soc_dapm_context *dapm = &codec->dapm; int ret; u16 reg; @@ -1269,9 +1270,9 @@ static int wm9081_probe(struct snd_soc_codec *codec) ARRAY_SIZE(wm9081_eq_controls)); } - snd_soc_dapm_new_controls(codec, wm9081_dapm_widgets, + snd_soc_dapm_new_controls(dapm, wm9081_dapm_widgets, ARRAY_SIZE(wm9081_dapm_widgets)); - snd_soc_dapm_add_routes(codec, audio_paths, ARRAY_SIZE(audio_paths)); + snd_soc_dapm_add_routes(dapm, audio_paths, ARRAY_SIZE(audio_paths)); return ret; } diff --git a/sound/soc/codecs/wm9090.c b/sound/soc/codecs/wm9090.c index 99c046ba46bb..b5afa01aa383 100644 --- a/sound/soc/codecs/wm9090.c +++ b/sound/soc/codecs/wm9090.c @@ -443,31 +443,32 @@ static const struct snd_soc_dapm_route audio_map_in2_diff[] = { static int wm9090_add_controls(struct snd_soc_codec *codec) { struct wm9090_priv *wm9090 = snd_soc_codec_get_drvdata(codec); + struct snd_soc_dapm_context *dapm = &codec->dapm; int i; - snd_soc_dapm_new_controls(codec, wm9090_dapm_widgets, + snd_soc_dapm_new_controls(dapm, wm9090_dapm_widgets, ARRAY_SIZE(wm9090_dapm_widgets)); - snd_soc_dapm_add_routes(codec, audio_map, ARRAY_SIZE(audio_map)); + snd_soc_dapm_add_routes(dapm, audio_map, ARRAY_SIZE(audio_map)); snd_soc_add_controls(codec, wm9090_controls, ARRAY_SIZE(wm9090_controls)); if (wm9090->pdata.lin1_diff) { - snd_soc_dapm_add_routes(codec, audio_map_in1_diff, + snd_soc_dapm_add_routes(dapm, audio_map_in1_diff, ARRAY_SIZE(audio_map_in1_diff)); } else { - snd_soc_dapm_add_routes(codec, audio_map_in1_se, + snd_soc_dapm_add_routes(dapm, audio_map_in1_se, ARRAY_SIZE(audio_map_in1_se)); snd_soc_add_controls(codec, wm9090_in1_se_controls, ARRAY_SIZE(wm9090_in1_se_controls)); } if (wm9090->pdata.lin2_diff) { - snd_soc_dapm_add_routes(codec, audio_map_in2_diff, + snd_soc_dapm_add_routes(dapm, audio_map_in2_diff, ARRAY_SIZE(audio_map_in2_diff)); } else { - snd_soc_dapm_add_routes(codec, audio_map_in2_se, + snd_soc_dapm_add_routes(dapm, audio_map_in2_se, ARRAY_SIZE(audio_map_in2_se)); snd_soc_add_controls(codec, wm9090_in2_se_controls, ARRAY_SIZE(wm9090_in2_se_controls)); @@ -514,7 +515,7 @@ static int wm9090_set_bias_level(struct snd_soc_codec *codec, break; case SND_SOC_BIAS_STANDBY: - if (codec->bias_level == SND_SOC_BIAS_OFF) { + if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) { /* Restore the register cache */ for (i = 1; i < codec->driver->reg_cache_size; i++) { if (reg_cache[i] == wm9090_reg_defaults[i]) @@ -544,7 +545,7 @@ static int wm9090_set_bias_level(struct snd_soc_codec *codec, break; } - codec->bias_level = level; + codec->dapm.bias_level = level; return 0; } diff --git a/sound/soc/codecs/wm9705.c b/sound/soc/codecs/wm9705.c index a144acda751c..58d120824498 100644 --- a/sound/soc/codecs/wm9705.c +++ b/sound/soc/codecs/wm9705.c @@ -203,9 +203,11 @@ static const struct snd_soc_dapm_route audio_map[] = { static int wm9705_add_widgets(struct snd_soc_codec *codec) { - snd_soc_dapm_new_controls(codec, wm9705_dapm_widgets, + struct snd_soc_dapm_context *dapm = &codec->dapm; + + snd_soc_dapm_new_controls(dapm, wm9705_dapm_widgets, ARRAY_SIZE(wm9705_dapm_widgets)); - snd_soc_dapm_add_routes(codec, audio_map, ARRAY_SIZE(audio_map)); + snd_soc_dapm_add_routes(dapm, audio_map, ARRAY_SIZE(audio_map)); return 0; } diff --git a/sound/soc/codecs/wm9712.c b/sound/soc/codecs/wm9712.c index d2f224d62744..3ca42a35e03a 100644 --- a/sound/soc/codecs/wm9712.c +++ b/sound/soc/codecs/wm9712.c @@ -432,10 +432,11 @@ static const struct snd_soc_dapm_route audio_map[] = { static int wm9712_add_widgets(struct snd_soc_codec *codec) { - snd_soc_dapm_new_controls(codec, wm9712_dapm_widgets, - ARRAY_SIZE(wm9712_dapm_widgets)); + struct snd_soc_dapm_context *dapm = &codec->dapm; - snd_soc_dapm_add_routes(codec, audio_map, ARRAY_SIZE(audio_map)); + snd_soc_dapm_new_controls(dapm, wm9712_dapm_widgets, + ARRAY_SIZE(wm9712_dapm_widgets)); + snd_soc_dapm_add_routes(dapm, audio_map, ARRAY_SIZE(audio_map)); return 0; } @@ -570,7 +571,7 @@ static int wm9712_set_bias_level(struct snd_soc_codec *codec, ac97_write(codec, AC97_POWERDOWN, 0xffff); break; } - codec->bias_level = level; + codec->dapm.bias_level = level; return 0; } diff --git a/sound/soc/codecs/wm9713.c b/sound/soc/codecs/wm9713.c index 7da13b07a53d..87b236b16016 100644 --- a/sound/soc/codecs/wm9713.c +++ b/sound/soc/codecs/wm9713.c @@ -647,10 +647,12 @@ static const struct snd_soc_dapm_route audio_map[] = { static int wm9713_add_widgets(struct snd_soc_codec *codec) { - snd_soc_dapm_new_controls(codec, wm9713_dapm_widgets, + struct snd_soc_dapm_context *dapm = &codec->dapm; + + snd_soc_dapm_new_controls(dapm, wm9713_dapm_widgets, ARRAY_SIZE(wm9713_dapm_widgets)); - snd_soc_dapm_add_routes(codec, audio_map, ARRAY_SIZE(audio_map)); + snd_soc_dapm_add_routes(dapm, audio_map, ARRAY_SIZE(audio_map)); return 0; } @@ -1147,7 +1149,7 @@ static int wm9713_set_bias_level(struct snd_soc_codec *codec, ac97_write(codec, AC97_POWERDOWN, 0xffff); break; } - codec->bias_level = level; + codec->dapm.bias_level = level; return 0; } diff --git a/sound/soc/codecs/wm_hubs.c b/sound/soc/codecs/wm_hubs.c index 008b1f27aea8..8aff0efe72f5 100644 --- a/sound/soc/codecs/wm_hubs.c +++ b/sound/soc/codecs/wm_hubs.c @@ -814,6 +814,8 @@ static const struct snd_soc_dapm_route lineout2_se_routes[] = { int wm_hubs_add_analogue_controls(struct snd_soc_codec *codec) { + struct snd_soc_dapm_context *dapm = &codec->dapm; + /* Latch volume update bits & default ZC on */ snd_soc_update_bits(codec, WM8993_LEFT_LINE_INPUT_1_2_VOLUME, WM8993_IN1_VU, WM8993_IN1_VU); @@ -842,7 +844,7 @@ int wm_hubs_add_analogue_controls(struct snd_soc_codec *codec) snd_soc_add_controls(codec, analogue_snd_controls, ARRAY_SIZE(analogue_snd_controls)); - snd_soc_dapm_new_controls(codec, analogue_dapm_widgets, + snd_soc_dapm_new_controls(dapm, analogue_dapm_widgets, ARRAY_SIZE(analogue_dapm_widgets)); return 0; } @@ -851,24 +853,26 @@ EXPORT_SYMBOL_GPL(wm_hubs_add_analogue_controls); int wm_hubs_add_analogue_routes(struct snd_soc_codec *codec, int lineout1_diff, int lineout2_diff) { - snd_soc_dapm_add_routes(codec, analogue_routes, + struct snd_soc_dapm_context *dapm = &codec->dapm; + + snd_soc_dapm_add_routes(dapm, analogue_routes, ARRAY_SIZE(analogue_routes)); if (lineout1_diff) - snd_soc_dapm_add_routes(codec, + snd_soc_dapm_add_routes(dapm, lineout1_diff_routes, ARRAY_SIZE(lineout1_diff_routes)); else - snd_soc_dapm_add_routes(codec, + snd_soc_dapm_add_routes(dapm, lineout1_se_routes, ARRAY_SIZE(lineout1_se_routes)); if (lineout2_diff) - snd_soc_dapm_add_routes(codec, + snd_soc_dapm_add_routes(dapm, lineout2_diff_routes, ARRAY_SIZE(lineout2_diff_routes)); else - snd_soc_dapm_add_routes(codec, + snd_soc_dapm_add_routes(dapm, lineout2_se_routes, ARRAY_SIZE(lineout2_se_routes)); @@ -895,7 +899,7 @@ int wm_hubs_handle_analogue_pdata(struct snd_soc_codec *codec, * VMID as an output and can disable it. */ if (lineout1_diff && lineout2_diff) - codec->idle_bias_off = 1; + codec->dapm.idle_bias_off = 1; if (lineout1fb) snd_soc_update_bits(codec, WM8993_ADDITIONAL_CONTROL, -- cgit v1.2.2 From 3a45b8672d3f8542e430e7a5c7366ec9bdded054 Mon Sep 17 00:00:00 2001 From: Jarkko Nikula Date: Fri, 5 Nov 2010 20:35:21 +0200 Subject: ASoC: Move pop time from DAPM context to sound card Based on discussion the dapm_pop_time in debugsfs should be per card rather than per device. Single pop time value for entire card is cleaner when the DAPM sequencing is extended to cross-device paths. debugfs/asoc/{card->name}/{codec dir}/dapm_pop_time -> debugfs/asoc/{card->name}/dapm_pop_time Signed-off-by: Jarkko Nikula Signed-off-by: Mark Brown --- sound/soc/codecs/cx20442.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'sound/soc/codecs') diff --git a/sound/soc/codecs/cx20442.c b/sound/soc/codecs/cx20442.c index 11beb1a77c4e..a9521acad99c 100644 --- a/sound/soc/codecs/cx20442.c +++ b/sound/soc/codecs/cx20442.c @@ -264,7 +264,7 @@ static void v253_close(struct tty_struct *tty) /* Prevent the codec driver from further accessing the modem */ codec->hw_write = NULL; cx20442->control_data = NULL; - codec->dapm.pop_time = 0; + codec->card->pop_time = 0; } /* Line discipline .hangup() */ @@ -292,7 +292,7 @@ static void v253_receive(struct tty_struct *tty, /* Set up codec driver access to modem controls */ cx20442->control_data = tty; codec->hw_write = (hw_write_t)tty->ops->write; - codec->dapm.pop_time = 1; + codec->card->pop_time = 1; } } @@ -349,7 +349,7 @@ static int cx20442_codec_probe(struct snd_soc_codec *codec) cx20442->control_data = NULL; codec->hw_write = NULL; - codec->dapm.pop_time = 0; + codec->card->pop_time = 0; return 0; } -- cgit v1.2.2 From c046fd4dd613b22b35379665a8f7656d17bde0b3 Mon Sep 17 00:00:00 2001 From: Dimitris Papastamos Date: Fri, 5 Nov 2010 18:41:25 +0000 Subject: ASoC: WM8770: Initial driver The WM8770 is a high performance, multi-channel audio codec. The WM8770 is ideal for surround sound processing applications for home hi-fi, automotive and other audio visual equipment. Signed-off-by: Dimitris Papastamos Signed-off-by: Mark Brown --- sound/soc/codecs/Kconfig | 4 + sound/soc/codecs/Makefile | 2 + sound/soc/codecs/wm8770.c | 750 ++++++++++++++++++++++++++++++++++++++++++++++ sound/soc/codecs/wm8770.h | 51 ++++ 4 files changed, 807 insertions(+) create mode 100644 sound/soc/codecs/wm8770.c create mode 100644 sound/soc/codecs/wm8770.h (limited to 'sound/soc/codecs') diff --git a/sound/soc/codecs/Kconfig b/sound/soc/codecs/Kconfig index e61fbab48aa2..6ebd3a685b2c 100644 --- a/sound/soc/codecs/Kconfig +++ b/sound/soc/codecs/Kconfig @@ -58,6 +58,7 @@ config SND_SOC_ALL_CODECS select SND_SOC_WM8741 if SND_SOC_I2C_AND_SPI select SND_SOC_WM8750 if SND_SOC_I2C_AND_SPI select SND_SOC_WM8753 if SND_SOC_I2C_AND_SPI + select SND_SOC_WM8770 if SPI_MASTER select SND_SOC_WM8776 if SND_SOC_I2C_AND_SPI select SND_SOC_WM8804 if SND_SOC_I2C_AND_SPI select SND_SOC_WM8900 if I2C @@ -244,6 +245,9 @@ config SND_SOC_WM8750 config SND_SOC_WM8753 tristate +config SND_SOC_WM8770 + tristate + config SND_SOC_WM8776 tristate diff --git a/sound/soc/codecs/Makefile b/sound/soc/codecs/Makefile index 0dcaed3e73f3..42f185d233f3 100644 --- a/sound/soc/codecs/Makefile +++ b/sound/soc/codecs/Makefile @@ -42,6 +42,7 @@ snd-soc-wm8731-objs := wm8731.o snd-soc-wm8741-objs := wm8741.o snd-soc-wm8750-objs := wm8750.o snd-soc-wm8753-objs := wm8753.o +snd-soc-wm8770-objs := wm8770.o snd-soc-wm8776-objs := wm8776.o snd-soc-wm8804-objs := wm8804.o snd-soc-wm8900-objs := wm8900.o @@ -118,6 +119,7 @@ obj-$(CONFIG_SND_SOC_WM8731) += snd-soc-wm8731.o obj-$(CONFIG_SND_SOC_WM8741) += snd-soc-wm8741.o obj-$(CONFIG_SND_SOC_WM8750) += snd-soc-wm8750.o obj-$(CONFIG_SND_SOC_WM8753) += snd-soc-wm8753.o +obj-$(CONFIG_SND_SOC_WM8770) += snd-soc-wm8770.o obj-$(CONFIG_SND_SOC_WM8776) += snd-soc-wm8776.o obj-$(CONFIG_SND_SOC_WM8804) += snd-soc-wm8804.o obj-$(CONFIG_SND_SOC_WM8900) += snd-soc-wm8900.o diff --git a/sound/soc/codecs/wm8770.c b/sound/soc/codecs/wm8770.c new file mode 100644 index 000000000000..8608b4a10b0a --- /dev/null +++ b/sound/soc/codecs/wm8770.c @@ -0,0 +1,750 @@ +/* + * wm8770.c -- WM8770 ALSA SoC Audio driver + * + * Copyright 2010 Wolfson Microelectronics plc + * + * Author: Dimitris Papastamos + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "wm8770.h" + +#define WM8770_NUM_SUPPLIES 3 +static const char *wm8770_supply_names[WM8770_NUM_SUPPLIES] = { + "AVDD1", + "AVDD2", + "DVDD" +}; + +static const u16 wm8770_reg_defs[WM8770_CACHEREGNUM] = { + 0x7f, 0x7f, 0x7f, 0x7f, + 0x7f, 0x7f, 0x7f, 0x7f, + 0x7f, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0, 0x90, 0, + 0, 0x22, 0x22, 0x3e, + 0xc, 0xc, 0x100, 0x189, + 0x189, 0x8770 +}; + +struct wm8770_priv { + enum snd_soc_control_type control_type; + struct regulator_bulk_data supplies[WM8770_NUM_SUPPLIES]; + struct notifier_block disable_nb[WM8770_NUM_SUPPLIES]; + struct snd_soc_codec *codec; + int sysclk; +}; + +static int vout12supply_event(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, int event); +static int vout34supply_event(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, int event); + +/* + * We can't use the same notifier block for more than one supply and + * there's no way I can see to get from a callback to the caller + * except container_of(). + */ +#define WM8770_REGULATOR_EVENT(n) \ +static int wm8770_regulator_event_##n(struct notifier_block *nb, \ + unsigned long event, void *data) \ +{ \ + struct wm8770_priv *wm8770 = container_of(nb, struct wm8770_priv, \ + disable_nb[n]); \ + if (event & REGULATOR_EVENT_DISABLE) { \ + wm8770->codec->cache_sync = 1; \ + } \ + return 0; \ +} + +WM8770_REGULATOR_EVENT(0) +WM8770_REGULATOR_EVENT(1) +WM8770_REGULATOR_EVENT(2) + +static const DECLARE_TLV_DB_SCALE(adc_tlv, -1200, 100, 0); +static const DECLARE_TLV_DB_SCALE(dac_dig_tlv, -12750, 50, 1); +static const DECLARE_TLV_DB_SCALE(dac_alg_tlv, -12700, 100, 1); + +static const char *dac_phase_text[][2] = { + { "DAC1 Normal", "DAC1 Inverted" }, + { "DAC2 Normal", "DAC2 Inverted" }, + { "DAC3 Normal", "DAC3 Inverted" }, + { "DAC4 Normal", "DAC4 Inverted" }, +}; + +static const struct soc_enum dac_phase[] = { + SOC_ENUM_DOUBLE(WM8770_DACPHASE, 0, 1, 2, dac_phase_text[0]), + SOC_ENUM_DOUBLE(WM8770_DACPHASE, 2, 3, 2, dac_phase_text[1]), + SOC_ENUM_DOUBLE(WM8770_DACPHASE, 4, 5, 2, dac_phase_text[2]), + SOC_ENUM_DOUBLE(WM8770_DACPHASE, 6, 7, 2, dac_phase_text[3]), +}; + +static const struct snd_kcontrol_new wm8770_snd_controls[] = { + /* global DAC playback controls */ + SOC_SINGLE_TLV("DAC Playback Volume", WM8770_MSDIGVOL, 0, 255, 0, + dac_dig_tlv), + SOC_SINGLE("DAC Playback Switch", WM8770_DACMUTE, 4, 1, 1), + SOC_SINGLE("DAC Playback ZC Switch", WM8770_DACCTRL1, 0, 1, 0), + + /* global VOUT playback controls */ + SOC_SINGLE_TLV("VOUT Playback Volume", WM8770_MSALGVOL, 0, 127, 0, + dac_alg_tlv), + SOC_SINGLE("VOUT Playback ZC Switch", WM8770_MSALGVOL, 7, 1, 0), + + /* VOUT1/2/3/4 specific controls */ + SOC_DOUBLE_R_TLV("VOUT1 Playback Volume", WM8770_VOUT1LVOL, + WM8770_VOUT1RVOL, 0, 127, 0, dac_alg_tlv), + SOC_DOUBLE_R("VOUT1 Playback ZC Switch", WM8770_VOUT1LVOL, + WM8770_VOUT1RVOL, 7, 1, 0), + SOC_DOUBLE_R_TLV("VOUT2 Playback Volume", WM8770_VOUT2LVOL, + WM8770_VOUT2RVOL, 0, 127, 0, dac_alg_tlv), + SOC_DOUBLE_R("VOUT2 Playback ZC Switch", WM8770_VOUT2LVOL, + WM8770_VOUT2RVOL, 7, 1, 0), + SOC_DOUBLE_R_TLV("VOUT3 Playback Volume", WM8770_VOUT3LVOL, + WM8770_VOUT3RVOL, 0, 127, 0, dac_alg_tlv), + SOC_DOUBLE_R("VOUT3 Playback ZC Switch", WM8770_VOUT3LVOL, + WM8770_VOUT3RVOL, 7, 1, 0), + SOC_DOUBLE_R_TLV("VOUT4 Playback Volume", WM8770_VOUT4LVOL, + WM8770_VOUT4RVOL, 0, 127, 0, dac_alg_tlv), + SOC_DOUBLE_R("VOUT4 Playback ZC Switch", WM8770_VOUT4LVOL, + WM8770_VOUT4RVOL, 7, 1, 0), + + /* DAC1/2/3/4 specific controls */ + SOC_DOUBLE_R_TLV("DAC1 Playback Volume", WM8770_DAC1LVOL, + WM8770_DAC1RVOL, 0, 255, 0, dac_dig_tlv), + SOC_SINGLE("DAC1 Deemphasis Switch", WM8770_DACCTRL2, 0, 1, 0), + SOC_ENUM("DAC1 Phase", dac_phase[0]), + SOC_DOUBLE_R_TLV("DAC2 Playback Volume", WM8770_DAC2LVOL, + WM8770_DAC2RVOL, 0, 255, 0, dac_dig_tlv), + SOC_SINGLE("DAC2 Deemphasis Switch", WM8770_DACCTRL2, 1, 1, 0), + SOC_ENUM("DAC2 Phase", dac_phase[1]), + SOC_DOUBLE_R_TLV("DAC3 Playback Volume", WM8770_DAC3LVOL, + WM8770_DAC3RVOL, 0, 255, 0, dac_dig_tlv), + SOC_SINGLE("DAC3 Deemphasis Switch", WM8770_DACCTRL2, 2, 1, 0), + SOC_ENUM("DAC3 Phase", dac_phase[2]), + SOC_DOUBLE_R_TLV("DAC4 Playback Volume", WM8770_DAC4LVOL, + WM8770_DAC4RVOL, 0, 255, 0, dac_dig_tlv), + SOC_SINGLE("DAC4 Deemphasis Switch", WM8770_DACCTRL2, 3, 1, 0), + SOC_ENUM("DAC4 Phase", dac_phase[3]), + + /* ADC specific controls */ + SOC_DOUBLE_R_TLV("Capture Volume", WM8770_ADCLCTRL, WM8770_ADCRCTRL, + 0, 31, 0, adc_tlv), + SOC_DOUBLE_R("Capture Switch", WM8770_ADCLCTRL, WM8770_ADCRCTRL, + 5, 1, 1), + + /* other controls */ + SOC_SINGLE("ADC 128x Oversampling Switch", WM8770_MSTRCTRL, 3, 1, 0), + SOC_SINGLE("ADC Highpass Filter Switch", WM8770_IFACECTRL, 8, 1, 1) +}; + +static const char *ain_text[] = { + "AIN1", "AIN2", "AIN3", "AIN4", + "AIN5", "AIN6", "AIN7", "AIN8" +}; + +static const struct soc_enum ain_enum = + SOC_ENUM_DOUBLE(WM8770_ADCMUX, 0, 4, 8, ain_text); + +static const struct snd_kcontrol_new ain_mux = + SOC_DAPM_ENUM("Capture Mux", ain_enum); + +static const struct snd_kcontrol_new vout1_mix_controls[] = { + SOC_DAPM_SINGLE("DAC1 Switch", WM8770_OUTMUX1, 0, 1, 0), + SOC_DAPM_SINGLE("AUX1 Switch", WM8770_OUTMUX1, 1, 1, 0), + SOC_DAPM_SINGLE("Bypass Switch", WM8770_OUTMUX1, 2, 1, 0) +}; + +static const struct snd_kcontrol_new vout2_mix_controls[] = { + SOC_DAPM_SINGLE("DAC2 Switch", WM8770_OUTMUX1, 3, 1, 0), + SOC_DAPM_SINGLE("AUX2 Switch", WM8770_OUTMUX1, 4, 1, 0), + SOC_DAPM_SINGLE("Bypass Switch", WM8770_OUTMUX1, 5, 1, 0) +}; + +static const struct snd_kcontrol_new vout3_mix_controls[] = { + SOC_DAPM_SINGLE("DAC3 Switch", WM8770_OUTMUX2, 0, 1, 0), + SOC_DAPM_SINGLE("AUX3 Switch", WM8770_OUTMUX2, 1, 1, 0), + SOC_DAPM_SINGLE("Bypass Switch", WM8770_OUTMUX2, 2, 1, 0) +}; + +static const struct snd_kcontrol_new vout4_mix_controls[] = { + SOC_DAPM_SINGLE("DAC4 Switch", WM8770_OUTMUX2, 3, 1, 0), + SOC_DAPM_SINGLE("Bypass Switch", WM8770_OUTMUX2, 4, 1, 0) +}; + +static const struct snd_soc_dapm_widget wm8770_dapm_widgets[] = { + SND_SOC_DAPM_INPUT("AUX1"), + SND_SOC_DAPM_INPUT("AUX2"), + SND_SOC_DAPM_INPUT("AUX3"), + + SND_SOC_DAPM_INPUT("AIN1"), + SND_SOC_DAPM_INPUT("AIN2"), + SND_SOC_DAPM_INPUT("AIN3"), + SND_SOC_DAPM_INPUT("AIN4"), + SND_SOC_DAPM_INPUT("AIN5"), + SND_SOC_DAPM_INPUT("AIN6"), + SND_SOC_DAPM_INPUT("AIN7"), + SND_SOC_DAPM_INPUT("AIN8"), + + SND_SOC_DAPM_MUX("Capture Mux", WM8770_ADCMUX, 8, 1, &ain_mux), + + SND_SOC_DAPM_ADC("ADC", "Capture", WM8770_PWDNCTRL, 1, 1), + + SND_SOC_DAPM_DAC("DAC1", "Playback", WM8770_PWDNCTRL, 2, 1), + SND_SOC_DAPM_DAC("DAC2", "Playback", WM8770_PWDNCTRL, 3, 1), + SND_SOC_DAPM_DAC("DAC3", "Playback", WM8770_PWDNCTRL, 4, 1), + SND_SOC_DAPM_DAC("DAC4", "Playback", WM8770_PWDNCTRL, 5, 1), + + SND_SOC_DAPM_SUPPLY("VOUT12 Supply", SND_SOC_NOPM, 0, 0, + vout12supply_event, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), + SND_SOC_DAPM_SUPPLY("VOUT34 Supply", SND_SOC_NOPM, 0, 0, + vout34supply_event, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), + + SND_SOC_DAPM_MIXER("VOUT1 Mixer", SND_SOC_NOPM, 0, 0, + vout1_mix_controls, ARRAY_SIZE(vout1_mix_controls)), + SND_SOC_DAPM_MIXER("VOUT2 Mixer", SND_SOC_NOPM, 0, 0, + vout2_mix_controls, ARRAY_SIZE(vout2_mix_controls)), + SND_SOC_DAPM_MIXER("VOUT3 Mixer", SND_SOC_NOPM, 0, 0, + vout3_mix_controls, ARRAY_SIZE(vout3_mix_controls)), + SND_SOC_DAPM_MIXER("VOUT4 Mixer", SND_SOC_NOPM, 0, 0, + vout4_mix_controls, ARRAY_SIZE(vout4_mix_controls)), + + SND_SOC_DAPM_OUTPUT("VOUT1"), + SND_SOC_DAPM_OUTPUT("VOUT2"), + SND_SOC_DAPM_OUTPUT("VOUT3"), + SND_SOC_DAPM_OUTPUT("VOUT4") +}; + +static const struct snd_soc_dapm_route wm8770_intercon[] = { + { "Capture Mux", "AIN1", "AIN1" }, + { "Capture Mux", "AIN2", "AIN2" }, + { "Capture Mux", "AIN3", "AIN3" }, + { "Capture Mux", "AIN4", "AIN4" }, + { "Capture Mux", "AIN5", "AIN5" }, + { "Capture Mux", "AIN6", "AIN6" }, + { "Capture Mux", "AIN7", "AIN7" }, + { "Capture Mux", "AIN8", "AIN8" }, + + { "ADC", NULL, "Capture Mux" }, + + { "VOUT1 Mixer", NULL, "VOUT12 Supply" }, + { "VOUT1 Mixer", "DAC1 Switch", "DAC1" }, + { "VOUT1 Mixer", "AUX1 Switch", "AUX1" }, + { "VOUT1 Mixer", "Bypass Switch", "Capture Mux" }, + + { "VOUT2 Mixer", NULL, "VOUT12 Supply" }, + { "VOUT2 Mixer", "DAC2 Switch", "DAC2" }, + { "VOUT2 Mixer", "AUX2 Switch", "AUX2" }, + { "VOUT2 Mixer", "Bypass Switch", "Capture Mux" }, + + { "VOUT3 Mixer", NULL, "VOUT34 Supply" }, + { "VOUT3 Mixer", "DAC3 Switch", "DAC3" }, + { "VOUT3 Mixer", "AUX3 Switch", "AUX3" }, + { "VOUT3 Mixer", "Bypass Switch", "Capture Mux" }, + + { "VOUT4 Mixer", NULL, "VOUT34 Supply" }, + { "VOUT4 Mixer", "DAC4 Switch", "DAC4" }, + { "VOUT4 Mixer", "Bypass Switch", "Capture Mux" }, + + { "VOUT1", NULL, "VOUT1 Mixer" }, + { "VOUT2", NULL, "VOUT2 Mixer" }, + { "VOUT3", NULL, "VOUT3 Mixer" }, + { "VOUT4", NULL, "VOUT4 Mixer" } +}; + +static int vout12supply_event(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, int event) +{ + struct snd_soc_codec *codec; + + codec = w->codec; + + switch (event) { + case SND_SOC_DAPM_PRE_PMU: + snd_soc_update_bits(codec, WM8770_OUTMUX1, 0x180, 0); + break; + case SND_SOC_DAPM_POST_PMD: + snd_soc_update_bits(codec, WM8770_OUTMUX1, 0x180, 0x180); + break; + } + + return 0; +} + +static int vout34supply_event(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, int event) +{ + struct snd_soc_codec *codec; + + codec = w->codec; + + switch (event) { + case SND_SOC_DAPM_PRE_PMU: + snd_soc_update_bits(codec, WM8770_OUTMUX2, 0x180, 0); + break; + case SND_SOC_DAPM_POST_PMD: + snd_soc_update_bits(codec, WM8770_OUTMUX2, 0x180, 0x180); + break; + } + + return 0; +} + +static int wm8770_reset(struct snd_soc_codec *codec) +{ + return snd_soc_write(codec, WM8770_RESET, 0); +} + +static int wm8770_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) +{ + struct snd_soc_codec *codec; + int iface, master; + + codec = dai->codec; + + switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { + case SND_SOC_DAIFMT_CBM_CFM: + master = 0x100; + break; + case SND_SOC_DAIFMT_CBS_CFS: + master = 0; + break; + default: + return -EINVAL; + } + + iface = 0; + switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { + case SND_SOC_DAIFMT_I2S: + iface |= 0x2; + break; + case SND_SOC_DAIFMT_RIGHT_J: + break; + case SND_SOC_DAIFMT_LEFT_J: + iface |= 0x1; + break; + default: + return -EINVAL; + } + + switch (fmt & SND_SOC_DAIFMT_INV_MASK) { + case SND_SOC_DAIFMT_NB_NF: + break; + case SND_SOC_DAIFMT_IB_IF: + iface |= 0xc; + break; + case SND_SOC_DAIFMT_IB_NF: + iface |= 0x8; + break; + case SND_SOC_DAIFMT_NB_IF: + iface |= 0x4; + break; + default: + return -EINVAL; + } + + snd_soc_update_bits(codec, WM8770_IFACECTRL, 0xf, iface); + snd_soc_update_bits(codec, WM8770_MSTRCTRL, 0x100, master); + + return 0; +} + +static const int mclk_ratios[] = { + 128, + 192, + 256, + 384, + 512, + 768 +}; + +static int wm8770_hw_params(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params, + struct snd_soc_dai *dai) +{ + struct snd_soc_codec *codec; + struct wm8770_priv *wm8770; + int i; + int iface; + int shift; + int ratio; + + codec = dai->codec; + wm8770 = snd_soc_codec_get_drvdata(codec); + + iface = 0; + switch (params_format(params)) { + case SNDRV_PCM_FORMAT_S16_LE: + break; + case SNDRV_PCM_FORMAT_S20_3LE: + iface |= 0x10; + break; + case SNDRV_PCM_FORMAT_S24_LE: + iface |= 0x20; + break; + case SNDRV_PCM_FORMAT_S32_LE: + iface |= 0x30; + break; + } + + switch (substream->stream) { + case SNDRV_PCM_STREAM_PLAYBACK: + i = 0; + shift = 4; + break; + case SNDRV_PCM_STREAM_CAPTURE: + i = 2; + shift = 0; + break; + default: + return -EINVAL; + } + + /* Only need to set MCLK/LRCLK ratio if we're master */ + if (snd_soc_read(codec, WM8770_MSTRCTRL) & 0x100) { + for (; i < ARRAY_SIZE(mclk_ratios); ++i) { + ratio = wm8770->sysclk / params_rate(params); + if (ratio == mclk_ratios[i]) + break; + } + + if (i == ARRAY_SIZE(mclk_ratios)) { + dev_err(codec->dev, + "Unable to configure MCLK ratio %d/%d\n", + wm8770->sysclk, params_rate(params)); + return -EINVAL; + } + + dev_dbg(codec->dev, "MCLK is %dfs\n", mclk_ratios[i]); + + snd_soc_update_bits(codec, WM8770_MSTRCTRL, 0x7 << shift, + i << shift); + } + + snd_soc_update_bits(codec, WM8770_IFACECTRL, 0x30, iface); + + return 0; +} + +static int wm8770_mute(struct snd_soc_dai *dai, int mute) +{ + struct snd_soc_codec *codec; + + codec = dai->codec; + return snd_soc_update_bits(codec, WM8770_DACMUTE, 0x10, + !!mute << 4); +} + +static int wm8770_set_sysclk(struct snd_soc_dai *dai, + int clk_id, unsigned int freq, int dir) +{ + struct snd_soc_codec *codec; + struct wm8770_priv *wm8770; + + codec = dai->codec; + wm8770 = snd_soc_codec_get_drvdata(codec); + wm8770->sysclk = freq; + return 0; +} + +static void wm8770_sync_cache(struct snd_soc_codec *codec) +{ + int i; + u16 *cache; + + if (!codec->cache_sync) + return; + + codec->cache_only = 0; + cache = codec->reg_cache; + for (i = 0; i < codec->driver->reg_cache_size; i++) { + if (i == WM8770_RESET || cache[i] == wm8770_reg_defs[i]) + continue; + snd_soc_write(codec, i, cache[i]); + } + codec->cache_sync = 0; +} + +static int wm8770_set_bias_level(struct snd_soc_codec *codec, + enum snd_soc_bias_level level) +{ + int ret; + struct wm8770_priv *wm8770; + + wm8770 = snd_soc_codec_get_drvdata(codec); + + switch (level) { + case SND_SOC_BIAS_ON: + break; + case SND_SOC_BIAS_PREPARE: + break; + case SND_SOC_BIAS_STANDBY: + if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) { + ret = regulator_bulk_enable(ARRAY_SIZE(wm8770->supplies), + wm8770->supplies); + if (ret) { + dev_err(codec->dev, + "Failed to enable supplies: %d\n", + ret); + return ret; + } + wm8770_sync_cache(codec); + /* global powerup */ + snd_soc_write(codec, WM8770_PWDNCTRL, 0); + } + break; + case SND_SOC_BIAS_OFF: + /* global powerdown */ + snd_soc_write(codec, WM8770_PWDNCTRL, 1); + regulator_bulk_disable(ARRAY_SIZE(wm8770->supplies), + wm8770->supplies); + break; + } + + codec->dapm.bias_level = level; + return 0; +} + +#define WM8770_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \ + SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE) + +static struct snd_soc_dai_ops wm8770_dai_ops = { + .digital_mute = wm8770_mute, + .hw_params = wm8770_hw_params, + .set_fmt = wm8770_set_fmt, + .set_sysclk = wm8770_set_sysclk, +}; + +static struct snd_soc_dai_driver wm8770_dai = { + .name = "wm8770-hifi", + .playback = { + .stream_name = "Playback", + .channels_min = 2, + .channels_max = 2, + .rates = SNDRV_PCM_RATE_8000_192000, + .formats = WM8770_FORMATS + }, + .capture = { + .stream_name = "Capture", + .channels_min = 2, + .channels_max = 2, + .rates = SNDRV_PCM_RATE_8000_96000, + .formats = WM8770_FORMATS + }, + .ops = &wm8770_dai_ops, + .symmetric_rates = 1 +}; + +#ifdef CONFIG_PM +static int wm8770_suspend(struct snd_soc_codec *codec, pm_message_t state) +{ + wm8770_set_bias_level(codec, SND_SOC_BIAS_OFF); + return 0; +} + +static int wm8770_resume(struct snd_soc_codec *codec) +{ + wm8770_set_bias_level(codec, SND_SOC_BIAS_STANDBY); + return 0; +} +#else +#define wm8770_suspend NULL +#define wm8770_resume NULL +#endif + +static int wm8770_probe(struct snd_soc_codec *codec) +{ + struct wm8770_priv *wm8770; + int ret; + int i; + + wm8770 = snd_soc_codec_get_drvdata(codec); + wm8770->codec = codec; + + codec->dapm.idle_bias_off = 1; + + ret = snd_soc_codec_set_cache_io(codec, 7, 9, wm8770->control_type); + if (ret < 0) { + dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret); + return ret; + } + + for (i = 0; i < ARRAY_SIZE(wm8770->supplies); i++) + wm8770->supplies[i].supply = wm8770_supply_names[i]; + + ret = regulator_bulk_get(codec->dev, ARRAY_SIZE(wm8770->supplies), + wm8770->supplies); + if (ret) { + dev_err(codec->dev, "Failed to request supplies: %d\n", ret); + return ret; + } + + wm8770->disable_nb[0].notifier_call = wm8770_regulator_event_0; + wm8770->disable_nb[1].notifier_call = wm8770_regulator_event_1; + wm8770->disable_nb[2].notifier_call = wm8770_regulator_event_2; + + /* This should really be moved into the regulator core */ + for (i = 0; i < ARRAY_SIZE(wm8770->supplies); i++) { + ret = regulator_register_notifier(wm8770->supplies[i].consumer, + &wm8770->disable_nb[i]); + if (ret) { + dev_err(codec->dev, + "Failed to register regulator notifier: %d\n", + ret); + } + } + + ret = regulator_bulk_enable(ARRAY_SIZE(wm8770->supplies), + wm8770->supplies); + if (ret) { + dev_err(codec->dev, "Failed to enable supplies: %d\n", ret); + goto err_reg_get; + } + + ret = wm8770_reset(codec); + if (ret < 0) { + dev_err(codec->dev, "Failed to issue reset: %d\n", ret); + goto err_reg_enable; + } + + wm8770_set_bias_level(codec, SND_SOC_BIAS_STANDBY); + + /* latch the volume update bits */ + snd_soc_update_bits(codec, WM8770_MSDIGVOL, 0x100, 0x100); + snd_soc_update_bits(codec, WM8770_MSALGVOL, 0x100, 0x100); + snd_soc_update_bits(codec, WM8770_VOUT1RVOL, 0x100, 0x100); + snd_soc_update_bits(codec, WM8770_VOUT2RVOL, 0x100, 0x100); + snd_soc_update_bits(codec, WM8770_VOUT3RVOL, 0x100, 0x100); + snd_soc_update_bits(codec, WM8770_VOUT4RVOL, 0x100, 0x100); + snd_soc_update_bits(codec, WM8770_DAC1RVOL, 0x100, 0x100); + snd_soc_update_bits(codec, WM8770_DAC2RVOL, 0x100, 0x100); + snd_soc_update_bits(codec, WM8770_DAC3RVOL, 0x100, 0x100); + snd_soc_update_bits(codec, WM8770_DAC4RVOL, 0x100, 0x100); + + /* mute all DACs */ + snd_soc_update_bits(codec, WM8770_DACMUTE, 0x10, 0x10); + + snd_soc_add_controls(codec, wm8770_snd_controls, + ARRAY_SIZE(wm8770_snd_controls)); + snd_soc_dapm_new_controls(&codec->dapm, wm8770_dapm_widgets, + ARRAY_SIZE(wm8770_dapm_widgets)); + snd_soc_dapm_add_routes(&codec->dapm, wm8770_intercon, + ARRAY_SIZE(wm8770_intercon)); + return 0; + +err_reg_enable: + regulator_bulk_disable(ARRAY_SIZE(wm8770->supplies), wm8770->supplies); +err_reg_get: + regulator_bulk_free(ARRAY_SIZE(wm8770->supplies), wm8770->supplies); + return ret; +} + +static int wm8770_remove(struct snd_soc_codec *codec) +{ + struct wm8770_priv *wm8770; + int i; + + wm8770 = snd_soc_codec_get_drvdata(codec); + wm8770_set_bias_level(codec, SND_SOC_BIAS_OFF); + + for (i = 0; i < ARRAY_SIZE(wm8770->supplies); ++i) + regulator_unregister_notifier(wm8770->supplies[i].consumer, + &wm8770->disable_nb[i]); + regulator_bulk_free(ARRAY_SIZE(wm8770->supplies), wm8770->supplies); + return 0; +} + +static struct snd_soc_codec_driver soc_codec_dev_wm8770 = { + .probe = wm8770_probe, + .remove = wm8770_remove, + .suspend = wm8770_suspend, + .resume = wm8770_resume, + .set_bias_level = wm8770_set_bias_level, + .reg_cache_size = ARRAY_SIZE(wm8770_reg_defs), + .reg_word_size = sizeof (u16), + .reg_cache_default = wm8770_reg_defs +}; + +#if defined(CONFIG_SPI_MASTER) +static int __devinit wm8770_spi_probe(struct spi_device *spi) +{ + struct wm8770_priv *wm8770; + int ret; + + wm8770 = kzalloc(sizeof(struct wm8770_priv), GFP_KERNEL); + if (!wm8770) + return -ENOMEM; + + wm8770->control_type = SND_SOC_SPI; + spi_set_drvdata(spi, wm8770); + + ret = snd_soc_register_codec(&spi->dev, + &soc_codec_dev_wm8770, &wm8770_dai, 1); + if (ret < 0) + kfree(wm8770); + return ret; +} + +static int __devexit wm8770_spi_remove(struct spi_device *spi) +{ + snd_soc_unregister_codec(&spi->dev); + kfree(spi_get_drvdata(spi)); + return 0; +} + +static struct spi_driver wm8770_spi_driver = { + .driver = { + .name = "wm8770", + .owner = THIS_MODULE, + }, + .probe = wm8770_spi_probe, + .remove = __devexit_p(wm8770_spi_remove) +}; +#endif + +static int __init wm8770_modinit(void) +{ + int ret = 0; + +#if defined(CONFIG_SPI_MASTER) + ret = spi_register_driver(&wm8770_spi_driver); + if (ret) { + printk(KERN_ERR "Failed to register wm8770 SPI driver: %d\n", + ret); + } +#endif + return ret; +} +module_init(wm8770_modinit); + +static void __exit wm8770_exit(void) +{ +#if defined(CONFIG_SPI_MASTER) + spi_unregister_driver(&wm8770_spi_driver); +#endif +} +module_exit(wm8770_exit); + +MODULE_DESCRIPTION("ASoC WM8770 driver"); +MODULE_AUTHOR("Dimitris Papastamos "); +MODULE_LICENSE("GPL"); diff --git a/sound/soc/codecs/wm8770.h b/sound/soc/codecs/wm8770.h new file mode 100644 index 000000000000..5f1b3bda6cc8 --- /dev/null +++ b/sound/soc/codecs/wm8770.h @@ -0,0 +1,51 @@ +/* + * wm8770.h -- WM8770 ASoC driver + * + * Copyright 2010 Wolfson Microelectronics plc + * + * Author: Dimitris Papastamos + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef _WM8770_H +#define _WM8770_H + +/* Registers */ +#define WM8770_VOUT1LVOL 0 +#define WM8770_VOUT1RVOL 0x1 +#define WM8770_VOUT2LVOL 0x2 +#define WM8770_VOUT2RVOL 0x3 +#define WM8770_VOUT3LVOL 0x4 +#define WM8770_VOUT3RVOL 0x5 +#define WM8770_VOUT4LVOL 0x6 +#define WM8770_VOUT4RVOL 0x7 +#define WM8770_MSALGVOL 0x8 +#define WM8770_DAC1LVOL 0x9 +#define WM8770_DAC1RVOL 0xa +#define WM8770_DAC2LVOL 0xb +#define WM8770_DAC2RVOL 0xc +#define WM8770_DAC3LVOL 0xd +#define WM8770_DAC3RVOL 0xe +#define WM8770_DAC4LVOL 0xf +#define WM8770_DAC4RVOL 0x10 +#define WM8770_MSDIGVOL 0x11 +#define WM8770_DACPHASE 0x12 +#define WM8770_DACCTRL1 0x13 +#define WM8770_DACMUTE 0x14 +#define WM8770_DACCTRL2 0x15 +#define WM8770_IFACECTRL 0x16 +#define WM8770_MSTRCTRL 0x17 +#define WM8770_PWDNCTRL 0x18 +#define WM8770_ADCLCTRL 0x19 +#define WM8770_ADCRCTRL 0x1a +#define WM8770_ADCMUX 0x1b +#define WM8770_OUTMUX1 0x1c +#define WM8770_OUTMUX2 0x1d +#define WM8770_RESET 0x31 + +#define WM8770_CACHEREGNUM 0x20 + +#endif -- cgit v1.2.2 From 0aa34b16f9f34a81bd50c097f1953877614220db Mon Sep 17 00:00:00 2001 From: Dimitris Papastamos Date: Mon, 8 Nov 2010 10:41:53 +0000 Subject: ASoC: Remove unneeded use of address-of operator There is no need to use '&' in this case. Either way, if a is an array of some type, then a == &a == &a[0]. Signed-off-by: Dimitris Papastamos Acked-by: Liam Girdwood Signed-off-by: Mark Brown --- sound/soc/codecs/wm8580.c | 2 +- sound/soc/codecs/wm8741.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'sound/soc/codecs') diff --git a/sound/soc/codecs/wm8580.c b/sound/soc/codecs/wm8580.c index dfd1dbd71f1d..36c035bf4e42 100644 --- a/sound/soc/codecs/wm8580.c +++ b/sound/soc/codecs/wm8580.c @@ -906,7 +906,7 @@ static struct snd_soc_codec_driver soc_codec_dev_wm8580 = { .set_bias_level = wm8580_set_bias_level, .reg_cache_size = ARRAY_SIZE(wm8580_reg), .reg_word_size = sizeof(u16), - .reg_cache_default = &wm8580_reg, + .reg_cache_default = wm8580_reg, }; #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) diff --git a/sound/soc/codecs/wm8741.c b/sound/soc/codecs/wm8741.c index 43c49dfc9928..2543a26513fb 100644 --- a/sound/soc/codecs/wm8741.c +++ b/sound/soc/codecs/wm8741.c @@ -456,7 +456,7 @@ static struct snd_soc_codec_driver soc_codec_dev_wm8741 = { .resume = wm8741_resume, .reg_cache_size = ARRAY_SIZE(wm8741_reg_defaults), .reg_word_size = sizeof(u16), - .reg_cache_default = &wm8741_reg_defaults, + .reg_cache_default = wm8741_reg_defaults, }; #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) -- cgit v1.2.2 From 0656f6cf6c394ede78657595dd5a8ca7a1e64853 Mon Sep 17 00:00:00 2001 From: Jarkko Nikula Date: Mon, 8 Nov 2010 10:57:57 +0200 Subject: ASoC: tpa6130a2: Revisit power-up sequence There are no known problems with current power-up sequence which first sets the /shutdown pin high and then enables the supply. However, swap the order so that the device is kept in shutdown/reset mode during the supply voltage transition since slowly rising voltages can usually cause problems if the device is not kept in reset. Signed-off-by: Jarkko Nikula Cc: Peter Ujfalusi Acked-by: Peter Ujfalusi Acked-by: Mark Brown Signed-off-by: Liam Girdwood --- sound/soc/codecs/tpa6130a2.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'sound/soc/codecs') diff --git a/sound/soc/codecs/tpa6130a2.c b/sound/soc/codecs/tpa6130a2.c index 329acc1a2074..e55317b35786 100644 --- a/sound/soc/codecs/tpa6130a2.c +++ b/sound/soc/codecs/tpa6130a2.c @@ -126,9 +126,6 @@ static int tpa6130a2_power(int power) mutex_lock(&data->mutex); if (power) { - /* Power on */ - if (data->power_gpio >= 0) - gpio_set_value(data->power_gpio, 1); ret = regulator_enable(data->supply); if (ret != 0) { @@ -136,6 +133,9 @@ static int tpa6130a2_power(int power) "Failed to enable supply: %d\n", ret); goto exit; } + /* Power on */ + if (data->power_gpio >= 0) + gpio_set_value(data->power_gpio, 1); data->power_state = 1; ret = tpa6130a2_initialize(); -- cgit v1.2.2 From cb2b3cf1fedd31916b7c64d61e2d20d23bd3681a Mon Sep 17 00:00:00 2001 From: Mark Brown Date: Thu, 11 Nov 2010 17:18:01 +0000 Subject: ASoC: Reset WM8962 with default ID value The value makes no odds and it makes life easier with caches. Signed-off-by: Mark Brown Acked-by: Liam Girdwood --- sound/soc/codecs/wm8962.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'sound/soc/codecs') diff --git a/sound/soc/codecs/wm8962.c b/sound/soc/codecs/wm8962.c index 80986105f52e..e021866f5a85 100644 --- a/sound/soc/codecs/wm8962.c +++ b/sound/soc/codecs/wm8962.c @@ -1958,7 +1958,7 @@ static int wm8962_readable_register(unsigned int reg) static int wm8962_reset(struct snd_soc_codec *codec) { - return snd_soc_write(codec, WM8962_SOFTWARE_RESET, 0); + return snd_soc_write(codec, WM8962_SOFTWARE_RESET, 0x6243); } static const DECLARE_TLV_DB_SCALE(inpga_tlv, -2325, 75, 0); -- cgit v1.2.2 From ef995e3a91e290684f24696e1d2e8767a2a2ebb6 Mon Sep 17 00:00:00 2001 From: Joe Perches Date: Mon, 15 Nov 2010 09:09:17 -0800 Subject: ASoC: Remove unnecessary semicolons Signed-off-by: Joe Perches Acked-by: Liam Girdwood Signed-off-by: Mark Brown --- sound/soc/codecs/wm8904.c | 2 +- sound/soc/codecs/wm8940.c | 1 - sound/soc/codecs/wm8993.c | 2 +- sound/soc/codecs/wm_hubs.c | 2 +- 4 files changed, 3 insertions(+), 4 deletions(-) (limited to 'sound/soc/codecs') diff --git a/sound/soc/codecs/wm8904.c b/sound/soc/codecs/wm8904.c index be90399c1cb4..5e57bd2483e8 100644 --- a/sound/soc/codecs/wm8904.c +++ b/sound/soc/codecs/wm8904.c @@ -1591,7 +1591,7 @@ static int wm8904_hw_params(struct snd_pcm_substream *substream, - wm8904->fs); for (i = 1; i < ARRAY_SIZE(clk_sys_rates); i++) { cur_val = abs((wm8904->sysclk_rate / - clk_sys_rates[i].ratio) - wm8904->fs);; + clk_sys_rates[i].ratio) - wm8904->fs); if (cur_val < best_val) { best = i; best_val = cur_val; diff --git a/sound/soc/codecs/wm8940.c b/sound/soc/codecs/wm8940.c index c2def1b01ae0..caed0849e005 100644 --- a/sound/soc/codecs/wm8940.c +++ b/sound/soc/codecs/wm8940.c @@ -736,7 +736,6 @@ static int wm8940_probe(struct snd_soc_codec *codec) return ret; return ret; -; } static int wm8940_remove(struct snd_soc_codec *codec) diff --git a/sound/soc/codecs/wm8993.c b/sound/soc/codecs/wm8993.c index bcc54be572ce..991d90c79dd2 100644 --- a/sound/soc/codecs/wm8993.c +++ b/sound/soc/codecs/wm8993.c @@ -1227,7 +1227,7 @@ static int wm8993_hw_params(struct snd_pcm_substream *substream, - wm8993->fs); for (i = 1; i < ARRAY_SIZE(clk_sys_rates); i++) { cur_val = abs((wm8993->sysclk_rate / - clk_sys_rates[i].ratio) - wm8993->fs);; + clk_sys_rates[i].ratio) - wm8993->fs); if (cur_val < best_val) { best = i; best_val = cur_val; diff --git a/sound/soc/codecs/wm_hubs.c b/sound/soc/codecs/wm_hubs.c index 8aff0efe72f5..422c7fb383eb 100644 --- a/sound/soc/codecs/wm_hubs.c +++ b/sound/soc/codecs/wm_hubs.c @@ -119,7 +119,7 @@ static void calibrate_dc_servo(struct snd_soc_codec *codec) switch (hubs->dcs_readback_mode) { case 0: reg_l = snd_soc_read(codec, WM8993_DC_SERVO_READBACK_1) - & WM8993_DCS_INTEG_CHAN_0_MASK;; + & WM8993_DCS_INTEG_CHAN_0_MASK; reg_r = snd_soc_read(codec, WM8993_DC_SERVO_READBACK_2) & WM8993_DCS_INTEG_CHAN_1_MASK; break; -- cgit v1.2.2 From af353d8a134d6147e29a3371015d2eef8d7f0657 Mon Sep 17 00:00:00 2001 From: Axel Lin Date: Tue, 16 Nov 2010 16:08:00 +0800 Subject: ASoC: Fix incorrect kfree in ad1836_probe error path We allocated memory for ad1836 in ad1836_spi_probe, and will free the memory in either ad1836_spi_probe error path or ad1836_spi_remove. Thus we should not call kfree(ad1836) in ad1836_probe, otherwise we have double free of ad1836. Signed-off-by: Axel Lin Acked-by: Liam Girdwood Signed-off-by: Mark Brown --- sound/soc/codecs/ad1836.c | 1 - 1 file changed, 1 deletion(-) (limited to 'sound/soc/codecs') diff --git a/sound/soc/codecs/ad1836.c b/sound/soc/codecs/ad1836.c index c71b05ddd752..e5d3db950a08 100644 --- a/sound/soc/codecs/ad1836.c +++ b/sound/soc/codecs/ad1836.c @@ -228,7 +228,6 @@ static int ad1836_probe(struct snd_soc_codec *codec) if (ret < 0) { dev_err(codec->dev, "failed to set cache I/O: %d\n", ret); - kfree(ad1836); return ret; } -- cgit v1.2.2 From 50d0ac2e1e98efa89f6dc167977b1a0d46d5e48e Mon Sep 17 00:00:00 2001 From: Axel Lin Date: Tue, 16 Nov 2010 16:08:51 +0800 Subject: ASoC: Fix incorrect kfree in ad193x_probe error path We allocated memory for ad193x in ad193x_spi_probe, and will free the memory in either ad193x_spi_probe error path or ad193x_spi_remove. Thus we should not call kfree(ad193x) in ad193x_probe, otherwise we have double free of ad193x. Signed-off-by: Axel Lin Acked-by: Liam Girdwood Signed-off-by: Mark Brown --- sound/soc/codecs/ad193x.c | 1 - 1 file changed, 1 deletion(-) (limited to 'sound/soc/codecs') diff --git a/sound/soc/codecs/ad193x.c b/sound/soc/codecs/ad193x.c index dc105d8aaa0f..fd3e659f90b1 100644 --- a/sound/soc/codecs/ad193x.c +++ b/sound/soc/codecs/ad193x.c @@ -364,7 +364,6 @@ static int ad193x_probe(struct snd_soc_codec *codec) if (ret < 0) { dev_err(codec->dev, "failed to set cache I/O: %d\n", ret); - kfree(ad193x); return ret; } -- cgit v1.2.2 From 4ab867d276b83582f15c61270de1cc178df95659 Mon Sep 17 00:00:00 2001 From: Axel Lin Date: Tue, 16 Nov 2010 16:09:41 +0800 Subject: ASoC: Fix incorrect kfree in aic3x_probe error path We allocated memory for aic3x in aic3x_i2c_probe, and will free the memory in either aic3x_i2c_probe error path or aic3x_i2c_remove. Thus we should not call kfree(aic3x) in aic3x_probe, otherwise we have double free of aic3x. Signed-off-by: Axel Lin Acked-by: Liam Girdwood Signed-off-by: Mark Brown --- sound/soc/codecs/tlv320aic3x.c | 1 - 1 file changed, 1 deletion(-) (limited to 'sound/soc/codecs') diff --git a/sound/soc/codecs/tlv320aic3x.c b/sound/soc/codecs/tlv320aic3x.c index 6173c2b4c364..df726a5066e8 100644 --- a/sound/soc/codecs/tlv320aic3x.c +++ b/sound/soc/codecs/tlv320aic3x.c @@ -1419,7 +1419,6 @@ err_get: if (aic3x->gpio_reset >= 0) gpio_free(aic3x->gpio_reset); err_gpio: - kfree(aic3x); return ret; } -- cgit v1.2.2 From 01cbea3293929acecef6785b7ea5be547dc039bc Mon Sep 17 00:00:00 2001 From: Axel Lin Date: Tue, 16 Nov 2010 16:10:41 +0800 Subject: ASoC: Fix incorrect kfree in wm8731_probe error path We allocated memory for wm8731 in wm8731_spi_probe / wm8731_i2c_probe, and will free the memory in either wm8731_spi_probe / wm8731_i2c_probe error path or wm8731_spi_remove / wm8731_i2c_remove. Thus we should not call kfree(wm8731) in wm8731_probe, otherwise we have double free of wm8731. Signed-off-by: Axel Lin Acked-by: Liam Girdwood Signed-off-by: Mark Brown --- sound/soc/codecs/wm8731.c | 1 - 1 file changed, 1 deletion(-) (limited to 'sound/soc/codecs') diff --git a/sound/soc/codecs/wm8731.c b/sound/soc/codecs/wm8731.c index 95ade3245056..4b709589e26c 100644 --- a/sound/soc/codecs/wm8731.c +++ b/sound/soc/codecs/wm8731.c @@ -543,7 +543,6 @@ err_regulator_enable: err_regulator_get: regulator_bulk_free(ARRAY_SIZE(wm8731->supplies), wm8731->supplies); - kfree(wm8731); return ret; } -- cgit v1.2.2 From ce0df3d79a1b305cb39ea15a07235b5a6c3435b6 Mon Sep 17 00:00:00 2001 From: Axel Lin Date: Tue, 16 Nov 2010 16:11:37 +0800 Subject: ASoC: Fix incorrect kfree in wm8962_probe error path We allocated memory for wm8962 in wm8962_i2c_probe, and will free the memory in either wm8962_i2c_probe error path or wm8962_i2c_remove. Thus we should not call kfree(wm8962) in wm8962_probe, otherwise we have double free of wm8962. Signed-off-by: Axel Lin Acked-by: Liam Girdwood Signed-off-by: Mark Brown --- sound/soc/codecs/wm8962.c | 1 - 1 file changed, 1 deletion(-) (limited to 'sound/soc/codecs') diff --git a/sound/soc/codecs/wm8962.c b/sound/soc/codecs/wm8962.c index e021866f5a85..9f6beca951c4 100644 --- a/sound/soc/codecs/wm8962.c +++ b/sound/soc/codecs/wm8962.c @@ -3874,7 +3874,6 @@ err_enable: err_get: regulator_bulk_free(ARRAY_SIZE(wm8962->supplies), wm8962->supplies); err: - kfree(wm8962); return ret; } -- cgit v1.2.2 From 96b101efae0ab68b6510fdbb30384849d211da2c Mon Sep 17 00:00:00 2001 From: Mark Brown Date: Thu, 18 Nov 2010 15:49:38 +0000 Subject: ASoC: Provide ADC left/right channel source selection on WM8994 Allow the application to choose if the ADC data presented on the left and right channels is sourced from the internal left or right channel. This allows a mono recording to be presented as stereo on the external bus. Signed-off-by: Mark Brown Acked-by: Liam Girdwood --- sound/soc/codecs/wm8994.c | 27 ++++++++++++++++++++++----- 1 file changed, 22 insertions(+), 5 deletions(-) (limited to 'sound/soc/codecs') diff --git a/sound/soc/codecs/wm8994.c b/sound/soc/codecs/wm8994.c index bfdb7daeed2d..7d2f488de6a7 100644 --- a/sound/soc/codecs/wm8994.c +++ b/sound/soc/codecs/wm8994.c @@ -2069,21 +2069,33 @@ static int wm8994_get_retune_mobile_enum(struct snd_kcontrol *kcontrol, return 0; } -static const char *aifdac_src_text[] = { +static const char *aif_chan_src_text[] = { "Left", "Right" }; +static const struct soc_enum aif1adcl_src = + SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_1, 15, 2, aif_chan_src_text); + +static const struct soc_enum aif1adcr_src = + SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_1, 14, 2, aif_chan_src_text); + +static const struct soc_enum aif2adcl_src = + SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_1, 15, 2, aif_chan_src_text); + +static const struct soc_enum aif2adcr_src = + SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_1, 14, 2, aif_chan_src_text); + static const struct soc_enum aif1dacl_src = - SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_2, 15, 2, aifdac_src_text); + SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_2, 15, 2, aif_chan_src_text); static const struct soc_enum aif1dacr_src = - SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_2, 14, 2, aifdac_src_text); + SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_2, 14, 2, aif_chan_src_text); static const struct soc_enum aif2dacl_src = - SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_2, 15, 2, aifdac_src_text); + SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_2, 15, 2, aif_chan_src_text); static const struct soc_enum aif2dacr_src = - SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_2, 14, 2, aifdac_src_text); + SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_2, 14, 2, aif_chan_src_text); static const struct snd_kcontrol_new wm8994_snd_controls[] = { SOC_DOUBLE_R_TLV("AIF1ADC1 Volume", WM8994_AIF1_ADC1_LEFT_VOLUME, @@ -2096,6 +2108,11 @@ SOC_DOUBLE_R_TLV("AIF2ADC Volume", WM8994_AIF2_ADC_LEFT_VOLUME, WM8994_AIF2_ADC_RIGHT_VOLUME, 1, 119, 0, digital_tlv), +SOC_ENUM("AIF1ADCL Source", aif1adcl_src), +SOC_ENUM("AIF1ADCR Source", aif1adcr_src), +SOC_ENUM("AIF2ADCL Source", aif1adcl_src), +SOC_ENUM("AIF2ADCR Source", aif1adcr_src), + SOC_ENUM("AIF1DACL Source", aif1dacl_src), SOC_ENUM("AIF1DACR Source", aif1dacr_src), SOC_ENUM("AIF2DACL Source", aif1dacl_src), -- cgit v1.2.2 From 7b306dae22ca377ea0020261ef13aea85b8f5f3f Mon Sep 17 00:00:00 2001 From: Mark Brown Date: Tue, 16 Nov 2010 20:11:40 +0000 Subject: ASoC: Move WM8994 read/write access data into separate file Makes the WM8994 driver file itself substantially smaller. Signed-off-by: Mark Brown Acked-by: Liam Girdwood --- sound/soc/codecs/Makefile | 2 +- sound/soc/codecs/wm8994-tables.c | 1575 +++++++++++++++++++++++++++++++++++++ sound/soc/codecs/wm8994.c | 1582 +------------------------------------- sound/soc/codecs/wm8994.h | 9 + 4 files changed, 1588 insertions(+), 1580 deletions(-) create mode 100644 sound/soc/codecs/wm8994-tables.c (limited to 'sound/soc/codecs') diff --git a/sound/soc/codecs/Makefile b/sound/soc/codecs/Makefile index 42f185d233f3..3469fab2863a 100644 --- a/sound/soc/codecs/Makefile +++ b/sound/soc/codecs/Makefile @@ -60,7 +60,7 @@ snd-soc-wm8985-objs := wm8985.o snd-soc-wm8988-objs := wm8988.o snd-soc-wm8990-objs := wm8990.o snd-soc-wm8993-objs := wm8993.o -snd-soc-wm8994-objs := wm8994.o +snd-soc-wm8994-objs := wm8994.o wm8994-tables.o snd-soc-wm9081-objs := wm9081.o snd-soc-wm9705-objs := wm9705.o snd-soc-wm9712-objs := wm9712.o diff --git a/sound/soc/codecs/wm8994-tables.c b/sound/soc/codecs/wm8994-tables.c new file mode 100644 index 000000000000..7b935387aeef --- /dev/null +++ b/sound/soc/codecs/wm8994-tables.c @@ -0,0 +1,1575 @@ +#include "wm8994.h" + +const struct wm8994_access_mask wm8994_access_masks[WM8994_CACHE_SIZE] = { + { 0xFFFF, 0xFFFF }, /* R0 - Software Reset */ + { 0x3B37, 0x3B37 }, /* R1 - Power Management (1) */ + { 0x6BF0, 0x6BF0 }, /* R2 - Power Management (2) */ + { 0x3FF0, 0x3FF0 }, /* R3 - Power Management (3) */ + { 0x3F3F, 0x3F3F }, /* R4 - Power Management (4) */ + { 0x3F0F, 0x3F0F }, /* R5 - Power Management (5) */ + { 0x003F, 0x003F }, /* R6 - Power Management (6) */ + { 0x0000, 0x0000 }, /* R7 */ + { 0x0000, 0x0000 }, /* R8 */ + { 0x0000, 0x0000 }, /* R9 */ + { 0x0000, 0x0000 }, /* R10 */ + { 0x0000, 0x0000 }, /* R11 */ + { 0x0000, 0x0000 }, /* R12 */ + { 0x0000, 0x0000 }, /* R13 */ + { 0x0000, 0x0000 }, /* R14 */ + { 0x0000, 0x0000 }, /* R15 */ + { 0x0000, 0x0000 }, /* R16 */ + { 0x0000, 0x0000 }, /* R17 */ + { 0x0000, 0x0000 }, /* R18 */ + { 0x0000, 0x0000 }, /* R19 */ + { 0x0000, 0x0000 }, /* R20 */ + { 0x01C0, 0x01C0 }, /* R21 - Input Mixer (1) */ + { 0x0000, 0x0000 }, /* R22 */ + { 0x0000, 0x0000 }, /* R23 */ + { 0x00DF, 0x01DF }, /* R24 - Left Line Input 1&2 Volume */ + { 0x00DF, 0x01DF }, /* R25 - Left Line Input 3&4 Volume */ + { 0x00DF, 0x01DF }, /* R26 - Right Line Input 1&2 Volume */ + { 0x00DF, 0x01DF }, /* R27 - Right Line Input 3&4 Volume */ + { 0x00FF, 0x01FF }, /* R28 - Left Output Volume */ + { 0x00FF, 0x01FF }, /* R29 - Right Output Volume */ + { 0x0077, 0x0077 }, /* R30 - Line Outputs Volume */ + { 0x0030, 0x0030 }, /* R31 - HPOUT2 Volume */ + { 0x00FF, 0x01FF }, /* R32 - Left OPGA Volume */ + { 0x00FF, 0x01FF }, /* R33 - Right OPGA Volume */ + { 0x007F, 0x007F }, /* R34 - SPKMIXL Attenuation */ + { 0x017F, 0x017F }, /* R35 - SPKMIXR Attenuation */ + { 0x003F, 0x003F }, /* R36 - SPKOUT Mixers */ + { 0x003F, 0x003F }, /* R37 - ClassD */ + { 0x00FF, 0x01FF }, /* R38 - Speaker Volume Left */ + { 0x00FF, 0x01FF }, /* R39 - Speaker Volume Right */ + { 0x00FF, 0x00FF }, /* R40 - Input Mixer (2) */ + { 0x01B7, 0x01B7 }, /* R41 - Input Mixer (3) */ + { 0x01B7, 0x01B7 }, /* R42 - Input Mixer (4) */ + { 0x01C7, 0x01C7 }, /* R43 - Input Mixer (5) */ + { 0x01C7, 0x01C7 }, /* R44 - Input Mixer (6) */ + { 0x01FF, 0x01FF }, /* R45 - Output Mixer (1) */ + { 0x01FF, 0x01FF }, /* R46 - Output Mixer (2) */ + { 0x0FFF, 0x0FFF }, /* R47 - Output Mixer (3) */ + { 0x0FFF, 0x0FFF }, /* R48 - Output Mixer (4) */ + { 0x0FFF, 0x0FFF }, /* R49 - Output Mixer (5) */ + { 0x0FFF, 0x0FFF }, /* R50 - Output Mixer (6) */ + { 0x0038, 0x0038 }, /* R51 - HPOUT2 Mixer */ + { 0x0077, 0x0077 }, /* R52 - Line Mixer (1) */ + { 0x0077, 0x0077 }, /* R53 - Line Mixer (2) */ + { 0x03FF, 0x03FF }, /* R54 - Speaker Mixer */ + { 0x00C1, 0x00C1 }, /* R55 - Additional Control */ + { 0x00F0, 0x00F0 }, /* R56 - AntiPOP (1) */ + { 0x01EF, 0x01EF }, /* R57 - AntiPOP (2) */ + { 0x00FF, 0x00FF }, /* R58 - MICBIAS */ + { 0x000F, 0x000F }, /* R59 - LDO 1 */ + { 0x0007, 0x0007 }, /* R60 - LDO 2 */ + { 0x0000, 0x0000 }, /* R61 */ + { 0x0000, 0x0000 }, /* R62 */ + { 0x0000, 0x0000 }, /* R63 */ + { 0x0000, 0x0000 }, /* R64 */ + { 0x0000, 0x0000 }, /* R65 */ + { 0x0000, 0x0000 }, /* R66 */ + { 0x0000, 0x0000 }, /* R67 */ + { 0x0000, 0x0000 }, /* R68 */ + { 0x0000, 0x0000 }, /* R69 */ + { 0x0000, 0x0000 }, /* R70 */ + { 0x0000, 0x0000 }, /* R71 */ + { 0x0000, 0x0000 }, /* R72 */ + { 0x0000, 0x0000 }, /* R73 */ + { 0x0000, 0x0000 }, /* R74 */ + { 0x0000, 0x0000 }, /* R75 */ + { 0x8000, 0x8000 }, /* R76 - Charge Pump (1) */ + { 0x0000, 0x0000 }, /* R77 */ + { 0x0000, 0x0000 }, /* R78 */ + { 0x0000, 0x0000 }, /* R79 */ + { 0x0000, 0x0000 }, /* R80 */ + { 0x0301, 0x0301 }, /* R81 - Class W (1) */ + { 0x0000, 0x0000 }, /* R82 */ + { 0x0000, 0x0000 }, /* R83 */ + { 0x333F, 0x333F }, /* R84 - DC Servo (1) */ + { 0x0FEF, 0x0FEF }, /* R85 - DC Servo (2) */ + { 0x0000, 0x0000 }, /* R86 */ + { 0xFFFF, 0xFFFF }, /* R87 - DC Servo (4) */ + { 0x0333, 0x0000 }, /* R88 - DC Servo Readback */ + { 0x0000, 0x0000 }, /* R89 */ + { 0x0000, 0x0000 }, /* R90 */ + { 0x0000, 0x0000 }, /* R91 */ + { 0x0000, 0x0000 }, /* R92 */ + { 0x0000, 0x0000 }, /* R93 */ + { 0x0000, 0x0000 }, /* R94 */ + { 0x0000, 0x0000 }, /* R95 */ + { 0x00EE, 0x00EE }, /* R96 - Analogue HP (1) */ + { 0x0000, 0x0000 }, /* R97 */ + { 0x0000, 0x0000 }, /* R98 */ + { 0x0000, 0x0000 }, /* R99 */ + { 0x0000, 0x0000 }, /* R100 */ + { 0x0000, 0x0000 }, /* R101 */ + { 0x0000, 0x0000 }, /* R102 */ + { 0x0000, 0x0000 }, /* R103 */ + { 0x0000, 0x0000 }, /* R104 */ + { 0x0000, 0x0000 }, /* R105 */ + { 0x0000, 0x0000 }, /* R106 */ + { 0x0000, 0x0000 }, /* R107 */ + { 0x0000, 0x0000 }, /* R108 */ + { 0x0000, 0x0000 }, /* R109 */ + { 0x0000, 0x0000 }, /* R110 */ + { 0x0000, 0x0000 }, /* R111 */ + { 0x0000, 0x0000 }, /* R112 */ + { 0x0000, 0x0000 }, /* R113 */ + { 0x0000, 0x0000 }, /* R114 */ + { 0x0000, 0x0000 }, /* R115 */ + { 0x0000, 0x0000 }, /* R116 */ + { 0x0000, 0x0000 }, /* R117 */ + { 0x0000, 0x0000 }, /* R118 */ + { 0x0000, 0x0000 }, /* R119 */ + { 0x0000, 0x0000 }, /* R120 */ + { 0x0000, 0x0000 }, /* R121 */ + { 0x0000, 0x0000 }, /* R122 */ + { 0x0000, 0x0000 }, /* R123 */ + { 0x0000, 0x0000 }, /* R124 */ + { 0x0000, 0x0000 }, /* R125 */ + { 0x0000, 0x0000 }, /* R126 */ + { 0x0000, 0x0000 }, /* R127 */ + { 0x0000, 0x0000 }, /* R128 */ + { 0x0000, 0x0000 }, /* R129 */ + { 0x0000, 0x0000 }, /* R130 */ + { 0x0000, 0x0000 }, /* R131 */ + { 0x0000, 0x0000 }, /* R132 */ + { 0x0000, 0x0000 }, /* R133 */ + { 0x0000, 0x0000 }, /* R134 */ + { 0x0000, 0x0000 }, /* R135 */ + { 0x0000, 0x0000 }, /* R136 */ + { 0x0000, 0x0000 }, /* R137 */ + { 0x0000, 0x0000 }, /* R138 */ + { 0x0000, 0x0000 }, /* R139 */ + { 0x0000, 0x0000 }, /* R140 */ + { 0x0000, 0x0000 }, /* R141 */ + { 0x0000, 0x0000 }, /* R142 */ + { 0x0000, 0x0000 }, /* R143 */ + { 0x0000, 0x0000 }, /* R144 */ + { 0x0000, 0x0000 }, /* R145 */ + { 0x0000, 0x0000 }, /* R146 */ + { 0x0000, 0x0000 }, /* R147 */ + { 0x0000, 0x0000 }, /* R148 */ + { 0x0000, 0x0000 }, /* R149 */ + { 0x0000, 0x0000 }, /* R150 */ + { 0x0000, 0x0000 }, /* R151 */ + { 0x0000, 0x0000 }, /* R152 */ + { 0x0000, 0x0000 }, /* R153 */ + { 0x0000, 0x0000 }, /* R154 */ + { 0x0000, 0x0000 }, /* R155 */ + { 0x0000, 0x0000 }, /* R156 */ + { 0x0000, 0x0000 }, /* R157 */ + { 0x0000, 0x0000 }, /* R158 */ + { 0x0000, 0x0000 }, /* R159 */ + { 0x0000, 0x0000 }, /* R160 */ + { 0x0000, 0x0000 }, /* R161 */ + { 0x0000, 0x0000 }, /* R162 */ + { 0x0000, 0x0000 }, /* R163 */ + { 0x0000, 0x0000 }, /* R164 */ + { 0x0000, 0x0000 }, /* R165 */ + { 0x0000, 0x0000 }, /* R166 */ + { 0x0000, 0x0000 }, /* R167 */ + { 0x0000, 0x0000 }, /* R168 */ + { 0x0000, 0x0000 }, /* R169 */ + { 0x0000, 0x0000 }, /* R170 */ + { 0x0000, 0x0000 }, /* R171 */ + { 0x0000, 0x0000 }, /* R172 */ + { 0x0000, 0x0000 }, /* R173 */ + { 0x0000, 0x0000 }, /* R174 */ + { 0x0000, 0x0000 }, /* R175 */ + { 0x0000, 0x0000 }, /* R176 */ + { 0x0000, 0x0000 }, /* R177 */ + { 0x0000, 0x0000 }, /* R178 */ + { 0x0000, 0x0000 }, /* R179 */ + { 0x0000, 0x0000 }, /* R180 */ + { 0x0000, 0x0000 }, /* R181 */ + { 0x0000, 0x0000 }, /* R182 */ + { 0x0000, 0x0000 }, /* R183 */ + { 0x0000, 0x0000 }, /* R184 */ + { 0x0000, 0x0000 }, /* R185 */ + { 0x0000, 0x0000 }, /* R186 */ + { 0x0000, 0x0000 }, /* R187 */ + { 0x0000, 0x0000 }, /* R188 */ + { 0x0000, 0x0000 }, /* R189 */ + { 0x0000, 0x0000 }, /* R190 */ + { 0x0000, 0x0000 }, /* R191 */ + { 0x0000, 0x0000 }, /* R192 */ + { 0x0000, 0x0000 }, /* R193 */ + { 0x0000, 0x0000 }, /* R194 */ + { 0x0000, 0x0000 }, /* R195 */ + { 0x0000, 0x0000 }, /* R196 */ + { 0x0000, 0x0000 }, /* R197 */ + { 0x0000, 0x0000 }, /* R198 */ + { 0x0000, 0x0000 }, /* R199 */ + { 0x0000, 0x0000 }, /* R200 */ + { 0x0000, 0x0000 }, /* R201 */ + { 0x0000, 0x0000 }, /* R202 */ + { 0x0000, 0x0000 }, /* R203 */ + { 0x0000, 0x0000 }, /* R204 */ + { 0x0000, 0x0000 }, /* R205 */ + { 0x0000, 0x0000 }, /* R206 */ + { 0x0000, 0x0000 }, /* R207 */ + { 0x0000, 0x0000 }, /* R208 */ + { 0x0000, 0x0000 }, /* R209 */ + { 0x0000, 0x0000 }, /* R210 */ + { 0x0000, 0x0000 }, /* R211 */ + { 0x0000, 0x0000 }, /* R212 */ + { 0x0000, 0x0000 }, /* R213 */ + { 0x0000, 0x0000 }, /* R214 */ + { 0x0000, 0x0000 }, /* R215 */ + { 0x0000, 0x0000 }, /* R216 */ + { 0x0000, 0x0000 }, /* R217 */ + { 0x0000, 0x0000 }, /* R218 */ + { 0x0000, 0x0000 }, /* R219 */ + { 0x0000, 0x0000 }, /* R220 */ + { 0x0000, 0x0000 }, /* R221 */ + { 0x0000, 0x0000 }, /* R222 */ + { 0x0000, 0x0000 }, /* R223 */ + { 0x0000, 0x0000 }, /* R224 */ + { 0x0000, 0x0000 }, /* R225 */ + { 0x0000, 0x0000 }, /* R226 */ + { 0x0000, 0x0000 }, /* R227 */ + { 0x0000, 0x0000 }, /* R228 */ + { 0x0000, 0x0000 }, /* R229 */ + { 0x0000, 0x0000 }, /* R230 */ + { 0x0000, 0x0000 }, /* R231 */ + { 0x0000, 0x0000 }, /* R232 */ + { 0x0000, 0x0000 }, /* R233 */ + { 0x0000, 0x0000 }, /* R234 */ + { 0x0000, 0x0000 }, /* R235 */ + { 0x0000, 0x0000 }, /* R236 */ + { 0x0000, 0x0000 }, /* R237 */ + { 0x0000, 0x0000 }, /* R238 */ + { 0x0000, 0x0000 }, /* R239 */ + { 0x0000, 0x0000 }, /* R240 */ + { 0x0000, 0x0000 }, /* R241 */ + { 0x0000, 0x0000 }, /* R242 */ + { 0x0000, 0x0000 }, /* R243 */ + { 0x0000, 0x0000 }, /* R244 */ + { 0x0000, 0x0000 }, /* R245 */ + { 0x0000, 0x0000 }, /* R246 */ + { 0x0000, 0x0000 }, /* R247 */ + { 0x0000, 0x0000 }, /* R248 */ + { 0x0000, 0x0000 }, /* R249 */ + { 0x0000, 0x0000 }, /* R250 */ + { 0x0000, 0x0000 }, /* R251 */ + { 0x0000, 0x0000 }, /* R252 */ + { 0x0000, 0x0000 }, /* R253 */ + { 0x0000, 0x0000 }, /* R254 */ + { 0x0000, 0x0000 }, /* R255 */ + { 0x000F, 0x0000 }, /* R256 - Chip Revision */ + { 0x0074, 0x0074 }, /* R257 - Control Interface */ + { 0x0000, 0x0000 }, /* R258 */ + { 0x0000, 0x0000 }, /* R259 */ + { 0x0000, 0x0000 }, /* R260 */ + { 0x0000, 0x0000 }, /* R261 */ + { 0x0000, 0x0000 }, /* R262 */ + { 0x0000, 0x0000 }, /* R263 */ + { 0x0000, 0x0000 }, /* R264 */ + { 0x0000, 0x0000 }, /* R265 */ + { 0x0000, 0x0000 }, /* R266 */ + { 0x0000, 0x0000 }, /* R267 */ + { 0x0000, 0x0000 }, /* R268 */ + { 0x0000, 0x0000 }, /* R269 */ + { 0x0000, 0x0000 }, /* R270 */ + { 0x0000, 0x0000 }, /* R271 */ + { 0x807F, 0x837F }, /* R272 - Write Sequencer Ctrl (1) */ + { 0x017F, 0x0000 }, /* R273 - Write Sequencer Ctrl (2) */ + { 0x0000, 0x0000 }, /* R274 */ + { 0x0000, 0x0000 }, /* R275 */ + { 0x0000, 0x0000 }, /* R276 */ + { 0x0000, 0x0000 }, /* R277 */ + { 0x0000, 0x0000 }, /* R278 */ + { 0x0000, 0x0000 }, /* R279 */ + { 0x0000, 0x0000 }, /* R280 */ + { 0x0000, 0x0000 }, /* R281 */ + { 0x0000, 0x0000 }, /* R282 */ + { 0x0000, 0x0000 }, /* R283 */ + { 0x0000, 0x0000 }, /* R284 */ + { 0x0000, 0x0000 }, /* R285 */ + { 0x0000, 0x0000 }, /* R286 */ + { 0x0000, 0x0000 }, /* R287 */ + { 0x0000, 0x0000 }, /* R288 */ + { 0x0000, 0x0000 }, /* R289 */ + { 0x0000, 0x0000 }, /* R290 */ + { 0x0000, 0x0000 }, /* R291 */ + { 0x0000, 0x0000 }, /* R292 */ + { 0x0000, 0x0000 }, /* R293 */ + { 0x0000, 0x0000 }, /* R294 */ + { 0x0000, 0x0000 }, /* R295 */ + { 0x0000, 0x0000 }, /* R296 */ + { 0x0000, 0x0000 }, /* R297 */ + { 0x0000, 0x0000 }, /* R298 */ + { 0x0000, 0x0000 }, /* R299 */ + { 0x0000, 0x0000 }, /* R300 */ + { 0x0000, 0x0000 }, /* R301 */ + { 0x0000, 0x0000 }, /* R302 */ + { 0x0000, 0x0000 }, /* R303 */ + { 0x0000, 0x0000 }, /* R304 */ + { 0x0000, 0x0000 }, /* R305 */ + { 0x0000, 0x0000 }, /* R306 */ + { 0x0000, 0x0000 }, /* R307 */ + { 0x0000, 0x0000 }, /* R308 */ + { 0x0000, 0x0000 }, /* R309 */ + { 0x0000, 0x0000 }, /* R310 */ + { 0x0000, 0x0000 }, /* R311 */ + { 0x0000, 0x0000 }, /* R312 */ + { 0x0000, 0x0000 }, /* R313 */ + { 0x0000, 0x0000 }, /* R314 */ + { 0x0000, 0x0000 }, /* R315 */ + { 0x0000, 0x0000 }, /* R316 */ + { 0x0000, 0x0000 }, /* R317 */ + { 0x0000, 0x0000 }, /* R318 */ + { 0x0000, 0x0000 }, /* R319 */ + { 0x0000, 0x0000 }, /* R320 */ + { 0x0000, 0x0000 }, /* R321 */ + { 0x0000, 0x0000 }, /* R322 */ + { 0x0000, 0x0000 }, /* R323 */ + { 0x0000, 0x0000 }, /* R324 */ + { 0x0000, 0x0000 }, /* R325 */ + { 0x0000, 0x0000 }, /* R326 */ + { 0x0000, 0x0000 }, /* R327 */ + { 0x0000, 0x0000 }, /* R328 */ + { 0x0000, 0x0000 }, /* R329 */ + { 0x0000, 0x0000 }, /* R330 */ + { 0x0000, 0x0000 }, /* R331 */ + { 0x0000, 0x0000 }, /* R332 */ + { 0x0000, 0x0000 }, /* R333 */ + { 0x0000, 0x0000 }, /* R334 */ + { 0x0000, 0x0000 }, /* R335 */ + { 0x0000, 0x0000 }, /* R336 */ + { 0x0000, 0x0000 }, /* R337 */ + { 0x0000, 0x0000 }, /* R338 */ + { 0x0000, 0x0000 }, /* R339 */ + { 0x0000, 0x0000 }, /* R340 */ + { 0x0000, 0x0000 }, /* R341 */ + { 0x0000, 0x0000 }, /* R342 */ + { 0x0000, 0x0000 }, /* R343 */ + { 0x0000, 0x0000 }, /* R344 */ + { 0x0000, 0x0000 }, /* R345 */ + { 0x0000, 0x0000 }, /* R346 */ + { 0x0000, 0x0000 }, /* R347 */ + { 0x0000, 0x0000 }, /* R348 */ + { 0x0000, 0x0000 }, /* R349 */ + { 0x0000, 0x0000 }, /* R350 */ + { 0x0000, 0x0000 }, /* R351 */ + { 0x0000, 0x0000 }, /* R352 */ + { 0x0000, 0x0000 }, /* R353 */ + { 0x0000, 0x0000 }, /* R354 */ + { 0x0000, 0x0000 }, /* R355 */ + { 0x0000, 0x0000 }, /* R356 */ + { 0x0000, 0x0000 }, /* R357 */ + { 0x0000, 0x0000 }, /* R358 */ + { 0x0000, 0x0000 }, /* R359 */ + { 0x0000, 0x0000 }, /* R360 */ + { 0x0000, 0x0000 }, /* R361 */ + { 0x0000, 0x0000 }, /* R362 */ + { 0x0000, 0x0000 }, /* R363 */ + { 0x0000, 0x0000 }, /* R364 */ + { 0x0000, 0x0000 }, /* R365 */ + { 0x0000, 0x0000 }, /* R366 */ + { 0x0000, 0x0000 }, /* R367 */ + { 0x0000, 0x0000 }, /* R368 */ + { 0x0000, 0x0000 }, /* R369 */ + { 0x0000, 0x0000 }, /* R370 */ + { 0x0000, 0x0000 }, /* R371 */ + { 0x0000, 0x0000 }, /* R372 */ + { 0x0000, 0x0000 }, /* R373 */ + { 0x0000, 0x0000 }, /* R374 */ + { 0x0000, 0x0000 }, /* R375 */ + { 0x0000, 0x0000 }, /* R376 */ + { 0x0000, 0x0000 }, /* R377 */ + { 0x0000, 0x0000 }, /* R378 */ + { 0x0000, 0x0000 }, /* R379 */ + { 0x0000, 0x0000 }, /* R380 */ + { 0x0000, 0x0000 }, /* R381 */ + { 0x0000, 0x0000 }, /* R382 */ + { 0x0000, 0x0000 }, /* R383 */ + { 0x0000, 0x0000 }, /* R384 */ + { 0x0000, 0x0000 }, /* R385 */ + { 0x0000, 0x0000 }, /* R386 */ + { 0x0000, 0x0000 }, /* R387 */ + { 0x0000, 0x0000 }, /* R388 */ + { 0x0000, 0x0000 }, /* R389 */ + { 0x0000, 0x0000 }, /* R390 */ + { 0x0000, 0x0000 }, /* R391 */ + { 0x0000, 0x0000 }, /* R392 */ + { 0x0000, 0x0000 }, /* R393 */ + { 0x0000, 0x0000 }, /* R394 */ + { 0x0000, 0x0000 }, /* R395 */ + { 0x0000, 0x0000 }, /* R396 */ + { 0x0000, 0x0000 }, /* R397 */ + { 0x0000, 0x0000 }, /* R398 */ + { 0x0000, 0x0000 }, /* R399 */ + { 0x0000, 0x0000 }, /* R400 */ + { 0x0000, 0x0000 }, /* R401 */ + { 0x0000, 0x0000 }, /* R402 */ + { 0x0000, 0x0000 }, /* R403 */ + { 0x0000, 0x0000 }, /* R404 */ + { 0x0000, 0x0000 }, /* R405 */ + { 0x0000, 0x0000 }, /* R406 */ + { 0x0000, 0x0000 }, /* R407 */ + { 0x0000, 0x0000 }, /* R408 */ + { 0x0000, 0x0000 }, /* R409 */ + { 0x0000, 0x0000 }, /* R410 */ + { 0x0000, 0x0000 }, /* R411 */ + { 0x0000, 0x0000 }, /* R412 */ + { 0x0000, 0x0000 }, /* R413 */ + { 0x0000, 0x0000 }, /* R414 */ + { 0x0000, 0x0000 }, /* R415 */ + { 0x0000, 0x0000 }, /* R416 */ + { 0x0000, 0x0000 }, /* R417 */ + { 0x0000, 0x0000 }, /* R418 */ + { 0x0000, 0x0000 }, /* R419 */ + { 0x0000, 0x0000 }, /* R420 */ + { 0x0000, 0x0000 }, /* R421 */ + { 0x0000, 0x0000 }, /* R422 */ + { 0x0000, 0x0000 }, /* R423 */ + { 0x0000, 0x0000 }, /* R424 */ + { 0x0000, 0x0000 }, /* R425 */ + { 0x0000, 0x0000 }, /* R426 */ + { 0x0000, 0x0000 }, /* R427 */ + { 0x0000, 0x0000 }, /* R428 */ + { 0x0000, 0x0000 }, /* R429 */ + { 0x0000, 0x0000 }, /* R430 */ + { 0x0000, 0x0000 }, /* R431 */ + { 0x0000, 0x0000 }, /* R432 */ + { 0x0000, 0x0000 }, /* R433 */ + { 0x0000, 0x0000 }, /* R434 */ + { 0x0000, 0x0000 }, /* R435 */ + { 0x0000, 0x0000 }, /* R436 */ + { 0x0000, 0x0000 }, /* R437 */ + { 0x0000, 0x0000 }, /* R438 */ + { 0x0000, 0x0000 }, /* R439 */ + { 0x0000, 0x0000 }, /* R440 */ + { 0x0000, 0x0000 }, /* R441 */ + { 0x0000, 0x0000 }, /* R442 */ + { 0x0000, 0x0000 }, /* R443 */ + { 0x0000, 0x0000 }, /* R444 */ + { 0x0000, 0x0000 }, /* R445 */ + { 0x0000, 0x0000 }, /* R446 */ + { 0x0000, 0x0000 }, /* R447 */ + { 0x0000, 0x0000 }, /* R448 */ + { 0x0000, 0x0000 }, /* R449 */ + { 0x0000, 0x0000 }, /* R450 */ + { 0x0000, 0x0000 }, /* R451 */ + { 0x0000, 0x0000 }, /* R452 */ + { 0x0000, 0x0000 }, /* R453 */ + { 0x0000, 0x0000 }, /* R454 */ + { 0x0000, 0x0000 }, /* R455 */ + { 0x0000, 0x0000 }, /* R456 */ + { 0x0000, 0x0000 }, /* R457 */ + { 0x0000, 0x0000 }, /* R458 */ + { 0x0000, 0x0000 }, /* R459 */ + { 0x0000, 0x0000 }, /* R460 */ + { 0x0000, 0x0000 }, /* R461 */ + { 0x0000, 0x0000 }, /* R462 */ + { 0x0000, 0x0000 }, /* R463 */ + { 0x0000, 0x0000 }, /* R464 */ + { 0x0000, 0x0000 }, /* R465 */ + { 0x0000, 0x0000 }, /* R466 */ + { 0x0000, 0x0000 }, /* R467 */ + { 0x0000, 0x0000 }, /* R468 */ + { 0x0000, 0x0000 }, /* R469 */ + { 0x0000, 0x0000 }, /* R470 */ + { 0x0000, 0x0000 }, /* R471 */ + { 0x0000, 0x0000 }, /* R472 */ + { 0x0000, 0x0000 }, /* R473 */ + { 0x0000, 0x0000 }, /* R474 */ + { 0x0000, 0x0000 }, /* R475 */ + { 0x0000, 0x0000 }, /* R476 */ + { 0x0000, 0x0000 }, /* R477 */ + { 0x0000, 0x0000 }, /* R478 */ + { 0x0000, 0x0000 }, /* R479 */ + { 0x0000, 0x0000 }, /* R480 */ + { 0x0000, 0x0000 }, /* R481 */ + { 0x0000, 0x0000 }, /* R482 */ + { 0x0000, 0x0000 }, /* R483 */ + { 0x0000, 0x0000 }, /* R484 */ + { 0x0000, 0x0000 }, /* R485 */ + { 0x0000, 0x0000 }, /* R486 */ + { 0x0000, 0x0000 }, /* R487 */ + { 0x0000, 0x0000 }, /* R488 */ + { 0x0000, 0x0000 }, /* R489 */ + { 0x0000, 0x0000 }, /* R490 */ + { 0x0000, 0x0000 }, /* R491 */ + { 0x0000, 0x0000 }, /* R492 */ + { 0x0000, 0x0000 }, /* R493 */ + { 0x0000, 0x0000 }, /* R494 */ + { 0x0000, 0x0000 }, /* R495 */ + { 0x0000, 0x0000 }, /* R496 */ + { 0x0000, 0x0000 }, /* R497 */ + { 0x0000, 0x0000 }, /* R498 */ + { 0x0000, 0x0000 }, /* R499 */ + { 0x0000, 0x0000 }, /* R500 */ + { 0x0000, 0x0000 }, /* R501 */ + { 0x0000, 0x0000 }, /* R502 */ + { 0x0000, 0x0000 }, /* R503 */ + { 0x0000, 0x0000 }, /* R504 */ + { 0x0000, 0x0000 }, /* R505 */ + { 0x0000, 0x0000 }, /* R506 */ + { 0x0000, 0x0000 }, /* R507 */ + { 0x0000, 0x0000 }, /* R508 */ + { 0x0000, 0x0000 }, /* R509 */ + { 0x0000, 0x0000 }, /* R510 */ + { 0x0000, 0x0000 }, /* R511 */ + { 0x001F, 0x001F }, /* R512 - AIF1 Clocking (1) */ + { 0x003F, 0x003F }, /* R513 - AIF1 Clocking (2) */ + { 0x0000, 0x0000 }, /* R514 */ + { 0x0000, 0x0000 }, /* R515 */ + { 0x001F, 0x001F }, /* R516 - AIF2 Clocking (1) */ + { 0x003F, 0x003F }, /* R517 - AIF2 Clocking (2) */ + { 0x0000, 0x0000 }, /* R518 */ + { 0x0000, 0x0000 }, /* R519 */ + { 0x001F, 0x001F }, /* R520 - Clocking (1) */ + { 0x0777, 0x0777 }, /* R521 - Clocking (2) */ + { 0x0000, 0x0000 }, /* R522 */ + { 0x0000, 0x0000 }, /* R523 */ + { 0x0000, 0x0000 }, /* R524 */ + { 0x0000, 0x0000 }, /* R525 */ + { 0x0000, 0x0000 }, /* R526 */ + { 0x0000, 0x0000 }, /* R527 */ + { 0x00FF, 0x00FF }, /* R528 - AIF1 Rate */ + { 0x00FF, 0x00FF }, /* R529 - AIF2 Rate */ + { 0x000F, 0x0000 }, /* R530 - Rate Status */ + { 0x0000, 0x0000 }, /* R531 */ + { 0x0000, 0x0000 }, /* R532 */ + { 0x0000, 0x0000 }, /* R533 */ + { 0x0000, 0x0000 }, /* R534 */ + { 0x0000, 0x0000 }, /* R535 */ + { 0x0000, 0x0000 }, /* R536 */ + { 0x0000, 0x0000 }, /* R537 */ + { 0x0000, 0x0000 }, /* R538 */ + { 0x0000, 0x0000 }, /* R539 */ + { 0x0000, 0x0000 }, /* R540 */ + { 0x0000, 0x0000 }, /* R541 */ + { 0x0000, 0x0000 }, /* R542 */ + { 0x0000, 0x0000 }, /* R543 */ + { 0x0007, 0x0007 }, /* R544 - FLL1 Control (1) */ + { 0x3F77, 0x3F77 }, /* R545 - FLL1 Control (2) */ + { 0xFFFF, 0xFFFF }, /* R546 - FLL1 Control (3) */ + { 0x7FEF, 0x7FEF }, /* R547 - FLL1 Control (4) */ + { 0x1FDB, 0x1FDB }, /* R548 - FLL1 Control (5) */ + { 0x0000, 0x0000 }, /* R549 */ + { 0x0000, 0x0000 }, /* R550 */ + { 0x0000, 0x0000 }, /* R551 */ + { 0x0000, 0x0000 }, /* R552 */ + { 0x0000, 0x0000 }, /* R553 */ + { 0x0000, 0x0000 }, /* R554 */ + { 0x0000, 0x0000 }, /* R555 */ + { 0x0000, 0x0000 }, /* R556 */ + { 0x0000, 0x0000 }, /* R557 */ + { 0x0000, 0x0000 }, /* R558 */ + { 0x0000, 0x0000 }, /* R559 */ + { 0x0000, 0x0000 }, /* R560 */ + { 0x0000, 0x0000 }, /* R561 */ + { 0x0000, 0x0000 }, /* R562 */ + { 0x0000, 0x0000 }, /* R563 */ + { 0x0000, 0x0000 }, /* R564 */ + { 0x0000, 0x0000 }, /* R565 */ + { 0x0000, 0x0000 }, /* R566 */ + { 0x0000, 0x0000 }, /* R567 */ + { 0x0000, 0x0000 }, /* R568 */ + { 0x0000, 0x0000 }, /* R569 */ + { 0x0000, 0x0000 }, /* R570 */ + { 0x0000, 0x0000 }, /* R571 */ + { 0x0000, 0x0000 }, /* R572 */ + { 0x0000, 0x0000 }, /* R573 */ + { 0x0000, 0x0000 }, /* R574 */ + { 0x0000, 0x0000 }, /* R575 */ + { 0x0007, 0x0007 }, /* R576 - FLL2 Control (1) */ + { 0x3F77, 0x3F77 }, /* R577 - FLL2 Control (2) */ + { 0xFFFF, 0xFFFF }, /* R578 - FLL2 Control (3) */ + { 0x7FEF, 0x7FEF }, /* R579 - FLL2 Control (4) */ + { 0x1FDB, 0x1FDB }, /* R580 - FLL2 Control (5) */ + { 0x0000, 0x0000 }, /* R581 */ + { 0x0000, 0x0000 }, /* R582 */ + { 0x0000, 0x0000 }, /* R583 */ + { 0x0000, 0x0000 }, /* R584 */ + { 0x0000, 0x0000 }, /* R585 */ + { 0x0000, 0x0000 }, /* R586 */ + { 0x0000, 0x0000 }, /* R587 */ + { 0x0000, 0x0000 }, /* R588 */ + { 0x0000, 0x0000 }, /* R589 */ + { 0x0000, 0x0000 }, /* R590 */ + { 0x0000, 0x0000 }, /* R591 */ + { 0x0000, 0x0000 }, /* R592 */ + { 0x0000, 0x0000 }, /* R593 */ + { 0x0000, 0x0000 }, /* R594 */ + { 0x0000, 0x0000 }, /* R595 */ + { 0x0000, 0x0000 }, /* R596 */ + { 0x0000, 0x0000 }, /* R597 */ + { 0x0000, 0x0000 }, /* R598 */ + { 0x0000, 0x0000 }, /* R599 */ + { 0x0000, 0x0000 }, /* R600 */ + { 0x0000, 0x0000 }, /* R601 */ + { 0x0000, 0x0000 }, /* R602 */ + { 0x0000, 0x0000 }, /* R603 */ + { 0x0000, 0x0000 }, /* R604 */ + { 0x0000, 0x0000 }, /* R605 */ + { 0x0000, 0x0000 }, /* R606 */ + { 0x0000, 0x0000 }, /* R607 */ + { 0x0000, 0x0000 }, /* R608 */ + { 0x0000, 0x0000 }, /* R609 */ + { 0x0000, 0x0000 }, /* R610 */ + { 0x0000, 0x0000 }, /* R611 */ + { 0x0000, 0x0000 }, /* R612 */ + { 0x0000, 0x0000 }, /* R613 */ + { 0x0000, 0x0000 }, /* R614 */ + { 0x0000, 0x0000 }, /* R615 */ + { 0x0000, 0x0000 }, /* R616 */ + { 0x0000, 0x0000 }, /* R617 */ + { 0x0000, 0x0000 }, /* R618 */ + { 0x0000, 0x0000 }, /* R619 */ + { 0x0000, 0x0000 }, /* R620 */ + { 0x0000, 0x0000 }, /* R621 */ + { 0x0000, 0x0000 }, /* R622 */ + { 0x0000, 0x0000 }, /* R623 */ + { 0x0000, 0x0000 }, /* R624 */ + { 0x0000, 0x0000 }, /* R625 */ + { 0x0000, 0x0000 }, /* R626 */ + { 0x0000, 0x0000 }, /* R627 */ + { 0x0000, 0x0000 }, /* R628 */ + { 0x0000, 0x0000 }, /* R629 */ + { 0x0000, 0x0000 }, /* R630 */ + { 0x0000, 0x0000 }, /* R631 */ + { 0x0000, 0x0000 }, /* R632 */ + { 0x0000, 0x0000 }, /* R633 */ + { 0x0000, 0x0000 }, /* R634 */ + { 0x0000, 0x0000 }, /* R635 */ + { 0x0000, 0x0000 }, /* R636 */ + { 0x0000, 0x0000 }, /* R637 */ + { 0x0000, 0x0000 }, /* R638 */ + { 0x0000, 0x0000 }, /* R639 */ + { 0x0000, 0x0000 }, /* R640 */ + { 0x0000, 0x0000 }, /* R641 */ + { 0x0000, 0x0000 }, /* R642 */ + { 0x0000, 0x0000 }, /* R643 */ + { 0x0000, 0x0000 }, /* R644 */ + { 0x0000, 0x0000 }, /* R645 */ + { 0x0000, 0x0000 }, /* R646 */ + { 0x0000, 0x0000 }, /* R647 */ + { 0x0000, 0x0000 }, /* R648 */ + { 0x0000, 0x0000 }, /* R649 */ + { 0x0000, 0x0000 }, /* R650 */ + { 0x0000, 0x0000 }, /* R651 */ + { 0x0000, 0x0000 }, /* R652 */ + { 0x0000, 0x0000 }, /* R653 */ + { 0x0000, 0x0000 }, /* R654 */ + { 0x0000, 0x0000 }, /* R655 */ + { 0x0000, 0x0000 }, /* R656 */ + { 0x0000, 0x0000 }, /* R657 */ + { 0x0000, 0x0000 }, /* R658 */ + { 0x0000, 0x0000 }, /* R659 */ + { 0x0000, 0x0000 }, /* R660 */ + { 0x0000, 0x0000 }, /* R661 */ + { 0x0000, 0x0000 }, /* R662 */ + { 0x0000, 0x0000 }, /* R663 */ + { 0x0000, 0x0000 }, /* R664 */ + { 0x0000, 0x0000 }, /* R665 */ + { 0x0000, 0x0000 }, /* R666 */ + { 0x0000, 0x0000 }, /* R667 */ + { 0x0000, 0x0000 }, /* R668 */ + { 0x0000, 0x0000 }, /* R669 */ + { 0x0000, 0x0000 }, /* R670 */ + { 0x0000, 0x0000 }, /* R671 */ + { 0x0000, 0x0000 }, /* R672 */ + { 0x0000, 0x0000 }, /* R673 */ + { 0x0000, 0x0000 }, /* R674 */ + { 0x0000, 0x0000 }, /* R675 */ + { 0x0000, 0x0000 }, /* R676 */ + { 0x0000, 0x0000 }, /* R677 */ + { 0x0000, 0x0000 }, /* R678 */ + { 0x0000, 0x0000 }, /* R679 */ + { 0x0000, 0x0000 }, /* R680 */ + { 0x0000, 0x0000 }, /* R681 */ + { 0x0000, 0x0000 }, /* R682 */ + { 0x0000, 0x0000 }, /* R683 */ + { 0x0000, 0x0000 }, /* R684 */ + { 0x0000, 0x0000 }, /* R685 */ + { 0x0000, 0x0000 }, /* R686 */ + { 0x0000, 0x0000 }, /* R687 */ + { 0x0000, 0x0000 }, /* R688 */ + { 0x0000, 0x0000 }, /* R689 */ + { 0x0000, 0x0000 }, /* R690 */ + { 0x0000, 0x0000 }, /* R691 */ + { 0x0000, 0x0000 }, /* R692 */ + { 0x0000, 0x0000 }, /* R693 */ + { 0x0000, 0x0000 }, /* R694 */ + { 0x0000, 0x0000 }, /* R695 */ + { 0x0000, 0x0000 }, /* R696 */ + { 0x0000, 0x0000 }, /* R697 */ + { 0x0000, 0x0000 }, /* R698 */ + { 0x0000, 0x0000 }, /* R699 */ + { 0x0000, 0x0000 }, /* R700 */ + { 0x0000, 0x0000 }, /* R701 */ + { 0x0000, 0x0000 }, /* R702 */ + { 0x0000, 0x0000 }, /* R703 */ + { 0x0000, 0x0000 }, /* R704 */ + { 0x0000, 0x0000 }, /* R705 */ + { 0x0000, 0x0000 }, /* R706 */ + { 0x0000, 0x0000 }, /* R707 */ + { 0x0000, 0x0000 }, /* R708 */ + { 0x0000, 0x0000 }, /* R709 */ + { 0x0000, 0x0000 }, /* R710 */ + { 0x0000, 0x0000 }, /* R711 */ + { 0x0000, 0x0000 }, /* R712 */ + { 0x0000, 0x0000 }, /* R713 */ + { 0x0000, 0x0000 }, /* R714 */ + { 0x0000, 0x0000 }, /* R715 */ + { 0x0000, 0x0000 }, /* R716 */ + { 0x0000, 0x0000 }, /* R717 */ + { 0x0000, 0x0000 }, /* R718 */ + { 0x0000, 0x0000 }, /* R719 */ + { 0x0000, 0x0000 }, /* R720 */ + { 0x0000, 0x0000 }, /* R721 */ + { 0x0000, 0x0000 }, /* R722 */ + { 0x0000, 0x0000 }, /* R723 */ + { 0x0000, 0x0000 }, /* R724 */ + { 0x0000, 0x0000 }, /* R725 */ + { 0x0000, 0x0000 }, /* R726 */ + { 0x0000, 0x0000 }, /* R727 */ + { 0x0000, 0x0000 }, /* R728 */ + { 0x0000, 0x0000 }, /* R729 */ + { 0x0000, 0x0000 }, /* R730 */ + { 0x0000, 0x0000 }, /* R731 */ + { 0x0000, 0x0000 }, /* R732 */ + { 0x0000, 0x0000 }, /* R733 */ + { 0x0000, 0x0000 }, /* R734 */ + { 0x0000, 0x0000 }, /* R735 */ + { 0x0000, 0x0000 }, /* R736 */ + { 0x0000, 0x0000 }, /* R737 */ + { 0x0000, 0x0000 }, /* R738 */ + { 0x0000, 0x0000 }, /* R739 */ + { 0x0000, 0x0000 }, /* R740 */ + { 0x0000, 0x0000 }, /* R741 */ + { 0x0000, 0x0000 }, /* R742 */ + { 0x0000, 0x0000 }, /* R743 */ + { 0x0000, 0x0000 }, /* R744 */ + { 0x0000, 0x0000 }, /* R745 */ + { 0x0000, 0x0000 }, /* R746 */ + { 0x0000, 0x0000 }, /* R747 */ + { 0x0000, 0x0000 }, /* R748 */ + { 0x0000, 0x0000 }, /* R749 */ + { 0x0000, 0x0000 }, /* R750 */ + { 0x0000, 0x0000 }, /* R751 */ + { 0x0000, 0x0000 }, /* R752 */ + { 0x0000, 0x0000 }, /* R753 */ + { 0x0000, 0x0000 }, /* R754 */ + { 0x0000, 0x0000 }, /* R755 */ + { 0x0000, 0x0000 }, /* R756 */ + { 0x0000, 0x0000 }, /* R757 */ + { 0x0000, 0x0000 }, /* R758 */ + { 0x0000, 0x0000 }, /* R759 */ + { 0x0000, 0x0000 }, /* R760 */ + { 0x0000, 0x0000 }, /* R761 */ + { 0x0000, 0x0000 }, /* R762 */ + { 0x0000, 0x0000 }, /* R763 */ + { 0x0000, 0x0000 }, /* R764 */ + { 0x0000, 0x0000 }, /* R765 */ + { 0x0000, 0x0000 }, /* R766 */ + { 0x0000, 0x0000 }, /* R767 */ + { 0xE1F8, 0xE1F8 }, /* R768 - AIF1 Control (1) */ + { 0xCD1F, 0xCD1F }, /* R769 - AIF1 Control (2) */ + { 0xF000, 0xF000 }, /* R770 - AIF1 Master/Slave */ + { 0x01F0, 0x01F0 }, /* R771 - AIF1 BCLK */ + { 0x0FFF, 0x0FFF }, /* R772 - AIF1ADC LRCLK */ + { 0x0FFF, 0x0FFF }, /* R773 - AIF1DAC LRCLK */ + { 0x0003, 0x0003 }, /* R774 - AIF1DAC Data */ + { 0x0003, 0x0003 }, /* R775 - AIF1ADC Data */ + { 0x0000, 0x0000 }, /* R776 */ + { 0x0000, 0x0000 }, /* R777 */ + { 0x0000, 0x0000 }, /* R778 */ + { 0x0000, 0x0000 }, /* R779 */ + { 0x0000, 0x0000 }, /* R780 */ + { 0x0000, 0x0000 }, /* R781 */ + { 0x0000, 0x0000 }, /* R782 */ + { 0x0000, 0x0000 }, /* R783 */ + { 0xF1F8, 0xF1F8 }, /* R784 - AIF2 Control (1) */ + { 0xFD1F, 0xFD1F }, /* R785 - AIF2 Control (2) */ + { 0xF000, 0xF000 }, /* R786 - AIF2 Master/Slave */ + { 0x01F0, 0x01F0 }, /* R787 - AIF2 BCLK */ + { 0x0FFF, 0x0FFF }, /* R788 - AIF2ADC LRCLK */ + { 0x0FFF, 0x0FFF }, /* R789 - AIF2DAC LRCLK */ + { 0x0003, 0x0003 }, /* R790 - AIF2DAC Data */ + { 0x0003, 0x0003 }, /* R791 - AIF2ADC Data */ + { 0x0000, 0x0000 }, /* R792 */ + { 0x0000, 0x0000 }, /* R793 */ + { 0x0000, 0x0000 }, /* R794 */ + { 0x0000, 0x0000 }, /* R795 */ + { 0x0000, 0x0000 }, /* R796 */ + { 0x0000, 0x0000 }, /* R797 */ + { 0x0000, 0x0000 }, /* R798 */ + { 0x0000, 0x0000 }, /* R799 */ + { 0x0000, 0x0000 }, /* R800 */ + { 0x0000, 0x0000 }, /* R801 */ + { 0x0000, 0x0000 }, /* R802 */ + { 0x0000, 0x0000 }, /* R803 */ + { 0x0000, 0x0000 }, /* R804 */ + { 0x0000, 0x0000 }, /* R805 */ + { 0x0000, 0x0000 }, /* R806 */ + { 0x0000, 0x0000 }, /* R807 */ + { 0x0000, 0x0000 }, /* R808 */ + { 0x0000, 0x0000 }, /* R809 */ + { 0x0000, 0x0000 }, /* R810 */ + { 0x0000, 0x0000 }, /* R811 */ + { 0x0000, 0x0000 }, /* R812 */ + { 0x0000, 0x0000 }, /* R813 */ + { 0x0000, 0x0000 }, /* R814 */ + { 0x0000, 0x0000 }, /* R815 */ + { 0x0000, 0x0000 }, /* R816 */ + { 0x0000, 0x0000 }, /* R817 */ + { 0x0000, 0x0000 }, /* R818 */ + { 0x0000, 0x0000 }, /* R819 */ + { 0x0000, 0x0000 }, /* R820 */ + { 0x0000, 0x0000 }, /* R821 */ + { 0x0000, 0x0000 }, /* R822 */ + { 0x0000, 0x0000 }, /* R823 */ + { 0x0000, 0x0000 }, /* R824 */ + { 0x0000, 0x0000 }, /* R825 */ + { 0x0000, 0x0000 }, /* R826 */ + { 0x0000, 0x0000 }, /* R827 */ + { 0x0000, 0x0000 }, /* R828 */ + { 0x0000, 0x0000 }, /* R829 */ + { 0x0000, 0x0000 }, /* R830 */ + { 0x0000, 0x0000 }, /* R831 */ + { 0x0000, 0x0000 }, /* R832 */ + { 0x0000, 0x0000 }, /* R833 */ + { 0x0000, 0x0000 }, /* R834 */ + { 0x0000, 0x0000 }, /* R835 */ + { 0x0000, 0x0000 }, /* R836 */ + { 0x0000, 0x0000 }, /* R837 */ + { 0x0000, 0x0000 }, /* R838 */ + { 0x0000, 0x0000 }, /* R839 */ + { 0x0000, 0x0000 }, /* R840 */ + { 0x0000, 0x0000 }, /* R841 */ + { 0x0000, 0x0000 }, /* R842 */ + { 0x0000, 0x0000 }, /* R843 */ + { 0x0000, 0x0000 }, /* R844 */ + { 0x0000, 0x0000 }, /* R845 */ + { 0x0000, 0x0000 }, /* R846 */ + { 0x0000, 0x0000 }, /* R847 */ + { 0x0000, 0x0000 }, /* R848 */ + { 0x0000, 0x0000 }, /* R849 */ + { 0x0000, 0x0000 }, /* R850 */ + { 0x0000, 0x0000 }, /* R851 */ + { 0x0000, 0x0000 }, /* R852 */ + { 0x0000, 0x0000 }, /* R853 */ + { 0x0000, 0x0000 }, /* R854 */ + { 0x0000, 0x0000 }, /* R855 */ + { 0x0000, 0x0000 }, /* R856 */ + { 0x0000, 0x0000 }, /* R857 */ + { 0x0000, 0x0000 }, /* R858 */ + { 0x0000, 0x0000 }, /* R859 */ + { 0x0000, 0x0000 }, /* R860 */ + { 0x0000, 0x0000 }, /* R861 */ + { 0x0000, 0x0000 }, /* R862 */ + { 0x0000, 0x0000 }, /* R863 */ + { 0x0000, 0x0000 }, /* R864 */ + { 0x0000, 0x0000 }, /* R865 */ + { 0x0000, 0x0000 }, /* R866 */ + { 0x0000, 0x0000 }, /* R867 */ + { 0x0000, 0x0000 }, /* R868 */ + { 0x0000, 0x0000 }, /* R869 */ + { 0x0000, 0x0000 }, /* R870 */ + { 0x0000, 0x0000 }, /* R871 */ + { 0x0000, 0x0000 }, /* R872 */ + { 0x0000, 0x0000 }, /* R873 */ + { 0x0000, 0x0000 }, /* R874 */ + { 0x0000, 0x0000 }, /* R875 */ + { 0x0000, 0x0000 }, /* R876 */ + { 0x0000, 0x0000 }, /* R877 */ + { 0x0000, 0x0000 }, /* R878 */ + { 0x0000, 0x0000 }, /* R879 */ + { 0x0000, 0x0000 }, /* R880 */ + { 0x0000, 0x0000 }, /* R881 */ + { 0x0000, 0x0000 }, /* R882 */ + { 0x0000, 0x0000 }, /* R883 */ + { 0x0000, 0x0000 }, /* R884 */ + { 0x0000, 0x0000 }, /* R885 */ + { 0x0000, 0x0000 }, /* R886 */ + { 0x0000, 0x0000 }, /* R887 */ + { 0x0000, 0x0000 }, /* R888 */ + { 0x0000, 0x0000 }, /* R889 */ + { 0x0000, 0x0000 }, /* R890 */ + { 0x0000, 0x0000 }, /* R891 */ + { 0x0000, 0x0000 }, /* R892 */ + { 0x0000, 0x0000 }, /* R893 */ + { 0x0000, 0x0000 }, /* R894 */ + { 0x0000, 0x0000 }, /* R895 */ + { 0x0000, 0x0000 }, /* R896 */ + { 0x0000, 0x0000 }, /* R897 */ + { 0x0000, 0x0000 }, /* R898 */ + { 0x0000, 0x0000 }, /* R899 */ + { 0x0000, 0x0000 }, /* R900 */ + { 0x0000, 0x0000 }, /* R901 */ + { 0x0000, 0x0000 }, /* R902 */ + { 0x0000, 0x0000 }, /* R903 */ + { 0x0000, 0x0000 }, /* R904 */ + { 0x0000, 0x0000 }, /* R905 */ + { 0x0000, 0x0000 }, /* R906 */ + { 0x0000, 0x0000 }, /* R907 */ + { 0x0000, 0x0000 }, /* R908 */ + { 0x0000, 0x0000 }, /* R909 */ + { 0x0000, 0x0000 }, /* R910 */ + { 0x0000, 0x0000 }, /* R911 */ + { 0x0000, 0x0000 }, /* R912 */ + { 0x0000, 0x0000 }, /* R913 */ + { 0x0000, 0x0000 }, /* R914 */ + { 0x0000, 0x0000 }, /* R915 */ + { 0x0000, 0x0000 }, /* R916 */ + { 0x0000, 0x0000 }, /* R917 */ + { 0x0000, 0x0000 }, /* R918 */ + { 0x0000, 0x0000 }, /* R919 */ + { 0x0000, 0x0000 }, /* R920 */ + { 0x0000, 0x0000 }, /* R921 */ + { 0x0000, 0x0000 }, /* R922 */ + { 0x0000, 0x0000 }, /* R923 */ + { 0x0000, 0x0000 }, /* R924 */ + { 0x0000, 0x0000 }, /* R925 */ + { 0x0000, 0x0000 }, /* R926 */ + { 0x0000, 0x0000 }, /* R927 */ + { 0x0000, 0x0000 }, /* R928 */ + { 0x0000, 0x0000 }, /* R929 */ + { 0x0000, 0x0000 }, /* R930 */ + { 0x0000, 0x0000 }, /* R931 */ + { 0x0000, 0x0000 }, /* R932 */ + { 0x0000, 0x0000 }, /* R933 */ + { 0x0000, 0x0000 }, /* R934 */ + { 0x0000, 0x0000 }, /* R935 */ + { 0x0000, 0x0000 }, /* R936 */ + { 0x0000, 0x0000 }, /* R937 */ + { 0x0000, 0x0000 }, /* R938 */ + { 0x0000, 0x0000 }, /* R939 */ + { 0x0000, 0x0000 }, /* R940 */ + { 0x0000, 0x0000 }, /* R941 */ + { 0x0000, 0x0000 }, /* R942 */ + { 0x0000, 0x0000 }, /* R943 */ + { 0x0000, 0x0000 }, /* R944 */ + { 0x0000, 0x0000 }, /* R945 */ + { 0x0000, 0x0000 }, /* R946 */ + { 0x0000, 0x0000 }, /* R947 */ + { 0x0000, 0x0000 }, /* R948 */ + { 0x0000, 0x0000 }, /* R949 */ + { 0x0000, 0x0000 }, /* R950 */ + { 0x0000, 0x0000 }, /* R951 */ + { 0x0000, 0x0000 }, /* R952 */ + { 0x0000, 0x0000 }, /* R953 */ + { 0x0000, 0x0000 }, /* R954 */ + { 0x0000, 0x0000 }, /* R955 */ + { 0x0000, 0x0000 }, /* R956 */ + { 0x0000, 0x0000 }, /* R957 */ + { 0x0000, 0x0000 }, /* R958 */ + { 0x0000, 0x0000 }, /* R959 */ + { 0x0000, 0x0000 }, /* R960 */ + { 0x0000, 0x0000 }, /* R961 */ + { 0x0000, 0x0000 }, /* R962 */ + { 0x0000, 0x0000 }, /* R963 */ + { 0x0000, 0x0000 }, /* R964 */ + { 0x0000, 0x0000 }, /* R965 */ + { 0x0000, 0x0000 }, /* R966 */ + { 0x0000, 0x0000 }, /* R967 */ + { 0x0000, 0x0000 }, /* R968 */ + { 0x0000, 0x0000 }, /* R969 */ + { 0x0000, 0x0000 }, /* R970 */ + { 0x0000, 0x0000 }, /* R971 */ + { 0x0000, 0x0000 }, /* R972 */ + { 0x0000, 0x0000 }, /* R973 */ + { 0x0000, 0x0000 }, /* R974 */ + { 0x0000, 0x0000 }, /* R975 */ + { 0x0000, 0x0000 }, /* R976 */ + { 0x0000, 0x0000 }, /* R977 */ + { 0x0000, 0x0000 }, /* R978 */ + { 0x0000, 0x0000 }, /* R979 */ + { 0x0000, 0x0000 }, /* R980 */ + { 0x0000, 0x0000 }, /* R981 */ + { 0x0000, 0x0000 }, /* R982 */ + { 0x0000, 0x0000 }, /* R983 */ + { 0x0000, 0x0000 }, /* R984 */ + { 0x0000, 0x0000 }, /* R985 */ + { 0x0000, 0x0000 }, /* R986 */ + { 0x0000, 0x0000 }, /* R987 */ + { 0x0000, 0x0000 }, /* R988 */ + { 0x0000, 0x0000 }, /* R989 */ + { 0x0000, 0x0000 }, /* R990 */ + { 0x0000, 0x0000 }, /* R991 */ + { 0x0000, 0x0000 }, /* R992 */ + { 0x0000, 0x0000 }, /* R993 */ + { 0x0000, 0x0000 }, /* R994 */ + { 0x0000, 0x0000 }, /* R995 */ + { 0x0000, 0x0000 }, /* R996 */ + { 0x0000, 0x0000 }, /* R997 */ + { 0x0000, 0x0000 }, /* R998 */ + { 0x0000, 0x0000 }, /* R999 */ + { 0x0000, 0x0000 }, /* R1000 */ + { 0x0000, 0x0000 }, /* R1001 */ + { 0x0000, 0x0000 }, /* R1002 */ + { 0x0000, 0x0000 }, /* R1003 */ + { 0x0000, 0x0000 }, /* R1004 */ + { 0x0000, 0x0000 }, /* R1005 */ + { 0x0000, 0x0000 }, /* R1006 */ + { 0x0000, 0x0000 }, /* R1007 */ + { 0x0000, 0x0000 }, /* R1008 */ + { 0x0000, 0x0000 }, /* R1009 */ + { 0x0000, 0x0000 }, /* R1010 */ + { 0x0000, 0x0000 }, /* R1011 */ + { 0x0000, 0x0000 }, /* R1012 */ + { 0x0000, 0x0000 }, /* R1013 */ + { 0x0000, 0x0000 }, /* R1014 */ + { 0x0000, 0x0000 }, /* R1015 */ + { 0x0000, 0x0000 }, /* R1016 */ + { 0x0000, 0x0000 }, /* R1017 */ + { 0x0000, 0x0000 }, /* R1018 */ + { 0x0000, 0x0000 }, /* R1019 */ + { 0x0000, 0x0000 }, /* R1020 */ + { 0x0000, 0x0000 }, /* R1021 */ + { 0x0000, 0x0000 }, /* R1022 */ + { 0x0000, 0x0000 }, /* R1023 */ + { 0x00FF, 0x01FF }, /* R1024 - AIF1 ADC1 Left Volume */ + { 0x00FF, 0x01FF }, /* R1025 - AIF1 ADC1 Right Volume */ + { 0x00FF, 0x01FF }, /* R1026 - AIF1 DAC1 Left Volume */ + { 0x00FF, 0x01FF }, /* R1027 - AIF1 DAC1 Right Volume */ + { 0x00FF, 0x01FF }, /* R1028 - AIF1 ADC2 Left Volume */ + { 0x00FF, 0x01FF }, /* R1029 - AIF1 ADC2 Right Volume */ + { 0x00FF, 0x01FF }, /* R1030 - AIF1 DAC2 Left Volume */ + { 0x00FF, 0x01FF }, /* R1031 - AIF1 DAC2 Right Volume */ + { 0x0000, 0x0000 }, /* R1032 */ + { 0x0000, 0x0000 }, /* R1033 */ + { 0x0000, 0x0000 }, /* R1034 */ + { 0x0000, 0x0000 }, /* R1035 */ + { 0x0000, 0x0000 }, /* R1036 */ + { 0x0000, 0x0000 }, /* R1037 */ + { 0x0000, 0x0000 }, /* R1038 */ + { 0x0000, 0x0000 }, /* R1039 */ + { 0xF800, 0xF800 }, /* R1040 - AIF1 ADC1 Filters */ + { 0x7800, 0x7800 }, /* R1041 - AIF1 ADC2 Filters */ + { 0x0000, 0x0000 }, /* R1042 */ + { 0x0000, 0x0000 }, /* R1043 */ + { 0x0000, 0x0000 }, /* R1044 */ + { 0x0000, 0x0000 }, /* R1045 */ + { 0x0000, 0x0000 }, /* R1046 */ + { 0x0000, 0x0000 }, /* R1047 */ + { 0x0000, 0x0000 }, /* R1048 */ + { 0x0000, 0x0000 }, /* R1049 */ + { 0x0000, 0x0000 }, /* R1050 */ + { 0x0000, 0x0000 }, /* R1051 */ + { 0x0000, 0x0000 }, /* R1052 */ + { 0x0000, 0x0000 }, /* R1053 */ + { 0x0000, 0x0000 }, /* R1054 */ + { 0x0000, 0x0000 }, /* R1055 */ + { 0x02B6, 0x02B6 }, /* R1056 - AIF1 DAC1 Filters (1) */ + { 0x3F00, 0x3F00 }, /* R1057 - AIF1 DAC1 Filters (2) */ + { 0x02B6, 0x02B6 }, /* R1058 - AIF1 DAC2 Filters (1) */ + { 0x3F00, 0x3F00 }, /* R1059 - AIF1 DAC2 Filters (2) */ + { 0x0000, 0x0000 }, /* R1060 */ + { 0x0000, 0x0000 }, /* R1061 */ + { 0x0000, 0x0000 }, /* R1062 */ + { 0x0000, 0x0000 }, /* R1063 */ + { 0x0000, 0x0000 }, /* R1064 */ + { 0x0000, 0x0000 }, /* R1065 */ + { 0x0000, 0x0000 }, /* R1066 */ + { 0x0000, 0x0000 }, /* R1067 */ + { 0x0000, 0x0000 }, /* R1068 */ + { 0x0000, 0x0000 }, /* R1069 */ + { 0x0000, 0x0000 }, /* R1070 */ + { 0x0000, 0x0000 }, /* R1071 */ + { 0x0000, 0x0000 }, /* R1072 */ + { 0x0000, 0x0000 }, /* R1073 */ + { 0x0000, 0x0000 }, /* R1074 */ + { 0x0000, 0x0000 }, /* R1075 */ + { 0x0000, 0x0000 }, /* R1076 */ + { 0x0000, 0x0000 }, /* R1077 */ + { 0x0000, 0x0000 }, /* R1078 */ + { 0x0000, 0x0000 }, /* R1079 */ + { 0x0000, 0x0000 }, /* R1080 */ + { 0x0000, 0x0000 }, /* R1081 */ + { 0x0000, 0x0000 }, /* R1082 */ + { 0x0000, 0x0000 }, /* R1083 */ + { 0x0000, 0x0000 }, /* R1084 */ + { 0x0000, 0x0000 }, /* R1085 */ + { 0x0000, 0x0000 }, /* R1086 */ + { 0x0000, 0x0000 }, /* R1087 */ + { 0xFFFF, 0xFFFF }, /* R1088 - AIF1 DRC1 (1) */ + { 0x1FFF, 0x1FFF }, /* R1089 - AIF1 DRC1 (2) */ + { 0xFFFF, 0xFFFF }, /* R1090 - AIF1 DRC1 (3) */ + { 0x07FF, 0x07FF }, /* R1091 - AIF1 DRC1 (4) */ + { 0x03FF, 0x03FF }, /* R1092 - AIF1 DRC1 (5) */ + { 0x0000, 0x0000 }, /* R1093 */ + { 0x0000, 0x0000 }, /* R1094 */ + { 0x0000, 0x0000 }, /* R1095 */ + { 0x0000, 0x0000 }, /* R1096 */ + { 0x0000, 0x0000 }, /* R1097 */ + { 0x0000, 0x0000 }, /* R1098 */ + { 0x0000, 0x0000 }, /* R1099 */ + { 0x0000, 0x0000 }, /* R1100 */ + { 0x0000, 0x0000 }, /* R1101 */ + { 0x0000, 0x0000 }, /* R1102 */ + { 0x0000, 0x0000 }, /* R1103 */ + { 0xFFFF, 0xFFFF }, /* R1104 - AIF1 DRC2 (1) */ + { 0x1FFF, 0x1FFF }, /* R1105 - AIF1 DRC2 (2) */ + { 0xFFFF, 0xFFFF }, /* R1106 - AIF1 DRC2 (3) */ + { 0x07FF, 0x07FF }, /* R1107 - AIF1 DRC2 (4) */ + { 0x03FF, 0x03FF }, /* R1108 - AIF1 DRC2 (5) */ + { 0x0000, 0x0000 }, /* R1109 */ + { 0x0000, 0x0000 }, /* R1110 */ + { 0x0000, 0x0000 }, /* R1111 */ + { 0x0000, 0x0000 }, /* R1112 */ + { 0x0000, 0x0000 }, /* R1113 */ + { 0x0000, 0x0000 }, /* R1114 */ + { 0x0000, 0x0000 }, /* R1115 */ + { 0x0000, 0x0000 }, /* R1116 */ + { 0x0000, 0x0000 }, /* R1117 */ + { 0x0000, 0x0000 }, /* R1118 */ + { 0x0000, 0x0000 }, /* R1119 */ + { 0x0000, 0x0000 }, /* R1120 */ + { 0x0000, 0x0000 }, /* R1121 */ + { 0x0000, 0x0000 }, /* R1122 */ + { 0x0000, 0x0000 }, /* R1123 */ + { 0x0000, 0x0000 }, /* R1124 */ + { 0x0000, 0x0000 }, /* R1125 */ + { 0x0000, 0x0000 }, /* R1126 */ + { 0x0000, 0x0000 }, /* R1127 */ + { 0x0000, 0x0000 }, /* R1128 */ + { 0x0000, 0x0000 }, /* R1129 */ + { 0x0000, 0x0000 }, /* R1130 */ + { 0x0000, 0x0000 }, /* R1131 */ + { 0x0000, 0x0000 }, /* R1132 */ + { 0x0000, 0x0000 }, /* R1133 */ + { 0x0000, 0x0000 }, /* R1134 */ + { 0x0000, 0x0000 }, /* R1135 */ + { 0x0000, 0x0000 }, /* R1136 */ + { 0x0000, 0x0000 }, /* R1137 */ + { 0x0000, 0x0000 }, /* R1138 */ + { 0x0000, 0x0000 }, /* R1139 */ + { 0x0000, 0x0000 }, /* R1140 */ + { 0x0000, 0x0000 }, /* R1141 */ + { 0x0000, 0x0000 }, /* R1142 */ + { 0x0000, 0x0000 }, /* R1143 */ + { 0x0000, 0x0000 }, /* R1144 */ + { 0x0000, 0x0000 }, /* R1145 */ + { 0x0000, 0x0000 }, /* R1146 */ + { 0x0000, 0x0000 }, /* R1147 */ + { 0x0000, 0x0000 }, /* R1148 */ + { 0x0000, 0x0000 }, /* R1149 */ + { 0x0000, 0x0000 }, /* R1150 */ + { 0x0000, 0x0000 }, /* R1151 */ + { 0xFFFF, 0xFFFF }, /* R1152 - AIF1 DAC1 EQ Gains (1) */ + { 0xFFC0, 0xFFC0 }, /* R1153 - AIF1 DAC1 EQ Gains (2) */ + { 0xFFFF, 0xFFFF }, /* R1154 - AIF1 DAC1 EQ Band 1 A */ + { 0xFFFF, 0xFFFF }, /* R1155 - AIF1 DAC1 EQ Band 1 B */ + { 0xFFFF, 0xFFFF }, /* R1156 - AIF1 DAC1 EQ Band 1 PG */ + { 0xFFFF, 0xFFFF }, /* R1157 - AIF1 DAC1 EQ Band 2 A */ + { 0xFFFF, 0xFFFF }, /* R1158 - AIF1 DAC1 EQ Band 2 B */ + { 0xFFFF, 0xFFFF }, /* R1159 - AIF1 DAC1 EQ Band 2 C */ + { 0xFFFF, 0xFFFF }, /* R1160 - AIF1 DAC1 EQ Band 2 PG */ + { 0xFFFF, 0xFFFF }, /* R1161 - AIF1 DAC1 EQ Band 3 A */ + { 0xFFFF, 0xFFFF }, /* R1162 - AIF1 DAC1 EQ Band 3 B */ + { 0xFFFF, 0xFFFF }, /* R1163 - AIF1 DAC1 EQ Band 3 C */ + { 0xFFFF, 0xFFFF }, /* R1164 - AIF1 DAC1 EQ Band 3 PG */ + { 0xFFFF, 0xFFFF }, /* R1165 - AIF1 DAC1 EQ Band 4 A */ + { 0xFFFF, 0xFFFF }, /* R1166 - AIF1 DAC1 EQ Band 4 B */ + { 0xFFFF, 0xFFFF }, /* R1167 - AIF1 DAC1 EQ Band 4 C */ + { 0xFFFF, 0xFFFF }, /* R1168 - AIF1 DAC1 EQ Band 4 PG */ + { 0xFFFF, 0xFFFF }, /* R1169 - AIF1 DAC1 EQ Band 5 A */ + { 0xFFFF, 0xFFFF }, /* R1170 - AIF1 DAC1 EQ Band 5 B */ + { 0xFFFF, 0xFFFF }, /* R1171 - AIF1 DAC1 EQ Band 5 PG */ + { 0x0000, 0x0000 }, /* R1172 */ + { 0x0000, 0x0000 }, /* R1173 */ + { 0x0000, 0x0000 }, /* R1174 */ + { 0x0000, 0x0000 }, /* R1175 */ + { 0x0000, 0x0000 }, /* R1176 */ + { 0x0000, 0x0000 }, /* R1177 */ + { 0x0000, 0x0000 }, /* R1178 */ + { 0x0000, 0x0000 }, /* R1179 */ + { 0x0000, 0x0000 }, /* R1180 */ + { 0x0000, 0x0000 }, /* R1181 */ + { 0x0000, 0x0000 }, /* R1182 */ + { 0x0000, 0x0000 }, /* R1183 */ + { 0xFFFF, 0xFFFF }, /* R1184 - AIF1 DAC2 EQ Gains (1) */ + { 0xFFC0, 0xFFC0 }, /* R1185 - AIF1 DAC2 EQ Gains (2) */ + { 0xFFFF, 0xFFFF }, /* R1186 - AIF1 DAC2 EQ Band 1 A */ + { 0xFFFF, 0xFFFF }, /* R1187 - AIF1 DAC2 EQ Band 1 B */ + { 0xFFFF, 0xFFFF }, /* R1188 - AIF1 DAC2 EQ Band 1 PG */ + { 0xFFFF, 0xFFFF }, /* R1189 - AIF1 DAC2 EQ Band 2 A */ + { 0xFFFF, 0xFFFF }, /* R1190 - AIF1 DAC2 EQ Band 2 B */ + { 0xFFFF, 0xFFFF }, /* R1191 - AIF1 DAC2 EQ Band 2 C */ + { 0xFFFF, 0xFFFF }, /* R1192 - AIF1 DAC2 EQ Band 2 PG */ + { 0xFFFF, 0xFFFF }, /* R1193 - AIF1 DAC2 EQ Band 3 A */ + { 0xFFFF, 0xFFFF }, /* R1194 - AIF1 DAC2 EQ Band 3 B */ + { 0xFFFF, 0xFFFF }, /* R1195 - AIF1 DAC2 EQ Band 3 C */ + { 0xFFFF, 0xFFFF }, /* R1196 - AIF1 DAC2 EQ Band 3 PG */ + { 0xFFFF, 0xFFFF }, /* R1197 - AIF1 DAC2 EQ Band 4 A */ + { 0xFFFF, 0xFFFF }, /* R1198 - AIF1 DAC2 EQ Band 4 B */ + { 0xFFFF, 0xFFFF }, /* R1199 - AIF1 DAC2 EQ Band 4 C */ + { 0xFFFF, 0xFFFF }, /* R1200 - AIF1 DAC2 EQ Band 4 PG */ + { 0xFFFF, 0xFFFF }, /* R1201 - AIF1 DAC2 EQ Band 5 A */ + { 0xFFFF, 0xFFFF }, /* R1202 - AIF1 DAC2 EQ Band 5 B */ + { 0xFFFF, 0xFFFF }, /* R1203 - AIF1 DAC2 EQ Band 5 PG */ + { 0x0000, 0x0000 }, /* R1204 */ + { 0x0000, 0x0000 }, /* R1205 */ + { 0x0000, 0x0000 }, /* R1206 */ + { 0x0000, 0x0000 }, /* R1207 */ + { 0x0000, 0x0000 }, /* R1208 */ + { 0x0000, 0x0000 }, /* R1209 */ + { 0x0000, 0x0000 }, /* R1210 */ + { 0x0000, 0x0000 }, /* R1211 */ + { 0x0000, 0x0000 }, /* R1212 */ + { 0x0000, 0x0000 }, /* R1213 */ + { 0x0000, 0x0000 }, /* R1214 */ + { 0x0000, 0x0000 }, /* R1215 */ + { 0x0000, 0x0000 }, /* R1216 */ + { 0x0000, 0x0000 }, /* R1217 */ + { 0x0000, 0x0000 }, /* R1218 */ + { 0x0000, 0x0000 }, /* R1219 */ + { 0x0000, 0x0000 }, /* R1220 */ + { 0x0000, 0x0000 }, /* R1221 */ + { 0x0000, 0x0000 }, /* R1222 */ + { 0x0000, 0x0000 }, /* R1223 */ + { 0x0000, 0x0000 }, /* R1224 */ + { 0x0000, 0x0000 }, /* R1225 */ + { 0x0000, 0x0000 }, /* R1226 */ + { 0x0000, 0x0000 }, /* R1227 */ + { 0x0000, 0x0000 }, /* R1228 */ + { 0x0000, 0x0000 }, /* R1229 */ + { 0x0000, 0x0000 }, /* R1230 */ + { 0x0000, 0x0000 }, /* R1231 */ + { 0x0000, 0x0000 }, /* R1232 */ + { 0x0000, 0x0000 }, /* R1233 */ + { 0x0000, 0x0000 }, /* R1234 */ + { 0x0000, 0x0000 }, /* R1235 */ + { 0x0000, 0x0000 }, /* R1236 */ + { 0x0000, 0x0000 }, /* R1237 */ + { 0x0000, 0x0000 }, /* R1238 */ + { 0x0000, 0x0000 }, /* R1239 */ + { 0x0000, 0x0000 }, /* R1240 */ + { 0x0000, 0x0000 }, /* R1241 */ + { 0x0000, 0x0000 }, /* R1242 */ + { 0x0000, 0x0000 }, /* R1243 */ + { 0x0000, 0x0000 }, /* R1244 */ + { 0x0000, 0x0000 }, /* R1245 */ + { 0x0000, 0x0000 }, /* R1246 */ + { 0x0000, 0x0000 }, /* R1247 */ + { 0x0000, 0x0000 }, /* R1248 */ + { 0x0000, 0x0000 }, /* R1249 */ + { 0x0000, 0x0000 }, /* R1250 */ + { 0x0000, 0x0000 }, /* R1251 */ + { 0x0000, 0x0000 }, /* R1252 */ + { 0x0000, 0x0000 }, /* R1253 */ + { 0x0000, 0x0000 }, /* R1254 */ + { 0x0000, 0x0000 }, /* R1255 */ + { 0x0000, 0x0000 }, /* R1256 */ + { 0x0000, 0x0000 }, /* R1257 */ + { 0x0000, 0x0000 }, /* R1258 */ + { 0x0000, 0x0000 }, /* R1259 */ + { 0x0000, 0x0000 }, /* R1260 */ + { 0x0000, 0x0000 }, /* R1261 */ + { 0x0000, 0x0000 }, /* R1262 */ + { 0x0000, 0x0000 }, /* R1263 */ + { 0x0000, 0x0000 }, /* R1264 */ + { 0x0000, 0x0000 }, /* R1265 */ + { 0x0000, 0x0000 }, /* R1266 */ + { 0x0000, 0x0000 }, /* R1267 */ + { 0x0000, 0x0000 }, /* R1268 */ + { 0x0000, 0x0000 }, /* R1269 */ + { 0x0000, 0x0000 }, /* R1270 */ + { 0x0000, 0x0000 }, /* R1271 */ + { 0x0000, 0x0000 }, /* R1272 */ + { 0x0000, 0x0000 }, /* R1273 */ + { 0x0000, 0x0000 }, /* R1274 */ + { 0x0000, 0x0000 }, /* R1275 */ + { 0x0000, 0x0000 }, /* R1276 */ + { 0x0000, 0x0000 }, /* R1277 */ + { 0x0000, 0x0000 }, /* R1278 */ + { 0x0000, 0x0000 }, /* R1279 */ + { 0x00FF, 0x01FF }, /* R1280 - AIF2 ADC Left Volume */ + { 0x00FF, 0x01FF }, /* R1281 - AIF2 ADC Right Volume */ + { 0x00FF, 0x01FF }, /* R1282 - AIF2 DAC Left Volume */ + { 0x00FF, 0x01FF }, /* R1283 - AIF2 DAC Right Volume */ + { 0x0000, 0x0000 }, /* R1284 */ + { 0x0000, 0x0000 }, /* R1285 */ + { 0x0000, 0x0000 }, /* R1286 */ + { 0x0000, 0x0000 }, /* R1287 */ + { 0x0000, 0x0000 }, /* R1288 */ + { 0x0000, 0x0000 }, /* R1289 */ + { 0x0000, 0x0000 }, /* R1290 */ + { 0x0000, 0x0000 }, /* R1291 */ + { 0x0000, 0x0000 }, /* R1292 */ + { 0x0000, 0x0000 }, /* R1293 */ + { 0x0000, 0x0000 }, /* R1294 */ + { 0x0000, 0x0000 }, /* R1295 */ + { 0xF800, 0xF800 }, /* R1296 - AIF2 ADC Filters */ + { 0x0000, 0x0000 }, /* R1297 */ + { 0x0000, 0x0000 }, /* R1298 */ + { 0x0000, 0x0000 }, /* R1299 */ + { 0x0000, 0x0000 }, /* R1300 */ + { 0x0000, 0x0000 }, /* R1301 */ + { 0x0000, 0x0000 }, /* R1302 */ + { 0x0000, 0x0000 }, /* R1303 */ + { 0x0000, 0x0000 }, /* R1304 */ + { 0x0000, 0x0000 }, /* R1305 */ + { 0x0000, 0x0000 }, /* R1306 */ + { 0x0000, 0x0000 }, /* R1307 */ + { 0x0000, 0x0000 }, /* R1308 */ + { 0x0000, 0x0000 }, /* R1309 */ + { 0x0000, 0x0000 }, /* R1310 */ + { 0x0000, 0x0000 }, /* R1311 */ + { 0x02B6, 0x02B6 }, /* R1312 - AIF2 DAC Filters (1) */ + { 0x3F00, 0x3F00 }, /* R1313 - AIF2 DAC Filters (2) */ + { 0x0000, 0x0000 }, /* R1314 */ + { 0x0000, 0x0000 }, /* R1315 */ + { 0x0000, 0x0000 }, /* R1316 */ + { 0x0000, 0x0000 }, /* R1317 */ + { 0x0000, 0x0000 }, /* R1318 */ + { 0x0000, 0x0000 }, /* R1319 */ + { 0x0000, 0x0000 }, /* R1320 */ + { 0x0000, 0x0000 }, /* R1321 */ + { 0x0000, 0x0000 }, /* R1322 */ + { 0x0000, 0x0000 }, /* R1323 */ + { 0x0000, 0x0000 }, /* R1324 */ + { 0x0000, 0x0000 }, /* R1325 */ + { 0x0000, 0x0000 }, /* R1326 */ + { 0x0000, 0x0000 }, /* R1327 */ + { 0x0000, 0x0000 }, /* R1328 */ + { 0x0000, 0x0000 }, /* R1329 */ + { 0x0000, 0x0000 }, /* R1330 */ + { 0x0000, 0x0000 }, /* R1331 */ + { 0x0000, 0x0000 }, /* R1332 */ + { 0x0000, 0x0000 }, /* R1333 */ + { 0x0000, 0x0000 }, /* R1334 */ + { 0x0000, 0x0000 }, /* R1335 */ + { 0x0000, 0x0000 }, /* R1336 */ + { 0x0000, 0x0000 }, /* R1337 */ + { 0x0000, 0x0000 }, /* R1338 */ + { 0x0000, 0x0000 }, /* R1339 */ + { 0x0000, 0x0000 }, /* R1340 */ + { 0x0000, 0x0000 }, /* R1341 */ + { 0x0000, 0x0000 }, /* R1342 */ + { 0x0000, 0x0000 }, /* R1343 */ + { 0xFFFF, 0xFFFF }, /* R1344 - AIF2 DRC (1) */ + { 0x1FFF, 0x1FFF }, /* R1345 - AIF2 DRC (2) */ + { 0xFFFF, 0xFFFF }, /* R1346 - AIF2 DRC (3) */ + { 0x07FF, 0x07FF }, /* R1347 - AIF2 DRC (4) */ + { 0x03FF, 0x03FF }, /* R1348 - AIF2 DRC (5) */ + { 0x0000, 0x0000 }, /* R1349 */ + { 0x0000, 0x0000 }, /* R1350 */ + { 0x0000, 0x0000 }, /* R1351 */ + { 0x0000, 0x0000 }, /* R1352 */ + { 0x0000, 0x0000 }, /* R1353 */ + { 0x0000, 0x0000 }, /* R1354 */ + { 0x0000, 0x0000 }, /* R1355 */ + { 0x0000, 0x0000 }, /* R1356 */ + { 0x0000, 0x0000 }, /* R1357 */ + { 0x0000, 0x0000 }, /* R1358 */ + { 0x0000, 0x0000 }, /* R1359 */ + { 0x0000, 0x0000 }, /* R1360 */ + { 0x0000, 0x0000 }, /* R1361 */ + { 0x0000, 0x0000 }, /* R1362 */ + { 0x0000, 0x0000 }, /* R1363 */ + { 0x0000, 0x0000 }, /* R1364 */ + { 0x0000, 0x0000 }, /* R1365 */ + { 0x0000, 0x0000 }, /* R1366 */ + { 0x0000, 0x0000 }, /* R1367 */ + { 0x0000, 0x0000 }, /* R1368 */ + { 0x0000, 0x0000 }, /* R1369 */ + { 0x0000, 0x0000 }, /* R1370 */ + { 0x0000, 0x0000 }, /* R1371 */ + { 0x0000, 0x0000 }, /* R1372 */ + { 0x0000, 0x0000 }, /* R1373 */ + { 0x0000, 0x0000 }, /* R1374 */ + { 0x0000, 0x0000 }, /* R1375 */ + { 0x0000, 0x0000 }, /* R1376 */ + { 0x0000, 0x0000 }, /* R1377 */ + { 0x0000, 0x0000 }, /* R1378 */ + { 0x0000, 0x0000 }, /* R1379 */ + { 0x0000, 0x0000 }, /* R1380 */ + { 0x0000, 0x0000 }, /* R1381 */ + { 0x0000, 0x0000 }, /* R1382 */ + { 0x0000, 0x0000 }, /* R1383 */ + { 0x0000, 0x0000 }, /* R1384 */ + { 0x0000, 0x0000 }, /* R1385 */ + { 0x0000, 0x0000 }, /* R1386 */ + { 0x0000, 0x0000 }, /* R1387 */ + { 0x0000, 0x0000 }, /* R1388 */ + { 0x0000, 0x0000 }, /* R1389 */ + { 0x0000, 0x0000 }, /* R1390 */ + { 0x0000, 0x0000 }, /* R1391 */ + { 0x0000, 0x0000 }, /* R1392 */ + { 0x0000, 0x0000 }, /* R1393 */ + { 0x0000, 0x0000 }, /* R1394 */ + { 0x0000, 0x0000 }, /* R1395 */ + { 0x0000, 0x0000 }, /* R1396 */ + { 0x0000, 0x0000 }, /* R1397 */ + { 0x0000, 0x0000 }, /* R1398 */ + { 0x0000, 0x0000 }, /* R1399 */ + { 0x0000, 0x0000 }, /* R1400 */ + { 0x0000, 0x0000 }, /* R1401 */ + { 0x0000, 0x0000 }, /* R1402 */ + { 0x0000, 0x0000 }, /* R1403 */ + { 0x0000, 0x0000 }, /* R1404 */ + { 0x0000, 0x0000 }, /* R1405 */ + { 0x0000, 0x0000 }, /* R1406 */ + { 0x0000, 0x0000 }, /* R1407 */ + { 0xFFFF, 0xFFFF }, /* R1408 - AIF2 EQ Gains (1) */ + { 0xFFC0, 0xFFC0 }, /* R1409 - AIF2 EQ Gains (2) */ + { 0xFFFF, 0xFFFF }, /* R1410 - AIF2 EQ Band 1 A */ + { 0xFFFF, 0xFFFF }, /* R1411 - AIF2 EQ Band 1 B */ + { 0xFFFF, 0xFFFF }, /* R1412 - AIF2 EQ Band 1 PG */ + { 0xFFFF, 0xFFFF }, /* R1413 - AIF2 EQ Band 2 A */ + { 0xFFFF, 0xFFFF }, /* R1414 - AIF2 EQ Band 2 B */ + { 0xFFFF, 0xFFFF }, /* R1415 - AIF2 EQ Band 2 C */ + { 0xFFFF, 0xFFFF }, /* R1416 - AIF2 EQ Band 2 PG */ + { 0xFFFF, 0xFFFF }, /* R1417 - AIF2 EQ Band 3 A */ + { 0xFFFF, 0xFFFF }, /* R1418 - AIF2 EQ Band 3 B */ + { 0xFFFF, 0xFFFF }, /* R1419 - AIF2 EQ Band 3 C */ + { 0xFFFF, 0xFFFF }, /* R1420 - AIF2 EQ Band 3 PG */ + { 0xFFFF, 0xFFFF }, /* R1421 - AIF2 EQ Band 4 A */ + { 0xFFFF, 0xFFFF }, /* R1422 - AIF2 EQ Band 4 B */ + { 0xFFFF, 0xFFFF }, /* R1423 - AIF2 EQ Band 4 C */ + { 0xFFFF, 0xFFFF }, /* R1424 - AIF2 EQ Band 4 PG */ + { 0xFFFF, 0xFFFF }, /* R1425 - AIF2 EQ Band 5 A */ + { 0xFFFF, 0xFFFF }, /* R1426 - AIF2 EQ Band 5 B */ + { 0xFFFF, 0xFFFF }, /* R1427 - AIF2 EQ Band 5 PG */ + { 0x0000, 0x0000 }, /* R1428 */ + { 0x0000, 0x0000 }, /* R1429 */ + { 0x0000, 0x0000 }, /* R1430 */ + { 0x0000, 0x0000 }, /* R1431 */ + { 0x0000, 0x0000 }, /* R1432 */ + { 0x0000, 0x0000 }, /* R1433 */ + { 0x0000, 0x0000 }, /* R1434 */ + { 0x0000, 0x0000 }, /* R1435 */ + { 0x0000, 0x0000 }, /* R1436 */ + { 0x0000, 0x0000 }, /* R1437 */ + { 0x0000, 0x0000 }, /* R1438 */ + { 0x0000, 0x0000 }, /* R1439 */ + { 0x0000, 0x0000 }, /* R1440 */ + { 0x0000, 0x0000 }, /* R1441 */ + { 0x0000, 0x0000 }, /* R1442 */ + { 0x0000, 0x0000 }, /* R1443 */ + { 0x0000, 0x0000 }, /* R1444 */ + { 0x0000, 0x0000 }, /* R1445 */ + { 0x0000, 0x0000 }, /* R1446 */ + { 0x0000, 0x0000 }, /* R1447 */ + { 0x0000, 0x0000 }, /* R1448 */ + { 0x0000, 0x0000 }, /* R1449 */ + { 0x0000, 0x0000 }, /* R1450 */ + { 0x0000, 0x0000 }, /* R1451 */ + { 0x0000, 0x0000 }, /* R1452 */ + { 0x0000, 0x0000 }, /* R1453 */ + { 0x0000, 0x0000 }, /* R1454 */ + { 0x0000, 0x0000 }, /* R1455 */ + { 0x0000, 0x0000 }, /* R1456 */ + { 0x0000, 0x0000 }, /* R1457 */ + { 0x0000, 0x0000 }, /* R1458 */ + { 0x0000, 0x0000 }, /* R1459 */ + { 0x0000, 0x0000 }, /* R1460 */ + { 0x0000, 0x0000 }, /* R1461 */ + { 0x0000, 0x0000 }, /* R1462 */ + { 0x0000, 0x0000 }, /* R1463 */ + { 0x0000, 0x0000 }, /* R1464 */ + { 0x0000, 0x0000 }, /* R1465 */ + { 0x0000, 0x0000 }, /* R1466 */ + { 0x0000, 0x0000 }, /* R1467 */ + { 0x0000, 0x0000 }, /* R1468 */ + { 0x0000, 0x0000 }, /* R1469 */ + { 0x0000, 0x0000 }, /* R1470 */ + { 0x0000, 0x0000 }, /* R1471 */ + { 0x0000, 0x0000 }, /* R1472 */ + { 0x0000, 0x0000 }, /* R1473 */ + { 0x0000, 0x0000 }, /* R1474 */ + { 0x0000, 0x0000 }, /* R1475 */ + { 0x0000, 0x0000 }, /* R1476 */ + { 0x0000, 0x0000 }, /* R1477 */ + { 0x0000, 0x0000 }, /* R1478 */ + { 0x0000, 0x0000 }, /* R1479 */ + { 0x0000, 0x0000 }, /* R1480 */ + { 0x0000, 0x0000 }, /* R1481 */ + { 0x0000, 0x0000 }, /* R1482 */ + { 0x0000, 0x0000 }, /* R1483 */ + { 0x0000, 0x0000 }, /* R1484 */ + { 0x0000, 0x0000 }, /* R1485 */ + { 0x0000, 0x0000 }, /* R1486 */ + { 0x0000, 0x0000 }, /* R1487 */ + { 0x0000, 0x0000 }, /* R1488 */ + { 0x0000, 0x0000 }, /* R1489 */ + { 0x0000, 0x0000 }, /* R1490 */ + { 0x0000, 0x0000 }, /* R1491 */ + { 0x0000, 0x0000 }, /* R1492 */ + { 0x0000, 0x0000 }, /* R1493 */ + { 0x0000, 0x0000 }, /* R1494 */ + { 0x0000, 0x0000 }, /* R1495 */ + { 0x0000, 0x0000 }, /* R1496 */ + { 0x0000, 0x0000 }, /* R1497 */ + { 0x0000, 0x0000 }, /* R1498 */ + { 0x0000, 0x0000 }, /* R1499 */ + { 0x0000, 0x0000 }, /* R1500 */ + { 0x0000, 0x0000 }, /* R1501 */ + { 0x0000, 0x0000 }, /* R1502 */ + { 0x0000, 0x0000 }, /* R1503 */ + { 0x0000, 0x0000 }, /* R1504 */ + { 0x0000, 0x0000 }, /* R1505 */ + { 0x0000, 0x0000 }, /* R1506 */ + { 0x0000, 0x0000 }, /* R1507 */ + { 0x0000, 0x0000 }, /* R1508 */ + { 0x0000, 0x0000 }, /* R1509 */ + { 0x0000, 0x0000 }, /* R1510 */ + { 0x0000, 0x0000 }, /* R1511 */ + { 0x0000, 0x0000 }, /* R1512 */ + { 0x0000, 0x0000 }, /* R1513 */ + { 0x0000, 0x0000 }, /* R1514 */ + { 0x0000, 0x0000 }, /* R1515 */ + { 0x0000, 0x0000 }, /* R1516 */ + { 0x0000, 0x0000 }, /* R1517 */ + { 0x0000, 0x0000 }, /* R1518 */ + { 0x0000, 0x0000 }, /* R1519 */ + { 0x0000, 0x0000 }, /* R1520 */ + { 0x0000, 0x0000 }, /* R1521 */ + { 0x0000, 0x0000 }, /* R1522 */ + { 0x0000, 0x0000 }, /* R1523 */ + { 0x0000, 0x0000 }, /* R1524 */ + { 0x0000, 0x0000 }, /* R1525 */ + { 0x0000, 0x0000 }, /* R1526 */ + { 0x0000, 0x0000 }, /* R1527 */ + { 0x0000, 0x0000 }, /* R1528 */ + { 0x0000, 0x0000 }, /* R1529 */ + { 0x0000, 0x0000 }, /* R1530 */ + { 0x0000, 0x0000 }, /* R1531 */ + { 0x0000, 0x0000 }, /* R1532 */ + { 0x0000, 0x0000 }, /* R1533 */ + { 0x0000, 0x0000 }, /* R1534 */ + { 0x0000, 0x0000 }, /* R1535 */ + { 0x01EF, 0x01EF }, /* R1536 - DAC1 Mixer Volumes */ + { 0x0037, 0x0037 }, /* R1537 - DAC1 Left Mixer Routing */ + { 0x0037, 0x0037 }, /* R1538 - DAC1 Right Mixer Routing */ + { 0x01EF, 0x01EF }, /* R1539 - DAC2 Mixer Volumes */ + { 0x0037, 0x0037 }, /* R1540 - DAC2 Left Mixer Routing */ + { 0x0037, 0x0037 }, /* R1541 - DAC2 Right Mixer Routing */ + { 0x0003, 0x0003 }, /* R1542 - AIF1 ADC1 Left Mixer Routing */ + { 0x0003, 0x0003 }, /* R1543 - AIF1 ADC1 Right Mixer Routing */ + { 0x0003, 0x0003 }, /* R1544 - AIF1 ADC2 Left Mixer Routing */ + { 0x0003, 0x0003 }, /* R1545 - AIF1 ADC2 Right mixer Routing */ + { 0x0000, 0x0000 }, /* R1546 */ + { 0x0000, 0x0000 }, /* R1547 */ + { 0x0000, 0x0000 }, /* R1548 */ + { 0x0000, 0x0000 }, /* R1549 */ + { 0x0000, 0x0000 }, /* R1550 */ + { 0x0000, 0x0000 }, /* R1551 */ + { 0x02FF, 0x03FF }, /* R1552 - DAC1 Left Volume */ + { 0x02FF, 0x03FF }, /* R1553 - DAC1 Right Volume */ + { 0x02FF, 0x03FF }, /* R1554 - DAC2 Left Volume */ + { 0x02FF, 0x03FF }, /* R1555 - DAC2 Right Volume */ + { 0x0003, 0x0003 }, /* R1556 - DAC Softmute */ + { 0x0000, 0x0000 }, /* R1557 */ + { 0x0000, 0x0000 }, /* R1558 */ + { 0x0000, 0x0000 }, /* R1559 */ + { 0x0000, 0x0000 }, /* R1560 */ + { 0x0000, 0x0000 }, /* R1561 */ + { 0x0000, 0x0000 }, /* R1562 */ + { 0x0000, 0x0000 }, /* R1563 */ + { 0x0000, 0x0000 }, /* R1564 */ + { 0x0000, 0x0000 }, /* R1565 */ + { 0x0000, 0x0000 }, /* R1566 */ + { 0x0000, 0x0000 }, /* R1567 */ + { 0x0003, 0x0003 }, /* R1568 - Oversampling */ + { 0x03C3, 0x03C3 }, /* R1569 - Sidetone */ +}; + diff --git a/sound/soc/codecs/wm8994.c b/sound/soc/codecs/wm8994.c index 7d2f488de6a7..189f00079d31 100644 --- a/sound/soc/codecs/wm8994.c +++ b/sound/soc/codecs/wm8994.c @@ -98,1582 +98,6 @@ struct wm8994_priv { struct wm8994_pdata *pdata; }; -static const struct { - unsigned short readable; /* Mask of readable bits */ - unsigned short writable; /* Mask of writable bits */ -} access_masks[] = { - { 0xFFFF, 0xFFFF }, /* R0 - Software Reset */ - { 0x3B37, 0x3B37 }, /* R1 - Power Management (1) */ - { 0x6BF0, 0x6BF0 }, /* R2 - Power Management (2) */ - { 0x3FF0, 0x3FF0 }, /* R3 - Power Management (3) */ - { 0x3F3F, 0x3F3F }, /* R4 - Power Management (4) */ - { 0x3F0F, 0x3F0F }, /* R5 - Power Management (5) */ - { 0x003F, 0x003F }, /* R6 - Power Management (6) */ - { 0x0000, 0x0000 }, /* R7 */ - { 0x0000, 0x0000 }, /* R8 */ - { 0x0000, 0x0000 }, /* R9 */ - { 0x0000, 0x0000 }, /* R10 */ - { 0x0000, 0x0000 }, /* R11 */ - { 0x0000, 0x0000 }, /* R12 */ - { 0x0000, 0x0000 }, /* R13 */ - { 0x0000, 0x0000 }, /* R14 */ - { 0x0000, 0x0000 }, /* R15 */ - { 0x0000, 0x0000 }, /* R16 */ - { 0x0000, 0x0000 }, /* R17 */ - { 0x0000, 0x0000 }, /* R18 */ - { 0x0000, 0x0000 }, /* R19 */ - { 0x0000, 0x0000 }, /* R20 */ - { 0x01C0, 0x01C0 }, /* R21 - Input Mixer (1) */ - { 0x0000, 0x0000 }, /* R22 */ - { 0x0000, 0x0000 }, /* R23 */ - { 0x00DF, 0x01DF }, /* R24 - Left Line Input 1&2 Volume */ - { 0x00DF, 0x01DF }, /* R25 - Left Line Input 3&4 Volume */ - { 0x00DF, 0x01DF }, /* R26 - Right Line Input 1&2 Volume */ - { 0x00DF, 0x01DF }, /* R27 - Right Line Input 3&4 Volume */ - { 0x00FF, 0x01FF }, /* R28 - Left Output Volume */ - { 0x00FF, 0x01FF }, /* R29 - Right Output Volume */ - { 0x0077, 0x0077 }, /* R30 - Line Outputs Volume */ - { 0x0030, 0x0030 }, /* R31 - HPOUT2 Volume */ - { 0x00FF, 0x01FF }, /* R32 - Left OPGA Volume */ - { 0x00FF, 0x01FF }, /* R33 - Right OPGA Volume */ - { 0x007F, 0x007F }, /* R34 - SPKMIXL Attenuation */ - { 0x017F, 0x017F }, /* R35 - SPKMIXR Attenuation */ - { 0x003F, 0x003F }, /* R36 - SPKOUT Mixers */ - { 0x003F, 0x003F }, /* R37 - ClassD */ - { 0x00FF, 0x01FF }, /* R38 - Speaker Volume Left */ - { 0x00FF, 0x01FF }, /* R39 - Speaker Volume Right */ - { 0x00FF, 0x00FF }, /* R40 - Input Mixer (2) */ - { 0x01B7, 0x01B7 }, /* R41 - Input Mixer (3) */ - { 0x01B7, 0x01B7 }, /* R42 - Input Mixer (4) */ - { 0x01C7, 0x01C7 }, /* R43 - Input Mixer (5) */ - { 0x01C7, 0x01C7 }, /* R44 - Input Mixer (6) */ - { 0x01FF, 0x01FF }, /* R45 - Output Mixer (1) */ - { 0x01FF, 0x01FF }, /* R46 - Output Mixer (2) */ - { 0x0FFF, 0x0FFF }, /* R47 - Output Mixer (3) */ - { 0x0FFF, 0x0FFF }, /* R48 - Output Mixer (4) */ - { 0x0FFF, 0x0FFF }, /* R49 - Output Mixer (5) */ - { 0x0FFF, 0x0FFF }, /* R50 - Output Mixer (6) */ - { 0x0038, 0x0038 }, /* R51 - HPOUT2 Mixer */ - { 0x0077, 0x0077 }, /* R52 - Line Mixer (1) */ - { 0x0077, 0x0077 }, /* R53 - Line Mixer (2) */ - { 0x03FF, 0x03FF }, /* R54 - Speaker Mixer */ - { 0x00C1, 0x00C1 }, /* R55 - Additional Control */ - { 0x00F0, 0x00F0 }, /* R56 - AntiPOP (1) */ - { 0x01EF, 0x01EF }, /* R57 - AntiPOP (2) */ - { 0x00FF, 0x00FF }, /* R58 - MICBIAS */ - { 0x000F, 0x000F }, /* R59 - LDO 1 */ - { 0x0007, 0x0007 }, /* R60 - LDO 2 */ - { 0x0000, 0x0000 }, /* R61 */ - { 0x0000, 0x0000 }, /* R62 */ - { 0x0000, 0x0000 }, /* R63 */ - { 0x0000, 0x0000 }, /* R64 */ - { 0x0000, 0x0000 }, /* R65 */ - { 0x0000, 0x0000 }, /* R66 */ - { 0x0000, 0x0000 }, /* R67 */ - { 0x0000, 0x0000 }, /* R68 */ - { 0x0000, 0x0000 }, /* R69 */ - { 0x0000, 0x0000 }, /* R70 */ - { 0x0000, 0x0000 }, /* R71 */ - { 0x0000, 0x0000 }, /* R72 */ - { 0x0000, 0x0000 }, /* R73 */ - { 0x0000, 0x0000 }, /* R74 */ - { 0x0000, 0x0000 }, /* R75 */ - { 0x8000, 0x8000 }, /* R76 - Charge Pump (1) */ - { 0x0000, 0x0000 }, /* R77 */ - { 0x0000, 0x0000 }, /* R78 */ - { 0x0000, 0x0000 }, /* R79 */ - { 0x0000, 0x0000 }, /* R80 */ - { 0x0301, 0x0301 }, /* R81 - Class W (1) */ - { 0x0000, 0x0000 }, /* R82 */ - { 0x0000, 0x0000 }, /* R83 */ - { 0x333F, 0x333F }, /* R84 - DC Servo (1) */ - { 0x0FEF, 0x0FEF }, /* R85 - DC Servo (2) */ - { 0x0000, 0x0000 }, /* R86 */ - { 0xFFFF, 0xFFFF }, /* R87 - DC Servo (4) */ - { 0x0333, 0x0000 }, /* R88 - DC Servo Readback */ - { 0x0000, 0x0000 }, /* R89 */ - { 0x0000, 0x0000 }, /* R90 */ - { 0x0000, 0x0000 }, /* R91 */ - { 0x0000, 0x0000 }, /* R92 */ - { 0x0000, 0x0000 }, /* R93 */ - { 0x0000, 0x0000 }, /* R94 */ - { 0x0000, 0x0000 }, /* R95 */ - { 0x00EE, 0x00EE }, /* R96 - Analogue HP (1) */ - { 0x0000, 0x0000 }, /* R97 */ - { 0x0000, 0x0000 }, /* R98 */ - { 0x0000, 0x0000 }, /* R99 */ - { 0x0000, 0x0000 }, /* R100 */ - { 0x0000, 0x0000 }, /* R101 */ - { 0x0000, 0x0000 }, /* R102 */ - { 0x0000, 0x0000 }, /* R103 */ - { 0x0000, 0x0000 }, /* R104 */ - { 0x0000, 0x0000 }, /* R105 */ - { 0x0000, 0x0000 }, /* R106 */ - { 0x0000, 0x0000 }, /* R107 */ - { 0x0000, 0x0000 }, /* R108 */ - { 0x0000, 0x0000 }, /* R109 */ - { 0x0000, 0x0000 }, /* R110 */ - { 0x0000, 0x0000 }, /* R111 */ - { 0x0000, 0x0000 }, /* R112 */ - { 0x0000, 0x0000 }, /* R113 */ - { 0x0000, 0x0000 }, /* R114 */ - { 0x0000, 0x0000 }, /* R115 */ - { 0x0000, 0x0000 }, /* R116 */ - { 0x0000, 0x0000 }, /* R117 */ - { 0x0000, 0x0000 }, /* R118 */ - { 0x0000, 0x0000 }, /* R119 */ - { 0x0000, 0x0000 }, /* R120 */ - { 0x0000, 0x0000 }, /* R121 */ - { 0x0000, 0x0000 }, /* R122 */ - { 0x0000, 0x0000 }, /* R123 */ - { 0x0000, 0x0000 }, /* R124 */ - { 0x0000, 0x0000 }, /* R125 */ - { 0x0000, 0x0000 }, /* R126 */ - { 0x0000, 0x0000 }, /* R127 */ - { 0x0000, 0x0000 }, /* R128 */ - { 0x0000, 0x0000 }, /* R129 */ - { 0x0000, 0x0000 }, /* R130 */ - { 0x0000, 0x0000 }, /* R131 */ - { 0x0000, 0x0000 }, /* R132 */ - { 0x0000, 0x0000 }, /* R133 */ - { 0x0000, 0x0000 }, /* R134 */ - { 0x0000, 0x0000 }, /* R135 */ - { 0x0000, 0x0000 }, /* R136 */ - { 0x0000, 0x0000 }, /* R137 */ - { 0x0000, 0x0000 }, /* R138 */ - { 0x0000, 0x0000 }, /* R139 */ - { 0x0000, 0x0000 }, /* R140 */ - { 0x0000, 0x0000 }, /* R141 */ - { 0x0000, 0x0000 }, /* R142 */ - { 0x0000, 0x0000 }, /* R143 */ - { 0x0000, 0x0000 }, /* R144 */ - { 0x0000, 0x0000 }, /* R145 */ - { 0x0000, 0x0000 }, /* R146 */ - { 0x0000, 0x0000 }, /* R147 */ - { 0x0000, 0x0000 }, /* R148 */ - { 0x0000, 0x0000 }, /* R149 */ - { 0x0000, 0x0000 }, /* R150 */ - { 0x0000, 0x0000 }, /* R151 */ - { 0x0000, 0x0000 }, /* R152 */ - { 0x0000, 0x0000 }, /* R153 */ - { 0x0000, 0x0000 }, /* R154 */ - { 0x0000, 0x0000 }, /* R155 */ - { 0x0000, 0x0000 }, /* R156 */ - { 0x0000, 0x0000 }, /* R157 */ - { 0x0000, 0x0000 }, /* R158 */ - { 0x0000, 0x0000 }, /* R159 */ - { 0x0000, 0x0000 }, /* R160 */ - { 0x0000, 0x0000 }, /* R161 */ - { 0x0000, 0x0000 }, /* R162 */ - { 0x0000, 0x0000 }, /* R163 */ - { 0x0000, 0x0000 }, /* R164 */ - { 0x0000, 0x0000 }, /* R165 */ - { 0x0000, 0x0000 }, /* R166 */ - { 0x0000, 0x0000 }, /* R167 */ - { 0x0000, 0x0000 }, /* R168 */ - { 0x0000, 0x0000 }, /* R169 */ - { 0x0000, 0x0000 }, /* R170 */ - { 0x0000, 0x0000 }, /* R171 */ - { 0x0000, 0x0000 }, /* R172 */ - { 0x0000, 0x0000 }, /* R173 */ - { 0x0000, 0x0000 }, /* R174 */ - { 0x0000, 0x0000 }, /* R175 */ - { 0x0000, 0x0000 }, /* R176 */ - { 0x0000, 0x0000 }, /* R177 */ - { 0x0000, 0x0000 }, /* R178 */ - { 0x0000, 0x0000 }, /* R179 */ - { 0x0000, 0x0000 }, /* R180 */ - { 0x0000, 0x0000 }, /* R181 */ - { 0x0000, 0x0000 }, /* R182 */ - { 0x0000, 0x0000 }, /* R183 */ - { 0x0000, 0x0000 }, /* R184 */ - { 0x0000, 0x0000 }, /* R185 */ - { 0x0000, 0x0000 }, /* R186 */ - { 0x0000, 0x0000 }, /* R187 */ - { 0x0000, 0x0000 }, /* R188 */ - { 0x0000, 0x0000 }, /* R189 */ - { 0x0000, 0x0000 }, /* R190 */ - { 0x0000, 0x0000 }, /* R191 */ - { 0x0000, 0x0000 }, /* R192 */ - { 0x0000, 0x0000 }, /* R193 */ - { 0x0000, 0x0000 }, /* R194 */ - { 0x0000, 0x0000 }, /* R195 */ - { 0x0000, 0x0000 }, /* R196 */ - { 0x0000, 0x0000 }, /* R197 */ - { 0x0000, 0x0000 }, /* R198 */ - { 0x0000, 0x0000 }, /* R199 */ - { 0x0000, 0x0000 }, /* R200 */ - { 0x0000, 0x0000 }, /* R201 */ - { 0x0000, 0x0000 }, /* R202 */ - { 0x0000, 0x0000 }, /* R203 */ - { 0x0000, 0x0000 }, /* R204 */ - { 0x0000, 0x0000 }, /* R205 */ - { 0x0000, 0x0000 }, /* R206 */ - { 0x0000, 0x0000 }, /* R207 */ - { 0x0000, 0x0000 }, /* R208 */ - { 0x0000, 0x0000 }, /* R209 */ - { 0x0000, 0x0000 }, /* R210 */ - { 0x0000, 0x0000 }, /* R211 */ - { 0x0000, 0x0000 }, /* R212 */ - { 0x0000, 0x0000 }, /* R213 */ - { 0x0000, 0x0000 }, /* R214 */ - { 0x0000, 0x0000 }, /* R215 */ - { 0x0000, 0x0000 }, /* R216 */ - { 0x0000, 0x0000 }, /* R217 */ - { 0x0000, 0x0000 }, /* R218 */ - { 0x0000, 0x0000 }, /* R219 */ - { 0x0000, 0x0000 }, /* R220 */ - { 0x0000, 0x0000 }, /* R221 */ - { 0x0000, 0x0000 }, /* R222 */ - { 0x0000, 0x0000 }, /* R223 */ - { 0x0000, 0x0000 }, /* R224 */ - { 0x0000, 0x0000 }, /* R225 */ - { 0x0000, 0x0000 }, /* R226 */ - { 0x0000, 0x0000 }, /* R227 */ - { 0x0000, 0x0000 }, /* R228 */ - { 0x0000, 0x0000 }, /* R229 */ - { 0x0000, 0x0000 }, /* R230 */ - { 0x0000, 0x0000 }, /* R231 */ - { 0x0000, 0x0000 }, /* R232 */ - { 0x0000, 0x0000 }, /* R233 */ - { 0x0000, 0x0000 }, /* R234 */ - { 0x0000, 0x0000 }, /* R235 */ - { 0x0000, 0x0000 }, /* R236 */ - { 0x0000, 0x0000 }, /* R237 */ - { 0x0000, 0x0000 }, /* R238 */ - { 0x0000, 0x0000 }, /* R239 */ - { 0x0000, 0x0000 }, /* R240 */ - { 0x0000, 0x0000 }, /* R241 */ - { 0x0000, 0x0000 }, /* R242 */ - { 0x0000, 0x0000 }, /* R243 */ - { 0x0000, 0x0000 }, /* R244 */ - { 0x0000, 0x0000 }, /* R245 */ - { 0x0000, 0x0000 }, /* R246 */ - { 0x0000, 0x0000 }, /* R247 */ - { 0x0000, 0x0000 }, /* R248 */ - { 0x0000, 0x0000 }, /* R249 */ - { 0x0000, 0x0000 }, /* R250 */ - { 0x0000, 0x0000 }, /* R251 */ - { 0x0000, 0x0000 }, /* R252 */ - { 0x0000, 0x0000 }, /* R253 */ - { 0x0000, 0x0000 }, /* R254 */ - { 0x0000, 0x0000 }, /* R255 */ - { 0x000F, 0x0000 }, /* R256 - Chip Revision */ - { 0x0074, 0x0074 }, /* R257 - Control Interface */ - { 0x0000, 0x0000 }, /* R258 */ - { 0x0000, 0x0000 }, /* R259 */ - { 0x0000, 0x0000 }, /* R260 */ - { 0x0000, 0x0000 }, /* R261 */ - { 0x0000, 0x0000 }, /* R262 */ - { 0x0000, 0x0000 }, /* R263 */ - { 0x0000, 0x0000 }, /* R264 */ - { 0x0000, 0x0000 }, /* R265 */ - { 0x0000, 0x0000 }, /* R266 */ - { 0x0000, 0x0000 }, /* R267 */ - { 0x0000, 0x0000 }, /* R268 */ - { 0x0000, 0x0000 }, /* R269 */ - { 0x0000, 0x0000 }, /* R270 */ - { 0x0000, 0x0000 }, /* R271 */ - { 0x807F, 0x837F }, /* R272 - Write Sequencer Ctrl (1) */ - { 0x017F, 0x0000 }, /* R273 - Write Sequencer Ctrl (2) */ - { 0x0000, 0x0000 }, /* R274 */ - { 0x0000, 0x0000 }, /* R275 */ - { 0x0000, 0x0000 }, /* R276 */ - { 0x0000, 0x0000 }, /* R277 */ - { 0x0000, 0x0000 }, /* R278 */ - { 0x0000, 0x0000 }, /* R279 */ - { 0x0000, 0x0000 }, /* R280 */ - { 0x0000, 0x0000 }, /* R281 */ - { 0x0000, 0x0000 }, /* R282 */ - { 0x0000, 0x0000 }, /* R283 */ - { 0x0000, 0x0000 }, /* R284 */ - { 0x0000, 0x0000 }, /* R285 */ - { 0x0000, 0x0000 }, /* R286 */ - { 0x0000, 0x0000 }, /* R287 */ - { 0x0000, 0x0000 }, /* R288 */ - { 0x0000, 0x0000 }, /* R289 */ - { 0x0000, 0x0000 }, /* R290 */ - { 0x0000, 0x0000 }, /* R291 */ - { 0x0000, 0x0000 }, /* R292 */ - { 0x0000, 0x0000 }, /* R293 */ - { 0x0000, 0x0000 }, /* R294 */ - { 0x0000, 0x0000 }, /* R295 */ - { 0x0000, 0x0000 }, /* R296 */ - { 0x0000, 0x0000 }, /* R297 */ - { 0x0000, 0x0000 }, /* R298 */ - { 0x0000, 0x0000 }, /* R299 */ - { 0x0000, 0x0000 }, /* R300 */ - { 0x0000, 0x0000 }, /* R301 */ - { 0x0000, 0x0000 }, /* R302 */ - { 0x0000, 0x0000 }, /* R303 */ - { 0x0000, 0x0000 }, /* R304 */ - { 0x0000, 0x0000 }, /* R305 */ - { 0x0000, 0x0000 }, /* R306 */ - { 0x0000, 0x0000 }, /* R307 */ - { 0x0000, 0x0000 }, /* R308 */ - { 0x0000, 0x0000 }, /* R309 */ - { 0x0000, 0x0000 }, /* R310 */ - { 0x0000, 0x0000 }, /* R311 */ - { 0x0000, 0x0000 }, /* R312 */ - { 0x0000, 0x0000 }, /* R313 */ - { 0x0000, 0x0000 }, /* R314 */ - { 0x0000, 0x0000 }, /* R315 */ - { 0x0000, 0x0000 }, /* R316 */ - { 0x0000, 0x0000 }, /* R317 */ - { 0x0000, 0x0000 }, /* R318 */ - { 0x0000, 0x0000 }, /* R319 */ - { 0x0000, 0x0000 }, /* R320 */ - { 0x0000, 0x0000 }, /* R321 */ - { 0x0000, 0x0000 }, /* R322 */ - { 0x0000, 0x0000 }, /* R323 */ - { 0x0000, 0x0000 }, /* R324 */ - { 0x0000, 0x0000 }, /* R325 */ - { 0x0000, 0x0000 }, /* R326 */ - { 0x0000, 0x0000 }, /* R327 */ - { 0x0000, 0x0000 }, /* R328 */ - { 0x0000, 0x0000 }, /* R329 */ - { 0x0000, 0x0000 }, /* R330 */ - { 0x0000, 0x0000 }, /* R331 */ - { 0x0000, 0x0000 }, /* R332 */ - { 0x0000, 0x0000 }, /* R333 */ - { 0x0000, 0x0000 }, /* R334 */ - { 0x0000, 0x0000 }, /* R335 */ - { 0x0000, 0x0000 }, /* R336 */ - { 0x0000, 0x0000 }, /* R337 */ - { 0x0000, 0x0000 }, /* R338 */ - { 0x0000, 0x0000 }, /* R339 */ - { 0x0000, 0x0000 }, /* R340 */ - { 0x0000, 0x0000 }, /* R341 */ - { 0x0000, 0x0000 }, /* R342 */ - { 0x0000, 0x0000 }, /* R343 */ - { 0x0000, 0x0000 }, /* R344 */ - { 0x0000, 0x0000 }, /* R345 */ - { 0x0000, 0x0000 }, /* R346 */ - { 0x0000, 0x0000 }, /* R347 */ - { 0x0000, 0x0000 }, /* R348 */ - { 0x0000, 0x0000 }, /* R349 */ - { 0x0000, 0x0000 }, /* R350 */ - { 0x0000, 0x0000 }, /* R351 */ - { 0x0000, 0x0000 }, /* R352 */ - { 0x0000, 0x0000 }, /* R353 */ - { 0x0000, 0x0000 }, /* R354 */ - { 0x0000, 0x0000 }, /* R355 */ - { 0x0000, 0x0000 }, /* R356 */ - { 0x0000, 0x0000 }, /* R357 */ - { 0x0000, 0x0000 }, /* R358 */ - { 0x0000, 0x0000 }, /* R359 */ - { 0x0000, 0x0000 }, /* R360 */ - { 0x0000, 0x0000 }, /* R361 */ - { 0x0000, 0x0000 }, /* R362 */ - { 0x0000, 0x0000 }, /* R363 */ - { 0x0000, 0x0000 }, /* R364 */ - { 0x0000, 0x0000 }, /* R365 */ - { 0x0000, 0x0000 }, /* R366 */ - { 0x0000, 0x0000 }, /* R367 */ - { 0x0000, 0x0000 }, /* R368 */ - { 0x0000, 0x0000 }, /* R369 */ - { 0x0000, 0x0000 }, /* R370 */ - { 0x0000, 0x0000 }, /* R371 */ - { 0x0000, 0x0000 }, /* R372 */ - { 0x0000, 0x0000 }, /* R373 */ - { 0x0000, 0x0000 }, /* R374 */ - { 0x0000, 0x0000 }, /* R375 */ - { 0x0000, 0x0000 }, /* R376 */ - { 0x0000, 0x0000 }, /* R377 */ - { 0x0000, 0x0000 }, /* R378 */ - { 0x0000, 0x0000 }, /* R379 */ - { 0x0000, 0x0000 }, /* R380 */ - { 0x0000, 0x0000 }, /* R381 */ - { 0x0000, 0x0000 }, /* R382 */ - { 0x0000, 0x0000 }, /* R383 */ - { 0x0000, 0x0000 }, /* R384 */ - { 0x0000, 0x0000 }, /* R385 */ - { 0x0000, 0x0000 }, /* R386 */ - { 0x0000, 0x0000 }, /* R387 */ - { 0x0000, 0x0000 }, /* R388 */ - { 0x0000, 0x0000 }, /* R389 */ - { 0x0000, 0x0000 }, /* R390 */ - { 0x0000, 0x0000 }, /* R391 */ - { 0x0000, 0x0000 }, /* R392 */ - { 0x0000, 0x0000 }, /* R393 */ - { 0x0000, 0x0000 }, /* R394 */ - { 0x0000, 0x0000 }, /* R395 */ - { 0x0000, 0x0000 }, /* R396 */ - { 0x0000, 0x0000 }, /* R397 */ - { 0x0000, 0x0000 }, /* R398 */ - { 0x0000, 0x0000 }, /* R399 */ - { 0x0000, 0x0000 }, /* R400 */ - { 0x0000, 0x0000 }, /* R401 */ - { 0x0000, 0x0000 }, /* R402 */ - { 0x0000, 0x0000 }, /* R403 */ - { 0x0000, 0x0000 }, /* R404 */ - { 0x0000, 0x0000 }, /* R405 */ - { 0x0000, 0x0000 }, /* R406 */ - { 0x0000, 0x0000 }, /* R407 */ - { 0x0000, 0x0000 }, /* R408 */ - { 0x0000, 0x0000 }, /* R409 */ - { 0x0000, 0x0000 }, /* R410 */ - { 0x0000, 0x0000 }, /* R411 */ - { 0x0000, 0x0000 }, /* R412 */ - { 0x0000, 0x0000 }, /* R413 */ - { 0x0000, 0x0000 }, /* R414 */ - { 0x0000, 0x0000 }, /* R415 */ - { 0x0000, 0x0000 }, /* R416 */ - { 0x0000, 0x0000 }, /* R417 */ - { 0x0000, 0x0000 }, /* R418 */ - { 0x0000, 0x0000 }, /* R419 */ - { 0x0000, 0x0000 }, /* R420 */ - { 0x0000, 0x0000 }, /* R421 */ - { 0x0000, 0x0000 }, /* R422 */ - { 0x0000, 0x0000 }, /* R423 */ - { 0x0000, 0x0000 }, /* R424 */ - { 0x0000, 0x0000 }, /* R425 */ - { 0x0000, 0x0000 }, /* R426 */ - { 0x0000, 0x0000 }, /* R427 */ - { 0x0000, 0x0000 }, /* R428 */ - { 0x0000, 0x0000 }, /* R429 */ - { 0x0000, 0x0000 }, /* R430 */ - { 0x0000, 0x0000 }, /* R431 */ - { 0x0000, 0x0000 }, /* R432 */ - { 0x0000, 0x0000 }, /* R433 */ - { 0x0000, 0x0000 }, /* R434 */ - { 0x0000, 0x0000 }, /* R435 */ - { 0x0000, 0x0000 }, /* R436 */ - { 0x0000, 0x0000 }, /* R437 */ - { 0x0000, 0x0000 }, /* R438 */ - { 0x0000, 0x0000 }, /* R439 */ - { 0x0000, 0x0000 }, /* R440 */ - { 0x0000, 0x0000 }, /* R441 */ - { 0x0000, 0x0000 }, /* R442 */ - { 0x0000, 0x0000 }, /* R443 */ - { 0x0000, 0x0000 }, /* R444 */ - { 0x0000, 0x0000 }, /* R445 */ - { 0x0000, 0x0000 }, /* R446 */ - { 0x0000, 0x0000 }, /* R447 */ - { 0x0000, 0x0000 }, /* R448 */ - { 0x0000, 0x0000 }, /* R449 */ - { 0x0000, 0x0000 }, /* R450 */ - { 0x0000, 0x0000 }, /* R451 */ - { 0x0000, 0x0000 }, /* R452 */ - { 0x0000, 0x0000 }, /* R453 */ - { 0x0000, 0x0000 }, /* R454 */ - { 0x0000, 0x0000 }, /* R455 */ - { 0x0000, 0x0000 }, /* R456 */ - { 0x0000, 0x0000 }, /* R457 */ - { 0x0000, 0x0000 }, /* R458 */ - { 0x0000, 0x0000 }, /* R459 */ - { 0x0000, 0x0000 }, /* R460 */ - { 0x0000, 0x0000 }, /* R461 */ - { 0x0000, 0x0000 }, /* R462 */ - { 0x0000, 0x0000 }, /* R463 */ - { 0x0000, 0x0000 }, /* R464 */ - { 0x0000, 0x0000 }, /* R465 */ - { 0x0000, 0x0000 }, /* R466 */ - { 0x0000, 0x0000 }, /* R467 */ - { 0x0000, 0x0000 }, /* R468 */ - { 0x0000, 0x0000 }, /* R469 */ - { 0x0000, 0x0000 }, /* R470 */ - { 0x0000, 0x0000 }, /* R471 */ - { 0x0000, 0x0000 }, /* R472 */ - { 0x0000, 0x0000 }, /* R473 */ - { 0x0000, 0x0000 }, /* R474 */ - { 0x0000, 0x0000 }, /* R475 */ - { 0x0000, 0x0000 }, /* R476 */ - { 0x0000, 0x0000 }, /* R477 */ - { 0x0000, 0x0000 }, /* R478 */ - { 0x0000, 0x0000 }, /* R479 */ - { 0x0000, 0x0000 }, /* R480 */ - { 0x0000, 0x0000 }, /* R481 */ - { 0x0000, 0x0000 }, /* R482 */ - { 0x0000, 0x0000 }, /* R483 */ - { 0x0000, 0x0000 }, /* R484 */ - { 0x0000, 0x0000 }, /* R485 */ - { 0x0000, 0x0000 }, /* R486 */ - { 0x0000, 0x0000 }, /* R487 */ - { 0x0000, 0x0000 }, /* R488 */ - { 0x0000, 0x0000 }, /* R489 */ - { 0x0000, 0x0000 }, /* R490 */ - { 0x0000, 0x0000 }, /* R491 */ - { 0x0000, 0x0000 }, /* R492 */ - { 0x0000, 0x0000 }, /* R493 */ - { 0x0000, 0x0000 }, /* R494 */ - { 0x0000, 0x0000 }, /* R495 */ - { 0x0000, 0x0000 }, /* R496 */ - { 0x0000, 0x0000 }, /* R497 */ - { 0x0000, 0x0000 }, /* R498 */ - { 0x0000, 0x0000 }, /* R499 */ - { 0x0000, 0x0000 }, /* R500 */ - { 0x0000, 0x0000 }, /* R501 */ - { 0x0000, 0x0000 }, /* R502 */ - { 0x0000, 0x0000 }, /* R503 */ - { 0x0000, 0x0000 }, /* R504 */ - { 0x0000, 0x0000 }, /* R505 */ - { 0x0000, 0x0000 }, /* R506 */ - { 0x0000, 0x0000 }, /* R507 */ - { 0x0000, 0x0000 }, /* R508 */ - { 0x0000, 0x0000 }, /* R509 */ - { 0x0000, 0x0000 }, /* R510 */ - { 0x0000, 0x0000 }, /* R511 */ - { 0x001F, 0x001F }, /* R512 - AIF1 Clocking (1) */ - { 0x003F, 0x003F }, /* R513 - AIF1 Clocking (2) */ - { 0x0000, 0x0000 }, /* R514 */ - { 0x0000, 0x0000 }, /* R515 */ - { 0x001F, 0x001F }, /* R516 - AIF2 Clocking (1) */ - { 0x003F, 0x003F }, /* R517 - AIF2 Clocking (2) */ - { 0x0000, 0x0000 }, /* R518 */ - { 0x0000, 0x0000 }, /* R519 */ - { 0x001F, 0x001F }, /* R520 - Clocking (1) */ - { 0x0777, 0x0777 }, /* R521 - Clocking (2) */ - { 0x0000, 0x0000 }, /* R522 */ - { 0x0000, 0x0000 }, /* R523 */ - { 0x0000, 0x0000 }, /* R524 */ - { 0x0000, 0x0000 }, /* R525 */ - { 0x0000, 0x0000 }, /* R526 */ - { 0x0000, 0x0000 }, /* R527 */ - { 0x00FF, 0x00FF }, /* R528 - AIF1 Rate */ - { 0x00FF, 0x00FF }, /* R529 - AIF2 Rate */ - { 0x000F, 0x0000 }, /* R530 - Rate Status */ - { 0x0000, 0x0000 }, /* R531 */ - { 0x0000, 0x0000 }, /* R532 */ - { 0x0000, 0x0000 }, /* R533 */ - { 0x0000, 0x0000 }, /* R534 */ - { 0x0000, 0x0000 }, /* R535 */ - { 0x0000, 0x0000 }, /* R536 */ - { 0x0000, 0x0000 }, /* R537 */ - { 0x0000, 0x0000 }, /* R538 */ - { 0x0000, 0x0000 }, /* R539 */ - { 0x0000, 0x0000 }, /* R540 */ - { 0x0000, 0x0000 }, /* R541 */ - { 0x0000, 0x0000 }, /* R542 */ - { 0x0000, 0x0000 }, /* R543 */ - { 0x0007, 0x0007 }, /* R544 - FLL1 Control (1) */ - { 0x3F77, 0x3F77 }, /* R545 - FLL1 Control (2) */ - { 0xFFFF, 0xFFFF }, /* R546 - FLL1 Control (3) */ - { 0x7FEF, 0x7FEF }, /* R547 - FLL1 Control (4) */ - { 0x1FDB, 0x1FDB }, /* R548 - FLL1 Control (5) */ - { 0x0000, 0x0000 }, /* R549 */ - { 0x0000, 0x0000 }, /* R550 */ - { 0x0000, 0x0000 }, /* R551 */ - { 0x0000, 0x0000 }, /* R552 */ - { 0x0000, 0x0000 }, /* R553 */ - { 0x0000, 0x0000 }, /* R554 */ - { 0x0000, 0x0000 }, /* R555 */ - { 0x0000, 0x0000 }, /* R556 */ - { 0x0000, 0x0000 }, /* R557 */ - { 0x0000, 0x0000 }, /* R558 */ - { 0x0000, 0x0000 }, /* R559 */ - { 0x0000, 0x0000 }, /* R560 */ - { 0x0000, 0x0000 }, /* R561 */ - { 0x0000, 0x0000 }, /* R562 */ - { 0x0000, 0x0000 }, /* R563 */ - { 0x0000, 0x0000 }, /* R564 */ - { 0x0000, 0x0000 }, /* R565 */ - { 0x0000, 0x0000 }, /* R566 */ - { 0x0000, 0x0000 }, /* R567 */ - { 0x0000, 0x0000 }, /* R568 */ - { 0x0000, 0x0000 }, /* R569 */ - { 0x0000, 0x0000 }, /* R570 */ - { 0x0000, 0x0000 }, /* R571 */ - { 0x0000, 0x0000 }, /* R572 */ - { 0x0000, 0x0000 }, /* R573 */ - { 0x0000, 0x0000 }, /* R574 */ - { 0x0000, 0x0000 }, /* R575 */ - { 0x0007, 0x0007 }, /* R576 - FLL2 Control (1) */ - { 0x3F77, 0x3F77 }, /* R577 - FLL2 Control (2) */ - { 0xFFFF, 0xFFFF }, /* R578 - FLL2 Control (3) */ - { 0x7FEF, 0x7FEF }, /* R579 - FLL2 Control (4) */ - { 0x1FDB, 0x1FDB }, /* R580 - FLL2 Control (5) */ - { 0x0000, 0x0000 }, /* R581 */ - { 0x0000, 0x0000 }, /* R582 */ - { 0x0000, 0x0000 }, /* R583 */ - { 0x0000, 0x0000 }, /* R584 */ - { 0x0000, 0x0000 }, /* R585 */ - { 0x0000, 0x0000 }, /* R586 */ - { 0x0000, 0x0000 }, /* R587 */ - { 0x0000, 0x0000 }, /* R588 */ - { 0x0000, 0x0000 }, /* R589 */ - { 0x0000, 0x0000 }, /* R590 */ - { 0x0000, 0x0000 }, /* R591 */ - { 0x0000, 0x0000 }, /* R592 */ - { 0x0000, 0x0000 }, /* R593 */ - { 0x0000, 0x0000 }, /* R594 */ - { 0x0000, 0x0000 }, /* R595 */ - { 0x0000, 0x0000 }, /* R596 */ - { 0x0000, 0x0000 }, /* R597 */ - { 0x0000, 0x0000 }, /* R598 */ - { 0x0000, 0x0000 }, /* R599 */ - { 0x0000, 0x0000 }, /* R600 */ - { 0x0000, 0x0000 }, /* R601 */ - { 0x0000, 0x0000 }, /* R602 */ - { 0x0000, 0x0000 }, /* R603 */ - { 0x0000, 0x0000 }, /* R604 */ - { 0x0000, 0x0000 }, /* R605 */ - { 0x0000, 0x0000 }, /* R606 */ - { 0x0000, 0x0000 }, /* R607 */ - { 0x0000, 0x0000 }, /* R608 */ - { 0x0000, 0x0000 }, /* R609 */ - { 0x0000, 0x0000 }, /* R610 */ - { 0x0000, 0x0000 }, /* R611 */ - { 0x0000, 0x0000 }, /* R612 */ - { 0x0000, 0x0000 }, /* R613 */ - { 0x0000, 0x0000 }, /* R614 */ - { 0x0000, 0x0000 }, /* R615 */ - { 0x0000, 0x0000 }, /* R616 */ - { 0x0000, 0x0000 }, /* R617 */ - { 0x0000, 0x0000 }, /* R618 */ - { 0x0000, 0x0000 }, /* R619 */ - { 0x0000, 0x0000 }, /* R620 */ - { 0x0000, 0x0000 }, /* R621 */ - { 0x0000, 0x0000 }, /* R622 */ - { 0x0000, 0x0000 }, /* R623 */ - { 0x0000, 0x0000 }, /* R624 */ - { 0x0000, 0x0000 }, /* R625 */ - { 0x0000, 0x0000 }, /* R626 */ - { 0x0000, 0x0000 }, /* R627 */ - { 0x0000, 0x0000 }, /* R628 */ - { 0x0000, 0x0000 }, /* R629 */ - { 0x0000, 0x0000 }, /* R630 */ - { 0x0000, 0x0000 }, /* R631 */ - { 0x0000, 0x0000 }, /* R632 */ - { 0x0000, 0x0000 }, /* R633 */ - { 0x0000, 0x0000 }, /* R634 */ - { 0x0000, 0x0000 }, /* R635 */ - { 0x0000, 0x0000 }, /* R636 */ - { 0x0000, 0x0000 }, /* R637 */ - { 0x0000, 0x0000 }, /* R638 */ - { 0x0000, 0x0000 }, /* R639 */ - { 0x0000, 0x0000 }, /* R640 */ - { 0x0000, 0x0000 }, /* R641 */ - { 0x0000, 0x0000 }, /* R642 */ - { 0x0000, 0x0000 }, /* R643 */ - { 0x0000, 0x0000 }, /* R644 */ - { 0x0000, 0x0000 }, /* R645 */ - { 0x0000, 0x0000 }, /* R646 */ - { 0x0000, 0x0000 }, /* R647 */ - { 0x0000, 0x0000 }, /* R648 */ - { 0x0000, 0x0000 }, /* R649 */ - { 0x0000, 0x0000 }, /* R650 */ - { 0x0000, 0x0000 }, /* R651 */ - { 0x0000, 0x0000 }, /* R652 */ - { 0x0000, 0x0000 }, /* R653 */ - { 0x0000, 0x0000 }, /* R654 */ - { 0x0000, 0x0000 }, /* R655 */ - { 0x0000, 0x0000 }, /* R656 */ - { 0x0000, 0x0000 }, /* R657 */ - { 0x0000, 0x0000 }, /* R658 */ - { 0x0000, 0x0000 }, /* R659 */ - { 0x0000, 0x0000 }, /* R660 */ - { 0x0000, 0x0000 }, /* R661 */ - { 0x0000, 0x0000 }, /* R662 */ - { 0x0000, 0x0000 }, /* R663 */ - { 0x0000, 0x0000 }, /* R664 */ - { 0x0000, 0x0000 }, /* R665 */ - { 0x0000, 0x0000 }, /* R666 */ - { 0x0000, 0x0000 }, /* R667 */ - { 0x0000, 0x0000 }, /* R668 */ - { 0x0000, 0x0000 }, /* R669 */ - { 0x0000, 0x0000 }, /* R670 */ - { 0x0000, 0x0000 }, /* R671 */ - { 0x0000, 0x0000 }, /* R672 */ - { 0x0000, 0x0000 }, /* R673 */ - { 0x0000, 0x0000 }, /* R674 */ - { 0x0000, 0x0000 }, /* R675 */ - { 0x0000, 0x0000 }, /* R676 */ - { 0x0000, 0x0000 }, /* R677 */ - { 0x0000, 0x0000 }, /* R678 */ - { 0x0000, 0x0000 }, /* R679 */ - { 0x0000, 0x0000 }, /* R680 */ - { 0x0000, 0x0000 }, /* R681 */ - { 0x0000, 0x0000 }, /* R682 */ - { 0x0000, 0x0000 }, /* R683 */ - { 0x0000, 0x0000 }, /* R684 */ - { 0x0000, 0x0000 }, /* R685 */ - { 0x0000, 0x0000 }, /* R686 */ - { 0x0000, 0x0000 }, /* R687 */ - { 0x0000, 0x0000 }, /* R688 */ - { 0x0000, 0x0000 }, /* R689 */ - { 0x0000, 0x0000 }, /* R690 */ - { 0x0000, 0x0000 }, /* R691 */ - { 0x0000, 0x0000 }, /* R692 */ - { 0x0000, 0x0000 }, /* R693 */ - { 0x0000, 0x0000 }, /* R694 */ - { 0x0000, 0x0000 }, /* R695 */ - { 0x0000, 0x0000 }, /* R696 */ - { 0x0000, 0x0000 }, /* R697 */ - { 0x0000, 0x0000 }, /* R698 */ - { 0x0000, 0x0000 }, /* R699 */ - { 0x0000, 0x0000 }, /* R700 */ - { 0x0000, 0x0000 }, /* R701 */ - { 0x0000, 0x0000 }, /* R702 */ - { 0x0000, 0x0000 }, /* R703 */ - { 0x0000, 0x0000 }, /* R704 */ - { 0x0000, 0x0000 }, /* R705 */ - { 0x0000, 0x0000 }, /* R706 */ - { 0x0000, 0x0000 }, /* R707 */ - { 0x0000, 0x0000 }, /* R708 */ - { 0x0000, 0x0000 }, /* R709 */ - { 0x0000, 0x0000 }, /* R710 */ - { 0x0000, 0x0000 }, /* R711 */ - { 0x0000, 0x0000 }, /* R712 */ - { 0x0000, 0x0000 }, /* R713 */ - { 0x0000, 0x0000 }, /* R714 */ - { 0x0000, 0x0000 }, /* R715 */ - { 0x0000, 0x0000 }, /* R716 */ - { 0x0000, 0x0000 }, /* R717 */ - { 0x0000, 0x0000 }, /* R718 */ - { 0x0000, 0x0000 }, /* R719 */ - { 0x0000, 0x0000 }, /* R720 */ - { 0x0000, 0x0000 }, /* R721 */ - { 0x0000, 0x0000 }, /* R722 */ - { 0x0000, 0x0000 }, /* R723 */ - { 0x0000, 0x0000 }, /* R724 */ - { 0x0000, 0x0000 }, /* R725 */ - { 0x0000, 0x0000 }, /* R726 */ - { 0x0000, 0x0000 }, /* R727 */ - { 0x0000, 0x0000 }, /* R728 */ - { 0x0000, 0x0000 }, /* R729 */ - { 0x0000, 0x0000 }, /* R730 */ - { 0x0000, 0x0000 }, /* R731 */ - { 0x0000, 0x0000 }, /* R732 */ - { 0x0000, 0x0000 }, /* R733 */ - { 0x0000, 0x0000 }, /* R734 */ - { 0x0000, 0x0000 }, /* R735 */ - { 0x0000, 0x0000 }, /* R736 */ - { 0x0000, 0x0000 }, /* R737 */ - { 0x0000, 0x0000 }, /* R738 */ - { 0x0000, 0x0000 }, /* R739 */ - { 0x0000, 0x0000 }, /* R740 */ - { 0x0000, 0x0000 }, /* R741 */ - { 0x0000, 0x0000 }, /* R742 */ - { 0x0000, 0x0000 }, /* R743 */ - { 0x0000, 0x0000 }, /* R744 */ - { 0x0000, 0x0000 }, /* R745 */ - { 0x0000, 0x0000 }, /* R746 */ - { 0x0000, 0x0000 }, /* R747 */ - { 0x0000, 0x0000 }, /* R748 */ - { 0x0000, 0x0000 }, /* R749 */ - { 0x0000, 0x0000 }, /* R750 */ - { 0x0000, 0x0000 }, /* R751 */ - { 0x0000, 0x0000 }, /* R752 */ - { 0x0000, 0x0000 }, /* R753 */ - { 0x0000, 0x0000 }, /* R754 */ - { 0x0000, 0x0000 }, /* R755 */ - { 0x0000, 0x0000 }, /* R756 */ - { 0x0000, 0x0000 }, /* R757 */ - { 0x0000, 0x0000 }, /* R758 */ - { 0x0000, 0x0000 }, /* R759 */ - { 0x0000, 0x0000 }, /* R760 */ - { 0x0000, 0x0000 }, /* R761 */ - { 0x0000, 0x0000 }, /* R762 */ - { 0x0000, 0x0000 }, /* R763 */ - { 0x0000, 0x0000 }, /* R764 */ - { 0x0000, 0x0000 }, /* R765 */ - { 0x0000, 0x0000 }, /* R766 */ - { 0x0000, 0x0000 }, /* R767 */ - { 0xE1F8, 0xE1F8 }, /* R768 - AIF1 Control (1) */ - { 0xCD1F, 0xCD1F }, /* R769 - AIF1 Control (2) */ - { 0xF000, 0xF000 }, /* R770 - AIF1 Master/Slave */ - { 0x01F0, 0x01F0 }, /* R771 - AIF1 BCLK */ - { 0x0FFF, 0x0FFF }, /* R772 - AIF1ADC LRCLK */ - { 0x0FFF, 0x0FFF }, /* R773 - AIF1DAC LRCLK */ - { 0x0003, 0x0003 }, /* R774 - AIF1DAC Data */ - { 0x0003, 0x0003 }, /* R775 - AIF1ADC Data */ - { 0x0000, 0x0000 }, /* R776 */ - { 0x0000, 0x0000 }, /* R777 */ - { 0x0000, 0x0000 }, /* R778 */ - { 0x0000, 0x0000 }, /* R779 */ - { 0x0000, 0x0000 }, /* R780 */ - { 0x0000, 0x0000 }, /* R781 */ - { 0x0000, 0x0000 }, /* R782 */ - { 0x0000, 0x0000 }, /* R783 */ - { 0xF1F8, 0xF1F8 }, /* R784 - AIF2 Control (1) */ - { 0xFD1F, 0xFD1F }, /* R785 - AIF2 Control (2) */ - { 0xF000, 0xF000 }, /* R786 - AIF2 Master/Slave */ - { 0x01F0, 0x01F0 }, /* R787 - AIF2 BCLK */ - { 0x0FFF, 0x0FFF }, /* R788 - AIF2ADC LRCLK */ - { 0x0FFF, 0x0FFF }, /* R789 - AIF2DAC LRCLK */ - { 0x0003, 0x0003 }, /* R790 - AIF2DAC Data */ - { 0x0003, 0x0003 }, /* R791 - AIF2ADC Data */ - { 0x0000, 0x0000 }, /* R792 */ - { 0x0000, 0x0000 }, /* R793 */ - { 0x0000, 0x0000 }, /* R794 */ - { 0x0000, 0x0000 }, /* R795 */ - { 0x0000, 0x0000 }, /* R796 */ - { 0x0000, 0x0000 }, /* R797 */ - { 0x0000, 0x0000 }, /* R798 */ - { 0x0000, 0x0000 }, /* R799 */ - { 0x0000, 0x0000 }, /* R800 */ - { 0x0000, 0x0000 }, /* R801 */ - { 0x0000, 0x0000 }, /* R802 */ - { 0x0000, 0x0000 }, /* R803 */ - { 0x0000, 0x0000 }, /* R804 */ - { 0x0000, 0x0000 }, /* R805 */ - { 0x0000, 0x0000 }, /* R806 */ - { 0x0000, 0x0000 }, /* R807 */ - { 0x0000, 0x0000 }, /* R808 */ - { 0x0000, 0x0000 }, /* R809 */ - { 0x0000, 0x0000 }, /* R810 */ - { 0x0000, 0x0000 }, /* R811 */ - { 0x0000, 0x0000 }, /* R812 */ - { 0x0000, 0x0000 }, /* R813 */ - { 0x0000, 0x0000 }, /* R814 */ - { 0x0000, 0x0000 }, /* R815 */ - { 0x0000, 0x0000 }, /* R816 */ - { 0x0000, 0x0000 }, /* R817 */ - { 0x0000, 0x0000 }, /* R818 */ - { 0x0000, 0x0000 }, /* R819 */ - { 0x0000, 0x0000 }, /* R820 */ - { 0x0000, 0x0000 }, /* R821 */ - { 0x0000, 0x0000 }, /* R822 */ - { 0x0000, 0x0000 }, /* R823 */ - { 0x0000, 0x0000 }, /* R824 */ - { 0x0000, 0x0000 }, /* R825 */ - { 0x0000, 0x0000 }, /* R826 */ - { 0x0000, 0x0000 }, /* R827 */ - { 0x0000, 0x0000 }, /* R828 */ - { 0x0000, 0x0000 }, /* R829 */ - { 0x0000, 0x0000 }, /* R830 */ - { 0x0000, 0x0000 }, /* R831 */ - { 0x0000, 0x0000 }, /* R832 */ - { 0x0000, 0x0000 }, /* R833 */ - { 0x0000, 0x0000 }, /* R834 */ - { 0x0000, 0x0000 }, /* R835 */ - { 0x0000, 0x0000 }, /* R836 */ - { 0x0000, 0x0000 }, /* R837 */ - { 0x0000, 0x0000 }, /* R838 */ - { 0x0000, 0x0000 }, /* R839 */ - { 0x0000, 0x0000 }, /* R840 */ - { 0x0000, 0x0000 }, /* R841 */ - { 0x0000, 0x0000 }, /* R842 */ - { 0x0000, 0x0000 }, /* R843 */ - { 0x0000, 0x0000 }, /* R844 */ - { 0x0000, 0x0000 }, /* R845 */ - { 0x0000, 0x0000 }, /* R846 */ - { 0x0000, 0x0000 }, /* R847 */ - { 0x0000, 0x0000 }, /* R848 */ - { 0x0000, 0x0000 }, /* R849 */ - { 0x0000, 0x0000 }, /* R850 */ - { 0x0000, 0x0000 }, /* R851 */ - { 0x0000, 0x0000 }, /* R852 */ - { 0x0000, 0x0000 }, /* R853 */ - { 0x0000, 0x0000 }, /* R854 */ - { 0x0000, 0x0000 }, /* R855 */ - { 0x0000, 0x0000 }, /* R856 */ - { 0x0000, 0x0000 }, /* R857 */ - { 0x0000, 0x0000 }, /* R858 */ - { 0x0000, 0x0000 }, /* R859 */ - { 0x0000, 0x0000 }, /* R860 */ - { 0x0000, 0x0000 }, /* R861 */ - { 0x0000, 0x0000 }, /* R862 */ - { 0x0000, 0x0000 }, /* R863 */ - { 0x0000, 0x0000 }, /* R864 */ - { 0x0000, 0x0000 }, /* R865 */ - { 0x0000, 0x0000 }, /* R866 */ - { 0x0000, 0x0000 }, /* R867 */ - { 0x0000, 0x0000 }, /* R868 */ - { 0x0000, 0x0000 }, /* R869 */ - { 0x0000, 0x0000 }, /* R870 */ - { 0x0000, 0x0000 }, /* R871 */ - { 0x0000, 0x0000 }, /* R872 */ - { 0x0000, 0x0000 }, /* R873 */ - { 0x0000, 0x0000 }, /* R874 */ - { 0x0000, 0x0000 }, /* R875 */ - { 0x0000, 0x0000 }, /* R876 */ - { 0x0000, 0x0000 }, /* R877 */ - { 0x0000, 0x0000 }, /* R878 */ - { 0x0000, 0x0000 }, /* R879 */ - { 0x0000, 0x0000 }, /* R880 */ - { 0x0000, 0x0000 }, /* R881 */ - { 0x0000, 0x0000 }, /* R882 */ - { 0x0000, 0x0000 }, /* R883 */ - { 0x0000, 0x0000 }, /* R884 */ - { 0x0000, 0x0000 }, /* R885 */ - { 0x0000, 0x0000 }, /* R886 */ - { 0x0000, 0x0000 }, /* R887 */ - { 0x0000, 0x0000 }, /* R888 */ - { 0x0000, 0x0000 }, /* R889 */ - { 0x0000, 0x0000 }, /* R890 */ - { 0x0000, 0x0000 }, /* R891 */ - { 0x0000, 0x0000 }, /* R892 */ - { 0x0000, 0x0000 }, /* R893 */ - { 0x0000, 0x0000 }, /* R894 */ - { 0x0000, 0x0000 }, /* R895 */ - { 0x0000, 0x0000 }, /* R896 */ - { 0x0000, 0x0000 }, /* R897 */ - { 0x0000, 0x0000 }, /* R898 */ - { 0x0000, 0x0000 }, /* R899 */ - { 0x0000, 0x0000 }, /* R900 */ - { 0x0000, 0x0000 }, /* R901 */ - { 0x0000, 0x0000 }, /* R902 */ - { 0x0000, 0x0000 }, /* R903 */ - { 0x0000, 0x0000 }, /* R904 */ - { 0x0000, 0x0000 }, /* R905 */ - { 0x0000, 0x0000 }, /* R906 */ - { 0x0000, 0x0000 }, /* R907 */ - { 0x0000, 0x0000 }, /* R908 */ - { 0x0000, 0x0000 }, /* R909 */ - { 0x0000, 0x0000 }, /* R910 */ - { 0x0000, 0x0000 }, /* R911 */ - { 0x0000, 0x0000 }, /* R912 */ - { 0x0000, 0x0000 }, /* R913 */ - { 0x0000, 0x0000 }, /* R914 */ - { 0x0000, 0x0000 }, /* R915 */ - { 0x0000, 0x0000 }, /* R916 */ - { 0x0000, 0x0000 }, /* R917 */ - { 0x0000, 0x0000 }, /* R918 */ - { 0x0000, 0x0000 }, /* R919 */ - { 0x0000, 0x0000 }, /* R920 */ - { 0x0000, 0x0000 }, /* R921 */ - { 0x0000, 0x0000 }, /* R922 */ - { 0x0000, 0x0000 }, /* R923 */ - { 0x0000, 0x0000 }, /* R924 */ - { 0x0000, 0x0000 }, /* R925 */ - { 0x0000, 0x0000 }, /* R926 */ - { 0x0000, 0x0000 }, /* R927 */ - { 0x0000, 0x0000 }, /* R928 */ - { 0x0000, 0x0000 }, /* R929 */ - { 0x0000, 0x0000 }, /* R930 */ - { 0x0000, 0x0000 }, /* R931 */ - { 0x0000, 0x0000 }, /* R932 */ - { 0x0000, 0x0000 }, /* R933 */ - { 0x0000, 0x0000 }, /* R934 */ - { 0x0000, 0x0000 }, /* R935 */ - { 0x0000, 0x0000 }, /* R936 */ - { 0x0000, 0x0000 }, /* R937 */ - { 0x0000, 0x0000 }, /* R938 */ - { 0x0000, 0x0000 }, /* R939 */ - { 0x0000, 0x0000 }, /* R940 */ - { 0x0000, 0x0000 }, /* R941 */ - { 0x0000, 0x0000 }, /* R942 */ - { 0x0000, 0x0000 }, /* R943 */ - { 0x0000, 0x0000 }, /* R944 */ - { 0x0000, 0x0000 }, /* R945 */ - { 0x0000, 0x0000 }, /* R946 */ - { 0x0000, 0x0000 }, /* R947 */ - { 0x0000, 0x0000 }, /* R948 */ - { 0x0000, 0x0000 }, /* R949 */ - { 0x0000, 0x0000 }, /* R950 */ - { 0x0000, 0x0000 }, /* R951 */ - { 0x0000, 0x0000 }, /* R952 */ - { 0x0000, 0x0000 }, /* R953 */ - { 0x0000, 0x0000 }, /* R954 */ - { 0x0000, 0x0000 }, /* R955 */ - { 0x0000, 0x0000 }, /* R956 */ - { 0x0000, 0x0000 }, /* R957 */ - { 0x0000, 0x0000 }, /* R958 */ - { 0x0000, 0x0000 }, /* R959 */ - { 0x0000, 0x0000 }, /* R960 */ - { 0x0000, 0x0000 }, /* R961 */ - { 0x0000, 0x0000 }, /* R962 */ - { 0x0000, 0x0000 }, /* R963 */ - { 0x0000, 0x0000 }, /* R964 */ - { 0x0000, 0x0000 }, /* R965 */ - { 0x0000, 0x0000 }, /* R966 */ - { 0x0000, 0x0000 }, /* R967 */ - { 0x0000, 0x0000 }, /* R968 */ - { 0x0000, 0x0000 }, /* R969 */ - { 0x0000, 0x0000 }, /* R970 */ - { 0x0000, 0x0000 }, /* R971 */ - { 0x0000, 0x0000 }, /* R972 */ - { 0x0000, 0x0000 }, /* R973 */ - { 0x0000, 0x0000 }, /* R974 */ - { 0x0000, 0x0000 }, /* R975 */ - { 0x0000, 0x0000 }, /* R976 */ - { 0x0000, 0x0000 }, /* R977 */ - { 0x0000, 0x0000 }, /* R978 */ - { 0x0000, 0x0000 }, /* R979 */ - { 0x0000, 0x0000 }, /* R980 */ - { 0x0000, 0x0000 }, /* R981 */ - { 0x0000, 0x0000 }, /* R982 */ - { 0x0000, 0x0000 }, /* R983 */ - { 0x0000, 0x0000 }, /* R984 */ - { 0x0000, 0x0000 }, /* R985 */ - { 0x0000, 0x0000 }, /* R986 */ - { 0x0000, 0x0000 }, /* R987 */ - { 0x0000, 0x0000 }, /* R988 */ - { 0x0000, 0x0000 }, /* R989 */ - { 0x0000, 0x0000 }, /* R990 */ - { 0x0000, 0x0000 }, /* R991 */ - { 0x0000, 0x0000 }, /* R992 */ - { 0x0000, 0x0000 }, /* R993 */ - { 0x0000, 0x0000 }, /* R994 */ - { 0x0000, 0x0000 }, /* R995 */ - { 0x0000, 0x0000 }, /* R996 */ - { 0x0000, 0x0000 }, /* R997 */ - { 0x0000, 0x0000 }, /* R998 */ - { 0x0000, 0x0000 }, /* R999 */ - { 0x0000, 0x0000 }, /* R1000 */ - { 0x0000, 0x0000 }, /* R1001 */ - { 0x0000, 0x0000 }, /* R1002 */ - { 0x0000, 0x0000 }, /* R1003 */ - { 0x0000, 0x0000 }, /* R1004 */ - { 0x0000, 0x0000 }, /* R1005 */ - { 0x0000, 0x0000 }, /* R1006 */ - { 0x0000, 0x0000 }, /* R1007 */ - { 0x0000, 0x0000 }, /* R1008 */ - { 0x0000, 0x0000 }, /* R1009 */ - { 0x0000, 0x0000 }, /* R1010 */ - { 0x0000, 0x0000 }, /* R1011 */ - { 0x0000, 0x0000 }, /* R1012 */ - { 0x0000, 0x0000 }, /* R1013 */ - { 0x0000, 0x0000 }, /* R1014 */ - { 0x0000, 0x0000 }, /* R1015 */ - { 0x0000, 0x0000 }, /* R1016 */ - { 0x0000, 0x0000 }, /* R1017 */ - { 0x0000, 0x0000 }, /* R1018 */ - { 0x0000, 0x0000 }, /* R1019 */ - { 0x0000, 0x0000 }, /* R1020 */ - { 0x0000, 0x0000 }, /* R1021 */ - { 0x0000, 0x0000 }, /* R1022 */ - { 0x0000, 0x0000 }, /* R1023 */ - { 0x00FF, 0x01FF }, /* R1024 - AIF1 ADC1 Left Volume */ - { 0x00FF, 0x01FF }, /* R1025 - AIF1 ADC1 Right Volume */ - { 0x00FF, 0x01FF }, /* R1026 - AIF1 DAC1 Left Volume */ - { 0x00FF, 0x01FF }, /* R1027 - AIF1 DAC1 Right Volume */ - { 0x00FF, 0x01FF }, /* R1028 - AIF1 ADC2 Left Volume */ - { 0x00FF, 0x01FF }, /* R1029 - AIF1 ADC2 Right Volume */ - { 0x00FF, 0x01FF }, /* R1030 - AIF1 DAC2 Left Volume */ - { 0x00FF, 0x01FF }, /* R1031 - AIF1 DAC2 Right Volume */ - { 0x0000, 0x0000 }, /* R1032 */ - { 0x0000, 0x0000 }, /* R1033 */ - { 0x0000, 0x0000 }, /* R1034 */ - { 0x0000, 0x0000 }, /* R1035 */ - { 0x0000, 0x0000 }, /* R1036 */ - { 0x0000, 0x0000 }, /* R1037 */ - { 0x0000, 0x0000 }, /* R1038 */ - { 0x0000, 0x0000 }, /* R1039 */ - { 0xF800, 0xF800 }, /* R1040 - AIF1 ADC1 Filters */ - { 0x7800, 0x7800 }, /* R1041 - AIF1 ADC2 Filters */ - { 0x0000, 0x0000 }, /* R1042 */ - { 0x0000, 0x0000 }, /* R1043 */ - { 0x0000, 0x0000 }, /* R1044 */ - { 0x0000, 0x0000 }, /* R1045 */ - { 0x0000, 0x0000 }, /* R1046 */ - { 0x0000, 0x0000 }, /* R1047 */ - { 0x0000, 0x0000 }, /* R1048 */ - { 0x0000, 0x0000 }, /* R1049 */ - { 0x0000, 0x0000 }, /* R1050 */ - { 0x0000, 0x0000 }, /* R1051 */ - { 0x0000, 0x0000 }, /* R1052 */ - { 0x0000, 0x0000 }, /* R1053 */ - { 0x0000, 0x0000 }, /* R1054 */ - { 0x0000, 0x0000 }, /* R1055 */ - { 0x02B6, 0x02B6 }, /* R1056 - AIF1 DAC1 Filters (1) */ - { 0x3F00, 0x3F00 }, /* R1057 - AIF1 DAC1 Filters (2) */ - { 0x02B6, 0x02B6 }, /* R1058 - AIF1 DAC2 Filters (1) */ - { 0x3F00, 0x3F00 }, /* R1059 - AIF1 DAC2 Filters (2) */ - { 0x0000, 0x0000 }, /* R1060 */ - { 0x0000, 0x0000 }, /* R1061 */ - { 0x0000, 0x0000 }, /* R1062 */ - { 0x0000, 0x0000 }, /* R1063 */ - { 0x0000, 0x0000 }, /* R1064 */ - { 0x0000, 0x0000 }, /* R1065 */ - { 0x0000, 0x0000 }, /* R1066 */ - { 0x0000, 0x0000 }, /* R1067 */ - { 0x0000, 0x0000 }, /* R1068 */ - { 0x0000, 0x0000 }, /* R1069 */ - { 0x0000, 0x0000 }, /* R1070 */ - { 0x0000, 0x0000 }, /* R1071 */ - { 0x0000, 0x0000 }, /* R1072 */ - { 0x0000, 0x0000 }, /* R1073 */ - { 0x0000, 0x0000 }, /* R1074 */ - { 0x0000, 0x0000 }, /* R1075 */ - { 0x0000, 0x0000 }, /* R1076 */ - { 0x0000, 0x0000 }, /* R1077 */ - { 0x0000, 0x0000 }, /* R1078 */ - { 0x0000, 0x0000 }, /* R1079 */ - { 0x0000, 0x0000 }, /* R1080 */ - { 0x0000, 0x0000 }, /* R1081 */ - { 0x0000, 0x0000 }, /* R1082 */ - { 0x0000, 0x0000 }, /* R1083 */ - { 0x0000, 0x0000 }, /* R1084 */ - { 0x0000, 0x0000 }, /* R1085 */ - { 0x0000, 0x0000 }, /* R1086 */ - { 0x0000, 0x0000 }, /* R1087 */ - { 0xFFFF, 0xFFFF }, /* R1088 - AIF1 DRC1 (1) */ - { 0x1FFF, 0x1FFF }, /* R1089 - AIF1 DRC1 (2) */ - { 0xFFFF, 0xFFFF }, /* R1090 - AIF1 DRC1 (3) */ - { 0x07FF, 0x07FF }, /* R1091 - AIF1 DRC1 (4) */ - { 0x03FF, 0x03FF }, /* R1092 - AIF1 DRC1 (5) */ - { 0x0000, 0x0000 }, /* R1093 */ - { 0x0000, 0x0000 }, /* R1094 */ - { 0x0000, 0x0000 }, /* R1095 */ - { 0x0000, 0x0000 }, /* R1096 */ - { 0x0000, 0x0000 }, /* R1097 */ - { 0x0000, 0x0000 }, /* R1098 */ - { 0x0000, 0x0000 }, /* R1099 */ - { 0x0000, 0x0000 }, /* R1100 */ - { 0x0000, 0x0000 }, /* R1101 */ - { 0x0000, 0x0000 }, /* R1102 */ - { 0x0000, 0x0000 }, /* R1103 */ - { 0xFFFF, 0xFFFF }, /* R1104 - AIF1 DRC2 (1) */ - { 0x1FFF, 0x1FFF }, /* R1105 - AIF1 DRC2 (2) */ - { 0xFFFF, 0xFFFF }, /* R1106 - AIF1 DRC2 (3) */ - { 0x07FF, 0x07FF }, /* R1107 - AIF1 DRC2 (4) */ - { 0x03FF, 0x03FF }, /* R1108 - AIF1 DRC2 (5) */ - { 0x0000, 0x0000 }, /* R1109 */ - { 0x0000, 0x0000 }, /* R1110 */ - { 0x0000, 0x0000 }, /* R1111 */ - { 0x0000, 0x0000 }, /* R1112 */ - { 0x0000, 0x0000 }, /* R1113 */ - { 0x0000, 0x0000 }, /* R1114 */ - { 0x0000, 0x0000 }, /* R1115 */ - { 0x0000, 0x0000 }, /* R1116 */ - { 0x0000, 0x0000 }, /* R1117 */ - { 0x0000, 0x0000 }, /* R1118 */ - { 0x0000, 0x0000 }, /* R1119 */ - { 0x0000, 0x0000 }, /* R1120 */ - { 0x0000, 0x0000 }, /* R1121 */ - { 0x0000, 0x0000 }, /* R1122 */ - { 0x0000, 0x0000 }, /* R1123 */ - { 0x0000, 0x0000 }, /* R1124 */ - { 0x0000, 0x0000 }, /* R1125 */ - { 0x0000, 0x0000 }, /* R1126 */ - { 0x0000, 0x0000 }, /* R1127 */ - { 0x0000, 0x0000 }, /* R1128 */ - { 0x0000, 0x0000 }, /* R1129 */ - { 0x0000, 0x0000 }, /* R1130 */ - { 0x0000, 0x0000 }, /* R1131 */ - { 0x0000, 0x0000 }, /* R1132 */ - { 0x0000, 0x0000 }, /* R1133 */ - { 0x0000, 0x0000 }, /* R1134 */ - { 0x0000, 0x0000 }, /* R1135 */ - { 0x0000, 0x0000 }, /* R1136 */ - { 0x0000, 0x0000 }, /* R1137 */ - { 0x0000, 0x0000 }, /* R1138 */ - { 0x0000, 0x0000 }, /* R1139 */ - { 0x0000, 0x0000 }, /* R1140 */ - { 0x0000, 0x0000 }, /* R1141 */ - { 0x0000, 0x0000 }, /* R1142 */ - { 0x0000, 0x0000 }, /* R1143 */ - { 0x0000, 0x0000 }, /* R1144 */ - { 0x0000, 0x0000 }, /* R1145 */ - { 0x0000, 0x0000 }, /* R1146 */ - { 0x0000, 0x0000 }, /* R1147 */ - { 0x0000, 0x0000 }, /* R1148 */ - { 0x0000, 0x0000 }, /* R1149 */ - { 0x0000, 0x0000 }, /* R1150 */ - { 0x0000, 0x0000 }, /* R1151 */ - { 0xFFFF, 0xFFFF }, /* R1152 - AIF1 DAC1 EQ Gains (1) */ - { 0xFFC0, 0xFFC0 }, /* R1153 - AIF1 DAC1 EQ Gains (2) */ - { 0xFFFF, 0xFFFF }, /* R1154 - AIF1 DAC1 EQ Band 1 A */ - { 0xFFFF, 0xFFFF }, /* R1155 - AIF1 DAC1 EQ Band 1 B */ - { 0xFFFF, 0xFFFF }, /* R1156 - AIF1 DAC1 EQ Band 1 PG */ - { 0xFFFF, 0xFFFF }, /* R1157 - AIF1 DAC1 EQ Band 2 A */ - { 0xFFFF, 0xFFFF }, /* R1158 - AIF1 DAC1 EQ Band 2 B */ - { 0xFFFF, 0xFFFF }, /* R1159 - AIF1 DAC1 EQ Band 2 C */ - { 0xFFFF, 0xFFFF }, /* R1160 - AIF1 DAC1 EQ Band 2 PG */ - { 0xFFFF, 0xFFFF }, /* R1161 - AIF1 DAC1 EQ Band 3 A */ - { 0xFFFF, 0xFFFF }, /* R1162 - AIF1 DAC1 EQ Band 3 B */ - { 0xFFFF, 0xFFFF }, /* R1163 - AIF1 DAC1 EQ Band 3 C */ - { 0xFFFF, 0xFFFF }, /* R1164 - AIF1 DAC1 EQ Band 3 PG */ - { 0xFFFF, 0xFFFF }, /* R1165 - AIF1 DAC1 EQ Band 4 A */ - { 0xFFFF, 0xFFFF }, /* R1166 - AIF1 DAC1 EQ Band 4 B */ - { 0xFFFF, 0xFFFF }, /* R1167 - AIF1 DAC1 EQ Band 4 C */ - { 0xFFFF, 0xFFFF }, /* R1168 - AIF1 DAC1 EQ Band 4 PG */ - { 0xFFFF, 0xFFFF }, /* R1169 - AIF1 DAC1 EQ Band 5 A */ - { 0xFFFF, 0xFFFF }, /* R1170 - AIF1 DAC1 EQ Band 5 B */ - { 0xFFFF, 0xFFFF }, /* R1171 - AIF1 DAC1 EQ Band 5 PG */ - { 0x0000, 0x0000 }, /* R1172 */ - { 0x0000, 0x0000 }, /* R1173 */ - { 0x0000, 0x0000 }, /* R1174 */ - { 0x0000, 0x0000 }, /* R1175 */ - { 0x0000, 0x0000 }, /* R1176 */ - { 0x0000, 0x0000 }, /* R1177 */ - { 0x0000, 0x0000 }, /* R1178 */ - { 0x0000, 0x0000 }, /* R1179 */ - { 0x0000, 0x0000 }, /* R1180 */ - { 0x0000, 0x0000 }, /* R1181 */ - { 0x0000, 0x0000 }, /* R1182 */ - { 0x0000, 0x0000 }, /* R1183 */ - { 0xFFFF, 0xFFFF }, /* R1184 - AIF1 DAC2 EQ Gains (1) */ - { 0xFFC0, 0xFFC0 }, /* R1185 - AIF1 DAC2 EQ Gains (2) */ - { 0xFFFF, 0xFFFF }, /* R1186 - AIF1 DAC2 EQ Band 1 A */ - { 0xFFFF, 0xFFFF }, /* R1187 - AIF1 DAC2 EQ Band 1 B */ - { 0xFFFF, 0xFFFF }, /* R1188 - AIF1 DAC2 EQ Band 1 PG */ - { 0xFFFF, 0xFFFF }, /* R1189 - AIF1 DAC2 EQ Band 2 A */ - { 0xFFFF, 0xFFFF }, /* R1190 - AIF1 DAC2 EQ Band 2 B */ - { 0xFFFF, 0xFFFF }, /* R1191 - AIF1 DAC2 EQ Band 2 C */ - { 0xFFFF, 0xFFFF }, /* R1192 - AIF1 DAC2 EQ Band 2 PG */ - { 0xFFFF, 0xFFFF }, /* R1193 - AIF1 DAC2 EQ Band 3 A */ - { 0xFFFF, 0xFFFF }, /* R1194 - AIF1 DAC2 EQ Band 3 B */ - { 0xFFFF, 0xFFFF }, /* R1195 - AIF1 DAC2 EQ Band 3 C */ - { 0xFFFF, 0xFFFF }, /* R1196 - AIF1 DAC2 EQ Band 3 PG */ - { 0xFFFF, 0xFFFF }, /* R1197 - AIF1 DAC2 EQ Band 4 A */ - { 0xFFFF, 0xFFFF }, /* R1198 - AIF1 DAC2 EQ Band 4 B */ - { 0xFFFF, 0xFFFF }, /* R1199 - AIF1 DAC2 EQ Band 4 C */ - { 0xFFFF, 0xFFFF }, /* R1200 - AIF1 DAC2 EQ Band 4 PG */ - { 0xFFFF, 0xFFFF }, /* R1201 - AIF1 DAC2 EQ Band 5 A */ - { 0xFFFF, 0xFFFF }, /* R1202 - AIF1 DAC2 EQ Band 5 B */ - { 0xFFFF, 0xFFFF }, /* R1203 - AIF1 DAC2 EQ Band 5 PG */ - { 0x0000, 0x0000 }, /* R1204 */ - { 0x0000, 0x0000 }, /* R1205 */ - { 0x0000, 0x0000 }, /* R1206 */ - { 0x0000, 0x0000 }, /* R1207 */ - { 0x0000, 0x0000 }, /* R1208 */ - { 0x0000, 0x0000 }, /* R1209 */ - { 0x0000, 0x0000 }, /* R1210 */ - { 0x0000, 0x0000 }, /* R1211 */ - { 0x0000, 0x0000 }, /* R1212 */ - { 0x0000, 0x0000 }, /* R1213 */ - { 0x0000, 0x0000 }, /* R1214 */ - { 0x0000, 0x0000 }, /* R1215 */ - { 0x0000, 0x0000 }, /* R1216 */ - { 0x0000, 0x0000 }, /* R1217 */ - { 0x0000, 0x0000 }, /* R1218 */ - { 0x0000, 0x0000 }, /* R1219 */ - { 0x0000, 0x0000 }, /* R1220 */ - { 0x0000, 0x0000 }, /* R1221 */ - { 0x0000, 0x0000 }, /* R1222 */ - { 0x0000, 0x0000 }, /* R1223 */ - { 0x0000, 0x0000 }, /* R1224 */ - { 0x0000, 0x0000 }, /* R1225 */ - { 0x0000, 0x0000 }, /* R1226 */ - { 0x0000, 0x0000 }, /* R1227 */ - { 0x0000, 0x0000 }, /* R1228 */ - { 0x0000, 0x0000 }, /* R1229 */ - { 0x0000, 0x0000 }, /* R1230 */ - { 0x0000, 0x0000 }, /* R1231 */ - { 0x0000, 0x0000 }, /* R1232 */ - { 0x0000, 0x0000 }, /* R1233 */ - { 0x0000, 0x0000 }, /* R1234 */ - { 0x0000, 0x0000 }, /* R1235 */ - { 0x0000, 0x0000 }, /* R1236 */ - { 0x0000, 0x0000 }, /* R1237 */ - { 0x0000, 0x0000 }, /* R1238 */ - { 0x0000, 0x0000 }, /* R1239 */ - { 0x0000, 0x0000 }, /* R1240 */ - { 0x0000, 0x0000 }, /* R1241 */ - { 0x0000, 0x0000 }, /* R1242 */ - { 0x0000, 0x0000 }, /* R1243 */ - { 0x0000, 0x0000 }, /* R1244 */ - { 0x0000, 0x0000 }, /* R1245 */ - { 0x0000, 0x0000 }, /* R1246 */ - { 0x0000, 0x0000 }, /* R1247 */ - { 0x0000, 0x0000 }, /* R1248 */ - { 0x0000, 0x0000 }, /* R1249 */ - { 0x0000, 0x0000 }, /* R1250 */ - { 0x0000, 0x0000 }, /* R1251 */ - { 0x0000, 0x0000 }, /* R1252 */ - { 0x0000, 0x0000 }, /* R1253 */ - { 0x0000, 0x0000 }, /* R1254 */ - { 0x0000, 0x0000 }, /* R1255 */ - { 0x0000, 0x0000 }, /* R1256 */ - { 0x0000, 0x0000 }, /* R1257 */ - { 0x0000, 0x0000 }, /* R1258 */ - { 0x0000, 0x0000 }, /* R1259 */ - { 0x0000, 0x0000 }, /* R1260 */ - { 0x0000, 0x0000 }, /* R1261 */ - { 0x0000, 0x0000 }, /* R1262 */ - { 0x0000, 0x0000 }, /* R1263 */ - { 0x0000, 0x0000 }, /* R1264 */ - { 0x0000, 0x0000 }, /* R1265 */ - { 0x0000, 0x0000 }, /* R1266 */ - { 0x0000, 0x0000 }, /* R1267 */ - { 0x0000, 0x0000 }, /* R1268 */ - { 0x0000, 0x0000 }, /* R1269 */ - { 0x0000, 0x0000 }, /* R1270 */ - { 0x0000, 0x0000 }, /* R1271 */ - { 0x0000, 0x0000 }, /* R1272 */ - { 0x0000, 0x0000 }, /* R1273 */ - { 0x0000, 0x0000 }, /* R1274 */ - { 0x0000, 0x0000 }, /* R1275 */ - { 0x0000, 0x0000 }, /* R1276 */ - { 0x0000, 0x0000 }, /* R1277 */ - { 0x0000, 0x0000 }, /* R1278 */ - { 0x0000, 0x0000 }, /* R1279 */ - { 0x00FF, 0x01FF }, /* R1280 - AIF2 ADC Left Volume */ - { 0x00FF, 0x01FF }, /* R1281 - AIF2 ADC Right Volume */ - { 0x00FF, 0x01FF }, /* R1282 - AIF2 DAC Left Volume */ - { 0x00FF, 0x01FF }, /* R1283 - AIF2 DAC Right Volume */ - { 0x0000, 0x0000 }, /* R1284 */ - { 0x0000, 0x0000 }, /* R1285 */ - { 0x0000, 0x0000 }, /* R1286 */ - { 0x0000, 0x0000 }, /* R1287 */ - { 0x0000, 0x0000 }, /* R1288 */ - { 0x0000, 0x0000 }, /* R1289 */ - { 0x0000, 0x0000 }, /* R1290 */ - { 0x0000, 0x0000 }, /* R1291 */ - { 0x0000, 0x0000 }, /* R1292 */ - { 0x0000, 0x0000 }, /* R1293 */ - { 0x0000, 0x0000 }, /* R1294 */ - { 0x0000, 0x0000 }, /* R1295 */ - { 0xF800, 0xF800 }, /* R1296 - AIF2 ADC Filters */ - { 0x0000, 0x0000 }, /* R1297 */ - { 0x0000, 0x0000 }, /* R1298 */ - { 0x0000, 0x0000 }, /* R1299 */ - { 0x0000, 0x0000 }, /* R1300 */ - { 0x0000, 0x0000 }, /* R1301 */ - { 0x0000, 0x0000 }, /* R1302 */ - { 0x0000, 0x0000 }, /* R1303 */ - { 0x0000, 0x0000 }, /* R1304 */ - { 0x0000, 0x0000 }, /* R1305 */ - { 0x0000, 0x0000 }, /* R1306 */ - { 0x0000, 0x0000 }, /* R1307 */ - { 0x0000, 0x0000 }, /* R1308 */ - { 0x0000, 0x0000 }, /* R1309 */ - { 0x0000, 0x0000 }, /* R1310 */ - { 0x0000, 0x0000 }, /* R1311 */ - { 0x02B6, 0x02B6 }, /* R1312 - AIF2 DAC Filters (1) */ - { 0x3F00, 0x3F00 }, /* R1313 - AIF2 DAC Filters (2) */ - { 0x0000, 0x0000 }, /* R1314 */ - { 0x0000, 0x0000 }, /* R1315 */ - { 0x0000, 0x0000 }, /* R1316 */ - { 0x0000, 0x0000 }, /* R1317 */ - { 0x0000, 0x0000 }, /* R1318 */ - { 0x0000, 0x0000 }, /* R1319 */ - { 0x0000, 0x0000 }, /* R1320 */ - { 0x0000, 0x0000 }, /* R1321 */ - { 0x0000, 0x0000 }, /* R1322 */ - { 0x0000, 0x0000 }, /* R1323 */ - { 0x0000, 0x0000 }, /* R1324 */ - { 0x0000, 0x0000 }, /* R1325 */ - { 0x0000, 0x0000 }, /* R1326 */ - { 0x0000, 0x0000 }, /* R1327 */ - { 0x0000, 0x0000 }, /* R1328 */ - { 0x0000, 0x0000 }, /* R1329 */ - { 0x0000, 0x0000 }, /* R1330 */ - { 0x0000, 0x0000 }, /* R1331 */ - { 0x0000, 0x0000 }, /* R1332 */ - { 0x0000, 0x0000 }, /* R1333 */ - { 0x0000, 0x0000 }, /* R1334 */ - { 0x0000, 0x0000 }, /* R1335 */ - { 0x0000, 0x0000 }, /* R1336 */ - { 0x0000, 0x0000 }, /* R1337 */ - { 0x0000, 0x0000 }, /* R1338 */ - { 0x0000, 0x0000 }, /* R1339 */ - { 0x0000, 0x0000 }, /* R1340 */ - { 0x0000, 0x0000 }, /* R1341 */ - { 0x0000, 0x0000 }, /* R1342 */ - { 0x0000, 0x0000 }, /* R1343 */ - { 0xFFFF, 0xFFFF }, /* R1344 - AIF2 DRC (1) */ - { 0x1FFF, 0x1FFF }, /* R1345 - AIF2 DRC (2) */ - { 0xFFFF, 0xFFFF }, /* R1346 - AIF2 DRC (3) */ - { 0x07FF, 0x07FF }, /* R1347 - AIF2 DRC (4) */ - { 0x03FF, 0x03FF }, /* R1348 - AIF2 DRC (5) */ - { 0x0000, 0x0000 }, /* R1349 */ - { 0x0000, 0x0000 }, /* R1350 */ - { 0x0000, 0x0000 }, /* R1351 */ - { 0x0000, 0x0000 }, /* R1352 */ - { 0x0000, 0x0000 }, /* R1353 */ - { 0x0000, 0x0000 }, /* R1354 */ - { 0x0000, 0x0000 }, /* R1355 */ - { 0x0000, 0x0000 }, /* R1356 */ - { 0x0000, 0x0000 }, /* R1357 */ - { 0x0000, 0x0000 }, /* R1358 */ - { 0x0000, 0x0000 }, /* R1359 */ - { 0x0000, 0x0000 }, /* R1360 */ - { 0x0000, 0x0000 }, /* R1361 */ - { 0x0000, 0x0000 }, /* R1362 */ - { 0x0000, 0x0000 }, /* R1363 */ - { 0x0000, 0x0000 }, /* R1364 */ - { 0x0000, 0x0000 }, /* R1365 */ - { 0x0000, 0x0000 }, /* R1366 */ - { 0x0000, 0x0000 }, /* R1367 */ - { 0x0000, 0x0000 }, /* R1368 */ - { 0x0000, 0x0000 }, /* R1369 */ - { 0x0000, 0x0000 }, /* R1370 */ - { 0x0000, 0x0000 }, /* R1371 */ - { 0x0000, 0x0000 }, /* R1372 */ - { 0x0000, 0x0000 }, /* R1373 */ - { 0x0000, 0x0000 }, /* R1374 */ - { 0x0000, 0x0000 }, /* R1375 */ - { 0x0000, 0x0000 }, /* R1376 */ - { 0x0000, 0x0000 }, /* R1377 */ - { 0x0000, 0x0000 }, /* R1378 */ - { 0x0000, 0x0000 }, /* R1379 */ - { 0x0000, 0x0000 }, /* R1380 */ - { 0x0000, 0x0000 }, /* R1381 */ - { 0x0000, 0x0000 }, /* R1382 */ - { 0x0000, 0x0000 }, /* R1383 */ - { 0x0000, 0x0000 }, /* R1384 */ - { 0x0000, 0x0000 }, /* R1385 */ - { 0x0000, 0x0000 }, /* R1386 */ - { 0x0000, 0x0000 }, /* R1387 */ - { 0x0000, 0x0000 }, /* R1388 */ - { 0x0000, 0x0000 }, /* R1389 */ - { 0x0000, 0x0000 }, /* R1390 */ - { 0x0000, 0x0000 }, /* R1391 */ - { 0x0000, 0x0000 }, /* R1392 */ - { 0x0000, 0x0000 }, /* R1393 */ - { 0x0000, 0x0000 }, /* R1394 */ - { 0x0000, 0x0000 }, /* R1395 */ - { 0x0000, 0x0000 }, /* R1396 */ - { 0x0000, 0x0000 }, /* R1397 */ - { 0x0000, 0x0000 }, /* R1398 */ - { 0x0000, 0x0000 }, /* R1399 */ - { 0x0000, 0x0000 }, /* R1400 */ - { 0x0000, 0x0000 }, /* R1401 */ - { 0x0000, 0x0000 }, /* R1402 */ - { 0x0000, 0x0000 }, /* R1403 */ - { 0x0000, 0x0000 }, /* R1404 */ - { 0x0000, 0x0000 }, /* R1405 */ - { 0x0000, 0x0000 }, /* R1406 */ - { 0x0000, 0x0000 }, /* R1407 */ - { 0xFFFF, 0xFFFF }, /* R1408 - AIF2 EQ Gains (1) */ - { 0xFFC0, 0xFFC0 }, /* R1409 - AIF2 EQ Gains (2) */ - { 0xFFFF, 0xFFFF }, /* R1410 - AIF2 EQ Band 1 A */ - { 0xFFFF, 0xFFFF }, /* R1411 - AIF2 EQ Band 1 B */ - { 0xFFFF, 0xFFFF }, /* R1412 - AIF2 EQ Band 1 PG */ - { 0xFFFF, 0xFFFF }, /* R1413 - AIF2 EQ Band 2 A */ - { 0xFFFF, 0xFFFF }, /* R1414 - AIF2 EQ Band 2 B */ - { 0xFFFF, 0xFFFF }, /* R1415 - AIF2 EQ Band 2 C */ - { 0xFFFF, 0xFFFF }, /* R1416 - AIF2 EQ Band 2 PG */ - { 0xFFFF, 0xFFFF }, /* R1417 - AIF2 EQ Band 3 A */ - { 0xFFFF, 0xFFFF }, /* R1418 - AIF2 EQ Band 3 B */ - { 0xFFFF, 0xFFFF }, /* R1419 - AIF2 EQ Band 3 C */ - { 0xFFFF, 0xFFFF }, /* R1420 - AIF2 EQ Band 3 PG */ - { 0xFFFF, 0xFFFF }, /* R1421 - AIF2 EQ Band 4 A */ - { 0xFFFF, 0xFFFF }, /* R1422 - AIF2 EQ Band 4 B */ - { 0xFFFF, 0xFFFF }, /* R1423 - AIF2 EQ Band 4 C */ - { 0xFFFF, 0xFFFF }, /* R1424 - AIF2 EQ Band 4 PG */ - { 0xFFFF, 0xFFFF }, /* R1425 - AIF2 EQ Band 5 A */ - { 0xFFFF, 0xFFFF }, /* R1426 - AIF2 EQ Band 5 B */ - { 0xFFFF, 0xFFFF }, /* R1427 - AIF2 EQ Band 5 PG */ - { 0x0000, 0x0000 }, /* R1428 */ - { 0x0000, 0x0000 }, /* R1429 */ - { 0x0000, 0x0000 }, /* R1430 */ - { 0x0000, 0x0000 }, /* R1431 */ - { 0x0000, 0x0000 }, /* R1432 */ - { 0x0000, 0x0000 }, /* R1433 */ - { 0x0000, 0x0000 }, /* R1434 */ - { 0x0000, 0x0000 }, /* R1435 */ - { 0x0000, 0x0000 }, /* R1436 */ - { 0x0000, 0x0000 }, /* R1437 */ - { 0x0000, 0x0000 }, /* R1438 */ - { 0x0000, 0x0000 }, /* R1439 */ - { 0x0000, 0x0000 }, /* R1440 */ - { 0x0000, 0x0000 }, /* R1441 */ - { 0x0000, 0x0000 }, /* R1442 */ - { 0x0000, 0x0000 }, /* R1443 */ - { 0x0000, 0x0000 }, /* R1444 */ - { 0x0000, 0x0000 }, /* R1445 */ - { 0x0000, 0x0000 }, /* R1446 */ - { 0x0000, 0x0000 }, /* R1447 */ - { 0x0000, 0x0000 }, /* R1448 */ - { 0x0000, 0x0000 }, /* R1449 */ - { 0x0000, 0x0000 }, /* R1450 */ - { 0x0000, 0x0000 }, /* R1451 */ - { 0x0000, 0x0000 }, /* R1452 */ - { 0x0000, 0x0000 }, /* R1453 */ - { 0x0000, 0x0000 }, /* R1454 */ - { 0x0000, 0x0000 }, /* R1455 */ - { 0x0000, 0x0000 }, /* R1456 */ - { 0x0000, 0x0000 }, /* R1457 */ - { 0x0000, 0x0000 }, /* R1458 */ - { 0x0000, 0x0000 }, /* R1459 */ - { 0x0000, 0x0000 }, /* R1460 */ - { 0x0000, 0x0000 }, /* R1461 */ - { 0x0000, 0x0000 }, /* R1462 */ - { 0x0000, 0x0000 }, /* R1463 */ - { 0x0000, 0x0000 }, /* R1464 */ - { 0x0000, 0x0000 }, /* R1465 */ - { 0x0000, 0x0000 }, /* R1466 */ - { 0x0000, 0x0000 }, /* R1467 */ - { 0x0000, 0x0000 }, /* R1468 */ - { 0x0000, 0x0000 }, /* R1469 */ - { 0x0000, 0x0000 }, /* R1470 */ - { 0x0000, 0x0000 }, /* R1471 */ - { 0x0000, 0x0000 }, /* R1472 */ - { 0x0000, 0x0000 }, /* R1473 */ - { 0x0000, 0x0000 }, /* R1474 */ - { 0x0000, 0x0000 }, /* R1475 */ - { 0x0000, 0x0000 }, /* R1476 */ - { 0x0000, 0x0000 }, /* R1477 */ - { 0x0000, 0x0000 }, /* R1478 */ - { 0x0000, 0x0000 }, /* R1479 */ - { 0x0000, 0x0000 }, /* R1480 */ - { 0x0000, 0x0000 }, /* R1481 */ - { 0x0000, 0x0000 }, /* R1482 */ - { 0x0000, 0x0000 }, /* R1483 */ - { 0x0000, 0x0000 }, /* R1484 */ - { 0x0000, 0x0000 }, /* R1485 */ - { 0x0000, 0x0000 }, /* R1486 */ - { 0x0000, 0x0000 }, /* R1487 */ - { 0x0000, 0x0000 }, /* R1488 */ - { 0x0000, 0x0000 }, /* R1489 */ - { 0x0000, 0x0000 }, /* R1490 */ - { 0x0000, 0x0000 }, /* R1491 */ - { 0x0000, 0x0000 }, /* R1492 */ - { 0x0000, 0x0000 }, /* R1493 */ - { 0x0000, 0x0000 }, /* R1494 */ - { 0x0000, 0x0000 }, /* R1495 */ - { 0x0000, 0x0000 }, /* R1496 */ - { 0x0000, 0x0000 }, /* R1497 */ - { 0x0000, 0x0000 }, /* R1498 */ - { 0x0000, 0x0000 }, /* R1499 */ - { 0x0000, 0x0000 }, /* R1500 */ - { 0x0000, 0x0000 }, /* R1501 */ - { 0x0000, 0x0000 }, /* R1502 */ - { 0x0000, 0x0000 }, /* R1503 */ - { 0x0000, 0x0000 }, /* R1504 */ - { 0x0000, 0x0000 }, /* R1505 */ - { 0x0000, 0x0000 }, /* R1506 */ - { 0x0000, 0x0000 }, /* R1507 */ - { 0x0000, 0x0000 }, /* R1508 */ - { 0x0000, 0x0000 }, /* R1509 */ - { 0x0000, 0x0000 }, /* R1510 */ - { 0x0000, 0x0000 }, /* R1511 */ - { 0x0000, 0x0000 }, /* R1512 */ - { 0x0000, 0x0000 }, /* R1513 */ - { 0x0000, 0x0000 }, /* R1514 */ - { 0x0000, 0x0000 }, /* R1515 */ - { 0x0000, 0x0000 }, /* R1516 */ - { 0x0000, 0x0000 }, /* R1517 */ - { 0x0000, 0x0000 }, /* R1518 */ - { 0x0000, 0x0000 }, /* R1519 */ - { 0x0000, 0x0000 }, /* R1520 */ - { 0x0000, 0x0000 }, /* R1521 */ - { 0x0000, 0x0000 }, /* R1522 */ - { 0x0000, 0x0000 }, /* R1523 */ - { 0x0000, 0x0000 }, /* R1524 */ - { 0x0000, 0x0000 }, /* R1525 */ - { 0x0000, 0x0000 }, /* R1526 */ - { 0x0000, 0x0000 }, /* R1527 */ - { 0x0000, 0x0000 }, /* R1528 */ - { 0x0000, 0x0000 }, /* R1529 */ - { 0x0000, 0x0000 }, /* R1530 */ - { 0x0000, 0x0000 }, /* R1531 */ - { 0x0000, 0x0000 }, /* R1532 */ - { 0x0000, 0x0000 }, /* R1533 */ - { 0x0000, 0x0000 }, /* R1534 */ - { 0x0000, 0x0000 }, /* R1535 */ - { 0x01EF, 0x01EF }, /* R1536 - DAC1 Mixer Volumes */ - { 0x0037, 0x0037 }, /* R1537 - DAC1 Left Mixer Routing */ - { 0x0037, 0x0037 }, /* R1538 - DAC1 Right Mixer Routing */ - { 0x01EF, 0x01EF }, /* R1539 - DAC2 Mixer Volumes */ - { 0x0037, 0x0037 }, /* R1540 - DAC2 Left Mixer Routing */ - { 0x0037, 0x0037 }, /* R1541 - DAC2 Right Mixer Routing */ - { 0x0003, 0x0003 }, /* R1542 - AIF1 ADC1 Left Mixer Routing */ - { 0x0003, 0x0003 }, /* R1543 - AIF1 ADC1 Right Mixer Routing */ - { 0x0003, 0x0003 }, /* R1544 - AIF1 ADC2 Left Mixer Routing */ - { 0x0003, 0x0003 }, /* R1545 - AIF1 ADC2 Right mixer Routing */ - { 0x0000, 0x0000 }, /* R1546 */ - { 0x0000, 0x0000 }, /* R1547 */ - { 0x0000, 0x0000 }, /* R1548 */ - { 0x0000, 0x0000 }, /* R1549 */ - { 0x0000, 0x0000 }, /* R1550 */ - { 0x0000, 0x0000 }, /* R1551 */ - { 0x02FF, 0x03FF }, /* R1552 - DAC1 Left Volume */ - { 0x02FF, 0x03FF }, /* R1553 - DAC1 Right Volume */ - { 0x02FF, 0x03FF }, /* R1554 - DAC2 Left Volume */ - { 0x02FF, 0x03FF }, /* R1555 - DAC2 Right Volume */ - { 0x0003, 0x0003 }, /* R1556 - DAC Softmute */ - { 0x0000, 0x0000 }, /* R1557 */ - { 0x0000, 0x0000 }, /* R1558 */ - { 0x0000, 0x0000 }, /* R1559 */ - { 0x0000, 0x0000 }, /* R1560 */ - { 0x0000, 0x0000 }, /* R1561 */ - { 0x0000, 0x0000 }, /* R1562 */ - { 0x0000, 0x0000 }, /* R1563 */ - { 0x0000, 0x0000 }, /* R1564 */ - { 0x0000, 0x0000 }, /* R1565 */ - { 0x0000, 0x0000 }, /* R1566 */ - { 0x0000, 0x0000 }, /* R1567 */ - { 0x0003, 0x0003 }, /* R1568 - Oversampling */ - { 0x03C3, 0x03C3 }, /* R1569 - Sidetone */ -}; - static int wm8994_readable(unsigned int reg) { switch (reg) { @@ -1696,9 +120,9 @@ static int wm8994_readable(unsigned int reg) break; } - if (reg >= ARRAY_SIZE(access_masks)) + if (reg >= WM8994_CACHE_SIZE) return 0; - return access_masks[reg].readable != 0; + return wm8994_access_masks[reg].readable != 0; } static int wm8994_volatile(unsigned int reg) @@ -3658,7 +2082,7 @@ static int wm8994_resume(struct snd_soc_codec *codec) break; } - if (!access_masks[i].writable) + if (!wm8994_access_masks[i].writable) continue; wm8994_reg_write(codec->control_data, i, reg_cache[i]); diff --git a/sound/soc/codecs/wm8994.h b/sound/soc/codecs/wm8994.h index d8dce260c430..b8b3166e1f03 100644 --- a/sound/soc/codecs/wm8994.h +++ b/sound/soc/codecs/wm8994.h @@ -31,4 +31,13 @@ int wm8994_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack, int micbias, int det, int shrt); +#define WM8994_CACHE_SIZE 1570 + +struct wm8994_access_mask { + unsigned short readable; /* Mask of readable bits */ + unsigned short writable; /* Mask of writable bits */ +}; + +extern const struct wm8994_access_mask wm8994_access_masks[WM8994_CACHE_SIZE]; + #endif -- cgit v1.2.2 From 5b3b0fa8fb0db9645b56361cdc9a9d0ddbc35e4d Mon Sep 17 00:00:00 2001 From: Axel Lin Date: Fri, 19 Nov 2010 17:31:08 +0800 Subject: ASoC: Move kfree(twl4030) to twl4030_soc_remove() As we allocate memory for twl4030 in twl4030_codec_probe(), twl4030_codec_remove() is a better place to free the memory. Signed-off-by: Axel Lin Acked-by: Mark Brown Signed-off-by: Liam Girdwood --- sound/soc/codecs/twl4030.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'sound/soc/codecs') diff --git a/sound/soc/codecs/twl4030.c b/sound/soc/codecs/twl4030.c index a6ceddb0bb7d..3820885c8c2a 100644 --- a/sound/soc/codecs/twl4030.c +++ b/sound/soc/codecs/twl4030.c @@ -2272,9 +2272,12 @@ static int twl4030_soc_probe(struct snd_soc_codec *codec) static int twl4030_soc_remove(struct snd_soc_codec *codec) { + struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec); + /* Reset registers to their chip default before leaving */ twl4030_reset_registers(codec); twl4030_set_bias_level(codec, SND_SOC_BIAS_OFF); + kfree(twl4030); return 0; } @@ -2306,10 +2309,7 @@ static int __devinit twl4030_codec_probe(struct platform_device *pdev) static int __devexit twl4030_codec_remove(struct platform_device *pdev) { - struct twl4030_priv *twl4030 = dev_get_drvdata(&pdev->dev); - snd_soc_unregister_codec(&pdev->dev); - kfree(twl4030); return 0; } -- cgit v1.2.2 From 1c8f2c4287bcc1eb596149b2b36be5c809598926 Mon Sep 17 00:00:00 2001 From: Jarkko Nikula Date: Sun, 21 Nov 2010 19:48:44 +0200 Subject: ASoC: Fix compile breakage in jz4740.c and smartq_wm8987.c Commit ce6120c require that soc-dapm.h cannot be included before soc.h but these two drivers were not checked. Fix them by including only soc.h as it includes soc-dapm.h. Signed-off-by: Jarkko Nikula Acked-by: Liam Girdwood Signed-off-by: Mark Brown --- sound/soc/codecs/jz4740.c | 1 - 1 file changed, 1 deletion(-) (limited to 'sound/soc/codecs') diff --git a/sound/soc/codecs/jz4740.c b/sound/soc/codecs/jz4740.c index 8a45562a96d4..f7cd346fd727 100644 --- a/sound/soc/codecs/jz4740.c +++ b/sound/soc/codecs/jz4740.c @@ -22,7 +22,6 @@ #include #include #include -#include #include #define JZ4740_REG_CODEC_1 0x0 -- cgit v1.2.2 From 505fb824e754efcc9702ce68d3911e7b86d3c690 Mon Sep 17 00:00:00 2001 From: Jarkko Nikula Date: Sun, 21 Nov 2010 19:48:45 +0200 Subject: ASoC: Do not include soc-dapm.h There is no need to include soc-dapm.h since soc.h includes it. Signed-off-by: Jarkko Nikula Acked-by: Liam Girdwood Signed-off-by: Mark Brown --- sound/soc/codecs/88pm860x-codec.c | 1 - sound/soc/codecs/ad1836.c | 1 - sound/soc/codecs/ad193x.c | 1 - sound/soc/codecs/ad1980.c | 1 - sound/soc/codecs/ak4535.c | 1 - sound/soc/codecs/ak4671.c | 1 - sound/soc/codecs/alc5623.c | 1 - sound/soc/codecs/cq93vc.c | 1 - sound/soc/codecs/cs42l51.c | 1 - sound/soc/codecs/max98088.c | 1 - sound/soc/codecs/ssm2602.c | 1 - sound/soc/codecs/stac9766.c | 1 - sound/soc/codecs/tlv320aic23.c | 1 - sound/soc/codecs/tlv320aic26.c | 1 - sound/soc/codecs/tlv320aic3x.c | 1 - sound/soc/codecs/tlv320dac33.c | 1 - sound/soc/codecs/tpa6130a2.c | 1 - sound/soc/codecs/twl4030.c | 1 - sound/soc/codecs/twl6040.c | 1 - sound/soc/codecs/uda134x.c | 1 - sound/soc/codecs/uda1380.c | 1 - sound/soc/codecs/wl1273.c | 1 - sound/soc/codecs/wm2000.c | 1 - sound/soc/codecs/wm8350.c | 1 - sound/soc/codecs/wm8400.c | 1 - sound/soc/codecs/wm8510.c | 1 - sound/soc/codecs/wm8523.c | 1 - sound/soc/codecs/wm8580.c | 1 - sound/soc/codecs/wm8711.c | 1 - sound/soc/codecs/wm8728.c | 1 - sound/soc/codecs/wm8731.c | 1 - sound/soc/codecs/wm8741.c | 1 - sound/soc/codecs/wm8750.c | 1 - sound/soc/codecs/wm8753.c | 1 - sound/soc/codecs/wm8770.c | 1 - sound/soc/codecs/wm8776.c | 1 - sound/soc/codecs/wm8804.c | 1 - sound/soc/codecs/wm8900.c | 1 - sound/soc/codecs/wm8903.c | 1 - sound/soc/codecs/wm8904.c | 1 - sound/soc/codecs/wm8940.c | 1 - sound/soc/codecs/wm8955.c | 1 - sound/soc/codecs/wm8960.c | 1 - sound/soc/codecs/wm8961.c | 1 - sound/soc/codecs/wm8962.c | 1 - sound/soc/codecs/wm8971.c | 1 - sound/soc/codecs/wm8974.c | 1 - sound/soc/codecs/wm8978.c | 1 - sound/soc/codecs/wm8985.c | 1 - sound/soc/codecs/wm8988.c | 1 - sound/soc/codecs/wm8990.c | 1 - sound/soc/codecs/wm8993.c | 1 - sound/soc/codecs/wm8994.c | 1 - sound/soc/codecs/wm9081.c | 1 - sound/soc/codecs/wm9090.c | 1 - sound/soc/codecs/wm9705.c | 1 - sound/soc/codecs/wm9712.c | 1 - sound/soc/codecs/wm9713.c | 1 - sound/soc/codecs/wm_hubs.c | 1 - 59 files changed, 59 deletions(-) (limited to 'sound/soc/codecs') diff --git a/sound/soc/codecs/88pm860x-codec.c b/sound/soc/codecs/88pm860x-codec.c index a15a3e974f0d..7e4d88007d4f 100644 --- a/sound/soc/codecs/88pm860x-codec.c +++ b/sound/soc/codecs/88pm860x-codec.c @@ -19,7 +19,6 @@ #include #include #include -#include #include #include #include diff --git a/sound/soc/codecs/ad1836.c b/sound/soc/codecs/ad1836.c index e5d3db950a08..ab63d52e36e1 100644 --- a/sound/soc/codecs/ad1836.c +++ b/sound/soc/codecs/ad1836.c @@ -27,7 +27,6 @@ #include #include #include -#include #include #include "ad1836.h" diff --git a/sound/soc/codecs/ad193x.c b/sound/soc/codecs/ad193x.c index fd3e659f90b1..a007bd7326fd 100644 --- a/sound/soc/codecs/ad193x.c +++ b/sound/soc/codecs/ad193x.c @@ -19,7 +19,6 @@ #include #include #include -#include #include "ad193x.h" /* codec private data */ diff --git a/sound/soc/codecs/ad1980.c b/sound/soc/codecs/ad1980.c index 410ccd5d41cd..34cb51ef2156 100644 --- a/sound/soc/codecs/ad1980.c +++ b/sound/soc/codecs/ad1980.c @@ -29,7 +29,6 @@ #include #include #include -#include #include "ad1980.h" diff --git a/sound/soc/codecs/ak4535.c b/sound/soc/codecs/ak4535.c index 52abb93a7dce..73675458076d 100644 --- a/sound/soc/codecs/ak4535.c +++ b/sound/soc/codecs/ak4535.c @@ -24,7 +24,6 @@ #include #include #include -#include #include #include "ak4535.h" diff --git a/sound/soc/codecs/ak4671.c b/sound/soc/codecs/ak4671.c index 1d6573c38af4..4faf10553a30 100644 --- a/sound/soc/codecs/ak4671.c +++ b/sound/soc/codecs/ak4671.c @@ -17,7 +17,6 @@ #include #include #include -#include #include #include diff --git a/sound/soc/codecs/alc5623.c b/sound/soc/codecs/alc5623.c index 5a45067b43ba..e84b26b0ce9e 100644 --- a/sound/soc/codecs/alc5623.c +++ b/sound/soc/codecs/alc5623.c @@ -28,7 +28,6 @@ #include #include #include -#include #include #include diff --git a/sound/soc/codecs/cq93vc.c b/sound/soc/codecs/cq93vc.c index 98b9e5294cbe..1a6f511051b6 100644 --- a/sound/soc/codecs/cq93vc.c +++ b/sound/soc/codecs/cq93vc.c @@ -37,7 +37,6 @@ #include #include #include -#include #include #include diff --git a/sound/soc/codecs/cs42l51.c b/sound/soc/codecs/cs42l51.c index a7fdca36b490..d4e60dc45bf6 100644 --- a/sound/soc/codecs/cs42l51.c +++ b/sound/soc/codecs/cs42l51.c @@ -26,7 +26,6 @@ #include #include #include -#include #include #include #include diff --git a/sound/soc/codecs/max98088.c b/sound/soc/codecs/max98088.c index 9c322373d5de..c44b5f70b5e0 100644 --- a/sound/soc/codecs/max98088.c +++ b/sound/soc/codecs/max98088.c @@ -20,7 +20,6 @@ #include #include #include -#include #include #include #include diff --git a/sound/soc/codecs/ssm2602.c b/sound/soc/codecs/ssm2602.c index adbc3e8dafc8..2727befd158e 100644 --- a/sound/soc/codecs/ssm2602.c +++ b/sound/soc/codecs/ssm2602.c @@ -38,7 +38,6 @@ #include #include #include -#include #include #include "ssm2602.h" diff --git a/sound/soc/codecs/stac9766.c b/sound/soc/codecs/stac9766.c index 8aad3a2c4f3d..7f2773038242 100644 --- a/sound/soc/codecs/stac9766.c +++ b/sound/soc/codecs/stac9766.c @@ -24,7 +24,6 @@ #include #include #include -#include #include #include "stac9766.h" diff --git a/sound/soc/codecs/tlv320aic23.c b/sound/soc/codecs/tlv320aic23.c index d9d8e844d63f..54a30ef0ec8b 100644 --- a/sound/soc/codecs/tlv320aic23.c +++ b/sound/soc/codecs/tlv320aic23.c @@ -30,7 +30,6 @@ #include #include #include -#include #include #include diff --git a/sound/soc/codecs/tlv320aic26.c b/sound/soc/codecs/tlv320aic26.c index 6b7d71ec0004..68f0ae47f608 100644 --- a/sound/soc/codecs/tlv320aic26.c +++ b/sound/soc/codecs/tlv320aic26.c @@ -18,7 +18,6 @@ #include #include #include -#include #include #include "tlv320aic26.h" diff --git a/sound/soc/codecs/tlv320aic3x.c b/sound/soc/codecs/tlv320aic3x.c index df726a5066e8..49b797ccc8d6 100644 --- a/sound/soc/codecs/tlv320aic3x.c +++ b/sound/soc/codecs/tlv320aic3x.c @@ -46,7 +46,6 @@ #include #include #include -#include #include #include #include diff --git a/sound/soc/codecs/tlv320dac33.c b/sound/soc/codecs/tlv320dac33.c index 7149c14b289e..ccb267f4e968 100644 --- a/sound/soc/codecs/tlv320dac33.c +++ b/sound/soc/codecs/tlv320dac33.c @@ -36,7 +36,6 @@ #include #include #include -#include #include #include diff --git a/sound/soc/codecs/tpa6130a2.c b/sound/soc/codecs/tpa6130a2.c index f9a92ea6b50a..bfef3da95f58 100644 --- a/sound/soc/codecs/tpa6130a2.c +++ b/sound/soc/codecs/tpa6130a2.c @@ -29,7 +29,6 @@ #include #include #include -#include #include #include "tpa6130a2.h" diff --git a/sound/soc/codecs/twl4030.c b/sound/soc/codecs/twl4030.c index f4602e8b67cc..0488d5514cd8 100644 --- a/sound/soc/codecs/twl4030.c +++ b/sound/soc/codecs/twl4030.c @@ -32,7 +32,6 @@ #include #include #include -#include #include #include diff --git a/sound/soc/codecs/twl6040.c b/sound/soc/codecs/twl6040.c index 0dd2d5397264..b92f2b737e4c 100644 --- a/sound/soc/codecs/twl6040.c +++ b/sound/soc/codecs/twl6040.c @@ -34,7 +34,6 @@ #include #include #include -#include #include #include diff --git a/sound/soc/codecs/uda134x.c b/sound/soc/codecs/uda134x.c index 6b6c0d291abf..e76847a9438b 100644 --- a/sound/soc/codecs/uda134x.c +++ b/sound/soc/codecs/uda134x.c @@ -19,7 +19,6 @@ #include #include #include -#include #include #include diff --git a/sound/soc/codecs/uda1380.c b/sound/soc/codecs/uda1380.c index cd6dd19fa1aa..800980e2e9ab 100644 --- a/sound/soc/codecs/uda1380.c +++ b/sound/soc/codecs/uda1380.c @@ -27,7 +27,6 @@ #include #include #include -#include #include #include diff --git a/sound/soc/codecs/wl1273.c b/sound/soc/codecs/wl1273.c index 0c47c788ccdf..c606b3e235fa 100644 --- a/sound/soc/codecs/wl1273.c +++ b/sound/soc/codecs/wl1273.c @@ -26,7 +26,6 @@ #include #include #include -#include #include #include "wl1273.h" diff --git a/sound/soc/codecs/wm2000.c b/sound/soc/codecs/wm2000.c index 9277d8d7474e..80ddf4fd23db 100644 --- a/sound/soc/codecs/wm2000.c +++ b/sound/soc/codecs/wm2000.c @@ -36,7 +36,6 @@ #include #include #include -#include #include #include diff --git a/sound/soc/codecs/wm8350.c b/sound/soc/codecs/wm8350.c index d5e6e02ff350..dc6912e9b667 100644 --- a/sound/soc/codecs/wm8350.c +++ b/sound/soc/codecs/wm8350.c @@ -24,7 +24,6 @@ #include #include #include -#include #include #include diff --git a/sound/soc/codecs/wm8400.c b/sound/soc/codecs/wm8400.c index 96927a457a34..3c3bc079167e 100644 --- a/sound/soc/codecs/wm8400.c +++ b/sound/soc/codecs/wm8400.c @@ -26,7 +26,6 @@ #include #include #include -#include #include #include diff --git a/sound/soc/codecs/wm8510.c b/sound/soc/codecs/wm8510.c index 6b3833c7bdf3..db0dced74843 100644 --- a/sound/soc/codecs/wm8510.c +++ b/sound/soc/codecs/wm8510.c @@ -24,7 +24,6 @@ #include #include #include -#include #include #include "wm8510.h" diff --git a/sound/soc/codecs/wm8523.c b/sound/soc/codecs/wm8523.c index d3318886f43e..1bda09baa851 100644 --- a/sound/soc/codecs/wm8523.c +++ b/sound/soc/codecs/wm8523.c @@ -24,7 +24,6 @@ #include #include #include -#include #include #include diff --git a/sound/soc/codecs/wm8580.c b/sound/soc/codecs/wm8580.c index 36c035bf4e42..e2a927684b48 100644 --- a/sound/soc/codecs/wm8580.c +++ b/sound/soc/codecs/wm8580.c @@ -31,7 +31,6 @@ #include #include #include -#include #include #include #include diff --git a/sound/soc/codecs/wm8711.c b/sound/soc/codecs/wm8711.c index ea2daf4da57c..fec37ebfdb34 100644 --- a/sound/soc/codecs/wm8711.c +++ b/sound/soc/codecs/wm8711.c @@ -25,7 +25,6 @@ #include #include #include -#include #include #include diff --git a/sound/soc/codecs/wm8728.c b/sound/soc/codecs/wm8728.c index 23939976c3cc..736b0352d0a7 100644 --- a/sound/soc/codecs/wm8728.c +++ b/sound/soc/codecs/wm8728.c @@ -23,7 +23,6 @@ #include #include #include -#include #include #include diff --git a/sound/soc/codecs/wm8731.c b/sound/soc/codecs/wm8731.c index 4b709589e26c..a1041450d9bb 100644 --- a/sound/soc/codecs/wm8731.c +++ b/sound/soc/codecs/wm8731.c @@ -26,7 +26,6 @@ #include #include #include -#include #include #include diff --git a/sound/soc/codecs/wm8741.c b/sound/soc/codecs/wm8741.c index 2543a26513fb..35789b7dcacf 100644 --- a/sound/soc/codecs/wm8741.c +++ b/sound/soc/codecs/wm8741.c @@ -24,7 +24,6 @@ #include #include #include -#include #include #include diff --git a/sound/soc/codecs/wm8750.c b/sound/soc/codecs/wm8750.c index 178b967af73f..51280e96d721 100644 --- a/sound/soc/codecs/wm8750.c +++ b/sound/soc/codecs/wm8750.c @@ -25,7 +25,6 @@ #include #include #include -#include #include #include "wm8750.h" diff --git a/sound/soc/codecs/wm8753.c b/sound/soc/codecs/wm8753.c index 26096b47a493..57bf9468d39a 100644 --- a/sound/soc/codecs/wm8753.c +++ b/sound/soc/codecs/wm8753.c @@ -45,7 +45,6 @@ #include #include #include -#include #include #include #include diff --git a/sound/soc/codecs/wm8770.c b/sound/soc/codecs/wm8770.c index 8608b4a10b0a..19b92baa9e8c 100644 --- a/sound/soc/codecs/wm8770.c +++ b/sound/soc/codecs/wm8770.c @@ -23,7 +23,6 @@ #include #include #include -#include #include #include diff --git a/sound/soc/codecs/wm8776.c b/sound/soc/codecs/wm8776.c index e09ed65e0868..8e7953b1b790 100644 --- a/sound/soc/codecs/wm8776.c +++ b/sound/soc/codecs/wm8776.c @@ -25,7 +25,6 @@ #include #include #include -#include #include #include diff --git a/sound/soc/codecs/wm8804.c b/sound/soc/codecs/wm8804.c index 031a0d421108..6dae1b40c9f7 100644 --- a/sound/soc/codecs/wm8804.c +++ b/sound/soc/codecs/wm8804.c @@ -23,7 +23,6 @@ #include #include #include -#include #include #include diff --git a/sound/soc/codecs/wm8900.c b/sound/soc/codecs/wm8900.c index 06ea9c0f863b..cfbaac1a0ead 100644 --- a/sound/soc/codecs/wm8900.c +++ b/sound/soc/codecs/wm8900.c @@ -30,7 +30,6 @@ #include #include #include -#include #include #include diff --git a/sound/soc/codecs/wm8903.c b/sound/soc/codecs/wm8903.c index 4a6df4b69a04..620793e51666 100644 --- a/sound/soc/codecs/wm8903.c +++ b/sound/soc/codecs/wm8903.c @@ -29,7 +29,6 @@ #include #include #include -#include #include #include diff --git a/sound/soc/codecs/wm8904.c b/sound/soc/codecs/wm8904.c index 5e57bd2483e8..da9192890187 100644 --- a/sound/soc/codecs/wm8904.c +++ b/sound/soc/codecs/wm8904.c @@ -24,7 +24,6 @@ #include #include #include -#include #include #include #include diff --git a/sound/soc/codecs/wm8940.c b/sound/soc/codecs/wm8940.c index caed0849e005..381934fff4ec 100644 --- a/sound/soc/codecs/wm8940.c +++ b/sound/soc/codecs/wm8940.c @@ -35,7 +35,6 @@ #include #include #include -#include #include #include diff --git a/sound/soc/codecs/wm8955.c b/sound/soc/codecs/wm8955.c index df1940fdbf69..6200beb082b2 100644 --- a/sound/soc/codecs/wm8955.c +++ b/sound/soc/codecs/wm8955.c @@ -23,7 +23,6 @@ #include #include #include -#include #include #include #include diff --git a/sound/soc/codecs/wm8960.c b/sound/soc/codecs/wm8960.c index 0ea578815003..0bcf36ee29bc 100644 --- a/sound/soc/codecs/wm8960.c +++ b/sound/soc/codecs/wm8960.c @@ -20,7 +20,6 @@ #include #include #include -#include #include #include #include diff --git a/sound/soc/codecs/wm8961.c b/sound/soc/codecs/wm8961.c index 79b650945bb2..a0bb972420b3 100644 --- a/sound/soc/codecs/wm8961.c +++ b/sound/soc/codecs/wm8961.c @@ -23,7 +23,6 @@ #include #include #include -#include #include #include diff --git a/sound/soc/codecs/wm8962.c b/sound/soc/codecs/wm8962.c index 9f6beca951c4..cf4b2722648a 100644 --- a/sound/soc/codecs/wm8962.c +++ b/sound/soc/codecs/wm8962.c @@ -29,7 +29,6 @@ #include #include #include -#include #include #include #include diff --git a/sound/soc/codecs/wm8971.c b/sound/soc/codecs/wm8971.c index 84b2dcb18aea..8805636bda53 100644 --- a/sound/soc/codecs/wm8971.c +++ b/sound/soc/codecs/wm8971.c @@ -25,7 +25,6 @@ #include #include #include -#include #include #include "wm8971.h" diff --git a/sound/soc/codecs/wm8974.c b/sound/soc/codecs/wm8974.c index d19bb14842d4..5d286427532a 100644 --- a/sound/soc/codecs/wm8974.c +++ b/sound/soc/codecs/wm8974.c @@ -23,7 +23,6 @@ #include #include #include -#include #include #include diff --git a/sound/soc/codecs/wm8978.c b/sound/soc/codecs/wm8978.c index ac43b6088e2e..a195af92b425 100644 --- a/sound/soc/codecs/wm8978.c +++ b/sound/soc/codecs/wm8978.c @@ -24,7 +24,6 @@ #include #include #include -#include #include #include #include diff --git a/sound/soc/codecs/wm8985.c b/sound/soc/codecs/wm8985.c index c3c8fd23d503..bae510acdec8 100644 --- a/sound/soc/codecs/wm8985.c +++ b/sound/soc/codecs/wm8985.c @@ -26,7 +26,6 @@ #include #include #include -#include #include #include diff --git a/sound/soc/codecs/wm8988.c b/sound/soc/codecs/wm8988.c index 0bc2eb530c7a..65807b15a2cc 100644 --- a/sound/soc/codecs/wm8988.c +++ b/sound/soc/codecs/wm8988.c @@ -25,7 +25,6 @@ #include #include #include -#include #include #include "wm8988.h" diff --git a/sound/soc/codecs/wm8990.c b/sound/soc/codecs/wm8990.c index 309664ea7dc3..5c87a634fc04 100644 --- a/sound/soc/codecs/wm8990.c +++ b/sound/soc/codecs/wm8990.c @@ -23,7 +23,6 @@ #include #include #include -#include #include #include #include diff --git a/sound/soc/codecs/wm8993.c b/sound/soc/codecs/wm8993.c index 991d90c79dd2..77b1d441c3d0 100644 --- a/sound/soc/codecs/wm8993.c +++ b/sound/soc/codecs/wm8993.c @@ -24,7 +24,6 @@ #include #include #include -#include #include #include diff --git a/sound/soc/codecs/wm8994.c b/sound/soc/codecs/wm8994.c index 189f00079d31..435508fd6137 100644 --- a/sound/soc/codecs/wm8994.c +++ b/sound/soc/codecs/wm8994.c @@ -24,7 +24,6 @@ #include #include #include -#include #include #include diff --git a/sound/soc/codecs/wm9081.c b/sound/soc/codecs/wm9081.c index c03e2c3e24e1..c7060775e88b 100644 --- a/sound/soc/codecs/wm9081.c +++ b/sound/soc/codecs/wm9081.c @@ -23,7 +23,6 @@ #include #include #include -#include #include #include diff --git a/sound/soc/codecs/wm9090.c b/sound/soc/codecs/wm9090.c index b5afa01aa383..7ba5807cac36 100644 --- a/sound/soc/codecs/wm9090.c +++ b/sound/soc/codecs/wm9090.c @@ -28,7 +28,6 @@ #include #include #include -#include #include #include diff --git a/sound/soc/codecs/wm9705.c b/sound/soc/codecs/wm9705.c index 58d120824498..47b357adabdd 100644 --- a/sound/soc/codecs/wm9705.c +++ b/sound/soc/codecs/wm9705.c @@ -19,7 +19,6 @@ #include #include #include -#include #include "wm9705.h" diff --git a/sound/soc/codecs/wm9712.c b/sound/soc/codecs/wm9712.c index 3ca42a35e03a..bf5d4ef1a2a6 100644 --- a/sound/soc/codecs/wm9712.c +++ b/sound/soc/codecs/wm9712.c @@ -20,7 +20,6 @@ #include #include #include -#include #include "wm9712.h" #define WM9712_VERSION "0.4" diff --git a/sound/soc/codecs/wm9713.c b/sound/soc/codecs/wm9713.c index 87b236b16016..38ed98558718 100644 --- a/sound/soc/codecs/wm9713.c +++ b/sound/soc/codecs/wm9713.c @@ -26,7 +26,6 @@ #include #include #include -#include #include "wm9713.h" diff --git a/sound/soc/codecs/wm_hubs.c b/sound/soc/codecs/wm_hubs.c index 422c7fb383eb..e7a19d6ada50 100644 --- a/sound/soc/codecs/wm_hubs.c +++ b/sound/soc/codecs/wm_hubs.c @@ -22,7 +22,6 @@ #include #include #include -#include #include #include -- cgit v1.2.2 From 0d911baebf983931cb37e25b36c3371d9e4b5196 Mon Sep 17 00:00:00 2001 From: Jarkko Nikula Date: Sun, 21 Nov 2010 19:48:46 +0200 Subject: ASoC: Do not include soc-dai.h There is no need to include soc-dai.h since soc.h includes it. Convert drivers to include only soc.h. Signed-off-by: Jarkko Nikula Acked-by: Liam Girdwood Signed-off-by: Mark Brown --- sound/soc/codecs/cq93vc.c | 1 - sound/soc/codecs/wl1273.c | 2 +- 2 files changed, 1 insertion(+), 2 deletions(-) (limited to 'sound/soc/codecs') diff --git a/sound/soc/codecs/cq93vc.c b/sound/soc/codecs/cq93vc.c index 1a6f511051b6..46dbfd067f79 100644 --- a/sound/soc/codecs/cq93vc.c +++ b/sound/soc/codecs/cq93vc.c @@ -36,7 +36,6 @@ #include #include #include -#include #include #include diff --git a/sound/soc/codecs/wl1273.c b/sound/soc/codecs/wl1273.c index c606b3e235fa..d3ffa2f0122a 100644 --- a/sound/soc/codecs/wl1273.c +++ b/sound/soc/codecs/wl1273.c @@ -25,7 +25,7 @@ #include #include #include -#include +#include #include #include "wl1273.h" -- cgit v1.2.2 From c7b642911ea0fa9168425757752f094a1255209a Mon Sep 17 00:00:00 2001 From: Axel Lin Date: Mon, 22 Nov 2010 08:34:07 +0800 Subject: ASoC: Fix a memory leak in alc5623_i2c_probe error path Signed-off-by: Axel Lin Acked-by: Liam Girdwood Signed-off-by: Mark Brown --- sound/soc/codecs/alc5623.c | 11 +++-------- 1 file changed, 3 insertions(+), 8 deletions(-) (limited to 'sound/soc/codecs') diff --git a/sound/soc/codecs/alc5623.c b/sound/soc/codecs/alc5623.c index e84b26b0ce9e..9783e7e2eb93 100644 --- a/sound/soc/codecs/alc5623.c +++ b/sound/soc/codecs/alc5623.c @@ -1022,10 +1022,8 @@ static int alc5623_i2c_probe(struct i2c_client *client, dev_dbg(&client->dev, "Found codec id : alc56%02x\n", vid2); alc5623 = kzalloc(sizeof(struct alc5623_priv), GFP_KERNEL); - if (alc5623 == NULL) { - ret = -ENOMEM; - goto err; - } + if (alc5623 == NULL) + return -ENOMEM; pdata = client->dev.platform_data; if (pdata) { @@ -1056,12 +1054,9 @@ static int alc5623_i2c_probe(struct i2c_client *client, &soc_codec_device_alc5623, &alc5623_dai, 1); if (ret != 0) { dev_err(&client->dev, "Failed to register codec: %d\n", ret); - goto err; + kfree(alc5623); } - return 0; - -err: return ret; } -- cgit v1.2.2 From 2a9ae13a2641373d06e24f866c7427644c39bfea Mon Sep 17 00:00:00 2001 From: Mark Brown Date: Tue, 23 Nov 2010 19:31:18 +0000 Subject: ASoC: Add initial WM8737 driver The WM8737 is a low power, flexible stereo ADC designed for portable applications. This driver supports most of the functionality of the WM8737, though some features such as the ALC are not yet implemented. Signed-off-by: Mark Brown --- sound/soc/codecs/Kconfig | 4 + sound/soc/codecs/Makefile | 2 + sound/soc/codecs/wm8737.c | 713 ++++++++++++++++++++++++++++++++++++++++++++++ sound/soc/codecs/wm8737.h | 322 +++++++++++++++++++++ 4 files changed, 1041 insertions(+) create mode 100644 sound/soc/codecs/wm8737.c create mode 100644 sound/soc/codecs/wm8737.h (limited to 'sound/soc/codecs') diff --git a/sound/soc/codecs/Kconfig b/sound/soc/codecs/Kconfig index 6ebd3a685b2c..0f33db2be25a 100644 --- a/sound/soc/codecs/Kconfig +++ b/sound/soc/codecs/Kconfig @@ -55,6 +55,7 @@ config SND_SOC_ALL_CODECS select SND_SOC_WM8727 select SND_SOC_WM8728 if SND_SOC_I2C_AND_SPI select SND_SOC_WM8731 if SND_SOC_I2C_AND_SPI + select SND_SOC_WM8737 if SND_SOC_I2C_AND_SPI select SND_SOC_WM8741 if SND_SOC_I2C_AND_SPI select SND_SOC_WM8750 if SND_SOC_I2C_AND_SPI select SND_SOC_WM8753 if SND_SOC_I2C_AND_SPI @@ -236,6 +237,9 @@ config SND_SOC_WM8728 config SND_SOC_WM8731 tristate +config SND_SOC_WM8737 + tristate + config SND_SOC_WM8741 tristate diff --git a/sound/soc/codecs/Makefile b/sound/soc/codecs/Makefile index 3469fab2863a..10e5e099334a 100644 --- a/sound/soc/codecs/Makefile +++ b/sound/soc/codecs/Makefile @@ -39,6 +39,7 @@ snd-soc-wm8711-objs := wm8711.o snd-soc-wm8727-objs := wm8727.o snd-soc-wm8728-objs := wm8728.o snd-soc-wm8731-objs := wm8731.o +snd-soc-wm8737-objs := wm8737.o snd-soc-wm8741-objs := wm8741.o snd-soc-wm8750-objs := wm8750.o snd-soc-wm8753-objs := wm8753.o @@ -116,6 +117,7 @@ obj-$(CONFIG_SND_SOC_WM8711) += snd-soc-wm8711.o obj-$(CONFIG_SND_SOC_WM8727) += snd-soc-wm8727.o obj-$(CONFIG_SND_SOC_WM8728) += snd-soc-wm8728.o obj-$(CONFIG_SND_SOC_WM8731) += snd-soc-wm8731.o +obj-$(CONFIG_SND_SOC_WM8737) += snd-soc-wm8737.o obj-$(CONFIG_SND_SOC_WM8741) += snd-soc-wm8741.o obj-$(CONFIG_SND_SOC_WM8750) += snd-soc-wm8750.o obj-$(CONFIG_SND_SOC_WM8753) += snd-soc-wm8753.o diff --git a/sound/soc/codecs/wm8737.c b/sound/soc/codecs/wm8737.c new file mode 100644 index 000000000000..a325fe60d26c --- /dev/null +++ b/sound/soc/codecs/wm8737.c @@ -0,0 +1,713 @@ +/* + * wm8737.c -- WM8737 ALSA SoC Audio driver + * + * Copyright 2010 Wolfson Microelectronics plc + * + * Author: Mark Brown + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "wm8737.h" + +#define WM8737_NUM_SUPPLIES 4 +static const char *wm8737_supply_names[WM8737_NUM_SUPPLIES] = { + "DCVDD", + "DBVDD", + "AVDD", + "MVDD", +}; + +/* codec private data */ +struct wm8737_priv { + enum snd_soc_control_type control_type; + struct regulator_bulk_data supplies[WM8737_NUM_SUPPLIES]; + unsigned int mclk; +}; + +static const u16 wm8737_reg[WM8737_REGISTER_COUNT] = { + 0x00C3, /* R0 - Left PGA volume */ + 0x00C3, /* R1 - Right PGA volume */ + 0x0007, /* R2 - AUDIO path L */ + 0x0007, /* R3 - AUDIO path R */ + 0x0000, /* R4 - 3D Enhance */ + 0x0000, /* R5 - ADC Control */ + 0x0000, /* R6 - Power Management */ + 0x000A, /* R7 - Audio Format */ + 0x0000, /* R8 - Clocking */ + 0x000F, /* R9 - MIC Preamp Control */ + 0x0003, /* R10 - Misc Bias Control */ + 0x0000, /* R11 - Noise Gate */ + 0x007C, /* R12 - ALC1 */ + 0x0000, /* R13 - ALC2 */ + 0x0032, /* R14 - ALC3 */ +}; + +static int wm8737_reset(struct snd_soc_codec *codec) +{ + return snd_soc_write(codec, WM8737_RESET, 0); +} + +static const unsigned int micboost_tlv[] = { + TLV_DB_RANGE_HEAD(4), + 0, 0, TLV_DB_SCALE_ITEM(1300, 0, 0), + 1, 1, TLV_DB_SCALE_ITEM(1800, 0, 0), + 2, 2, TLV_DB_SCALE_ITEM(2800, 0, 0), + 3, 3, TLV_DB_SCALE_ITEM(3300, 0, 0), +}; +static const DECLARE_TLV_DB_SCALE(pga_tlv, -9750, 50, 1); +static const DECLARE_TLV_DB_SCALE(adc_tlv, -600, 600, 0); +static const DECLARE_TLV_DB_SCALE(ng_tlv, -7800, 600, 0); + +static const char *micbias_enum_text[] = { + "25%", + "50%", + "75%", + "100%", +}; + +static const struct soc_enum micbias_enum = + SOC_ENUM_SINGLE(WM8737_MIC_PREAMP_CONTROL, 0, 4, micbias_enum_text); + +static const char *low_cutoff_text[] = { + "Low", "High" +}; + +static const struct soc_enum low_3d = + SOC_ENUM_SINGLE(WM8737_3D_ENHANCE, 6, 2, low_cutoff_text); + +static const char *high_cutoff_text[] = { + "High", "Low" +}; + +static const struct soc_enum high_3d = + SOC_ENUM_SINGLE(WM8737_3D_ENHANCE, 5, 2, high_cutoff_text); + +static const struct snd_kcontrol_new wm8737_snd_controls[] = { +SOC_DOUBLE_R_TLV("Mic Boost Volume", WM8737_AUDIO_PATH_L, WM8737_AUDIO_PATH_R, + 6, 3, 0, micboost_tlv), +SOC_DOUBLE_R("Mic Boost Switch", WM8737_AUDIO_PATH_L, WM8737_AUDIO_PATH_R, + 4, 1, 0), +SOC_DOUBLE("Mic ZC Switch", WM8737_AUDIO_PATH_L, WM8737_AUDIO_PATH_R, + 3, 1, 0), + +SOC_DOUBLE_R_TLV("Capture Volume", WM8737_LEFT_PGA_VOLUME, + WM8737_RIGHT_PGA_VOLUME, 0, 255, 0, pga_tlv), +SOC_DOUBLE("Capture ZC Switch", WM8737_AUDIO_PATH_L, WM8737_AUDIO_PATH_R, + 2, 1, 0), + +SOC_DOUBLE("INPUT1 DC Bias Switch", WM8737_MISC_BIAS_CONTROL, 0, 1, 1, 0), + +SOC_ENUM("Mic PGA Bias", micbias_enum), +SOC_SINGLE("ADC Low Power Switch", WM8737_ADC_CONTROL, 2, 1, 0), +SOC_SINGLE("High Pass Filter Switch", WM8737_ADC_CONTROL, 0, 1, 1), +SOC_DOUBLE("Polarity Invert Switch", WM8737_ADC_CONTROL, 5, 6, 1, 0), + +SOC_SINGLE("3D Switch", WM8737_3D_ENHANCE, 0, 1, 0), +SOC_SINGLE("3D Depth", WM8737_3D_ENHANCE, 1, 15, 0), +SOC_ENUM("3D Low Cut-off", low_3d), +SOC_ENUM("3D High Cut-off", low_3d), +SOC_SINGLE_TLV("3D ADC Volume", WM8737_3D_ENHANCE, 7, 1, 1, adc_tlv), + +SOC_SINGLE("Noise Gate Switch", WM8737_NOISE_GATE, 0, 1, 0), +SOC_SINGLE_TLV("Noise Gate Threshold Volume", WM8737_NOISE_GATE, 2, 7, 0, + ng_tlv), +}; + +static const char *linsel_text[] = { + "LINPUT1", "LINPUT2", "LINPUT3", "LINPUT1 DC", +}; + +static const struct soc_enum linsel_enum = + SOC_ENUM_SINGLE(WM8737_AUDIO_PATH_L, 7, 4, linsel_text); + +static const struct snd_kcontrol_new linsel_mux = + SOC_DAPM_ENUM("LINSEL", linsel_enum); + + +static const char *rinsel_text[] = { + "RINPUT1", "RINPUT2", "RINPUT3", "RINPUT1 DC", +}; + +static const struct soc_enum rinsel_enum = + SOC_ENUM_SINGLE(WM8737_AUDIO_PATH_R, 7, 4, rinsel_text); + +static const struct snd_kcontrol_new rinsel_mux = + SOC_DAPM_ENUM("RINSEL", rinsel_enum); + +static const char *bypass_text[] = { + "Direct", "Preamp" +}; + +static const struct soc_enum lbypass_enum = + SOC_ENUM_SINGLE(WM8737_MIC_PREAMP_CONTROL, 2, 2, bypass_text); + +static const struct snd_kcontrol_new lbypass_mux = + SOC_DAPM_ENUM("Left Bypass", lbypass_enum); + + +static const struct soc_enum rbypass_enum = + SOC_ENUM_SINGLE(WM8737_MIC_PREAMP_CONTROL, 3, 2, bypass_text); + +static const struct snd_kcontrol_new rbypass_mux = + SOC_DAPM_ENUM("Left Bypass", rbypass_enum); + +static const struct snd_soc_dapm_widget wm8737_dapm_widgets[] = { +SND_SOC_DAPM_INPUT("LINPUT1"), +SND_SOC_DAPM_INPUT("LINPUT2"), +SND_SOC_DAPM_INPUT("LINPUT3"), +SND_SOC_DAPM_INPUT("RINPUT1"), +SND_SOC_DAPM_INPUT("RINPUT2"), +SND_SOC_DAPM_INPUT("RINPUT3"), +SND_SOC_DAPM_INPUT("LACIN"), +SND_SOC_DAPM_INPUT("RACIN"), + +SND_SOC_DAPM_MUX("LINSEL", SND_SOC_NOPM, 0, 0, &linsel_mux), +SND_SOC_DAPM_MUX("RINSEL", SND_SOC_NOPM, 0, 0, &rinsel_mux), + +SND_SOC_DAPM_MUX("Left Preamp Mux", SND_SOC_NOPM, 0, 0, &lbypass_mux), +SND_SOC_DAPM_MUX("Right Preamp Mux", SND_SOC_NOPM, 0, 0, &rbypass_mux), + +SND_SOC_DAPM_PGA("PGAL", WM8737_POWER_MANAGEMENT, 5, 0, NULL, 0), +SND_SOC_DAPM_PGA("PGAR", WM8737_POWER_MANAGEMENT, 4, 0, NULL, 0), + +SND_SOC_DAPM_DAC("ADCL", NULL, WM8737_POWER_MANAGEMENT, 3, 0), +SND_SOC_DAPM_DAC("ADCR", NULL, WM8737_POWER_MANAGEMENT, 2, 0), + +SND_SOC_DAPM_AIF_OUT("AIF", "Capture", 0, WM8737_POWER_MANAGEMENT, 6, 0), +}; + +static const struct snd_soc_dapm_route intercon[] = { + { "LINSEL", "LINPUT1", "LINPUT1" }, + { "LINSEL", "LINPUT2", "LINPUT2" }, + { "LINSEL", "LINPUT3", "LINPUT3" }, + { "LINSEL", "LINPUT1 DC", "LINPUT1" }, + + { "RINSEL", "RINPUT1", "RINPUT1" }, + { "RINSEL", "RINPUT2", "RINPUT2" }, + { "RINSEL", "RINPUT3", "RINPUT3" }, + { "RINSEL", "RINPUT1 DC", "RINPUT1" }, + + { "Left Preamp Mux", "Preamp", "LINSEL" }, + { "Left Preamp Mux", "Direct", "LACIN" }, + + { "Right Preamp Mux", "Preamp", "RINSEL" }, + { "Right Preamp Mux", "Direct", "RACIN" }, + + { "PGAL", NULL, "Left Preamp Mux" }, + { "PGAR", NULL, "Right Preamp Mux" }, + + { "ADCL", NULL, "PGAL" }, + { "ADCR", NULL, "PGAR" }, + + { "AIF", NULL, "ADCL" }, + { "AIF", NULL, "ADCR" }, +}; + +static int wm8737_add_widgets(struct snd_soc_codec *codec) +{ + struct snd_soc_dapm_context *dapm = &codec->dapm; + + snd_soc_dapm_new_controls(dapm, wm8737_dapm_widgets, + ARRAY_SIZE(wm8737_dapm_widgets)); + snd_soc_dapm_add_routes(dapm, intercon, ARRAY_SIZE(intercon)); + + return 0; +} + +/* codec mclk clock divider coefficients */ +static const struct { + u32 mclk; + u32 rate; + u8 usb; + u8 sr; +} coeff_div[] = { + { 12288000, 8000, 0, 0x4 }, + { 12288000, 12000, 0, 0x8 }, + { 12288000, 16000, 0, 0xa }, + { 12288000, 24000, 0, 0x1c }, + { 12288000, 32000, 0, 0xc }, + { 12288000, 48000, 0, 0 }, + { 12288000, 96000, 0, 0xe }, + + { 11289600, 8000, 0, 0x14 }, + { 11289600, 11025, 0, 0x18 }, + { 11289600, 22050, 0, 0x1a }, + { 11289600, 44100, 0, 0x10 }, + { 11289600, 88200, 0, 0x1e }, + + { 18432000, 8000, 0, 0x5 }, + { 18432000, 12000, 0, 0x9 }, + { 18432000, 16000, 0, 0xb }, + { 18432000, 24000, 0, 0x1b }, + { 18432000, 32000, 0, 0xd }, + { 18432000, 48000, 0, 0x1 }, + { 18432000, 96000, 0, 0x1f }, + + { 16934400, 8000, 0, 0x15 }, + { 16934400, 11025, 0, 0x19 }, + { 16934400, 22050, 0, 0x1b }, + { 16934400, 44100, 0, 0x11 }, + { 16934400, 88200, 0, 0x1f }, + + { 12000000, 8000, 1, 0x4 }, + { 12000000, 11025, 1, 0x19 }, + { 12000000, 12000, 1, 0x8 }, + { 12000000, 16000, 1, 0xa }, + { 12000000, 22050, 1, 0x1b }, + { 12000000, 24000, 1, 0x1c }, + { 12000000, 32000, 1, 0xc }, + { 12000000, 44100, 1, 0x11 }, + { 12000000, 48000, 1, 0x0 }, + { 12000000, 88200, 1, 0x1f }, + { 12000000, 96000, 1, 0xe }, +}; + +static int wm8737_hw_params(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params, + struct snd_soc_dai *dai) +{ + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct snd_soc_codec *codec = rtd->codec; + struct wm8737_priv *wm8737 = snd_soc_codec_get_drvdata(codec); + int i; + u16 clocking = 0; + u16 af = 0; + + for (i = 0; i < ARRAY_SIZE(coeff_div); i++) { + if (coeff_div[i].rate != params_rate(params)) + continue; + + if (coeff_div[i].mclk == wm8737->mclk) + break; + + if (coeff_div[i].mclk == wm8737->mclk * 2) { + clocking |= WM8737_CLKDIV2; + break; + } + } + + if (i == ARRAY_SIZE(coeff_div)) { + dev_err(codec->dev, "%dHz MCLK can't support %dHz\n", + wm8737->mclk, params_rate(params)); + return -EINVAL; + } + + clocking |= coeff_div[i].usb | (coeff_div[i].sr << WM8737_SR_SHIFT); + + switch (params_format(params)) { + case SNDRV_PCM_FORMAT_S16_LE: + break; + case SNDRV_PCM_FORMAT_S20_3LE: + af |= 0x8; + break; + case SNDRV_PCM_FORMAT_S24_LE: + af |= 0x10; + break; + case SNDRV_PCM_FORMAT_S32_LE: + af |= 0x18; + break; + default: + return -EINVAL; + } + + snd_soc_update_bits(codec, WM8737_AUDIO_FORMAT, WM8737_WL_MASK, af); + snd_soc_update_bits(codec, WM8737_CLOCKING, + WM8737_USB_MODE | WM8737_CLKDIV2 | WM8737_SR_MASK, + clocking); + + return 0; +} + +static int wm8737_set_dai_sysclk(struct snd_soc_dai *codec_dai, + int clk_id, unsigned int freq, int dir) +{ + struct snd_soc_codec *codec = codec_dai->codec; + struct wm8737_priv *wm8737 = snd_soc_codec_get_drvdata(codec); + int i; + + for (i = 0; i < ARRAY_SIZE(coeff_div); i++) { + if (freq == coeff_div[i].mclk || + freq == coeff_div[i].mclk * 2) { + wm8737->mclk = freq; + return 0; + } + } + + dev_err(codec->dev, "MCLK rate %dHz not supported\n", freq); + + return -EINVAL; +} + + +static int wm8737_set_dai_fmt(struct snd_soc_dai *codec_dai, + unsigned int fmt) +{ + struct snd_soc_codec *codec = codec_dai->codec; + u16 af = 0; + + switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { + case SND_SOC_DAIFMT_CBM_CFM: + af |= WM8737_MS; + break; + case SND_SOC_DAIFMT_CBS_CFS: + break; + default: + return -EINVAL; + } + + switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { + case SND_SOC_DAIFMT_I2S: + af |= 0x2; + break; + case SND_SOC_DAIFMT_RIGHT_J: + break; + case SND_SOC_DAIFMT_LEFT_J: + af |= 0x1; + break; + case SND_SOC_DAIFMT_DSP_A: + af |= 0x3; + break; + case SND_SOC_DAIFMT_DSP_B: + af |= 0x13; + break; + default: + return -EINVAL; + } + + switch (fmt & SND_SOC_DAIFMT_INV_MASK) { + case SND_SOC_DAIFMT_NB_NF: + break; + case SND_SOC_DAIFMT_NB_IF: + af |= WM8737_LRP; + break; + default: + return -EINVAL; + } + + snd_soc_update_bits(codec, WM8737_AUDIO_FORMAT, + WM8737_FORMAT_MASK | WM8737_LRP | WM8737_MS, af); + + return 0; +} + +static int wm8737_set_bias_level(struct snd_soc_codec *codec, + enum snd_soc_bias_level level) +{ + struct wm8737_priv *wm8737 = snd_soc_codec_get_drvdata(codec); + int ret; + + switch (level) { + case SND_SOC_BIAS_ON: + break; + + case SND_SOC_BIAS_PREPARE: + /* VMID at 2*75k */ + snd_soc_update_bits(codec, WM8737_MISC_BIAS_CONTROL, + WM8737_VMIDSEL_MASK, 0); + break; + + case SND_SOC_BIAS_STANDBY: + if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) { + ret = regulator_bulk_enable(ARRAY_SIZE(wm8737->supplies), + wm8737->supplies); + if (ret != 0) { + dev_err(codec->dev, + "Failed to enable supplies: %d\n", + ret); + return ret; + } + + snd_soc_cache_sync(codec); + + /* Fast VMID ramp at 2*2.5k */ + snd_soc_update_bits(codec, WM8737_MISC_BIAS_CONTROL, + WM8737_VMIDSEL_MASK, 0x4); + + /* Bring VMID up */ + snd_soc_update_bits(codec, WM8737_POWER_MANAGEMENT, + WM8737_VMID_MASK | + WM8737_VREF_MASK, + WM8737_VMID_MASK | + WM8737_VREF_MASK); + + msleep(500); + } + + /* VMID at 2*300k */ + snd_soc_update_bits(codec, WM8737_MISC_BIAS_CONTROL, + WM8737_VMIDSEL_MASK, 2); + + break; + + case SND_SOC_BIAS_OFF: + snd_soc_update_bits(codec, WM8737_POWER_MANAGEMENT, + WM8737_VMID_MASK | WM8737_VREF_MASK, 0); + + regulator_bulk_disable(ARRAY_SIZE(wm8737->supplies), + wm8737->supplies); + break; + } + + codec->dapm.bias_level = level; + return 0; +} + +#define WM8737_RATES SNDRV_PCM_RATE_8000_96000 + +#define WM8737_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\ + SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE) + +static struct snd_soc_dai_ops wm8737_dai_ops = { + .hw_params = wm8737_hw_params, + .set_sysclk = wm8737_set_dai_sysclk, + .set_fmt = wm8737_set_dai_fmt, +}; + +static struct snd_soc_dai_driver wm8737_dai = { + .name = "wm8737", + .capture = { + .stream_name = "Capture", + .channels_min = 2, /* Mono modes not yet supported */ + .channels_max = 2, + .rates = WM8737_RATES, + .formats = WM8737_FORMATS, + }, + .ops = &wm8737_dai_ops, +}; + +#ifdef CONFIG_PM +static int wm8737_suspend(struct snd_soc_codec *codec, pm_message_t state) +{ + wm8737_set_bias_level(codec, SND_SOC_BIAS_OFF); + return 0; +} + +static int wm8737_resume(struct snd_soc_codec *codec) +{ + wm8737_set_bias_level(codec, SND_SOC_BIAS_STANDBY); + return 0; +} +#else +#define wm8737_suspend NULL +#define wm8737_resume NULL +#endif + +static int wm8737_probe(struct snd_soc_codec *codec) +{ + struct wm8737_priv *wm8737 = snd_soc_codec_get_drvdata(codec); + int ret, i; + + codec->hw_write = (hw_write_t)i2c_master_send; + ret = snd_soc_codec_set_cache_io(codec, 7, 9, wm8737->control_type); + if (ret != 0) { + dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret); + return ret; + } + + for (i = 0; i < ARRAY_SIZE(wm8737->supplies); i++) + wm8737->supplies[i].supply = wm8737_supply_names[i]; + + ret = regulator_bulk_get(codec->dev, ARRAY_SIZE(wm8737->supplies), + wm8737->supplies); + if (ret != 0) { + dev_err(codec->dev, "Failed to request supplies: %d\n", ret); + return ret; + } + + ret = regulator_bulk_enable(ARRAY_SIZE(wm8737->supplies), + wm8737->supplies); + if (ret != 0) { + dev_err(codec->dev, "Failed to enable supplies: %d\n", ret); + goto err_get; + } + + ret = wm8737_reset(codec); + if (ret < 0) { + dev_err(codec->dev, "Failed to issue reset\n"); + goto err_enable; + } + + snd_soc_update_bits(codec, WM8737_LEFT_PGA_VOLUME, WM8737_LVU, + WM8737_LVU); + snd_soc_update_bits(codec, WM8737_RIGHT_PGA_VOLUME, WM8737_RVU, + WM8737_RVU); + + wm8737_set_bias_level(codec, SND_SOC_BIAS_STANDBY); + + /* Bias level configuration will have done an extra enable */ + regulator_bulk_disable(ARRAY_SIZE(wm8737->supplies), wm8737->supplies); + + snd_soc_add_controls(codec, wm8737_snd_controls, + ARRAY_SIZE(wm8737_snd_controls)); + wm8737_add_widgets(codec); + + return 0; + +err_enable: + regulator_bulk_disable(ARRAY_SIZE(wm8737->supplies), wm8737->supplies); +err_get: + regulator_bulk_free(ARRAY_SIZE(wm8737->supplies), wm8737->supplies); + + return ret; +} + +static int wm8737_remove(struct snd_soc_codec *codec) +{ + struct wm8737_priv *wm8737 = snd_soc_codec_get_drvdata(codec); + + wm8737_set_bias_level(codec, SND_SOC_BIAS_OFF); + regulator_bulk_free(ARRAY_SIZE(wm8737->supplies), wm8737->supplies); + return 0; +} + +static struct snd_soc_codec_driver soc_codec_dev_wm8737 = { + .probe = wm8737_probe, + .remove = wm8737_remove, + .suspend = wm8737_suspend, + .resume = wm8737_resume, + .set_bias_level = wm8737_set_bias_level, + + .reg_cache_size = WM8737_REGISTER_COUNT - 1, /* Skip reset */ + .reg_word_size = sizeof(u16), + .reg_cache_default = wm8737_reg, +}; + +#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) +static __devinit int wm8737_i2c_probe(struct i2c_client *i2c, + const struct i2c_device_id *id) +{ + struct wm8737_priv *wm8737; + int ret; + + wm8737 = kzalloc(sizeof(struct wm8737_priv), GFP_KERNEL); + if (wm8737 == NULL) + return -ENOMEM; + + i2c_set_clientdata(i2c, wm8737); + wm8737->control_type = SND_SOC_I2C; + + ret = snd_soc_register_codec(&i2c->dev, + &soc_codec_dev_wm8737, &wm8737_dai, 1); + if (ret < 0) + kfree(wm8737); + return ret; + +} + +static __devexit int wm8737_i2c_remove(struct i2c_client *client) +{ + snd_soc_unregister_codec(&client->dev); + kfree(i2c_get_clientdata(client)); + return 0; +} + +static const struct i2c_device_id wm8737_i2c_id[] = { + { "wm8737", 0 }, + { } +}; +MODULE_DEVICE_TABLE(i2c, wm8737_i2c_id); + +static struct i2c_driver wm8737_i2c_driver = { + .driver = { + .name = "wm8737", + .owner = THIS_MODULE, + }, + .probe = wm8737_i2c_probe, + .remove = __devexit_p(wm8737_i2c_remove), + .id_table = wm8737_i2c_id, +}; +#endif + +#if defined(CONFIG_SPI_MASTER) +static int __devinit wm8737_spi_probe(struct spi_device *spi) +{ + struct wm8737_priv *wm8737; + int ret; + + wm8737 = kzalloc(sizeof(struct wm8737_priv), GFP_KERNEL); + if (wm8737 == NULL) + return -ENOMEM; + + wm8737->control_type = SND_SOC_SPI; + spi_set_drvdata(spi, wm8737); + + ret = snd_soc_register_codec(&spi->dev, + &soc_codec_dev_wm8737, &wm8737_dai, 1); + if (ret < 0) + kfree(wm8737); + return ret; +} + +static int __devexit wm8737_spi_remove(struct spi_device *spi) +{ + snd_soc_unregister_codec(&spi->dev); + kfree(spi_get_drvdata(spi)); + return 0; +} + +static struct spi_driver wm8737_spi_driver = { + .driver = { + .name = "wm8737", + .owner = THIS_MODULE, + }, + .probe = wm8737_spi_probe, + .remove = __devexit_p(wm8737_spi_remove), +}; +#endif /* CONFIG_SPI_MASTER */ + +static int __init wm8737_modinit(void) +{ + int ret; +#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) + ret = i2c_add_driver(&wm8737_i2c_driver); + if (ret != 0) { + printk(KERN_ERR "Failed to register WM8737 I2C driver: %d\n", + ret); + } +#endif +#if defined(CONFIG_SPI_MASTER) + ret = spi_register_driver(&wm8737_spi_driver); + if (ret != 0) { + printk(KERN_ERR "Failed to register WM8737 SPI driver: %d\n", + ret); + } +#endif + return 0; +} +module_init(wm8737_modinit); + +static void __exit wm8737_exit(void) +{ +#if defined(CONFIG_SPI_MASTER) + spi_unregister_driver(&wm8737_spi_driver); +#endif +#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) + i2c_del_driver(&wm8737_i2c_driver); +#endif +} +module_exit(wm8737_exit); + +MODULE_DESCRIPTION("ASoC WM8737 driver"); +MODULE_AUTHOR("Mark Brown "); +MODULE_LICENSE("GPL"); diff --git a/sound/soc/codecs/wm8737.h b/sound/soc/codecs/wm8737.h new file mode 100644 index 000000000000..23d14c8ff6e7 --- /dev/null +++ b/sound/soc/codecs/wm8737.h @@ -0,0 +1,322 @@ +#ifndef _WM8737_H +#define _WM8737_H + +/* + * wm8737.c -- WM8523 ALSA SoC Audio driver + * + * Copyright 2010 Wolfson Microelectronics plc + * + * Author: Mark Brown + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/* + * Register values. + */ +#define WM8737_LEFT_PGA_VOLUME 0x00 +#define WM8737_RIGHT_PGA_VOLUME 0x01 +#define WM8737_AUDIO_PATH_L 0x02 +#define WM8737_AUDIO_PATH_R 0x03 +#define WM8737_3D_ENHANCE 0x04 +#define WM8737_ADC_CONTROL 0x05 +#define WM8737_POWER_MANAGEMENT 0x06 +#define WM8737_AUDIO_FORMAT 0x07 +#define WM8737_CLOCKING 0x08 +#define WM8737_MIC_PREAMP_CONTROL 0x09 +#define WM8737_MISC_BIAS_CONTROL 0x0A +#define WM8737_NOISE_GATE 0x0B +#define WM8737_ALC1 0x0C +#define WM8737_ALC2 0x0D +#define WM8737_ALC3 0x0E +#define WM8737_RESET 0x0F + +#define WM8737_REGISTER_COUNT 16 +#define WM8737_MAX_REGISTER 0x0F + +/* + * Field Definitions. + */ + +/* + * R0 (0x00) - Left PGA volume + */ +#define WM8737_LVU 0x0100 /* LVU */ +#define WM8737_LVU_MASK 0x0100 /* LVU */ +#define WM8737_LVU_SHIFT 8 /* LVU */ +#define WM8737_LVU_WIDTH 1 /* LVU */ +#define WM8737_LINVOL_MASK 0x00FF /* LINVOL - [7:0] */ +#define WM8737_LINVOL_SHIFT 0 /* LINVOL - [7:0] */ +#define WM8737_LINVOL_WIDTH 8 /* LINVOL - [7:0] */ + +/* + * R1 (0x01) - Right PGA volume + */ +#define WM8737_RVU 0x0100 /* RVU */ +#define WM8737_RVU_MASK 0x0100 /* RVU */ +#define WM8737_RVU_SHIFT 8 /* RVU */ +#define WM8737_RVU_WIDTH 1 /* RVU */ +#define WM8737_RINVOL_MASK 0x00FF /* RINVOL - [7:0] */ +#define WM8737_RINVOL_SHIFT 0 /* RINVOL - [7:0] */ +#define WM8737_RINVOL_WIDTH 8 /* RINVOL - [7:0] */ + +/* + * R2 (0x02) - AUDIO path L + */ +#define WM8737_LINSEL_MASK 0x0180 /* LINSEL - [8:7] */ +#define WM8737_LINSEL_SHIFT 7 /* LINSEL - [8:7] */ +#define WM8737_LINSEL_WIDTH 2 /* LINSEL - [8:7] */ +#define WM8737_LMICBOOST_MASK 0x0060 /* LMICBOOST - [6:5] */ +#define WM8737_LMICBOOST_SHIFT 5 /* LMICBOOST - [6:5] */ +#define WM8737_LMICBOOST_WIDTH 2 /* LMICBOOST - [6:5] */ +#define WM8737_LMBE 0x0010 /* LMBE */ +#define WM8737_LMBE_MASK 0x0010 /* LMBE */ +#define WM8737_LMBE_SHIFT 4 /* LMBE */ +#define WM8737_LMBE_WIDTH 1 /* LMBE */ +#define WM8737_LMZC 0x0008 /* LMZC */ +#define WM8737_LMZC_MASK 0x0008 /* LMZC */ +#define WM8737_LMZC_SHIFT 3 /* LMZC */ +#define WM8737_LMZC_WIDTH 1 /* LMZC */ +#define WM8737_LPZC 0x0004 /* LPZC */ +#define WM8737_LPZC_MASK 0x0004 /* LPZC */ +#define WM8737_LPZC_SHIFT 2 /* LPZC */ +#define WM8737_LPZC_WIDTH 1 /* LPZC */ +#define WM8737_LZCTO_MASK 0x0003 /* LZCTO - [1:0] */ +#define WM8737_LZCTO_SHIFT 0 /* LZCTO - [1:0] */ +#define WM8737_LZCTO_WIDTH 2 /* LZCTO - [1:0] */ + +/* + * R3 (0x03) - AUDIO path R + */ +#define WM8737_RINSEL_MASK 0x0180 /* RINSEL - [8:7] */ +#define WM8737_RINSEL_SHIFT 7 /* RINSEL - [8:7] */ +#define WM8737_RINSEL_WIDTH 2 /* RINSEL - [8:7] */ +#define WM8737_RMICBOOST_MASK 0x0060 /* RMICBOOST - [6:5] */ +#define WM8737_RMICBOOST_SHIFT 5 /* RMICBOOST - [6:5] */ +#define WM8737_RMICBOOST_WIDTH 2 /* RMICBOOST - [6:5] */ +#define WM8737_RMBE 0x0010 /* RMBE */ +#define WM8737_RMBE_MASK 0x0010 /* RMBE */ +#define WM8737_RMBE_SHIFT 4 /* RMBE */ +#define WM8737_RMBE_WIDTH 1 /* RMBE */ +#define WM8737_RMZC 0x0008 /* RMZC */ +#define WM8737_RMZC_MASK 0x0008 /* RMZC */ +#define WM8737_RMZC_SHIFT 3 /* RMZC */ +#define WM8737_RMZC_WIDTH 1 /* RMZC */ +#define WM8737_RPZC 0x0004 /* RPZC */ +#define WM8737_RPZC_MASK 0x0004 /* RPZC */ +#define WM8737_RPZC_SHIFT 2 /* RPZC */ +#define WM8737_RPZC_WIDTH 1 /* RPZC */ +#define WM8737_RZCTO_MASK 0x0003 /* RZCTO - [1:0] */ +#define WM8737_RZCTO_SHIFT 0 /* RZCTO - [1:0] */ +#define WM8737_RZCTO_WIDTH 2 /* RZCTO - [1:0] */ + +/* + * R4 (0x04) - 3D Enhance + */ +#define WM8737_DIV2 0x0080 /* DIV2 */ +#define WM8737_DIV2_MASK 0x0080 /* DIV2 */ +#define WM8737_DIV2_SHIFT 7 /* DIV2 */ +#define WM8737_DIV2_WIDTH 1 /* DIV2 */ +#define WM8737_3DLC 0x0040 /* 3DLC */ +#define WM8737_3DLC_MASK 0x0040 /* 3DLC */ +#define WM8737_3DLC_SHIFT 6 /* 3DLC */ +#define WM8737_3DLC_WIDTH 1 /* 3DLC */ +#define WM8737_3DUC 0x0020 /* 3DUC */ +#define WM8737_3DUC_MASK 0x0020 /* 3DUC */ +#define WM8737_3DUC_SHIFT 5 /* 3DUC */ +#define WM8737_3DUC_WIDTH 1 /* 3DUC */ +#define WM8737_3DDEPTH_MASK 0x001E /* 3DDEPTH - [4:1] */ +#define WM8737_3DDEPTH_SHIFT 1 /* 3DDEPTH - [4:1] */ +#define WM8737_3DDEPTH_WIDTH 4 /* 3DDEPTH - [4:1] */ +#define WM8737_3DE 0x0001 /* 3DE */ +#define WM8737_3DE_MASK 0x0001 /* 3DE */ +#define WM8737_3DE_SHIFT 0 /* 3DE */ +#define WM8737_3DE_WIDTH 1 /* 3DE */ + +/* + * R5 (0x05) - ADC Control + */ +#define WM8737_MONOMIX_MASK 0x0180 /* MONOMIX - [8:7] */ +#define WM8737_MONOMIX_SHIFT 7 /* MONOMIX - [8:7] */ +#define WM8737_MONOMIX_WIDTH 2 /* MONOMIX - [8:7] */ +#define WM8737_POLARITY_MASK 0x0060 /* POLARITY - [6:5] */ +#define WM8737_POLARITY_SHIFT 5 /* POLARITY - [6:5] */ +#define WM8737_POLARITY_WIDTH 2 /* POLARITY - [6:5] */ +#define WM8737_HPOR 0x0010 /* HPOR */ +#define WM8737_HPOR_MASK 0x0010 /* HPOR */ +#define WM8737_HPOR_SHIFT 4 /* HPOR */ +#define WM8737_HPOR_WIDTH 1 /* HPOR */ +#define WM8737_LP 0x0004 /* LP */ +#define WM8737_LP_MASK 0x0004 /* LP */ +#define WM8737_LP_SHIFT 2 /* LP */ +#define WM8737_LP_WIDTH 1 /* LP */ +#define WM8737_MONOUT 0x0002 /* MONOUT */ +#define WM8737_MONOUT_MASK 0x0002 /* MONOUT */ +#define WM8737_MONOUT_SHIFT 1 /* MONOUT */ +#define WM8737_MONOUT_WIDTH 1 /* MONOUT */ +#define WM8737_ADCHPD 0x0001 /* ADCHPD */ +#define WM8737_ADCHPD_MASK 0x0001 /* ADCHPD */ +#define WM8737_ADCHPD_SHIFT 0 /* ADCHPD */ +#define WM8737_ADCHPD_WIDTH 1 /* ADCHPD */ + +/* + * R6 (0x06) - Power Management + */ +#define WM8737_VMID 0x0100 /* VMID */ +#define WM8737_VMID_MASK 0x0100 /* VMID */ +#define WM8737_VMID_SHIFT 8 /* VMID */ +#define WM8737_VMID_WIDTH 1 /* VMID */ +#define WM8737_VREF 0x0080 /* VREF */ +#define WM8737_VREF_MASK 0x0080 /* VREF */ +#define WM8737_VREF_SHIFT 7 /* VREF */ +#define WM8737_VREF_WIDTH 1 /* VREF */ +#define WM8737_AI 0x0040 /* AI */ +#define WM8737_AI_MASK 0x0040 /* AI */ +#define WM8737_AI_SHIFT 6 /* AI */ +#define WM8737_AI_WIDTH 1 /* AI */ +#define WM8737_PGL 0x0020 /* PGL */ +#define WM8737_PGL_MASK 0x0020 /* PGL */ +#define WM8737_PGL_SHIFT 5 /* PGL */ +#define WM8737_PGL_WIDTH 1 /* PGL */ +#define WM8737_PGR 0x0010 /* PGR */ +#define WM8737_PGR_MASK 0x0010 /* PGR */ +#define WM8737_PGR_SHIFT 4 /* PGR */ +#define WM8737_PGR_WIDTH 1 /* PGR */ +#define WM8737_ADL 0x0008 /* ADL */ +#define WM8737_ADL_MASK 0x0008 /* ADL */ +#define WM8737_ADL_SHIFT 3 /* ADL */ +#define WM8737_ADL_WIDTH 1 /* ADL */ +#define WM8737_ADR 0x0004 /* ADR */ +#define WM8737_ADR_MASK 0x0004 /* ADR */ +#define WM8737_ADR_SHIFT 2 /* ADR */ +#define WM8737_ADR_WIDTH 1 /* ADR */ +#define WM8737_MICBIAS_MASK 0x0003 /* MICBIAS - [1:0] */ +#define WM8737_MICBIAS_SHIFT 0 /* MICBIAS - [1:0] */ +#define WM8737_MICBIAS_WIDTH 2 /* MICBIAS - [1:0] */ + +/* + * R7 (0x07) - Audio Format + */ +#define WM8737_SDODIS 0x0080 /* SDODIS */ +#define WM8737_SDODIS_MASK 0x0080 /* SDODIS */ +#define WM8737_SDODIS_SHIFT 7 /* SDODIS */ +#define WM8737_SDODIS_WIDTH 1 /* SDODIS */ +#define WM8737_MS 0x0040 /* MS */ +#define WM8737_MS_MASK 0x0040 /* MS */ +#define WM8737_MS_SHIFT 6 /* MS */ +#define WM8737_MS_WIDTH 1 /* MS */ +#define WM8737_LRP 0x0010 /* LRP */ +#define WM8737_LRP_MASK 0x0010 /* LRP */ +#define WM8737_LRP_SHIFT 4 /* LRP */ +#define WM8737_LRP_WIDTH 1 /* LRP */ +#define WM8737_WL_MASK 0x000C /* WL - [3:2] */ +#define WM8737_WL_SHIFT 2 /* WL - [3:2] */ +#define WM8737_WL_WIDTH 2 /* WL - [3:2] */ +#define WM8737_FORMAT_MASK 0x0003 /* FORMAT - [1:0] */ +#define WM8737_FORMAT_SHIFT 0 /* FORMAT - [1:0] */ +#define WM8737_FORMAT_WIDTH 2 /* FORMAT - [1:0] */ + +/* + * R8 (0x08) - Clocking + */ +#define WM8737_AUTODETECT 0x0080 /* AUTODETECT */ +#define WM8737_AUTODETECT_MASK 0x0080 /* AUTODETECT */ +#define WM8737_AUTODETECT_SHIFT 7 /* AUTODETECT */ +#define WM8737_AUTODETECT_WIDTH 1 /* AUTODETECT */ +#define WM8737_CLKDIV2 0x0040 /* CLKDIV2 */ +#define WM8737_CLKDIV2_MASK 0x0040 /* CLKDIV2 */ +#define WM8737_CLKDIV2_SHIFT 6 /* CLKDIV2 */ +#define WM8737_CLKDIV2_WIDTH 1 /* CLKDIV2 */ +#define WM8737_SR_MASK 0x003E /* SR - [5:1] */ +#define WM8737_SR_SHIFT 1 /* SR - [5:1] */ +#define WM8737_SR_WIDTH 5 /* SR - [5:1] */ +#define WM8737_USB_MODE 0x0001 /* USB MODE */ +#define WM8737_USB_MODE_MASK 0x0001 /* USB MODE */ +#define WM8737_USB_MODE_SHIFT 0 /* USB MODE */ +#define WM8737_USB_MODE_WIDTH 1 /* USB MODE */ + +/* + * R9 (0x09) - MIC Preamp Control + */ +#define WM8737_RBYPEN 0x0008 /* RBYPEN */ +#define WM8737_RBYPEN_MASK 0x0008 /* RBYPEN */ +#define WM8737_RBYPEN_SHIFT 3 /* RBYPEN */ +#define WM8737_RBYPEN_WIDTH 1 /* RBYPEN */ +#define WM8737_LBYPEN 0x0004 /* LBYPEN */ +#define WM8737_LBYPEN_MASK 0x0004 /* LBYPEN */ +#define WM8737_LBYPEN_SHIFT 2 /* LBYPEN */ +#define WM8737_LBYPEN_WIDTH 1 /* LBYPEN */ +#define WM8737_MBCTRL_MASK 0x0003 /* MBCTRL - [1:0] */ +#define WM8737_MBCTRL_SHIFT 0 /* MBCTRL - [1:0] */ +#define WM8737_MBCTRL_WIDTH 2 /* MBCTRL - [1:0] */ + +/* + * R10 (0x0A) - Misc Bias Control + */ +#define WM8737_VMIDSEL_MASK 0x000C /* VMIDSEL - [3:2] */ +#define WM8737_VMIDSEL_SHIFT 2 /* VMIDSEL - [3:2] */ +#define WM8737_VMIDSEL_WIDTH 2 /* VMIDSEL - [3:2] */ +#define WM8737_LINPUT1_DC_BIAS_ENABLE 0x0002 /* LINPUT1 DC BIAS ENABLE */ +#define WM8737_LINPUT1_DC_BIAS_ENABLE_MASK 0x0002 /* LINPUT1 DC BIAS ENABLE */ +#define WM8737_LINPUT1_DC_BIAS_ENABLE_SHIFT 1 /* LINPUT1 DC BIAS ENABLE */ +#define WM8737_LINPUT1_DC_BIAS_ENABLE_WIDTH 1 /* LINPUT1 DC BIAS ENABLE */ +#define WM8737_RINPUT1_DC_BIAS_ENABLE 0x0001 /* RINPUT1 DC BIAS ENABLE */ +#define WM8737_RINPUT1_DC_BIAS_ENABLE_MASK 0x0001 /* RINPUT1 DC BIAS ENABLE */ +#define WM8737_RINPUT1_DC_BIAS_ENABLE_SHIFT 0 /* RINPUT1 DC BIAS ENABLE */ +#define WM8737_RINPUT1_DC_BIAS_ENABLE_WIDTH 1 /* RINPUT1 DC BIAS ENABLE */ + +/* + * R11 (0x0B) - Noise Gate + */ +#define WM8737_NGTH_MASK 0x001C /* NGTH - [4:2] */ +#define WM8737_NGTH_SHIFT 2 /* NGTH - [4:2] */ +#define WM8737_NGTH_WIDTH 3 /* NGTH - [4:2] */ +#define WM8737_NGAT 0x0001 /* NGAT */ +#define WM8737_NGAT_MASK 0x0001 /* NGAT */ +#define WM8737_NGAT_SHIFT 0 /* NGAT */ +#define WM8737_NGAT_WIDTH 1 /* NGAT */ + +/* + * R12 (0x0C) - ALC1 + */ +#define WM8737_ALCSEL_MASK 0x0180 /* ALCSEL - [8:7] */ +#define WM8737_ALCSEL_SHIFT 7 /* ALCSEL - [8:7] */ +#define WM8737_ALCSEL_WIDTH 2 /* ALCSEL - [8:7] */ +#define WM8737_MAX_GAIN_MASK 0x0070 /* MAX GAIN - [6:4] */ +#define WM8737_MAX_GAIN_SHIFT 4 /* MAX GAIN - [6:4] */ +#define WM8737_MAX_GAIN_WIDTH 3 /* MAX GAIN - [6:4] */ +#define WM8737_ALCL_MASK 0x000F /* ALCL - [3:0] */ +#define WM8737_ALCL_SHIFT 0 /* ALCL - [3:0] */ +#define WM8737_ALCL_WIDTH 4 /* ALCL - [3:0] */ + +/* + * R13 (0x0D) - ALC2 + */ +#define WM8737_ALCZCE 0x0010 /* ALCZCE */ +#define WM8737_ALCZCE_MASK 0x0010 /* ALCZCE */ +#define WM8737_ALCZCE_SHIFT 4 /* ALCZCE */ +#define WM8737_ALCZCE_WIDTH 1 /* ALCZCE */ +#define WM8737_HLD_MASK 0x000F /* HLD - [3:0] */ +#define WM8737_HLD_SHIFT 0 /* HLD - [3:0] */ +#define WM8737_HLD_WIDTH 4 /* HLD - [3:0] */ + +/* + * R14 (0x0E) - ALC3 + */ +#define WM8737_DCY_MASK 0x00F0 /* DCY - [7:4] */ +#define WM8737_DCY_SHIFT 4 /* DCY - [7:4] */ +#define WM8737_DCY_WIDTH 4 /* DCY - [7:4] */ +#define WM8737_ATK_MASK 0x000F /* ATK - [3:0] */ +#define WM8737_ATK_SHIFT 0 /* ATK - [3:0] */ +#define WM8737_ATK_WIDTH 4 /* ATK - [3:0] */ + +/* + * R15 (0x0F) - Reset + */ +#define WM8737_RESET_MASK 0x01FF /* RESET - [8:0] */ +#define WM8737_RESET_SHIFT 0 /* RESET - [8:0] */ +#define WM8737_RESET_WIDTH 9 /* RESET - [8:0] */ + +#endif -- cgit v1.2.2 From fcd02e261bb3b1ae14830d33da5401c6c4ee9bcc Mon Sep 17 00:00:00 2001 From: Mark Brown Date: Wed, 24 Nov 2010 16:27:08 +0000 Subject: ASoC: Add WM8737 ALC support Signed-off-by: Mark Brown Acked-by: Liam Girdwood --- sound/soc/codecs/wm8737.c | 42 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 42 insertions(+) (limited to 'sound/soc/codecs') diff --git a/sound/soc/codecs/wm8737.c b/sound/soc/codecs/wm8737.c index a325fe60d26c..2301338cb2c9 100644 --- a/sound/soc/codecs/wm8737.c +++ b/sound/soc/codecs/wm8737.c @@ -78,6 +78,8 @@ static const unsigned int micboost_tlv[] = { static const DECLARE_TLV_DB_SCALE(pga_tlv, -9750, 50, 1); static const DECLARE_TLV_DB_SCALE(adc_tlv, -600, 600, 0); static const DECLARE_TLV_DB_SCALE(ng_tlv, -7800, 600, 0); +static const DECLARE_TLV_DB_SCALE(alc_max_tlv, -1200, 600, 0); +static const DECLARE_TLV_DB_SCALE(alc_target_tlv, -1800, 100, 0); static const char *micbias_enum_text[] = { "25%", @@ -103,6 +105,38 @@ static const char *high_cutoff_text[] = { static const struct soc_enum high_3d = SOC_ENUM_SINGLE(WM8737_3D_ENHANCE, 5, 2, high_cutoff_text); +static const char *alc_fn_text[] = { + "Disabled", "Right", "Left", "Stereo" +}; + +static const struct soc_enum alc_fn = + SOC_ENUM_SINGLE(WM8737_ALC1, 7, 4, alc_fn_text); + +static const char *alc_hold_text[] = { + "0", "2.67ms", "5.33ms", "10.66ms", "21.32ms", "42.64ms", "85.28ms", + "170.56ms", "341.12ms", "682.24ms", "1.364s", "2.728s", "5.458s", + "10.916s", "21.832s", "43.691s" +}; + +static const struct soc_enum alc_hold = + SOC_ENUM_SINGLE(WM8737_ALC2, 0, 16, alc_hold_text); + +static const char *alc_atk_text[] = { + "8.4ms", "16.8ms", "33.6ms", "67.2ms", "134.4ms", "268.8ms", "537.6ms", + "1.075s", "2.15s", "4.3s", "8.6s" +}; + +static const struct soc_enum alc_atk = + SOC_ENUM_SINGLE(WM8737_ALC3, 0, 11, alc_atk_text); + +static const char *alc_dcy_text[] = { + "33.6ms", "67.2ms", "134.4ms", "268.8ms", "537.6ms", "1.075s", "2.15s", + "4.3s", "8.6s", "17.2s", "34.41s" +}; + +static const struct soc_enum alc_dcy = + SOC_ENUM_SINGLE(WM8737_ALC3, 4, 11, alc_dcy_text); + static const struct snd_kcontrol_new wm8737_snd_controls[] = { SOC_DOUBLE_R_TLV("Mic Boost Volume", WM8737_AUDIO_PATH_L, WM8737_AUDIO_PATH_R, 6, 3, 0, micboost_tlv), @@ -132,6 +166,14 @@ SOC_SINGLE_TLV("3D ADC Volume", WM8737_3D_ENHANCE, 7, 1, 1, adc_tlv), SOC_SINGLE("Noise Gate Switch", WM8737_NOISE_GATE, 0, 1, 0), SOC_SINGLE_TLV("Noise Gate Threshold Volume", WM8737_NOISE_GATE, 2, 7, 0, ng_tlv), + +SOC_ENUM("ALC", alc_fn), +SOC_SINGLE_TLV("ALC Max Gain Volume", WM8737_ALC1, 4, 7, 0, alc_max_tlv), +SOC_SINGLE_TLV("ALC Target Volume", WM8737_ALC1, 0, 15, 0, alc_target_tlv), +SOC_ENUM("ALC Hold Time", alc_hold), +SOC_SINGLE("ALC ZC Switch", WM8737_ALC2, 4, 1, 0), +SOC_ENUM("ALC Attack Time", alc_atk), +SOC_ENUM("ALC Decay Time", alc_dcy), }; static const char *linsel_text[] = { -- cgit v1.2.2 From ccf1fa403e44c4107ef4d73f73cafe81b5148d40 Mon Sep 17 00:00:00 2001 From: Mark Brown Date: Fri, 26 Nov 2010 11:50:03 +0000 Subject: ASoC: Remove redundant hw_write initialisation in WM8737 Signed-off-by: Mark Brown Acked-by: Liam Girdwood --- sound/soc/codecs/wm8737.c | 1 - 1 file changed, 1 deletion(-) (limited to 'sound/soc/codecs') diff --git a/sound/soc/codecs/wm8737.c b/sound/soc/codecs/wm8737.c index 2301338cb2c9..30c67d06a904 100644 --- a/sound/soc/codecs/wm8737.c +++ b/sound/soc/codecs/wm8737.c @@ -560,7 +560,6 @@ static int wm8737_probe(struct snd_soc_codec *codec) struct wm8737_priv *wm8737 = snd_soc_codec_get_drvdata(codec); int ret, i; - codec->hw_write = (hw_write_t)i2c_master_send; ret = snd_soc_codec_set_cache_io(codec, 7, 9, wm8737->control_type); if (ret != 0) { dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret); -- cgit v1.2.2 From 11cef5f07ba0e925af432fc3229fb87585ccccf0 Mon Sep 17 00:00:00 2001 From: Mark Brown Date: Fri, 26 Nov 2010 17:23:44 +0000 Subject: ASoC: Use DC servo startup mode when not doing DCS correction Devices which do not have a DCS correction applied can use the explicit DC servo startup mode for optimal startup performance. This most immediately affects the WM8958. Signed-off-by: Mark Brown Acked-by: Liam Girdwood --- sound/soc/codecs/wm_hubs.c | 20 ++++++++++++++------ 1 file changed, 14 insertions(+), 6 deletions(-) (limited to 'sound/soc/codecs') diff --git a/sound/soc/codecs/wm_hubs.c b/sound/soc/codecs/wm_hubs.c index e7a19d6ada50..b24ba9fa7ef7 100644 --- a/sound/soc/codecs/wm_hubs.c +++ b/sound/soc/codecs/wm_hubs.c @@ -105,12 +105,20 @@ static void calibrate_dc_servo(struct snd_soc_codec *codec) return; } - /* Set for 32 series updates */ - snd_soc_update_bits(codec, WM8993_DC_SERVO_1, - WM8993_DCS_SERIES_NO_01_MASK, - 32 << WM8993_DCS_SERIES_NO_01_SHIFT); - wait_for_dc_servo(codec, - WM8993_DCS_TRIG_SERIES_0 | WM8993_DCS_TRIG_SERIES_1); + /* Devices not using a DCS code correction have startup mode */ + if (hubs->dcs_codes) { + /* Set for 32 series updates */ + snd_soc_update_bits(codec, WM8993_DC_SERVO_1, + WM8993_DCS_SERIES_NO_01_MASK, + 32 << WM8993_DCS_SERIES_NO_01_SHIFT); + wait_for_dc_servo(codec, + WM8993_DCS_TRIG_SERIES_0 | + WM8993_DCS_TRIG_SERIES_1); + } else { + wait_for_dc_servo(codec, + WM8993_DCS_TRIG_STARTUP_0 | + WM8993_DCS_TRIG_STARTUP_1); + } /* Different chips in the family support different readback * methods. -- cgit v1.2.2 From 3a42315740fa80bb4579eb25fedec9d09ff154e7 Mon Sep 17 00:00:00 2001 From: Mark Brown Date: Fri, 26 Nov 2010 15:21:06 +0000 Subject: ASoC: Initial WM8958 audio configuration The WM8958 is a WM8994 derivative. This patch merely ensures that some revision specific configuration for WM8994 is not enabled on WM8994, additional patches will add support for the new features introduced on the WM8958. Signed-off-by: Mark Brown Acked-by: Liam Girdwood --- sound/soc/codecs/wm8994.c | 110 ++++++++++++++++++++++++++++++++-------------- 1 file changed, 76 insertions(+), 34 deletions(-) (limited to 'sound/soc/codecs') diff --git a/sound/soc/codecs/wm8994.c b/sound/soc/codecs/wm8994.c index 283399468b0c..8232d5e73194 100644 --- a/sound/soc/codecs/wm8994.c +++ b/sound/soc/codecs/wm8994.c @@ -1535,6 +1535,7 @@ static int wm8994_set_dai_sysclk(struct snd_soc_dai *dai, static int wm8994_set_bias_level(struct snd_soc_codec *codec, enum snd_soc_bias_level level) { + struct wm8994 *control = codec->control_data; struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); switch (level) { @@ -1551,7 +1552,7 @@ static int wm8994_set_bias_level(struct snd_soc_codec *codec, if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) { /* Tweak DC servo and DSP configuration for * improved performance. */ - if (wm8994->revision < 4) { + if (control->type == WM8994 && wm8994->revision < 4) { /* Tweak DC servo and DSP configuration for * improved performance. */ snd_soc_write(codec, 0x102, 0x3); @@ -2264,8 +2265,12 @@ int wm8994_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack, { struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); struct wm8994_micdet *micdet; + struct wm8994 *control = codec->control_data; int reg; + if (control->type != WM8994) + return -EINVAL; + switch (micbias) { case 1: micdet = &wm8994->micdet[0]; @@ -2334,11 +2339,13 @@ static irqreturn_t wm8994_mic_irq(int irq, void *data) static int wm8994_codec_probe(struct snd_soc_codec *codec) { + struct wm8994 *control; struct wm8994_priv *wm8994; struct snd_soc_dapm_context *dapm = &codec->dapm; int ret, i; codec->control_data = dev_get_drvdata(codec->dev->parent); + control = codec->control_data; wm8994 = kzalloc(sizeof(struct wm8994_priv), GFP_KERNEL); if (wm8994 == NULL) @@ -2369,41 +2376,67 @@ static int wm8994_codec_probe(struct snd_soc_codec *codec) /* Set revision-specific configuration */ wm8994->revision = snd_soc_read(codec, WM8994_CHIP_REVISION); - switch (wm8994->revision) { - case 2: - case 3: - wm8994->hubs.dcs_codes = -5; - wm8994->hubs.hp_startup_mode = 1; + switch (control->type) { + case WM8994: + switch (wm8994->revision) { + case 2: + case 3: + wm8994->hubs.dcs_codes = -5; + wm8994->hubs.hp_startup_mode = 1; + wm8994->hubs.dcs_readback_mode = 1; + break; + default: + wm8994->hubs.dcs_readback_mode = 1; + break; + } + + case WM8958: wm8994->hubs.dcs_readback_mode = 1; break; + default: - wm8994->hubs.dcs_readback_mode = 1; break; } - ret = wm8994_request_irq(codec->control_data, WM8994_IRQ_MIC1_DET, - wm8994_mic_irq, "Mic 1 detect", wm8994); - if (ret != 0) - dev_warn(codec->dev, - "Failed to request Mic1 detect IRQ: %d\n", ret); - - ret = wm8994_request_irq(codec->control_data, WM8994_IRQ_MIC1_SHRT, - wm8994_mic_irq, "Mic 1 short", wm8994); - if (ret != 0) - dev_warn(codec->dev, - "Failed to request Mic1 short IRQ: %d\n", ret); - - ret = wm8994_request_irq(codec->control_data, WM8994_IRQ_MIC2_DET, - wm8994_mic_irq, "Mic 2 detect", wm8994); - if (ret != 0) - dev_warn(codec->dev, - "Failed to request Mic2 detect IRQ: %d\n", ret); - - ret = wm8994_request_irq(codec->control_data, WM8994_IRQ_MIC2_SHRT, - wm8994_mic_irq, "Mic 2 short", wm8994); - if (ret != 0) - dev_warn(codec->dev, - "Failed to request Mic2 short IRQ: %d\n", ret); + switch (control->type) { + case WM8994: + ret = wm8994_request_irq(codec->control_data, + WM8994_IRQ_MIC1_DET, + wm8994_mic_irq, "Mic 1 detect", + wm8994); + if (ret != 0) + dev_warn(codec->dev, + "Failed to request Mic1 detect IRQ: %d\n", + ret); + + ret = wm8994_request_irq(codec->control_data, + WM8994_IRQ_MIC1_SHRT, + wm8994_mic_irq, "Mic 1 short", + wm8994); + if (ret != 0) + dev_warn(codec->dev, + "Failed to request Mic1 short IRQ: %d\n", + ret); + + ret = wm8994_request_irq(codec->control_data, + WM8994_IRQ_MIC2_DET, + wm8994_mic_irq, "Mic 2 detect", + wm8994); + if (ret != 0) + dev_warn(codec->dev, + "Failed to request Mic2 detect IRQ: %d\n", + ret); + + ret = wm8994_request_irq(codec->control_data, + WM8994_IRQ_MIC2_SHRT, + wm8994_mic_irq, "Mic 2 short", + wm8994); + if (ret != 0) + dev_warn(codec->dev, + "Failed to request Mic2 short IRQ: %d\n", + ret); + break; + } /* Remember if AIFnLRCLK is configured as a GPIO. This should be * configured on init - if a system wants to do this dynamically @@ -2496,13 +2529,22 @@ err: static int wm8994_codec_remove(struct snd_soc_codec *codec) { struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); + struct wm8994 *control = codec->control_data; wm8994_set_bias_level(codec, SND_SOC_BIAS_OFF); - wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC2_SHRT, wm8994); - wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC2_DET, wm8994); - wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC1_SHRT, wm8994); - wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC1_DET, wm8994); + switch (control->type) { + case WM8994: + wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC2_SHRT, + wm8994); + wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC2_DET, + wm8994); + wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC1_SHRT, + wm8994); + wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC1_DET, + wm8994); + break; + } kfree(wm8994->retune_mobile_texts); kfree(wm8994->drc_texts); kfree(wm8994); -- cgit v1.2.2 From c4431df050ff124cae7716e301cead1e8f33c575 Mon Sep 17 00:00:00 2001 From: Mark Brown Date: Fri, 26 Nov 2010 15:21:07 +0000 Subject: ASoC: Implement support for enhanced AIF3 on WM8958 Additional audio routing options are available on the WM8958 audio interface 3. Add support for these. Signed-off-by: Mark Brown Acked-by: Liam Girdwood --- sound/soc/codecs/wm8994.c | 166 +++++++++++++++++++++++++++++++++++++++++++--- 1 file changed, 157 insertions(+), 9 deletions(-) (limited to 'sound/soc/codecs') diff --git a/sound/soc/codecs/wm8994.c b/sound/soc/codecs/wm8994.c index 8232d5e73194..fb0609315cd6 100644 --- a/sound/soc/codecs/wm8994.c +++ b/sound/soc/codecs/wm8994.c @@ -647,6 +647,10 @@ SOC_SINGLE_TLV("AIF2 EQ5 Volume", WM8994_AIF2_EQ_GAINS_2, 6, 31, 0, eq_tlv), }; +static const struct snd_kcontrol_new wm8958_snd_controls[] = { +SOC_SINGLE_TLV("AIF3 Boost Volume", WM8958_AIF3_CONTROL_2, 10, 3, 0, aif_tlv), +}; + static int clk_sys_event(struct snd_soc_dapm_widget *w, struct snd_kcontrol *kcontrol, int event) { @@ -953,14 +957,47 @@ static const struct snd_kcontrol_new aif2adc_mux = SOC_DAPM_ENUM("AIF2ADC Mux", aif2adc_enum); static const char *aif3adc_text[] = { - "AIF1ADCDAT", "AIF2ADCDAT", "AIF2DACDAT", + "AIF1ADCDAT", "AIF2ADCDAT", "AIF2DACDAT", "Mono PCM", }; -static const struct soc_enum aif3adc_enum = +static const struct soc_enum wm8994_aif3adc_enum = SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 3, 3, aif3adc_text); -static const struct snd_kcontrol_new aif3adc_mux = - SOC_DAPM_ENUM("AIF3ADC Mux", aif3adc_enum); +static const struct snd_kcontrol_new wm8994_aif3adc_mux = + SOC_DAPM_ENUM("AIF3ADC Mux", wm8994_aif3adc_enum); + +static const struct soc_enum wm8958_aif3adc_enum = + SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 3, 4, aif3adc_text); + +static const struct snd_kcontrol_new wm8958_aif3adc_mux = + SOC_DAPM_ENUM("AIF3ADC Mux", wm8958_aif3adc_enum); + +static const char *mono_pcm_out_text[] = { + "None", "AIF2ADCL", "AIF2ADCR", +}; + +static const struct soc_enum mono_pcm_out_enum = + SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 9, 3, mono_pcm_out_text); + +static const struct snd_kcontrol_new mono_pcm_out_mux = + SOC_DAPM_ENUM("Mono PCM Out Mux", mono_pcm_out_enum); + +static const char *aif2dac_src_text[] = { + "AIF2", "AIF3", +}; + +/* Note that these two control shouldn't be simultaneously switched to AIF3 */ +static const struct soc_enum aif2dacl_src_enum = + SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 7, 2, aif2dac_src_text); + +static const struct snd_kcontrol_new aif2dacl_src_mux = + SOC_DAPM_ENUM("AIF2DACL Mux", aif2dacl_src_enum); + +static const struct soc_enum aif2dacr_src_enum = + SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 8, 2, aif2dac_src_text); + +static const struct snd_kcontrol_new aif2dacr_src_mux = + SOC_DAPM_ENUM("AIF2DACR Mux", aif2dacr_src_enum); static const struct snd_soc_dapm_widget wm8994_dapm_widgets[] = { SND_SOC_DAPM_INPUT("DMIC1DAT"), @@ -1034,7 +1071,6 @@ SND_SOC_DAPM_AIF_OUT("AIF2ADCDAT", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0), SND_SOC_DAPM_MUX("AIF1DAC Mux", SND_SOC_NOPM, 0, 0, &aif1dac_mux), SND_SOC_DAPM_MUX("AIF2DAC Mux", SND_SOC_NOPM, 0, 0, &aif2dac_mux), SND_SOC_DAPM_MUX("AIF2ADC Mux", SND_SOC_NOPM, 0, 0, &aif2adc_mux), -SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &aif3adc_mux), SND_SOC_DAPM_AIF_IN("AIF3DACDAT", "AIF3 Playback", 0, SND_SOC_NOPM, 0, 0), SND_SOC_DAPM_AIF_IN("AIF3ADCDAT", "AIF3 Capture", 0, SND_SOC_NOPM, 0, 0), @@ -1072,8 +1108,18 @@ SND_SOC_DAPM_MIXER("SPKR", WM8994_POWER_MANAGEMENT_3, 9, 0, SND_SOC_DAPM_POST("Debug log", post_ev), }; -static const struct snd_soc_dapm_route intercon[] = { +static const struct snd_soc_dapm_widget wm8994_specific_dapm_widgets[] = { +SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &wm8994_aif3adc_mux), +}; +static const struct snd_soc_dapm_widget wm8958_dapm_widgets[] = { +SND_SOC_DAPM_MUX("Mono PCM Out Mux", SND_SOC_NOPM, 0, 0, &mono_pcm_out_mux), +SND_SOC_DAPM_MUX("AIF2DACL Mux", SND_SOC_NOPM, 0, 0, &aif2dacl_src_mux), +SND_SOC_DAPM_MUX("AIF2DACR Mux", SND_SOC_NOPM, 0, 0, &aif2dacr_src_mux), +SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &wm8958_aif3adc_mux), +}; + +static const struct snd_soc_dapm_route intercon[] = { { "CLK_SYS", NULL, "AIF1CLK", check_clk_sys }, { "CLK_SYS", NULL, "AIF2CLK", check_clk_sys }, @@ -1181,9 +1227,6 @@ static const struct snd_soc_dapm_route intercon[] = { { "AIF1DAC2L", NULL, "AIF1DAC Mux" }, { "AIF1DAC2R", NULL, "AIF1DAC Mux" }, - { "AIF2DACL", NULL, "AIF2DAC Mux" }, - { "AIF2DACR", NULL, "AIF2DAC Mux" }, - { "AIF1DAC Mux", "AIF1DACDAT", "AIF1DACDAT" }, { "AIF1DAC Mux", "AIF3DACDAT", "AIF3DACDAT" }, { "AIF2DAC Mux", "AIF2DACDAT", "AIF2DACDAT" }, @@ -1256,6 +1299,26 @@ static const struct snd_soc_dapm_route intercon[] = { { "Right Headphone Mux", "DAC", "DAC1R" }, }; +static const struct snd_soc_dapm_route wm8994_intercon[] = { + { "AIF2DACL", NULL, "AIF2DAC Mux" }, + { "AIF2DACR", NULL, "AIF2DAC Mux" }, +}; + +static const struct snd_soc_dapm_route wm8958_intercon[] = { + { "AIF2DACL", NULL, "AIF2DACL Mux" }, + { "AIF2DACR", NULL, "AIF2DACR Mux" }, + + { "AIF2DACL Mux", "AIF2", "AIF2DAC Mux" }, + { "AIF2DACL Mux", "AIF3", "AIF3DACDAT" }, + { "AIF2DACR Mux", "AIF2", "AIF2DAC Mux" }, + { "AIF2DACR Mux", "AIF3", "AIF3DACDAT" }, + + { "Mono PCM Out Mux", "AIF2ADCL", "AIF2ADCL" }, + { "Mono PCM Out Mux", "AIF2ADCR", "AIF2ADCR" }, + + { "AIF3ADC Mux", "Mono PCM", "Mono PCM Out Mux" }, +}; + /* The size in bits of the FLL divide multiplied by 10 * to allow rounding later */ #define FIXED_FLL_SIZE ((1 << 16) * 10) @@ -1635,6 +1698,7 @@ static int wm8994_set_bias_level(struct snd_soc_codec *codec, static int wm8994_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt) { struct snd_soc_codec *codec = dai->codec; + struct wm8994 *control = codec->control_data; int ms_reg; int aif1_reg; int ms = 0; @@ -1719,6 +1783,13 @@ static int wm8994_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt) return -EINVAL; } + /* The AIF2 format configuration needs to be mirrored to AIF3 + * on WM8958 if it's in use so just do it all the time. */ + if (control->type == WM8958 && dai->id == 2) + snd_soc_update_bits(codec, WM8958_AIF3_CONTROL_1, + WM8994_AIF1_LRCLK_INV | + WM8958_AIF3_FMT_MASK, aif1); + snd_soc_update_bits(codec, aif1_reg, WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV | WM8994_AIF1_FMT_MASK, @@ -1759,6 +1830,7 @@ static int wm8994_hw_params(struct snd_pcm_substream *substream, struct snd_soc_dai *dai) { struct snd_soc_codec *codec = dai->codec; + struct wm8994 *control = codec->control_data; struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); int aif1_reg; int bclk_reg; @@ -1797,6 +1869,14 @@ static int wm8994_hw_params(struct snd_pcm_substream *substream, dev_dbg(codec->dev, "AIF2 using split LRCLK\n"); } break; + case 3: + switch (control->type) { + case WM8958: + aif1_reg = WM8958_AIF3_CONTROL_1; + break; + default: + return 0; + } default: return -EINVAL; } @@ -1900,6 +1980,47 @@ static int wm8994_hw_params(struct snd_pcm_substream *substream, return 0; } +static int wm8994_aif3_hw_params(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params, + struct snd_soc_dai *dai) +{ + struct snd_soc_codec *codec = dai->codec; + struct wm8994 *control = codec->control_data; + int aif1_reg; + int aif1 = 0; + + switch (dai->id) { + case 3: + switch (control->type) { + case WM8958: + aif1_reg = WM8958_AIF3_CONTROL_1; + break; + default: + return 0; + } + default: + return 0; + } + + switch (params_format(params)) { + case SNDRV_PCM_FORMAT_S16_LE: + break; + case SNDRV_PCM_FORMAT_S20_3LE: + aif1 |= 0x20; + break; + case SNDRV_PCM_FORMAT_S24_LE: + aif1 |= 0x40; + break; + case SNDRV_PCM_FORMAT_S32_LE: + aif1 |= 0x60; + break; + default: + return -EINVAL; + } + + return snd_soc_update_bits(codec, aif1_reg, WM8994_AIF1_WL_MASK, aif1); +} + static int wm8994_aif_mute(struct snd_soc_dai *codec_dai, int mute) { struct snd_soc_codec *codec = codec_dai->codec; @@ -1981,6 +2102,7 @@ static struct snd_soc_dai_ops wm8994_aif2_dai_ops = { }; static struct snd_soc_dai_ops wm8994_aif3_dai_ops = { + .hw_params = wm8994_aif3_hw_params, .set_tristate = wm8994_set_tristate, }; @@ -2511,9 +2633,35 @@ static int wm8994_codec_probe(struct snd_soc_codec *codec) ARRAY_SIZE(wm8994_snd_controls)); snd_soc_dapm_new_controls(dapm, wm8994_dapm_widgets, ARRAY_SIZE(wm8994_dapm_widgets)); + + switch (control->type) { + case WM8994: + snd_soc_dapm_new_controls(dapm, wm8994_specific_dapm_widgets, + ARRAY_SIZE(wm8994_specific_dapm_widgets)); + break; + case WM8958: + snd_soc_add_controls(codec, wm8958_snd_controls, + ARRAY_SIZE(wm8958_snd_controls)); + snd_soc_dapm_new_controls(dapm, wm8958_dapm_widgets, + ARRAY_SIZE(wm8958_dapm_widgets)); + break; + } + + wm_hubs_add_analogue_routes(codec, 0, 0); snd_soc_dapm_add_routes(dapm, intercon, ARRAY_SIZE(intercon)); + switch (control->type) { + case WM8994: + snd_soc_dapm_add_routes(dapm, wm8994_intercon, + ARRAY_SIZE(wm8994_intercon)); + break; + case WM8958: + snd_soc_dapm_add_routes(dapm, wm8958_intercon, + ARRAY_SIZE(wm8958_intercon)); + break; + } + return 0; err_irq: -- cgit v1.2.2 From d6addcc9d88aeac4a0cc63a06d36baef04f5dc3b Mon Sep 17 00:00:00 2001 From: Mark Brown Date: Fri, 26 Nov 2010 15:21:08 +0000 Subject: ASoC: Add WM8958 Multi-band compressor support The WM8958 features a multi-band compressor which can be enabled on any of the AIF inputs. The MBC allows different gains to be applied to differnt audio bands, providing an improvement in perceived loudness of the signal by avoiding overdriving the output transducers. This patch enables support for the MBC. Signed-off-by: Mark Brown Acked-by: Liam Girdwood --- sound/soc/codecs/wm8994.c | 198 +++++++++++++++++++++++++++++++++++++++++++--- 1 file changed, 186 insertions(+), 12 deletions(-) (limited to 'sound/soc/codecs') diff --git a/sound/soc/codecs/wm8994.c b/sound/soc/codecs/wm8994.c index fb0609315cd6..b30b2dd3f1f4 100644 --- a/sound/soc/codecs/wm8994.c +++ b/sound/soc/codecs/wm8994.c @@ -80,6 +80,8 @@ struct wm8994_priv { int dac_rates[2]; int lrclk_shared[2]; + int mbc_ena[3]; + /* Platform dependant DRC configuration */ const char **drc_texts; int drc_cfg[WM8994_NUM_DRC]; @@ -137,6 +139,7 @@ static int wm8994_volatile(unsigned int reg) case WM8994_RATE_STATUS: case WM8994_LDO_1: case WM8994_LDO_2: + case WM8958_DSP2_EXECCONTROL: return 1; default: return 0; @@ -520,6 +523,168 @@ static const struct soc_enum aif2dacl_src = static const struct soc_enum aif2dacr_src = SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_2, 14, 2, aif_chan_src_text); +static void wm8958_mbc_apply(struct snd_soc_codec *codec, int mbc, int start) +{ + struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); + int pwr_reg = snd_soc_read(codec, WM8994_POWER_MANAGEMENT_5); + int ena, reg, aif; + + switch (mbc) { + case 0: + pwr_reg &= (WM8994_AIF1DAC1L_ENA | WM8994_AIF1DAC1R_ENA); + aif = 0; + break; + case 1: + pwr_reg &= (WM8994_AIF1DAC2L_ENA | WM8994_AIF1DAC2R_ENA); + aif = 0; + break; + case 2: + pwr_reg &= (WM8994_AIF2DACL_ENA | WM8994_AIF2DACR_ENA); + aif = 1; + break; + default: + BUG(); + return; + } + + /* We can only enable the MBC if the AIF is enabled and we + * want it to be enabled. */ + ena = pwr_reg && wm8994->mbc_ena[mbc]; + + reg = snd_soc_read(codec, WM8958_DSP2_PROGRAM); + + dev_dbg(codec->dev, "MBC %d startup: %d, power: %x, DSP: %x\n", + mbc, start, pwr_reg, reg); + + if (start && ena) { + /* If the DSP is already running then noop */ + if (reg & WM8958_DSP2_ENA) + return; + + /* Switch the clock over to the appropriate AIF */ + snd_soc_update_bits(codec, WM8994_CLOCKING_1, + WM8958_DSP2CLK_SRC | WM8958_DSP2CLK_ENA, + aif << WM8958_DSP2CLK_SRC_SHIFT | + WM8958_DSP2CLK_ENA); + + snd_soc_update_bits(codec, WM8958_DSP2_PROGRAM, + WM8958_DSP2_ENA, WM8958_DSP2_ENA); + + /* TODO: Apply any user specified MBC settings */ + + /* Run the DSP */ + snd_soc_write(codec, WM8958_DSP2_EXECCONTROL, + WM8958_DSP2_RUNR); + + /* And we're off! */ + snd_soc_update_bits(codec, WM8958_DSP2_CONFIG, + WM8958_MBC_ENA | WM8958_MBC_SEL_MASK, + mbc << WM8958_MBC_SEL_SHIFT | + WM8958_MBC_ENA); + } else { + /* If the DSP is already stopped then noop */ + if (!(reg & WM8958_DSP2_ENA)) + return; + + snd_soc_update_bits(codec, WM8958_DSP2_CONFIG, + WM8958_MBC_ENA, 0); + snd_soc_update_bits(codec, WM8958_DSP2_PROGRAM, + WM8958_DSP2_ENA, 0); + snd_soc_update_bits(codec, WM8994_CLOCKING_1, + WM8958_DSP2CLK_ENA, 0); + } +} + +static int wm8958_aif_ev(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, int event) +{ + struct snd_soc_codec *codec = w->codec; + int mbc; + + switch (w->shift) { + case 13: + case 12: + mbc = 2; + break; + case 11: + case 10: + mbc = 1; + break; + case 9: + case 8: + mbc = 0; + break; + default: + BUG(); + return -EINVAL; + } + + switch (event) { + case SND_SOC_DAPM_POST_PMU: + wm8958_mbc_apply(codec, mbc, 1); + break; + case SND_SOC_DAPM_POST_PMD: + wm8958_mbc_apply(codec, mbc, 0); + break; + } + + return 0; +} + +static int wm8958_mbc_info(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_info *uinfo) +{ + uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN; + uinfo->count = 1; + uinfo->value.integer.min = 0; + uinfo->value.integer.max = 1; + return 0; +} + +static int wm8958_mbc_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + int mbc = kcontrol->private_value; + struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); + struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); + + ucontrol->value.integer.value[0] = wm8994->mbc_ena[mbc]; + + return 0; +} + +static int wm8958_mbc_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + int mbc = kcontrol->private_value; + int i; + struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); + struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); + + if (ucontrol->value.integer.value[0] > 1) + return -EINVAL; + + for (i = 0; i < ARRAY_SIZE(wm8994->mbc_ena); i++) { + if (mbc != i && wm8994->mbc_ena[i]) { + dev_dbg(codec->dev, "MBC %d active already\n", mbc); + return -EBUSY; + } + } + + wm8994->mbc_ena[mbc] = ucontrol->value.integer.value[0]; + + wm8958_mbc_apply(codec, mbc, wm8994->mbc_ena[mbc]); + + return 0; +} + +#define WM8958_MBC_SWITCH(xname, xval) {\ + .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \ + .access = SNDRV_CTL_ELEM_ACCESS_READWRITE,\ + .info = wm8958_mbc_info, \ + .get = wm8958_mbc_get, .put = wm8958_mbc_put, \ + .private_value = xval } + static const struct snd_kcontrol_new wm8994_snd_controls[] = { SOC_DOUBLE_R_TLV("AIF1ADC1 Volume", WM8994_AIF1_ADC1_LEFT_VOLUME, WM8994_AIF1_ADC1_RIGHT_VOLUME, @@ -649,6 +814,9 @@ SOC_SINGLE_TLV("AIF2 EQ5 Volume", WM8994_AIF2_EQ_GAINS_2, 6, 31, 0, static const struct snd_kcontrol_new wm8958_snd_controls[] = { SOC_SINGLE_TLV("AIF3 Boost Volume", WM8958_AIF3_CONTROL_2, 10, 3, 0, aif_tlv), +WM8958_MBC_SWITCH("AIF1DAC1 MBC Switch", 0), +WM8958_MBC_SWITCH("AIF1DAC2 MBC Switch", 1), +WM8958_MBC_SWITCH("AIF2DAC MBC Switch", 2), }; static int clk_sys_event(struct snd_soc_dapm_widget *w, @@ -1018,19 +1186,23 @@ SND_SOC_DAPM_AIF_OUT("AIF1ADC1L", "AIF1 Capture", 0, WM8994_POWER_MANAGEMENT_4, 9, 0), SND_SOC_DAPM_AIF_OUT("AIF1ADC1R", "AIF1 Capture", 0, WM8994_POWER_MANAGEMENT_4, 8, 0), -SND_SOC_DAPM_AIF_IN("AIF1DAC1L", NULL, 0, - WM8994_POWER_MANAGEMENT_5, 9, 0), -SND_SOC_DAPM_AIF_IN("AIF1DAC1R", NULL, 0, - WM8994_POWER_MANAGEMENT_5, 8, 0), +SND_SOC_DAPM_AIF_IN_E("AIF1DAC1L", NULL, 0, + WM8994_POWER_MANAGEMENT_5, 9, 0, wm8958_aif_ev, + SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), +SND_SOC_DAPM_AIF_IN_E("AIF1DAC1R", NULL, 0, + WM8994_POWER_MANAGEMENT_5, 8, 0, wm8958_aif_ev, + SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), SND_SOC_DAPM_AIF_OUT("AIF1ADC2L", "AIF1 Capture", 0, WM8994_POWER_MANAGEMENT_4, 11, 0), SND_SOC_DAPM_AIF_OUT("AIF1ADC2R", "AIF1 Capture", 0, WM8994_POWER_MANAGEMENT_4, 10, 0), -SND_SOC_DAPM_AIF_IN("AIF1DAC2L", NULL, 0, - WM8994_POWER_MANAGEMENT_5, 11, 0), -SND_SOC_DAPM_AIF_IN("AIF1DAC2R", NULL, 0, - WM8994_POWER_MANAGEMENT_5, 10, 0), +SND_SOC_DAPM_AIF_IN_E("AIF1DAC2L", NULL, 0, + WM8994_POWER_MANAGEMENT_5, 11, 0, wm8958_aif_ev, + SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), +SND_SOC_DAPM_AIF_IN_E("AIF1DAC2R", NULL, 0, + WM8994_POWER_MANAGEMENT_5, 10, 0, wm8958_aif_ev, + SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), SND_SOC_DAPM_MIXER("AIF1ADC1L Mixer", SND_SOC_NOPM, 0, 0, aif1adc1l_mix, ARRAY_SIZE(aif1adc1l_mix)), @@ -1059,10 +1231,12 @@ SND_SOC_DAPM_AIF_OUT("AIF2ADCL", NULL, 0, WM8994_POWER_MANAGEMENT_4, 13, 0), SND_SOC_DAPM_AIF_OUT("AIF2ADCR", NULL, 0, WM8994_POWER_MANAGEMENT_4, 12, 0), -SND_SOC_DAPM_AIF_IN("AIF2DACL", NULL, 0, - WM8994_POWER_MANAGEMENT_5, 13, 0), -SND_SOC_DAPM_AIF_IN("AIF2DACR", NULL, 0, - WM8994_POWER_MANAGEMENT_5, 12, 0), +SND_SOC_DAPM_AIF_IN_E("AIF2DACL", NULL, 0, + WM8994_POWER_MANAGEMENT_5, 13, 0, wm8958_aif_ev, + SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), +SND_SOC_DAPM_AIF_IN_E("AIF2DACR", NULL, 0, + WM8994_POWER_MANAGEMENT_5, 12, 0, wm8958_aif_ev, + SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), SND_SOC_DAPM_AIF_IN("AIF1DACDAT", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0), SND_SOC_DAPM_AIF_IN("AIF2DACDAT", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0), -- cgit v1.2.2 From 821edd2fb5b289b84d715fb744106019fa2e1920 Mon Sep 17 00:00:00 2001 From: Mark Brown Date: Fri, 26 Nov 2010 15:21:09 +0000 Subject: ASoC: Add WM8958 microphone detection support The WM8958 contains an advanced accessory detection feature which allows detection of up to seven different impedence levels on the microphone bias output, including detection of video outputs. Since some of the more involved accessory interfaces may involve noticable interactions with external components a simple detection scheme is provided by default with the option to provide custom handling of accessory detect. Signed-off-by: Mark Brown Acked-by: Liam Girdwood --- sound/soc/codecs/wm8994.c | 150 ++++++++++++++++++++++++++++++++++++++++++++++ sound/soc/codecs/wm8994.h | 4 ++ 2 files changed, 154 insertions(+) (limited to 'sound/soc/codecs') diff --git a/sound/soc/codecs/wm8994.c b/sound/soc/codecs/wm8994.c index b30b2dd3f1f4..948677b581b1 100644 --- a/sound/soc/codecs/wm8994.c +++ b/sound/soc/codecs/wm8994.c @@ -21,6 +21,7 @@ #include #include #include +#include #include #include #include @@ -95,6 +96,11 @@ struct wm8994_priv { struct wm8994_micdet micdet[2]; + wm8958_micdet_cb jack_cb; + void *jack_cb_data; + bool jack_is_mic; + bool jack_is_video; + int revision; struct wm8994_pdata *pdata; }; @@ -140,6 +146,7 @@ static int wm8994_volatile(unsigned int reg) case WM8994_LDO_1: case WM8994_LDO_2: case WM8958_DSP2_EXECCONTROL: + case WM8958_MIC_DETECT_3: return 1; default: return 0; @@ -2633,6 +2640,133 @@ static irqreturn_t wm8994_mic_irq(int irq, void *data) return IRQ_HANDLED; } +/* Default microphone detection handler for WM8958 - the user can + * override this if they wish. + */ +static void wm8958_default_micdet(u16 status, void *data) +{ + struct snd_soc_codec *codec = data; + struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); + int report = 0; + + /* If nothing present then clear our statuses */ + if (!(status & WM8958_MICD_STS)) { + wm8994->jack_is_video = false; + wm8994->jack_is_mic = false; + goto done; + } + + /* Assume anything over 475 ohms is a microphone and remember + * that we've seen one (since buttons override it) */ + if (status & 0x600) + wm8994->jack_is_mic = true; + if (wm8994->jack_is_mic) + report |= SND_JACK_MICROPHONE; + + /* Video has an impedence of approximately 75 ohms; assume + * this isn't used as a button and remember it since buttons + * override it. */ + if (status & 0x40) + wm8994->jack_is_video = true; + if (wm8994->jack_is_video) + report |= SND_JACK_VIDEOOUT; + + /* Everything else is buttons; just assign slots */ + if (status & 0x4) + report |= SND_JACK_BTN_0; + if (status & 0x8) + report |= SND_JACK_BTN_1; + if (status & 0x10) + report |= SND_JACK_BTN_2; + if (status & 0x20) + report |= SND_JACK_BTN_3; + if (status & 0x80) + report |= SND_JACK_BTN_4; + if (status & 0x100) + report |= SND_JACK_BTN_5; + +done: + snd_soc_jack_report(wm8994->micdet[0].jack, + SND_JACK_BTN_0 | SND_JACK_BTN_1 | SND_JACK_BTN_2 | + SND_JACK_BTN_3 | SND_JACK_BTN_4 | SND_JACK_BTN_5 | + SND_JACK_MICROPHONE | SND_JACK_VIDEOOUT, + report); +} + +/** + * wm8958_mic_detect - Enable microphone detection via the WM8958 IRQ + * + * @codec: WM8958 codec + * @jack: jack to report detection events on + * + * Enable microphone detection functionality for the WM8958. By + * default simple detection which supports the detection of up to 6 + * buttons plus video and microphone functionality is supported. + * + * The WM8958 has an advanced jack detection facility which is able to + * support complex accessory detection, especially when used in + * conjunction with external circuitry. In order to provide maximum + * flexiblity a callback is provided which allows a completely custom + * detection algorithm. + */ +int wm8958_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack, + wm8958_micdet_cb cb, void *cb_data) +{ + struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); + struct wm8994 *control = codec->control_data; + + if (control->type != WM8958) + return -EINVAL; + + if (jack) { + if (!cb) { + dev_dbg(codec->dev, "Using default micdet callback\n"); + cb = wm8958_default_micdet; + cb_data = codec; + } + + wm8994->micdet[0].jack = jack; + wm8994->jack_cb = cb; + wm8994->jack_cb_data = cb_data; + + snd_soc_update_bits(codec, WM8958_MIC_DETECT_1, + WM8958_MICD_ENA, WM8958_MICD_ENA); + } else { + snd_soc_update_bits(codec, WM8958_MIC_DETECT_1, + WM8958_MICD_ENA, 0); + } + + return 0; +} +EXPORT_SYMBOL_GPL(wm8958_mic_detect); + +static irqreturn_t wm8958_mic_irq(int irq, void *data) +{ + struct wm8994_priv *wm8994 = data; + struct snd_soc_codec *codec = wm8994->codec; + int reg; + + reg = snd_soc_read(codec, WM8958_MIC_DETECT_3); + if (reg < 0) { + dev_err(codec->dev, "Failed to read mic detect status: %d\n", + reg); + return IRQ_NONE; + } + + if (!(reg & WM8958_MICD_VALID)) { + dev_dbg(codec->dev, "Mic detect data not valid\n"); + goto out; + } + + if (wm8994->jack_cb) + wm8994->jack_cb(reg, wm8994->jack_cb_data); + else + dev_warn(codec->dev, "Accessory detection with no callback\n"); + +out: + return IRQ_HANDLED; +} + static int wm8994_codec_probe(struct snd_soc_codec *codec) { struct wm8994 *control; @@ -2732,6 +2866,17 @@ static int wm8994_codec_probe(struct snd_soc_codec *codec) "Failed to request Mic2 short IRQ: %d\n", ret); break; + + case WM8958: + ret = wm8994_request_irq(codec->control_data, + WM8994_IRQ_MIC1_DET, + wm8958_mic_irq, "Mic detect", + wm8994); + if (ret != 0) + dev_warn(codec->dev, + "Failed to request Mic detect IRQ: %d\n", + ret); + break; } /* Remember if AIFnLRCLK is configured as a GPIO. This should be @@ -2866,6 +3011,11 @@ static int wm8994_codec_remove(struct snd_soc_codec *codec) wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC1_DET, wm8994); break; + + case WM8958: + wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC1_DET, + wm8994); + break; } kfree(wm8994->retune_mobile_texts); kfree(wm8994->drc_texts); diff --git a/sound/soc/codecs/wm8994.h b/sound/soc/codecs/wm8994.h index b8b3166e1f03..455cae6b4356 100644 --- a/sound/soc/codecs/wm8994.h +++ b/sound/soc/codecs/wm8994.h @@ -28,8 +28,12 @@ #define WM8994_FLL_SRC_LRCLK 3 #define WM8994_FLL_SRC_BCLK 4 +typedef void (*wm8958_micdet_cb)(u16 status, void *data); + int wm8994_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack, int micbias, int det, int shrt); +int wm8958_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack, + wm8958_micdet_cb cb, void *cb_data); #define WM8994_CACHE_SIZE 1570 -- cgit v1.2.2 From ca9aef50727dec76ab12513ba833a1cf5e9d7e83 Mon Sep 17 00:00:00 2001 From: Mark Brown Date: Fri, 26 Nov 2010 17:23:41 +0000 Subject: ASoC: Convert WM8994 to use soc-cache.c cache functions In the process we convert the driver to read registers one at a time when initialising the cache. This has the effect of working around limitations in the sizes of I2C transactions which can be done by some CPUs. Due to the sparseness of the register map the overhead from this should be minimual unless I2C transactions are very expensive to start. Signed-off-by: Mark Brown Acked-by: Liam Girdwood --- sound/soc/codecs/wm8994-tables.c | 1572 ++++++++++++++++++++++++++++++++++++++ sound/soc/codecs/wm8994.c | 95 ++- sound/soc/codecs/wm8994.h | 1 + 3 files changed, 1620 insertions(+), 48 deletions(-) (limited to 'sound/soc/codecs') diff --git a/sound/soc/codecs/wm8994-tables.c b/sound/soc/codecs/wm8994-tables.c index 7b935387aeef..68e9b024dd48 100644 --- a/sound/soc/codecs/wm8994-tables.c +++ b/sound/soc/codecs/wm8994-tables.c @@ -1573,3 +1573,1575 @@ const struct wm8994_access_mask wm8994_access_masks[WM8994_CACHE_SIZE] = { { 0x03C3, 0x03C3 }, /* R1569 - Sidetone */ }; +const __devinitdata u16 wm8994_reg_defaults[WM8994_CACHE_SIZE] = { + 0x8994, /* R0 - Software Reset */ + 0x0000, /* R1 - Power Management (1) */ + 0x6000, /* R2 - Power Management (2) */ + 0x0000, /* R3 - Power Management (3) */ + 0x0000, /* R4 - Power Management (4) */ + 0x0000, /* R5 - Power Management (5) */ + 0x0000, /* R6 - Power Management (6) */ + 0x0000, /* R7 */ + 0x0000, /* R8 */ + 0x0000, /* R9 */ + 0x0000, /* R10 */ + 0x0000, /* R11 */ + 0x0000, /* R12 */ + 0x0000, /* R13 */ + 0x0000, /* R14 */ + 0x0000, /* R15 */ + 0x0000, /* R16 */ + 0x0000, /* R17 */ + 0x0000, /* R18 */ + 0x0000, /* R19 */ + 0x0000, /* R20 */ + 0x0000, /* R21 - Input Mixer (1) */ + 0x0000, /* R22 */ + 0x0000, /* R23 */ + 0x008B, /* R24 - Left Line Input 1&2 Volume */ + 0x008B, /* R25 - Left Line Input 3&4 Volume */ + 0x008B, /* R26 - Right Line Input 1&2 Volume */ + 0x008B, /* R27 - Right Line Input 3&4 Volume */ + 0x006D, /* R28 - Left Output Volume */ + 0x006D, /* R29 - Right Output Volume */ + 0x0066, /* R30 - Line Outputs Volume */ + 0x0020, /* R31 - HPOUT2 Volume */ + 0x0079, /* R32 - Left OPGA Volume */ + 0x0079, /* R33 - Right OPGA Volume */ + 0x0003, /* R34 - SPKMIXL Attenuation */ + 0x0003, /* R35 - SPKMIXR Attenuation */ + 0x0011, /* R36 - SPKOUT Mixers */ + 0x0140, /* R37 - ClassD */ + 0x0079, /* R38 - Speaker Volume Left */ + 0x0079, /* R39 - Speaker Volume Right */ + 0x0000, /* R40 - Input Mixer (2) */ + 0x0000, /* R41 - Input Mixer (3) */ + 0x0000, /* R42 - Input Mixer (4) */ + 0x0000, /* R43 - Input Mixer (5) */ + 0x0000, /* R44 - Input Mixer (6) */ + 0x0000, /* R45 - Output Mixer (1) */ + 0x0000, /* R46 - Output Mixer (2) */ + 0x0000, /* R47 - Output Mixer (3) */ + 0x0000, /* R48 - Output Mixer (4) */ + 0x0000, /* R49 - Output Mixer (5) */ + 0x0000, /* R50 - Output Mixer (6) */ + 0x0000, /* R51 - HPOUT2 Mixer */ + 0x0000, /* R52 - Line Mixer (1) */ + 0x0000, /* R53 - Line Mixer (2) */ + 0x0000, /* R54 - Speaker Mixer */ + 0x0000, /* R55 - Additional Control */ + 0x0000, /* R56 - AntiPOP (1) */ + 0x0000, /* R57 - AntiPOP (2) */ + 0x0000, /* R58 - MICBIAS */ + 0x000D, /* R59 - LDO 1 */ + 0x0003, /* R60 - LDO 2 */ + 0x0000, /* R61 */ + 0x0000, /* R62 */ + 0x0000, /* R63 */ + 0x0000, /* R64 */ + 0x0000, /* R65 */ + 0x0000, /* R66 */ + 0x0000, /* R67 */ + 0x0000, /* R68 */ + 0x0000, /* R69 */ + 0x0000, /* R70 */ + 0x0000, /* R71 */ + 0x0000, /* R72 */ + 0x0000, /* R73 */ + 0x0000, /* R74 */ + 0x0000, /* R75 */ + 0x1F25, /* R76 - Charge Pump (1) */ + 0x0000, /* R77 */ + 0x0000, /* R78 */ + 0x0000, /* R79 */ + 0x0000, /* R80 */ + 0x0004, /* R81 - Class W (1) */ + 0x0000, /* R82 */ + 0x0000, /* R83 */ + 0x0000, /* R84 - DC Servo (1) */ + 0x054A, /* R85 - DC Servo (2) */ + 0x0000, /* R86 */ + 0x0000, /* R87 - DC Servo (4) */ + 0x0000, /* R88 - DC Servo Readback */ + 0x0000, /* R89 */ + 0x0000, /* R90 */ + 0x0000, /* R91 */ + 0x0000, /* R92 */ + 0x0000, /* R93 */ + 0x0000, /* R94 */ + 0x0000, /* R95 */ + 0x0000, /* R96 - Analogue HP (1) */ + 0x0000, /* R97 */ + 0x0000, /* R98 */ + 0x0000, /* R99 */ + 0x0000, /* R100 */ + 0x0000, /* R101 */ + 0x0000, /* R102 */ + 0x0000, /* R103 */ + 0x0000, /* R104 */ + 0x0000, /* R105 */ + 0x0000, /* R106 */ + 0x0000, /* R107 */ + 0x0000, /* R108 */ + 0x0000, /* R109 */ + 0x0000, /* R110 */ + 0x0000, /* R111 */ + 0x0000, /* R112 */ + 0x0000, /* R113 */ + 0x0000, /* R114 */ + 0x0000, /* R115 */ + 0x0000, /* R116 */ + 0x0000, /* R117 */ + 0x0000, /* R118 */ + 0x0000, /* R119 */ + 0x0000, /* R120 */ + 0x0000, /* R121 */ + 0x0000, /* R122 */ + 0x0000, /* R123 */ + 0x0000, /* R124 */ + 0x0000, /* R125 */ + 0x0000, /* R126 */ + 0x0000, /* R127 */ + 0x0000, /* R128 */ + 0x0000, /* R129 */ + 0x0000, /* R130 */ + 0x0000, /* R131 */ + 0x0000, /* R132 */ + 0x0000, /* R133 */ + 0x0000, /* R134 */ + 0x0000, /* R135 */ + 0x0000, /* R136 */ + 0x0000, /* R137 */ + 0x0000, /* R138 */ + 0x0000, /* R139 */ + 0x0000, /* R140 */ + 0x0000, /* R141 */ + 0x0000, /* R142 */ + 0x0000, /* R143 */ + 0x0000, /* R144 */ + 0x0000, /* R145 */ + 0x0000, /* R146 */ + 0x0000, /* R147 */ + 0x0000, /* R148 */ + 0x0000, /* R149 */ + 0x0000, /* R150 */ + 0x0000, /* R151 */ + 0x0000, /* R152 */ + 0x0000, /* R153 */ + 0x0000, /* R154 */ + 0x0000, /* R155 */ + 0x0000, /* R156 */ + 0x0000, /* R157 */ + 0x0000, /* R158 */ + 0x0000, /* R159 */ + 0x0000, /* R160 */ + 0x0000, /* R161 */ + 0x0000, /* R162 */ + 0x0000, /* R163 */ + 0x0000, /* R164 */ + 0x0000, /* R165 */ + 0x0000, /* R166 */ + 0x0000, /* R167 */ + 0x0000, /* R168 */ + 0x0000, /* R169 */ + 0x0000, /* R170 */ + 0x0000, /* R171 */ + 0x0000, /* R172 */ + 0x0000, /* R173 */ + 0x0000, /* R174 */ + 0x0000, /* R175 */ + 0x0000, /* R176 */ + 0x0000, /* R177 */ + 0x0000, /* R178 */ + 0x0000, /* R179 */ + 0x0000, /* R180 */ + 0x0000, /* R181 */ + 0x0000, /* R182 */ + 0x0000, /* R183 */ + 0x0000, /* R184 */ + 0x0000, /* R185 */ + 0x0000, /* R186 */ + 0x0000, /* R187 */ + 0x0000, /* R188 */ + 0x0000, /* R189 */ + 0x0000, /* R190 */ + 0x0000, /* R191 */ + 0x0000, /* R192 */ + 0x0000, /* R193 */ + 0x0000, /* R194 */ + 0x0000, /* R195 */ + 0x0000, /* R196 */ + 0x0000, /* R197 */ + 0x0000, /* R198 */ + 0x0000, /* R199 */ + 0x0000, /* R200 */ + 0x0000, /* R201 */ + 0x0000, /* R202 */ + 0x0000, /* R203 */ + 0x0000, /* R204 */ + 0x0000, /* R205 */ + 0x0000, /* R206 */ + 0x0000, /* R207 */ + 0x0000, /* R208 */ + 0x0000, /* R209 */ + 0x0000, /* R210 */ + 0x0000, /* R211 */ + 0x0000, /* R212 */ + 0x0000, /* R213 */ + 0x0000, /* R214 */ + 0x0000, /* R215 */ + 0x0000, /* R216 */ + 0x0000, /* R217 */ + 0x0000, /* R218 */ + 0x0000, /* R219 */ + 0x0000, /* R220 */ + 0x0000, /* R221 */ + 0x0000, /* R222 */ + 0x0000, /* R223 */ + 0x0000, /* R224 */ + 0x0000, /* R225 */ + 0x0000, /* R226 */ + 0x0000, /* R227 */ + 0x0000, /* R228 */ + 0x0000, /* R229 */ + 0x0000, /* R230 */ + 0x0000, /* R231 */ + 0x0000, /* R232 */ + 0x0000, /* R233 */ + 0x0000, /* R234 */ + 0x0000, /* R235 */ + 0x0000, /* R236 */ + 0x0000, /* R237 */ + 0x0000, /* R238 */ + 0x0000, /* R239 */ + 0x0000, /* R240 */ + 0x0000, /* R241 */ + 0x0000, /* R242 */ + 0x0000, /* R243 */ + 0x0000, /* R244 */ + 0x0000, /* R245 */ + 0x0000, /* R246 */ + 0x0000, /* R247 */ + 0x0000, /* R248 */ + 0x0000, /* R249 */ + 0x0000, /* R250 */ + 0x0000, /* R251 */ + 0x0000, /* R252 */ + 0x0000, /* R253 */ + 0x0000, /* R254 */ + 0x0000, /* R255 */ + 0x0003, /* R256 - Chip Revision */ + 0x8004, /* R257 - Control Interface */ + 0x0000, /* R258 */ + 0x0000, /* R259 */ + 0x0000, /* R260 */ + 0x0000, /* R261 */ + 0x0000, /* R262 */ + 0x0000, /* R263 */ + 0x0000, /* R264 */ + 0x0000, /* R265 */ + 0x0000, /* R266 */ + 0x0000, /* R267 */ + 0x0000, /* R268 */ + 0x0000, /* R269 */ + 0x0000, /* R270 */ + 0x0000, /* R271 */ + 0x0000, /* R272 - Write Sequencer Ctrl (1) */ + 0x0000, /* R273 - Write Sequencer Ctrl (2) */ + 0x0000, /* R274 */ + 0x0000, /* R275 */ + 0x0000, /* R276 */ + 0x0000, /* R277 */ + 0x0000, /* R278 */ + 0x0000, /* R279 */ + 0x0000, /* R280 */ + 0x0000, /* R281 */ + 0x0000, /* R282 */ + 0x0000, /* R283 */ + 0x0000, /* R284 */ + 0x0000, /* R285 */ + 0x0000, /* R286 */ + 0x0000, /* R287 */ + 0x0000, /* R288 */ + 0x0000, /* R289 */ + 0x0000, /* R290 */ + 0x0000, /* R291 */ + 0x0000, /* R292 */ + 0x0000, /* R293 */ + 0x0000, /* R294 */ + 0x0000, /* R295 */ + 0x0000, /* R296 */ + 0x0000, /* R297 */ + 0x0000, /* R298 */ + 0x0000, /* R299 */ + 0x0000, /* R300 */ + 0x0000, /* R301 */ + 0x0000, /* R302 */ + 0x0000, /* R303 */ + 0x0000, /* R304 */ + 0x0000, /* R305 */ + 0x0000, /* R306 */ + 0x0000, /* R307 */ + 0x0000, /* R308 */ + 0x0000, /* R309 */ + 0x0000, /* R310 */ + 0x0000, /* R311 */ + 0x0000, /* R312 */ + 0x0000, /* R313 */ + 0x0000, /* R314 */ + 0x0000, /* R315 */ + 0x0000, /* R316 */ + 0x0000, /* R317 */ + 0x0000, /* R318 */ + 0x0000, /* R319 */ + 0x0000, /* R320 */ + 0x0000, /* R321 */ + 0x0000, /* R322 */ + 0x0000, /* R323 */ + 0x0000, /* R324 */ + 0x0000, /* R325 */ + 0x0000, /* R326 */ + 0x0000, /* R327 */ + 0x0000, /* R328 */ + 0x0000, /* R329 */ + 0x0000, /* R330 */ + 0x0000, /* R331 */ + 0x0000, /* R332 */ + 0x0000, /* R333 */ + 0x0000, /* R334 */ + 0x0000, /* R335 */ + 0x0000, /* R336 */ + 0x0000, /* R337 */ + 0x0000, /* R338 */ + 0x0000, /* R339 */ + 0x0000, /* R340 */ + 0x0000, /* R341 */ + 0x0000, /* R342 */ + 0x0000, /* R343 */ + 0x0000, /* R344 */ + 0x0000, /* R345 */ + 0x0000, /* R346 */ + 0x0000, /* R347 */ + 0x0000, /* R348 */ + 0x0000, /* R349 */ + 0x0000, /* R350 */ + 0x0000, /* R351 */ + 0x0000, /* R352 */ + 0x0000, /* R353 */ + 0x0000, /* R354 */ + 0x0000, /* R355 */ + 0x0000, /* R356 */ + 0x0000, /* R357 */ + 0x0000, /* R358 */ + 0x0000, /* R359 */ + 0x0000, /* R360 */ + 0x0000, /* R361 */ + 0x0000, /* R362 */ + 0x0000, /* R363 */ + 0x0000, /* R364 */ + 0x0000, /* R365 */ + 0x0000, /* R366 */ + 0x0000, /* R367 */ + 0x0000, /* R368 */ + 0x0000, /* R369 */ + 0x0000, /* R370 */ + 0x0000, /* R371 */ + 0x0000, /* R372 */ + 0x0000, /* R373 */ + 0x0000, /* R374 */ + 0x0000, /* R375 */ + 0x0000, /* R376 */ + 0x0000, /* R377 */ + 0x0000, /* R378 */ + 0x0000, /* R379 */ + 0x0000, /* R380 */ + 0x0000, /* R381 */ + 0x0000, /* R382 */ + 0x0000, /* R383 */ + 0x0000, /* R384 */ + 0x0000, /* R385 */ + 0x0000, /* R386 */ + 0x0000, /* R387 */ + 0x0000, /* R388 */ + 0x0000, /* R389 */ + 0x0000, /* R390 */ + 0x0000, /* R391 */ + 0x0000, /* R392 */ + 0x0000, /* R393 */ + 0x0000, /* R394 */ + 0x0000, /* R395 */ + 0x0000, /* R396 */ + 0x0000, /* R397 */ + 0x0000, /* R398 */ + 0x0000, /* R399 */ + 0x0000, /* R400 */ + 0x0000, /* R401 */ + 0x0000, /* R402 */ + 0x0000, /* R403 */ + 0x0000, /* R404 */ + 0x0000, /* R405 */ + 0x0000, /* R406 */ + 0x0000, /* R407 */ + 0x0000, /* R408 */ + 0x0000, /* R409 */ + 0x0000, /* R410 */ + 0x0000, /* R411 */ + 0x0000, /* R412 */ + 0x0000, /* R413 */ + 0x0000, /* R414 */ + 0x0000, /* R415 */ + 0x0000, /* R416 */ + 0x0000, /* R417 */ + 0x0000, /* R418 */ + 0x0000, /* R419 */ + 0x0000, /* R420 */ + 0x0000, /* R421 */ + 0x0000, /* R422 */ + 0x0000, /* R423 */ + 0x0000, /* R424 */ + 0x0000, /* R425 */ + 0x0000, /* R426 */ + 0x0000, /* R427 */ + 0x0000, /* R428 */ + 0x0000, /* R429 */ + 0x0000, /* R430 */ + 0x0000, /* R431 */ + 0x0000, /* R432 */ + 0x0000, /* R433 */ + 0x0000, /* R434 */ + 0x0000, /* R435 */ + 0x0000, /* R436 */ + 0x0000, /* R437 */ + 0x0000, /* R438 */ + 0x0000, /* R439 */ + 0x0000, /* R440 */ + 0x0000, /* R441 */ + 0x0000, /* R442 */ + 0x0000, /* R443 */ + 0x0000, /* R444 */ + 0x0000, /* R445 */ + 0x0000, /* R446 */ + 0x0000, /* R447 */ + 0x0000, /* R448 */ + 0x0000, /* R449 */ + 0x0000, /* R450 */ + 0x0000, /* R451 */ + 0x0000, /* R452 */ + 0x0000, /* R453 */ + 0x0000, /* R454 */ + 0x0000, /* R455 */ + 0x0000, /* R456 */ + 0x0000, /* R457 */ + 0x0000, /* R458 */ + 0x0000, /* R459 */ + 0x0000, /* R460 */ + 0x0000, /* R461 */ + 0x0000, /* R462 */ + 0x0000, /* R463 */ + 0x0000, /* R464 */ + 0x0000, /* R465 */ + 0x0000, /* R466 */ + 0x0000, /* R467 */ + 0x0000, /* R468 */ + 0x0000, /* R469 */ + 0x0000, /* R470 */ + 0x0000, /* R471 */ + 0x0000, /* R472 */ + 0x0000, /* R473 */ + 0x0000, /* R474 */ + 0x0000, /* R475 */ + 0x0000, /* R476 */ + 0x0000, /* R477 */ + 0x0000, /* R478 */ + 0x0000, /* R479 */ + 0x0000, /* R480 */ + 0x0000, /* R481 */ + 0x0000, /* R482 */ + 0x0000, /* R483 */ + 0x0000, /* R484 */ + 0x0000, /* R485 */ + 0x0000, /* R486 */ + 0x0000, /* R487 */ + 0x0000, /* R488 */ + 0x0000, /* R489 */ + 0x0000, /* R490 */ + 0x0000, /* R491 */ + 0x0000, /* R492 */ + 0x0000, /* R493 */ + 0x0000, /* R494 */ + 0x0000, /* R495 */ + 0x0000, /* R496 */ + 0x0000, /* R497 */ + 0x0000, /* R498 */ + 0x0000, /* R499 */ + 0x0000, /* R500 */ + 0x0000, /* R501 */ + 0x0000, /* R502 */ + 0x0000, /* R503 */ + 0x0000, /* R504 */ + 0x0000, /* R505 */ + 0x0000, /* R506 */ + 0x0000, /* R507 */ + 0x0000, /* R508 */ + 0x0000, /* R509 */ + 0x0000, /* R510 */ + 0x0000, /* R511 */ + 0x0000, /* R512 - AIF1 Clocking (1) */ + 0x0000, /* R513 - AIF1 Clocking (2) */ + 0x0000, /* R514 */ + 0x0000, /* R515 */ + 0x0000, /* R516 - AIF2 Clocking (1) */ + 0x0000, /* R517 - AIF2 Clocking (2) */ + 0x0000, /* R518 */ + 0x0000, /* R519 */ + 0x0000, /* R520 - Clocking (1) */ + 0x0000, /* R521 - Clocking (2) */ + 0x0000, /* R522 */ + 0x0000, /* R523 */ + 0x0000, /* R524 */ + 0x0000, /* R525 */ + 0x0000, /* R526 */ + 0x0000, /* R527 */ + 0x0083, /* R528 - AIF1 Rate */ + 0x0083, /* R529 - AIF2 Rate */ + 0x0000, /* R530 - Rate Status */ + 0x0000, /* R531 */ + 0x0000, /* R532 */ + 0x0000, /* R533 */ + 0x0000, /* R534 */ + 0x0000, /* R535 */ + 0x0000, /* R536 */ + 0x0000, /* R537 */ + 0x0000, /* R538 */ + 0x0000, /* R539 */ + 0x0000, /* R540 */ + 0x0000, /* R541 */ + 0x0000, /* R542 */ + 0x0000, /* R543 */ + 0x0000, /* R544 - FLL1 Control (1) */ + 0x0000, /* R545 - FLL1 Control (2) */ + 0x0000, /* R546 - FLL1 Control (3) */ + 0x0000, /* R547 - FLL1 Control (4) */ + 0x0C80, /* R548 - FLL1 Control (5) */ + 0x0000, /* R549 */ + 0x0000, /* R550 */ + 0x0000, /* R551 */ + 0x0000, /* R552 */ + 0x0000, /* R553 */ + 0x0000, /* R554 */ + 0x0000, /* R555 */ + 0x0000, /* R556 */ + 0x0000, /* R557 */ + 0x0000, /* R558 */ + 0x0000, /* R559 */ + 0x0000, /* R560 */ + 0x0000, /* R561 */ + 0x0000, /* R562 */ + 0x0000, /* R563 */ + 0x0000, /* R564 */ + 0x0000, /* R565 */ + 0x0000, /* R566 */ + 0x0000, /* R567 */ + 0x0000, /* R568 */ + 0x0000, /* R569 */ + 0x0000, /* R570 */ + 0x0000, /* R571 */ + 0x0000, /* R572 */ + 0x0000, /* R573 */ + 0x0000, /* R574 */ + 0x0000, /* R575 */ + 0x0000, /* R576 - FLL2 Control (1) */ + 0x0000, /* R577 - FLL2 Control (2) */ + 0x0000, /* R578 - FLL2 Control (3) */ + 0x0000, /* R579 - FLL2 Control (4) */ + 0x0C80, /* R580 - FLL2 Control (5) */ + 0x0000, /* R581 */ + 0x0000, /* R582 */ + 0x0000, /* R583 */ + 0x0000, /* R584 */ + 0x0000, /* R585 */ + 0x0000, /* R586 */ + 0x0000, /* R587 */ + 0x0000, /* R588 */ + 0x0000, /* R589 */ + 0x0000, /* R590 */ + 0x0000, /* R591 */ + 0x0000, /* R592 */ + 0x0000, /* R593 */ + 0x0000, /* R594 */ + 0x0000, /* R595 */ + 0x0000, /* R596 */ + 0x0000, /* R597 */ + 0x0000, /* R598 */ + 0x0000, /* R599 */ + 0x0000, /* R600 */ + 0x0000, /* R601 */ + 0x0000, /* R602 */ + 0x0000, /* R603 */ + 0x0000, /* R604 */ + 0x0000, /* R605 */ + 0x0000, /* R606 */ + 0x0000, /* R607 */ + 0x0000, /* R608 */ + 0x0000, /* R609 */ + 0x0000, /* R610 */ + 0x0000, /* R611 */ + 0x0000, /* R612 */ + 0x0000, /* R613 */ + 0x0000, /* R614 */ + 0x0000, /* R615 */ + 0x0000, /* R616 */ + 0x0000, /* R617 */ + 0x0000, /* R618 */ + 0x0000, /* R619 */ + 0x0000, /* R620 */ + 0x0000, /* R621 */ + 0x0000, /* R622 */ + 0x0000, /* R623 */ + 0x0000, /* R624 */ + 0x0000, /* R625 */ + 0x0000, /* R626 */ + 0x0000, /* R627 */ + 0x0000, /* R628 */ + 0x0000, /* R629 */ + 0x0000, /* R630 */ + 0x0000, /* R631 */ + 0x0000, /* R632 */ + 0x0000, /* R633 */ + 0x0000, /* R634 */ + 0x0000, /* R635 */ + 0x0000, /* R636 */ + 0x0000, /* R637 */ + 0x0000, /* R638 */ + 0x0000, /* R639 */ + 0x0000, /* R640 */ + 0x0000, /* R641 */ + 0x0000, /* R642 */ + 0x0000, /* R643 */ + 0x0000, /* R644 */ + 0x0000, /* R645 */ + 0x0000, /* R646 */ + 0x0000, /* R647 */ + 0x0000, /* R648 */ + 0x0000, /* R649 */ + 0x0000, /* R650 */ + 0x0000, /* R651 */ + 0x0000, /* R652 */ + 0x0000, /* R653 */ + 0x0000, /* R654 */ + 0x0000, /* R655 */ + 0x0000, /* R656 */ + 0x0000, /* R657 */ + 0x0000, /* R658 */ + 0x0000, /* R659 */ + 0x0000, /* R660 */ + 0x0000, /* R661 */ + 0x0000, /* R662 */ + 0x0000, /* R663 */ + 0x0000, /* R664 */ + 0x0000, /* R665 */ + 0x0000, /* R666 */ + 0x0000, /* R667 */ + 0x0000, /* R668 */ + 0x0000, /* R669 */ + 0x0000, /* R670 */ + 0x0000, /* R671 */ + 0x0000, /* R672 */ + 0x0000, /* R673 */ + 0x0000, /* R674 */ + 0x0000, /* R675 */ + 0x0000, /* R676 */ + 0x0000, /* R677 */ + 0x0000, /* R678 */ + 0x0000, /* R679 */ + 0x0000, /* R680 */ + 0x0000, /* R681 */ + 0x0000, /* R682 */ + 0x0000, /* R683 */ + 0x0000, /* R684 */ + 0x0000, /* R685 */ + 0x0000, /* R686 */ + 0x0000, /* R687 */ + 0x0000, /* R688 */ + 0x0000, /* R689 */ + 0x0000, /* R690 */ + 0x0000, /* R691 */ + 0x0000, /* R692 */ + 0x0000, /* R693 */ + 0x0000, /* R694 */ + 0x0000, /* R695 */ + 0x0000, /* R696 */ + 0x0000, /* R697 */ + 0x0000, /* R698 */ + 0x0000, /* R699 */ + 0x0000, /* R700 */ + 0x0000, /* R701 */ + 0x0000, /* R702 */ + 0x0000, /* R703 */ + 0x0000, /* R704 */ + 0x0000, /* R705 */ + 0x0000, /* R706 */ + 0x0000, /* R707 */ + 0x0000, /* R708 */ + 0x0000, /* R709 */ + 0x0000, /* R710 */ + 0x0000, /* R711 */ + 0x0000, /* R712 */ + 0x0000, /* R713 */ + 0x0000, /* R714 */ + 0x0000, /* R715 */ + 0x0000, /* R716 */ + 0x0000, /* R717 */ + 0x0000, /* R718 */ + 0x0000, /* R719 */ + 0x0000, /* R720 */ + 0x0000, /* R721 */ + 0x0000, /* R722 */ + 0x0000, /* R723 */ + 0x0000, /* R724 */ + 0x0000, /* R725 */ + 0x0000, /* R726 */ + 0x0000, /* R727 */ + 0x0000, /* R728 */ + 0x0000, /* R729 */ + 0x0000, /* R730 */ + 0x0000, /* R731 */ + 0x0000, /* R732 */ + 0x0000, /* R733 */ + 0x0000, /* R734 */ + 0x0000, /* R735 */ + 0x0000, /* R736 */ + 0x0000, /* R737 */ + 0x0000, /* R738 */ + 0x0000, /* R739 */ + 0x0000, /* R740 */ + 0x0000, /* R741 */ + 0x0000, /* R742 */ + 0x0000, /* R743 */ + 0x0000, /* R744 */ + 0x0000, /* R745 */ + 0x0000, /* R746 */ + 0x0000, /* R747 */ + 0x0000, /* R748 */ + 0x0000, /* R749 */ + 0x0000, /* R750 */ + 0x0000, /* R751 */ + 0x0000, /* R752 */ + 0x0000, /* R753 */ + 0x0000, /* R754 */ + 0x0000, /* R755 */ + 0x0000, /* R756 */ + 0x0000, /* R757 */ + 0x0000, /* R758 */ + 0x0000, /* R759 */ + 0x0000, /* R760 */ + 0x0000, /* R761 */ + 0x0000, /* R762 */ + 0x0000, /* R763 */ + 0x0000, /* R764 */ + 0x0000, /* R765 */ + 0x0000, /* R766 */ + 0x0000, /* R767 */ + 0x4050, /* R768 - AIF1 Control (1) */ + 0x4000, /* R769 - AIF1 Control (2) */ + 0x0000, /* R770 - AIF1 Master/Slave */ + 0x0040, /* R771 - AIF1 BCLK */ + 0x0040, /* R772 - AIF1ADC LRCLK */ + 0x0040, /* R773 - AIF1DAC LRCLK */ + 0x0004, /* R774 - AIF1DAC Data */ + 0x0100, /* R775 - AIF1ADC Data */ + 0x0000, /* R776 */ + 0x0000, /* R777 */ + 0x0000, /* R778 */ + 0x0000, /* R779 */ + 0x0000, /* R780 */ + 0x0000, /* R781 */ + 0x0000, /* R782 */ + 0x0000, /* R783 */ + 0x4050, /* R784 - AIF2 Control (1) */ + 0x4000, /* R785 - AIF2 Control (2) */ + 0x0000, /* R786 - AIF2 Master/Slave */ + 0x0040, /* R787 - AIF2 BCLK */ + 0x0040, /* R788 - AIF2ADC LRCLK */ + 0x0040, /* R789 - AIF2DAC LRCLK */ + 0x0000, /* R790 - AIF2DAC Data */ + 0x0000, /* R791 - AIF2ADC Data */ + 0x0000, /* R792 */ + 0x0000, /* R793 */ + 0x0000, /* R794 */ + 0x0000, /* R795 */ + 0x0000, /* R796 */ + 0x0000, /* R797 */ + 0x0000, /* R798 */ + 0x0000, /* R799 */ + 0x0000, /* R800 */ + 0x0000, /* R801 */ + 0x0000, /* R802 */ + 0x0000, /* R803 */ + 0x0000, /* R804 */ + 0x0000, /* R805 */ + 0x0000, /* R806 */ + 0x0000, /* R807 */ + 0x0000, /* R808 */ + 0x0000, /* R809 */ + 0x0000, /* R810 */ + 0x0000, /* R811 */ + 0x0000, /* R812 */ + 0x0000, /* R813 */ + 0x0000, /* R814 */ + 0x0000, /* R815 */ + 0x0000, /* R816 */ + 0x0000, /* R817 */ + 0x0000, /* R818 */ + 0x0000, /* R819 */ + 0x0000, /* R820 */ + 0x0000, /* R821 */ + 0x0000, /* R822 */ + 0x0000, /* R823 */ + 0x0000, /* R824 */ + 0x0000, /* R825 */ + 0x0000, /* R826 */ + 0x0000, /* R827 */ + 0x0000, /* R828 */ + 0x0000, /* R829 */ + 0x0000, /* R830 */ + 0x0000, /* R831 */ + 0x0000, /* R832 */ + 0x0000, /* R833 */ + 0x0000, /* R834 */ + 0x0000, /* R835 */ + 0x0000, /* R836 */ + 0x0000, /* R837 */ + 0x0000, /* R838 */ + 0x0000, /* R839 */ + 0x0000, /* R840 */ + 0x0000, /* R841 */ + 0x0000, /* R842 */ + 0x0000, /* R843 */ + 0x0000, /* R844 */ + 0x0000, /* R845 */ + 0x0000, /* R846 */ + 0x0000, /* R847 */ + 0x0000, /* R848 */ + 0x0000, /* R849 */ + 0x0000, /* R850 */ + 0x0000, /* R851 */ + 0x0000, /* R852 */ + 0x0000, /* R853 */ + 0x0000, /* R854 */ + 0x0000, /* R855 */ + 0x0000, /* R856 */ + 0x0000, /* R857 */ + 0x0000, /* R858 */ + 0x0000, /* R859 */ + 0x0000, /* R860 */ + 0x0000, /* R861 */ + 0x0000, /* R862 */ + 0x0000, /* R863 */ + 0x0000, /* R864 */ + 0x0000, /* R865 */ + 0x0000, /* R866 */ + 0x0000, /* R867 */ + 0x0000, /* R868 */ + 0x0000, /* R869 */ + 0x0000, /* R870 */ + 0x0000, /* R871 */ + 0x0000, /* R872 */ + 0x0000, /* R873 */ + 0x0000, /* R874 */ + 0x0000, /* R875 */ + 0x0000, /* R876 */ + 0x0000, /* R877 */ + 0x0000, /* R878 */ + 0x0000, /* R879 */ + 0x0000, /* R880 */ + 0x0000, /* R881 */ + 0x0000, /* R882 */ + 0x0000, /* R883 */ + 0x0000, /* R884 */ + 0x0000, /* R885 */ + 0x0000, /* R886 */ + 0x0000, /* R887 */ + 0x0000, /* R888 */ + 0x0000, /* R889 */ + 0x0000, /* R890 */ + 0x0000, /* R891 */ + 0x0000, /* R892 */ + 0x0000, /* R893 */ + 0x0000, /* R894 */ + 0x0000, /* R895 */ + 0x0000, /* R896 */ + 0x0000, /* R897 */ + 0x0000, /* R898 */ + 0x0000, /* R899 */ + 0x0000, /* R900 */ + 0x0000, /* R901 */ + 0x0000, /* R902 */ + 0x0000, /* R903 */ + 0x0000, /* R904 */ + 0x0000, /* R905 */ + 0x0000, /* R906 */ + 0x0000, /* R907 */ + 0x0000, /* R908 */ + 0x0000, /* R909 */ + 0x0000, /* R910 */ + 0x0000, /* R911 */ + 0x0000, /* R912 */ + 0x0000, /* R913 */ + 0x0000, /* R914 */ + 0x0000, /* R915 */ + 0x0000, /* R916 */ + 0x0000, /* R917 */ + 0x0000, /* R918 */ + 0x0000, /* R919 */ + 0x0000, /* R920 */ + 0x0000, /* R921 */ + 0x0000, /* R922 */ + 0x0000, /* R923 */ + 0x0000, /* R924 */ + 0x0000, /* R925 */ + 0x0000, /* R926 */ + 0x0000, /* R927 */ + 0x0000, /* R928 */ + 0x0000, /* R929 */ + 0x0000, /* R930 */ + 0x0000, /* R931 */ + 0x0000, /* R932 */ + 0x0000, /* R933 */ + 0x0000, /* R934 */ + 0x0000, /* R935 */ + 0x0000, /* R936 */ + 0x0000, /* R937 */ + 0x0000, /* R938 */ + 0x0000, /* R939 */ + 0x0000, /* R940 */ + 0x0000, /* R941 */ + 0x0000, /* R942 */ + 0x0000, /* R943 */ + 0x0000, /* R944 */ + 0x0000, /* R945 */ + 0x0000, /* R946 */ + 0x0000, /* R947 */ + 0x0000, /* R948 */ + 0x0000, /* R949 */ + 0x0000, /* R950 */ + 0x0000, /* R951 */ + 0x0000, /* R952 */ + 0x0000, /* R953 */ + 0x0000, /* R954 */ + 0x0000, /* R955 */ + 0x0000, /* R956 */ + 0x0000, /* R957 */ + 0x0000, /* R958 */ + 0x0000, /* R959 */ + 0x0000, /* R960 */ + 0x0000, /* R961 */ + 0x0000, /* R962 */ + 0x0000, /* R963 */ + 0x0000, /* R964 */ + 0x0000, /* R965 */ + 0x0000, /* R966 */ + 0x0000, /* R967 */ + 0x0000, /* R968 */ + 0x0000, /* R969 */ + 0x0000, /* R970 */ + 0x0000, /* R971 */ + 0x0000, /* R972 */ + 0x0000, /* R973 */ + 0x0000, /* R974 */ + 0x0000, /* R975 */ + 0x0000, /* R976 */ + 0x0000, /* R977 */ + 0x0000, /* R978 */ + 0x0000, /* R979 */ + 0x0000, /* R980 */ + 0x0000, /* R981 */ + 0x0000, /* R982 */ + 0x0000, /* R983 */ + 0x0000, /* R984 */ + 0x0000, /* R985 */ + 0x0000, /* R986 */ + 0x0000, /* R987 */ + 0x0000, /* R988 */ + 0x0000, /* R989 */ + 0x0000, /* R990 */ + 0x0000, /* R991 */ + 0x0000, /* R992 */ + 0x0000, /* R993 */ + 0x0000, /* R994 */ + 0x0000, /* R995 */ + 0x0000, /* R996 */ + 0x0000, /* R997 */ + 0x0000, /* R998 */ + 0x0000, /* R999 */ + 0x0000, /* R1000 */ + 0x0000, /* R1001 */ + 0x0000, /* R1002 */ + 0x0000, /* R1003 */ + 0x0000, /* R1004 */ + 0x0000, /* R1005 */ + 0x0000, /* R1006 */ + 0x0000, /* R1007 */ + 0x0000, /* R1008 */ + 0x0000, /* R1009 */ + 0x0000, /* R1010 */ + 0x0000, /* R1011 */ + 0x0000, /* R1012 */ + 0x0000, /* R1013 */ + 0x0000, /* R1014 */ + 0x0000, /* R1015 */ + 0x0000, /* R1016 */ + 0x0000, /* R1017 */ + 0x0000, /* R1018 */ + 0x0000, /* R1019 */ + 0x0000, /* R1020 */ + 0x0000, /* R1021 */ + 0x0000, /* R1022 */ + 0x0000, /* R1023 */ + 0x00C0, /* R1024 - AIF1 ADC1 Left Volume */ + 0x00C0, /* R1025 - AIF1 ADC1 Right Volume */ + 0x00C0, /* R1026 - AIF1 DAC1 Left Volume */ + 0x00C0, /* R1027 - AIF1 DAC1 Right Volume */ + 0x00C0, /* R1028 - AIF1 ADC2 Left Volume */ + 0x00C0, /* R1029 - AIF1 ADC2 Right Volume */ + 0x00C0, /* R1030 - AIF1 DAC2 Left Volume */ + 0x00C0, /* R1031 - AIF1 DAC2 Right Volume */ + 0x0000, /* R1032 */ + 0x0000, /* R1033 */ + 0x0000, /* R1034 */ + 0x0000, /* R1035 */ + 0x0000, /* R1036 */ + 0x0000, /* R1037 */ + 0x0000, /* R1038 */ + 0x0000, /* R1039 */ + 0x0000, /* R1040 - AIF1 ADC1 Filters */ + 0x0000, /* R1041 - AIF1 ADC2 Filters */ + 0x0000, /* R1042 */ + 0x0000, /* R1043 */ + 0x0000, /* R1044 */ + 0x0000, /* R1045 */ + 0x0000, /* R1046 */ + 0x0000, /* R1047 */ + 0x0000, /* R1048 */ + 0x0000, /* R1049 */ + 0x0000, /* R1050 */ + 0x0000, /* R1051 */ + 0x0000, /* R1052 */ + 0x0000, /* R1053 */ + 0x0000, /* R1054 */ + 0x0000, /* R1055 */ + 0x0200, /* R1056 - AIF1 DAC1 Filters (1) */ + 0x0010, /* R1057 - AIF1 DAC1 Filters (2) */ + 0x0200, /* R1058 - AIF1 DAC2 Filters (1) */ + 0x0010, /* R1059 - AIF1 DAC2 Filters (2) */ + 0x0000, /* R1060 */ + 0x0000, /* R1061 */ + 0x0000, /* R1062 */ + 0x0000, /* R1063 */ + 0x0000, /* R1064 */ + 0x0000, /* R1065 */ + 0x0000, /* R1066 */ + 0x0000, /* R1067 */ + 0x0000, /* R1068 */ + 0x0000, /* R1069 */ + 0x0000, /* R1070 */ + 0x0000, /* R1071 */ + 0x0000, /* R1072 */ + 0x0000, /* R1073 */ + 0x0000, /* R1074 */ + 0x0000, /* R1075 */ + 0x0000, /* R1076 */ + 0x0000, /* R1077 */ + 0x0000, /* R1078 */ + 0x0000, /* R1079 */ + 0x0000, /* R1080 */ + 0x0000, /* R1081 */ + 0x0000, /* R1082 */ + 0x0000, /* R1083 */ + 0x0000, /* R1084 */ + 0x0000, /* R1085 */ + 0x0000, /* R1086 */ + 0x0000, /* R1087 */ + 0x0098, /* R1088 - AIF1 DRC1 (1) */ + 0x0845, /* R1089 - AIF1 DRC1 (2) */ + 0x0000, /* R1090 - AIF1 DRC1 (3) */ + 0x0000, /* R1091 - AIF1 DRC1 (4) */ + 0x0000, /* R1092 - AIF1 DRC1 (5) */ + 0x0000, /* R1093 */ + 0x0000, /* R1094 */ + 0x0000, /* R1095 */ + 0x0000, /* R1096 */ + 0x0000, /* R1097 */ + 0x0000, /* R1098 */ + 0x0000, /* R1099 */ + 0x0000, /* R1100 */ + 0x0000, /* R1101 */ + 0x0000, /* R1102 */ + 0x0000, /* R1103 */ + 0x0098, /* R1104 - AIF1 DRC2 (1) */ + 0x0845, /* R1105 - AIF1 DRC2 (2) */ + 0x0000, /* R1106 - AIF1 DRC2 (3) */ + 0x0000, /* R1107 - AIF1 DRC2 (4) */ + 0x0000, /* R1108 - AIF1 DRC2 (5) */ + 0x0000, /* R1109 */ + 0x0000, /* R1110 */ + 0x0000, /* R1111 */ + 0x0000, /* R1112 */ + 0x0000, /* R1113 */ + 0x0000, /* R1114 */ + 0x0000, /* R1115 */ + 0x0000, /* R1116 */ + 0x0000, /* R1117 */ + 0x0000, /* R1118 */ + 0x0000, /* R1119 */ + 0x0000, /* R1120 */ + 0x0000, /* R1121 */ + 0x0000, /* R1122 */ + 0x0000, /* R1123 */ + 0x0000, /* R1124 */ + 0x0000, /* R1125 */ + 0x0000, /* R1126 */ + 0x0000, /* R1127 */ + 0x0000, /* R1128 */ + 0x0000, /* R1129 */ + 0x0000, /* R1130 */ + 0x0000, /* R1131 */ + 0x0000, /* R1132 */ + 0x0000, /* R1133 */ + 0x0000, /* R1134 */ + 0x0000, /* R1135 */ + 0x0000, /* R1136 */ + 0x0000, /* R1137 */ + 0x0000, /* R1138 */ + 0x0000, /* R1139 */ + 0x0000, /* R1140 */ + 0x0000, /* R1141 */ + 0x0000, /* R1142 */ + 0x0000, /* R1143 */ + 0x0000, /* R1144 */ + 0x0000, /* R1145 */ + 0x0000, /* R1146 */ + 0x0000, /* R1147 */ + 0x0000, /* R1148 */ + 0x0000, /* R1149 */ + 0x0000, /* R1150 */ + 0x0000, /* R1151 */ + 0x6318, /* R1152 - AIF1 DAC1 EQ Gains (1) */ + 0x6300, /* R1153 - AIF1 DAC1 EQ Gains (2) */ + 0x0FCA, /* R1154 - AIF1 DAC1 EQ Band 1 A */ + 0x0400, /* R1155 - AIF1 DAC1 EQ Band 1 B */ + 0x00D8, /* R1156 - AIF1 DAC1 EQ Band 1 PG */ + 0x1EB5, /* R1157 - AIF1 DAC1 EQ Band 2 A */ + 0xF145, /* R1158 - AIF1 DAC1 EQ Band 2 B */ + 0x0B75, /* R1159 - AIF1 DAC1 EQ Band 2 C */ + 0x01C5, /* R1160 - AIF1 DAC1 EQ Band 2 PG */ + 0x1C58, /* R1161 - AIF1 DAC1 EQ Band 3 A */ + 0xF373, /* R1162 - AIF1 DAC1 EQ Band 3 B */ + 0x0A54, /* R1163 - AIF1 DAC1 EQ Band 3 C */ + 0x0558, /* R1164 - AIF1 DAC1 EQ Band 3 PG */ + 0x168E, /* R1165 - AIF1 DAC1 EQ Band 4 A */ + 0xF829, /* R1166 - AIF1 DAC1 EQ Band 4 B */ + 0x07AD, /* R1167 - AIF1 DAC1 EQ Band 4 C */ + 0x1103, /* R1168 - AIF1 DAC1 EQ Band 4 PG */ + 0x0564, /* R1169 - AIF1 DAC1 EQ Band 5 A */ + 0x0559, /* R1170 - AIF1 DAC1 EQ Band 5 B */ + 0x4000, /* R1171 - AIF1 DAC1 EQ Band 5 PG */ + 0x0000, /* R1172 */ + 0x0000, /* R1173 */ + 0x0000, /* R1174 */ + 0x0000, /* R1175 */ + 0x0000, /* R1176 */ + 0x0000, /* R1177 */ + 0x0000, /* R1178 */ + 0x0000, /* R1179 */ + 0x0000, /* R1180 */ + 0x0000, /* R1181 */ + 0x0000, /* R1182 */ + 0x0000, /* R1183 */ + 0x6318, /* R1184 - AIF1 DAC2 EQ Gains (1) */ + 0x6300, /* R1185 - AIF1 DAC2 EQ Gains (2) */ + 0x0FCA, /* R1186 - AIF1 DAC2 EQ Band 1 A */ + 0x0400, /* R1187 - AIF1 DAC2 EQ Band 1 B */ + 0x00D8, /* R1188 - AIF1 DAC2 EQ Band 1 PG */ + 0x1EB5, /* R1189 - AIF1 DAC2 EQ Band 2 A */ + 0xF145, /* R1190 - AIF1 DAC2 EQ Band 2 B */ + 0x0B75, /* R1191 - AIF1 DAC2 EQ Band 2 C */ + 0x01C5, /* R1192 - AIF1 DAC2 EQ Band 2 PG */ + 0x1C58, /* R1193 - AIF1 DAC2 EQ Band 3 A */ + 0xF373, /* R1194 - AIF1 DAC2 EQ Band 3 B */ + 0x0A54, /* R1195 - AIF1 DAC2 EQ Band 3 C */ + 0x0558, /* R1196 - AIF1 DAC2 EQ Band 3 PG */ + 0x168E, /* R1197 - AIF1 DAC2 EQ Band 4 A */ + 0xF829, /* R1198 - AIF1 DAC2 EQ Band 4 B */ + 0x07AD, /* R1199 - AIF1 DAC2 EQ Band 4 C */ + 0x1103, /* R1200 - AIF1 DAC2 EQ Band 4 PG */ + 0x0564, /* R1201 - AIF1 DAC2 EQ Band 5 A */ + 0x0559, /* R1202 - AIF1 DAC2 EQ Band 5 B */ + 0x4000, /* R1203 - AIF1 DAC2 EQ Band 5 PG */ + 0x0000, /* R1204 */ + 0x0000, /* R1205 */ + 0x0000, /* R1206 */ + 0x0000, /* R1207 */ + 0x0000, /* R1208 */ + 0x0000, /* R1209 */ + 0x0000, /* R1210 */ + 0x0000, /* R1211 */ + 0x0000, /* R1212 */ + 0x0000, /* R1213 */ + 0x0000, /* R1214 */ + 0x0000, /* R1215 */ + 0x0000, /* R1216 */ + 0x0000, /* R1217 */ + 0x0000, /* R1218 */ + 0x0000, /* R1219 */ + 0x0000, /* R1220 */ + 0x0000, /* R1221 */ + 0x0000, /* R1222 */ + 0x0000, /* R1223 */ + 0x0000, /* R1224 */ + 0x0000, /* R1225 */ + 0x0000, /* R1226 */ + 0x0000, /* R1227 */ + 0x0000, /* R1228 */ + 0x0000, /* R1229 */ + 0x0000, /* R1230 */ + 0x0000, /* R1231 */ + 0x0000, /* R1232 */ + 0x0000, /* R1233 */ + 0x0000, /* R1234 */ + 0x0000, /* R1235 */ + 0x0000, /* R1236 */ + 0x0000, /* R1237 */ + 0x0000, /* R1238 */ + 0x0000, /* R1239 */ + 0x0000, /* R1240 */ + 0x0000, /* R1241 */ + 0x0000, /* R1242 */ + 0x0000, /* R1243 */ + 0x0000, /* R1244 */ + 0x0000, /* R1245 */ + 0x0000, /* R1246 */ + 0x0000, /* R1247 */ + 0x0000, /* R1248 */ + 0x0000, /* R1249 */ + 0x0000, /* R1250 */ + 0x0000, /* R1251 */ + 0x0000, /* R1252 */ + 0x0000, /* R1253 */ + 0x0000, /* R1254 */ + 0x0000, /* R1255 */ + 0x0000, /* R1256 */ + 0x0000, /* R1257 */ + 0x0000, /* R1258 */ + 0x0000, /* R1259 */ + 0x0000, /* R1260 */ + 0x0000, /* R1261 */ + 0x0000, /* R1262 */ + 0x0000, /* R1263 */ + 0x0000, /* R1264 */ + 0x0000, /* R1265 */ + 0x0000, /* R1266 */ + 0x0000, /* R1267 */ + 0x0000, /* R1268 */ + 0x0000, /* R1269 */ + 0x0000, /* R1270 */ + 0x0000, /* R1271 */ + 0x0000, /* R1272 */ + 0x0000, /* R1273 */ + 0x0000, /* R1274 */ + 0x0000, /* R1275 */ + 0x0000, /* R1276 */ + 0x0000, /* R1277 */ + 0x0000, /* R1278 */ + 0x0000, /* R1279 */ + 0x00C0, /* R1280 - AIF2 ADC Left Volume */ + 0x00C0, /* R1281 - AIF2 ADC Right Volume */ + 0x00C0, /* R1282 - AIF2 DAC Left Volume */ + 0x00C0, /* R1283 - AIF2 DAC Right Volume */ + 0x0000, /* R1284 */ + 0x0000, /* R1285 */ + 0x0000, /* R1286 */ + 0x0000, /* R1287 */ + 0x0000, /* R1288 */ + 0x0000, /* R1289 */ + 0x0000, /* R1290 */ + 0x0000, /* R1291 */ + 0x0000, /* R1292 */ + 0x0000, /* R1293 */ + 0x0000, /* R1294 */ + 0x0000, /* R1295 */ + 0x0000, /* R1296 - AIF2 ADC Filters */ + 0x0000, /* R1297 */ + 0x0000, /* R1298 */ + 0x0000, /* R1299 */ + 0x0000, /* R1300 */ + 0x0000, /* R1301 */ + 0x0000, /* R1302 */ + 0x0000, /* R1303 */ + 0x0000, /* R1304 */ + 0x0000, /* R1305 */ + 0x0000, /* R1306 */ + 0x0000, /* R1307 */ + 0x0000, /* R1308 */ + 0x0000, /* R1309 */ + 0x0000, /* R1310 */ + 0x0000, /* R1311 */ + 0x0200, /* R1312 - AIF2 DAC Filters (1) */ + 0x0010, /* R1313 - AIF2 DAC Filters (2) */ + 0x0000, /* R1314 */ + 0x0000, /* R1315 */ + 0x0000, /* R1316 */ + 0x0000, /* R1317 */ + 0x0000, /* R1318 */ + 0x0000, /* R1319 */ + 0x0000, /* R1320 */ + 0x0000, /* R1321 */ + 0x0000, /* R1322 */ + 0x0000, /* R1323 */ + 0x0000, /* R1324 */ + 0x0000, /* R1325 */ + 0x0000, /* R1326 */ + 0x0000, /* R1327 */ + 0x0000, /* R1328 */ + 0x0000, /* R1329 */ + 0x0000, /* R1330 */ + 0x0000, /* R1331 */ + 0x0000, /* R1332 */ + 0x0000, /* R1333 */ + 0x0000, /* R1334 */ + 0x0000, /* R1335 */ + 0x0000, /* R1336 */ + 0x0000, /* R1337 */ + 0x0000, /* R1338 */ + 0x0000, /* R1339 */ + 0x0000, /* R1340 */ + 0x0000, /* R1341 */ + 0x0000, /* R1342 */ + 0x0000, /* R1343 */ + 0x0098, /* R1344 - AIF2 DRC (1) */ + 0x0845, /* R1345 - AIF2 DRC (2) */ + 0x0000, /* R1346 - AIF2 DRC (3) */ + 0x0000, /* R1347 - AIF2 DRC (4) */ + 0x0000, /* R1348 - AIF2 DRC (5) */ + 0x0000, /* R1349 */ + 0x0000, /* R1350 */ + 0x0000, /* R1351 */ + 0x0000, /* R1352 */ + 0x0000, /* R1353 */ + 0x0000, /* R1354 */ + 0x0000, /* R1355 */ + 0x0000, /* R1356 */ + 0x0000, /* R1357 */ + 0x0000, /* R1358 */ + 0x0000, /* R1359 */ + 0x0000, /* R1360 */ + 0x0000, /* R1361 */ + 0x0000, /* R1362 */ + 0x0000, /* R1363 */ + 0x0000, /* R1364 */ + 0x0000, /* R1365 */ + 0x0000, /* R1366 */ + 0x0000, /* R1367 */ + 0x0000, /* R1368 */ + 0x0000, /* R1369 */ + 0x0000, /* R1370 */ + 0x0000, /* R1371 */ + 0x0000, /* R1372 */ + 0x0000, /* R1373 */ + 0x0000, /* R1374 */ + 0x0000, /* R1375 */ + 0x0000, /* R1376 */ + 0x0000, /* R1377 */ + 0x0000, /* R1378 */ + 0x0000, /* R1379 */ + 0x0000, /* R1380 */ + 0x0000, /* R1381 */ + 0x0000, /* R1382 */ + 0x0000, /* R1383 */ + 0x0000, /* R1384 */ + 0x0000, /* R1385 */ + 0x0000, /* R1386 */ + 0x0000, /* R1387 */ + 0x0000, /* R1388 */ + 0x0000, /* R1389 */ + 0x0000, /* R1390 */ + 0x0000, /* R1391 */ + 0x0000, /* R1392 */ + 0x0000, /* R1393 */ + 0x0000, /* R1394 */ + 0x0000, /* R1395 */ + 0x0000, /* R1396 */ + 0x0000, /* R1397 */ + 0x0000, /* R1398 */ + 0x0000, /* R1399 */ + 0x0000, /* R1400 */ + 0x0000, /* R1401 */ + 0x0000, /* R1402 */ + 0x0000, /* R1403 */ + 0x0000, /* R1404 */ + 0x0000, /* R1405 */ + 0x0000, /* R1406 */ + 0x0000, /* R1407 */ + 0x6318, /* R1408 - AIF2 EQ Gains (1) */ + 0x6300, /* R1409 - AIF2 EQ Gains (2) */ + 0x0FCA, /* R1410 - AIF2 EQ Band 1 A */ + 0x0400, /* R1411 - AIF2 EQ Band 1 B */ + 0x00D8, /* R1412 - AIF2 EQ Band 1 PG */ + 0x1EB5, /* R1413 - AIF2 EQ Band 2 A */ + 0xF145, /* R1414 - AIF2 EQ Band 2 B */ + 0x0B75, /* R1415 - AIF2 EQ Band 2 C */ + 0x01C5, /* R1416 - AIF2 EQ Band 2 PG */ + 0x1C58, /* R1417 - AIF2 EQ Band 3 A */ + 0xF373, /* R1418 - AIF2 EQ Band 3 B */ + 0x0A54, /* R1419 - AIF2 EQ Band 3 C */ + 0x0558, /* R1420 - AIF2 EQ Band 3 PG */ + 0x168E, /* R1421 - AIF2 EQ Band 4 A */ + 0xF829, /* R1422 - AIF2 EQ Band 4 B */ + 0x07AD, /* R1423 - AIF2 EQ Band 4 C */ + 0x1103, /* R1424 - AIF2 EQ Band 4 PG */ + 0x0564, /* R1425 - AIF2 EQ Band 5 A */ + 0x0559, /* R1426 - AIF2 EQ Band 5 B */ + 0x4000, /* R1427 - AIF2 EQ Band 5 PG */ + 0x0000, /* R1428 */ + 0x0000, /* R1429 */ + 0x0000, /* R1430 */ + 0x0000, /* R1431 */ + 0x0000, /* R1432 */ + 0x0000, /* R1433 */ + 0x0000, /* R1434 */ + 0x0000, /* R1435 */ + 0x0000, /* R1436 */ + 0x0000, /* R1437 */ + 0x0000, /* R1438 */ + 0x0000, /* R1439 */ + 0x0000, /* R1440 */ + 0x0000, /* R1441 */ + 0x0000, /* R1442 */ + 0x0000, /* R1443 */ + 0x0000, /* R1444 */ + 0x0000, /* R1445 */ + 0x0000, /* R1446 */ + 0x0000, /* R1447 */ + 0x0000, /* R1448 */ + 0x0000, /* R1449 */ + 0x0000, /* R1450 */ + 0x0000, /* R1451 */ + 0x0000, /* R1452 */ + 0x0000, /* R1453 */ + 0x0000, /* R1454 */ + 0x0000, /* R1455 */ + 0x0000, /* R1456 */ + 0x0000, /* R1457 */ + 0x0000, /* R1458 */ + 0x0000, /* R1459 */ + 0x0000, /* R1460 */ + 0x0000, /* R1461 */ + 0x0000, /* R1462 */ + 0x0000, /* R1463 */ + 0x0000, /* R1464 */ + 0x0000, /* R1465 */ + 0x0000, /* R1466 */ + 0x0000, /* R1467 */ + 0x0000, /* R1468 */ + 0x0000, /* R1469 */ + 0x0000, /* R1470 */ + 0x0000, /* R1471 */ + 0x0000, /* R1472 */ + 0x0000, /* R1473 */ + 0x0000, /* R1474 */ + 0x0000, /* R1475 */ + 0x0000, /* R1476 */ + 0x0000, /* R1477 */ + 0x0000, /* R1478 */ + 0x0000, /* R1479 */ + 0x0000, /* R1480 */ + 0x0000, /* R1481 */ + 0x0000, /* R1482 */ + 0x0000, /* R1483 */ + 0x0000, /* R1484 */ + 0x0000, /* R1485 */ + 0x0000, /* R1486 */ + 0x0000, /* R1487 */ + 0x0000, /* R1488 */ + 0x0000, /* R1489 */ + 0x0000, /* R1490 */ + 0x0000, /* R1491 */ + 0x0000, /* R1492 */ + 0x0000, /* R1493 */ + 0x0000, /* R1494 */ + 0x0000, /* R1495 */ + 0x0000, /* R1496 */ + 0x0000, /* R1497 */ + 0x0000, /* R1498 */ + 0x0000, /* R1499 */ + 0x0000, /* R1500 */ + 0x0000, /* R1501 */ + 0x0000, /* R1502 */ + 0x0000, /* R1503 */ + 0x0000, /* R1504 */ + 0x0000, /* R1505 */ + 0x0000, /* R1506 */ + 0x0000, /* R1507 */ + 0x0000, /* R1508 */ + 0x0000, /* R1509 */ + 0x0000, /* R1510 */ + 0x0000, /* R1511 */ + 0x0000, /* R1512 */ + 0x0000, /* R1513 */ + 0x0000, /* R1514 */ + 0x0000, /* R1515 */ + 0x0000, /* R1516 */ + 0x0000, /* R1517 */ + 0x0000, /* R1518 */ + 0x0000, /* R1519 */ + 0x0000, /* R1520 */ + 0x0000, /* R1521 */ + 0x0000, /* R1522 */ + 0x0000, /* R1523 */ + 0x0000, /* R1524 */ + 0x0000, /* R1525 */ + 0x0000, /* R1526 */ + 0x0000, /* R1527 */ + 0x0000, /* R1528 */ + 0x0000, /* R1529 */ + 0x0000, /* R1530 */ + 0x0000, /* R1531 */ + 0x0000, /* R1532 */ + 0x0000, /* R1533 */ + 0x0000, /* R1534 */ + 0x0000, /* R1535 */ + 0x0000, /* R1536 - DAC1 Mixer Volumes */ + 0x0000, /* R1537 - DAC1 Left Mixer Routing */ + 0x0000, /* R1538 - DAC1 Right Mixer Routing */ + 0x0000, /* R1539 - DAC2 Mixer Volumes */ + 0x0000, /* R1540 - DAC2 Left Mixer Routing */ + 0x0000, /* R1541 - DAC2 Right Mixer Routing */ + 0x0000, /* R1542 - AIF1 ADC1 Left Mixer Routing */ + 0x0000, /* R1543 - AIF1 ADC1 Right Mixer Routing */ + 0x0000, /* R1544 - AIF1 ADC2 Left Mixer Routing */ + 0x0000, /* R1545 - AIF1 ADC2 Right mixer Routing */ + 0x0000, /* R1546 */ + 0x0000, /* R1547 */ + 0x0000, /* R1548 */ + 0x0000, /* R1549 */ + 0x0000, /* R1550 */ + 0x0000, /* R1551 */ + 0x02C0, /* R1552 - DAC1 Left Volume */ + 0x02C0, /* R1553 - DAC1 Right Volume */ + 0x02C0, /* R1554 - DAC2 Left Volume */ + 0x02C0, /* R1555 - DAC2 Right Volume */ + 0x0000, /* R1556 - DAC Softmute */ + 0x0000, /* R1557 */ + 0x0000, /* R1558 */ + 0x0000, /* R1559 */ + 0x0000, /* R1560 */ + 0x0000, /* R1561 */ + 0x0000, /* R1562 */ + 0x0000, /* R1563 */ + 0x0000, /* R1564 */ + 0x0000, /* R1565 */ + 0x0000, /* R1566 */ + 0x0000, /* R1567 */ + 0x0002, /* R1568 - Oversampling */ + 0x0000, /* R1569 - Sidetone */ +}; diff --git a/sound/soc/codecs/wm8994.c b/sound/soc/codecs/wm8994.c index 948677b581b1..d9c6dd5823b4 100644 --- a/sound/soc/codecs/wm8994.c +++ b/sound/soc/codecs/wm8994.c @@ -57,8 +57,6 @@ static int wm8994_retune_mobile_base[] = { WM8994_AIF2_EQ_GAINS_1, }; -#define WM8994_REG_CACHE_SIZE 0x621 - struct wm8994_micdet { struct snd_soc_jack *jack; int det; @@ -71,7 +69,6 @@ struct wm8994_priv { enum snd_soc_control_type control_type; void *control_data; struct snd_soc_codec *codec; - u16 reg_cache[WM8994_REG_CACHE_SIZE + 1]; int sysclk[2]; int sysclk_rate[2]; int mclk[2]; @@ -134,7 +131,7 @@ static int wm8994_readable(unsigned int reg) static int wm8994_volatile(unsigned int reg) { - if (reg >= WM8994_REG_CACHE_SIZE) + if (reg >= WM8994_CACHE_SIZE) return 1; switch (reg) { @@ -156,12 +153,16 @@ static int wm8994_volatile(unsigned int reg) static int wm8994_write(struct snd_soc_codec *codec, unsigned int reg, unsigned int value) { - struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); + int ret; BUG_ON(reg > WM8994_MAX_REGISTER); - if (!wm8994_volatile(reg)) - wm8994->reg_cache[reg] = value; + if (!wm8994_volatile(reg)) { + ret = snd_soc_cache_write(codec, reg, value); + if (ret != 0) + dev_err(codec->dev, "Cache write to %x failed: %d\n", + reg, ret); + } return wm8994_reg_write(codec->control_data, reg, value); } @@ -169,14 +170,22 @@ static int wm8994_write(struct snd_soc_codec *codec, unsigned int reg, static unsigned int wm8994_read(struct snd_soc_codec *codec, unsigned int reg) { - u16 *reg_cache = codec->reg_cache; + unsigned int val; + int ret; BUG_ON(reg > WM8994_MAX_REGISTER); - if (wm8994_volatile(reg)) - return wm8994_reg_read(codec->control_data, reg); - else - return reg_cache[reg]; + if (!wm8994_volatile(reg) && wm8994_readable(reg) && + reg < codec->driver->reg_cache_size) { + ret = snd_soc_cache_read(codec, reg, &val); + if (ret >= 0) + return val; + else + dev_err(codec->dev, "Cache read from %x failed: %d\n", + reg, ret); + } + + return wm8994_reg_read(codec->control_data, reg); } static int configure_aif_clock(struct snd_soc_codec *codec, int aif) @@ -2370,26 +2379,12 @@ static int wm8994_suspend(struct snd_soc_codec *codec, pm_message_t state) static int wm8994_resume(struct snd_soc_codec *codec) { struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); - u16 *reg_cache = codec->reg_cache; int i, ret; /* Restore the registers */ - for (i = 1; i < ARRAY_SIZE(wm8994->reg_cache); i++) { - switch (i) { - case WM8994_LDO_1: - case WM8994_LDO_2: - case WM8994_SOFTWARE_RESET: - /* Handled by other MFD drivers */ - continue; - default: - break; - } - - if (!wm8994_access_masks[i].writable) - continue; - - wm8994_reg_write(codec->control_data, i, reg_cache[i]); - } + ret = snd_soc_cache_sync(codec); + if (ret != 0) + dev_err(codec->dev, "Failed to sync cache: %d\n", ret); wm8994_set_bias_level(codec, SND_SOC_BIAS_STANDBY); @@ -2782,27 +2777,27 @@ static int wm8994_codec_probe(struct snd_soc_codec *codec) return -ENOMEM; snd_soc_codec_set_drvdata(codec, wm8994); - codec->reg_cache = &wm8994->reg_cache; - wm8994->pdata = dev_get_platdata(codec->dev->parent); wm8994->codec = codec; - /* Fill the cache with physical values we inherited; don't reset */ - ret = wm8994_bulk_read(codec->control_data, 0, - ARRAY_SIZE(wm8994->reg_cache) - 1, - codec->reg_cache); - if (ret < 0) { - dev_err(codec->dev, "Failed to fill register cache: %d\n", - ret); - goto err; - } + /* Read our current status back from the chip - we don't want to + * reset as this may interfere with the GPIO or LDO operation. */ + for (i = 0; i < WM8994_CACHE_SIZE; i++) { + if (!wm8994_readable(i) || wm8994_volatile(i)) + continue; - /* Clear the cached values for unreadable/volatile registers to - * avoid potential confusion. - */ - for (i = 0; i < ARRAY_SIZE(wm8994->reg_cache); i++) - if (wm8994_volatile(i) || !wm8994_readable(i)) - wm8994->reg_cache[i] = 0; + ret = wm8994_reg_read(codec->control_data, i); + if (ret <= 0) + continue; + + ret = snd_soc_cache_write(codec, i, ret); + if (ret != 0) { + dev_err(codec->dev, + "Failed to initialise cache for 0x%x: %d\n", + i, ret); + goto err; + } + } /* Set revision-specific configuration */ wm8994->revision = snd_soc_read(codec, WM8994_CHIP_REVISION); @@ -3029,11 +3024,15 @@ static struct snd_soc_codec_driver soc_codec_dev_wm8994 = { .remove = wm8994_codec_remove, .suspend = wm8994_suspend, .resume = wm8994_resume, - .read = wm8994_read, - .write = wm8994_write, + .read = wm8994_read, + .write = wm8994_write, .readable_register = wm8994_readable, .volatile_register = wm8994_volatile, .set_bias_level = wm8994_set_bias_level, + + .reg_cache_size = WM8994_CACHE_SIZE, + .reg_cache_default = wm8994_reg_defaults, + .reg_word_size = 2, }; static int __devinit wm8994_probe(struct platform_device *pdev) diff --git a/sound/soc/codecs/wm8994.h b/sound/soc/codecs/wm8994.h index 455cae6b4356..0c355bfc88f1 100644 --- a/sound/soc/codecs/wm8994.h +++ b/sound/soc/codecs/wm8994.h @@ -43,5 +43,6 @@ struct wm8994_access_mask { }; extern const struct wm8994_access_mask wm8994_access_masks[WM8994_CACHE_SIZE]; +extern const __devinitdata u16 wm8994_reg_defaults[WM8994_CACHE_SIZE]; #endif -- cgit v1.2.2 From 2e19b0c8c21cb06eb5b902588c30ae0529ce8ec3 Mon Sep 17 00:00:00 2001 From: Mark Brown Date: Fri, 26 Nov 2010 17:23:42 +0000 Subject: ASoC: Enable rbtree compression for WM8994/58 register cache The WM8994 and WM8958 register map is relatively sparse so benefits from compression. The rbtree compression gives better results than LZO for both memory and CPU consumption on a map as sparse as this. Signed-off-by: Mark Brown Acked-by: Liam Girdwood --- sound/soc/codecs/wm8994.c | 1 + 1 file changed, 1 insertion(+) (limited to 'sound/soc/codecs') diff --git a/sound/soc/codecs/wm8994.c b/sound/soc/codecs/wm8994.c index d9c6dd5823b4..5f203c545e00 100644 --- a/sound/soc/codecs/wm8994.c +++ b/sound/soc/codecs/wm8994.c @@ -3033,6 +3033,7 @@ static struct snd_soc_codec_driver soc_codec_dev_wm8994 = { .reg_cache_size = WM8994_CACHE_SIZE, .reg_cache_default = wm8994_reg_defaults, .reg_word_size = 2, + .compress_type = SND_SOC_RBTREE_COMPRESSION, }; static int __devinit wm8994_probe(struct platform_device *pdev) -- cgit v1.2.2 From 39fb51a123c125e36e9bcb67686b3e2945784250 Mon Sep 17 00:00:00 2001 From: Mark Brown Date: Fri, 26 Nov 2010 17:23:43 +0000 Subject: ASoC: Implement runtime PM for WM8994/58 This allows us to communicate our power management state back to the parent device, allowing it to do a full power down when the device is idle. Signed-off-by: Mark Brown Acked-by: Liam Girdwood --- sound/soc/codecs/wm8994.c | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'sound/soc/codecs') diff --git a/sound/soc/codecs/wm8994.c b/sound/soc/codecs/wm8994.c index 5f203c545e00..bfd4cf4fde5f 100644 --- a/sound/soc/codecs/wm8994.c +++ b/sound/soc/codecs/wm8994.c @@ -18,6 +18,7 @@ #include #include #include +#include #include #include #include @@ -1803,6 +1804,8 @@ static int wm8994_set_bias_level(struct snd_soc_codec *codec, case SND_SOC_BIAS_STANDBY: if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) { + pm_runtime_get_sync(codec->dev); + /* Tweak DC servo and DSP configuration for * improved performance. */ if (control->type == WM8994 && wm8994->revision < 4) { @@ -1878,6 +1881,8 @@ static int wm8994_set_bias_level(struct snd_soc_codec *codec, WM8994_STARTUP_BIAS_ENA | WM8994_VMID_BUF_ENA | WM8994_VMID_RAMP_MASK, 0); + + pm_runtime_put(codec->dev); } break; } @@ -2780,6 +2785,9 @@ static int wm8994_codec_probe(struct snd_soc_codec *codec) wm8994->pdata = dev_get_platdata(codec->dev->parent); wm8994->codec = codec; + pm_runtime_enable(codec->dev); + pm_runtime_resume(codec->dev); + /* Read our current status back from the chip - we don't want to * reset as this may interfere with the GPIO or LDO operation. */ for (i = 0; i < WM8994_CACHE_SIZE; i++) { @@ -2995,6 +3003,8 @@ static int wm8994_codec_remove(struct snd_soc_codec *codec) wm8994_set_bias_level(codec, SND_SOC_BIAS_OFF); + pm_runtime_disable(codec->dev); + switch (control->type) { case WM8994: wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC2_SHRT, -- cgit v1.2.2 From 551102762ebe8bc0aa867d28960d9be97bbe17c1 Mon Sep 17 00:00:00 2001 From: Axel Lin Date: Tue, 30 Nov 2010 15:34:11 +0800 Subject: ASoC: Simplify pm860x_probe error handling Simplify pm860x_probe error handling and return actual error code we got. Signed-off-by: Axel Lin Acked-by: Liam Girdwood Signed-off-by: Mark Brown --- sound/soc/codecs/88pm860x-codec.c | 12 +++++------- 1 file changed, 5 insertions(+), 7 deletions(-) (limited to 'sound/soc/codecs') diff --git a/sound/soc/codecs/88pm860x-codec.c b/sound/soc/codecs/88pm860x-codec.c index 7e4d88007d4f..08e15dee9182 100644 --- a/sound/soc/codecs/88pm860x-codec.c +++ b/sound/soc/codecs/88pm860x-codec.c @@ -1358,7 +1358,7 @@ static int pm860x_probe(struct snd_soc_codec *codec) pm860x->name[i], pm860x); if (ret < 0) { dev_err(codec->dev, "Failed to request IRQ!\n"); - goto out_irq; + goto out; } } @@ -1369,7 +1369,7 @@ static int pm860x_probe(struct snd_soc_codec *codec) if (ret < 0) { dev_err(codec->dev, "Failed to fill register cache: %d\n", ret); - goto out_codec; + goto out; } snd_soc_add_controls(codec, pm860x_snd_controls, @@ -1379,12 +1379,10 @@ static int pm860x_probe(struct snd_soc_codec *codec) snd_soc_dapm_add_routes(dapm, audio_map, ARRAY_SIZE(audio_map)); return 0; -out_codec: - i = 3; -out_irq: - for (; i >= 0; i--) +out: + while (--i >= 0) free_irq(pm860x->irq[i], pm860x); - return -EINVAL; + return ret; } static int pm860x_remove(struct snd_soc_codec *codec) -- cgit v1.2.2 From 18f454047b3d009e347dc3aeacb1aec91a4c493f Mon Sep 17 00:00:00 2001 From: Peter Ujfalusi Date: Tue, 30 Nov 2010 14:31:45 +0200 Subject: ASoC: tlv320dac33: Do not enable the codec in init_chip No need to enable the codec at this time. The codec will be enabled later by other events Signed-off-by: Peter Ujfalusi Acked-by: Mark Brown Signed-off-by: Liam Girdwood --- sound/soc/codecs/tlv320dac33.c | 2 -- 1 file changed, 2 deletions(-) (limited to 'sound/soc/codecs') diff --git a/sound/soc/codecs/tlv320dac33.c b/sound/soc/codecs/tlv320dac33.c index ccb267f4e968..080ec9183f67 100644 --- a/sound/soc/codecs/tlv320dac33.c +++ b/sound/soc/codecs/tlv320dac33.c @@ -315,8 +315,6 @@ static void dac33_init_chip(struct snd_soc_codec *codec) clock source = internal osc (?) */ dac33_write(codec, DAC33_ANA_VOL_SOFT_STEP_CTRL, DAC33_VOLCLKEN); - dac33_write(codec, DAC33_PWR_CTRL, DAC33_PDNALLB); - /* Restore only selected registers (gains mostly) */ dac33_write(codec, DAC33_LDAC_DIG_VOL_CTRL, dac33_read_reg_cache(codec, DAC33_LDAC_DIG_VOL_CTRL)); -- cgit v1.2.2 From 3e202345abc2cea09a3601df527629102f37e563 Mon Sep 17 00:00:00 2001 From: Peter Ujfalusi Date: Tue, 30 Nov 2010 14:31:46 +0200 Subject: ASoC: tlv320dac33: Avoid multiple soft power up During playback start the codec has been already powered at BIAS_ON event time, so there's no need to enable the codec again. Signed-off-by: Peter Ujfalusi Acked-by: Mark Brown Signed-off-by: Liam Girdwood --- sound/soc/codecs/tlv320dac33.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'sound/soc/codecs') diff --git a/sound/soc/codecs/tlv320dac33.c b/sound/soc/codecs/tlv320dac33.c index 080ec9183f67..a0ba5d1be1b3 100644 --- a/sound/soc/codecs/tlv320dac33.c +++ b/sound/soc/codecs/tlv320dac33.c @@ -642,7 +642,8 @@ static int dac33_set_bias_level(struct snd_soc_codec *codec, switch (level) { case SND_SOC_BIAS_ON: - dac33_soft_power(codec, 1); + if (!dac33->substream) + dac33_soft_power(codec, 1); break; case SND_SOC_BIAS_PREPARE: break; -- cgit v1.2.2 From d5876ce1242b78987e6243ba3cb23bb61d44d4a9 Mon Sep 17 00:00:00 2001 From: Peter Ujfalusi Date: Tue, 30 Nov 2010 16:00:00 +0200 Subject: ASoC: tpa6130a2: Simplify power state management Use simpler way to avoid setting the same power state for the amplifier. Simplifies the check introduced by patch: ASoC: tpa6130a2: Fix unbalanced regulator disables Signed-off-by: Peter Ujfalusi Cc: Jarkko Nikula Signed-off-by: Liam Girdwood --- sound/soc/codecs/tpa6130a2.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) (limited to 'sound/soc/codecs') diff --git a/sound/soc/codecs/tpa6130a2.c b/sound/soc/codecs/tpa6130a2.c index 9d61a1d6fce0..199edf07f47e 100644 --- a/sound/soc/codecs/tpa6130a2.c +++ b/sound/soc/codecs/tpa6130a2.c @@ -41,7 +41,7 @@ struct tpa6130a2_data { unsigned char regs[TPA6130A2_CACHEREGNUM]; struct regulator *supply; int power_gpio; - unsigned char power_state; + u8 power_state:1; enum tpa_model id; }; @@ -116,7 +116,7 @@ static int tpa6130a2_initialize(void) return ret; } -static int tpa6130a2_power(int power) +static int tpa6130a2_power(u8 power) { struct tpa6130a2_data *data; u8 val; @@ -126,8 +126,10 @@ static int tpa6130a2_power(int power) data = i2c_get_clientdata(tpa6130a2_client); mutex_lock(&data->mutex); - if (power && !data->power_state) { + if (power == data->power_state) + goto exit; + if (power) { ret = regulator_enable(data->supply); if (ret != 0) { dev_err(&tpa6130a2_client->dev, @@ -154,7 +156,7 @@ static int tpa6130a2_power(int power) val = tpa6130a2_read(TPA6130A2_REG_CONTROL); val &= ~TPA6130A2_SWS; tpa6130a2_i2c_write(TPA6130A2_REG_CONTROL, val); - } else if (!power && data->power_state) { + } else { /* set SWS */ val = tpa6130a2_read(TPA6130A2_REG_CONTROL); val |= TPA6130A2_SWS; -- cgit v1.2.2 From d534bacd918fcf0909039b95db7c090702e739d5 Mon Sep 17 00:00:00 2001 From: Peter Ujfalusi Date: Tue, 30 Nov 2010 16:00:01 +0200 Subject: ASoC: tpa6130a2: Defer SW enable from power enable Do not enable the amplifier right after the power has been restored to the amplifier. The DAPM_SUPPLY widget turns on the amp early in the DAPM power walk, and the unmuting of channel happens quite late. Keeping the amp in SW reset state ensures better muting. In this way the pop noise coming from other components (codec) can be filtered out. Signed-off-by: Peter Ujfalusi Acked-by: Mark Brown Signed-off-by: Liam Girdwood --- sound/soc/codecs/tpa6130a2.c | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) (limited to 'sound/soc/codecs') diff --git a/sound/soc/codecs/tpa6130a2.c b/sound/soc/codecs/tpa6130a2.c index 199edf07f47e..42887ae1568b 100644 --- a/sound/soc/codecs/tpa6130a2.c +++ b/sound/soc/codecs/tpa6130a2.c @@ -151,11 +151,6 @@ static int tpa6130a2_power(u8 power) data->power_state = 0; goto exit; } - - /* Clear SWS */ - val = tpa6130a2_read(TPA6130A2_REG_CONTROL); - val &= ~TPA6130A2_SWS; - tpa6130a2_i2c_write(TPA6130A2_REG_CONTROL, val); } else { /* set SWS */ val = tpa6130a2_read(TPA6130A2_REG_CONTROL); @@ -301,6 +296,7 @@ static void tpa6130a2_channel_enable(u8 channel, int enable) /* Enable amplifier */ val = tpa6130a2_read(TPA6130A2_REG_CONTROL); val |= channel; + val &= ~TPA6130A2_SWS; tpa6130a2_i2c_write(TPA6130A2_REG_CONTROL, val); /* Unmute channel */ -- cgit v1.2.2 From 8cc14e13d15ec558c880ce6eaaddf99c08f85ab6 Mon Sep 17 00:00:00 2001 From: Peter Ujfalusi Date: Tue, 30 Nov 2010 16:00:02 +0200 Subject: ASoC: tpa6130a2: Use one event handler for PGA_E Reduce the amount of duplicated code by using single event handler for PGA_E to enable the needed channel. Use the w->shift to pass the channel information to the handler function. Signed-off-by: Peter Ujfalusi Acked-by: Mark Brown Signed-off-by: Liam Girdwood --- sound/soc/codecs/tpa6130a2.c | 24 +++++------------------- 1 file changed, 5 insertions(+), 19 deletions(-) (limited to 'sound/soc/codecs') diff --git a/sound/soc/codecs/tpa6130a2.c b/sound/soc/codecs/tpa6130a2.c index 42887ae1568b..4c77a82d9780 100644 --- a/sound/soc/codecs/tpa6130a2.c +++ b/sound/soc/codecs/tpa6130a2.c @@ -317,29 +317,15 @@ static void tpa6130a2_channel_enable(u8 channel, int enable) } } -static int tpa6130a2_left_event(struct snd_soc_dapm_widget *w, +static int tpa6130a2_pga_event(struct snd_soc_dapm_widget *w, struct snd_kcontrol *kcontrol, int event) { switch (event) { case SND_SOC_DAPM_POST_PMU: - tpa6130a2_channel_enable(TPA6130A2_HP_EN_L, 1); + tpa6130a2_channel_enable(w->shift, 1); break; case SND_SOC_DAPM_POST_PMD: - tpa6130a2_channel_enable(TPA6130A2_HP_EN_L, 0); - break; - } - return 0; -} - -static int tpa6130a2_right_event(struct snd_soc_dapm_widget *w, - struct snd_kcontrol *kcontrol, int event) -{ - switch (event) { - case SND_SOC_DAPM_POST_PMU: - tpa6130a2_channel_enable(TPA6130A2_HP_EN_R, 1); - break; - case SND_SOC_DAPM_POST_PMD: - tpa6130a2_channel_enable(TPA6130A2_HP_EN_R, 0); + tpa6130a2_channel_enable(w->shift, 0); break; } return 0; @@ -363,10 +349,10 @@ static int tpa6130a2_supply_event(struct snd_soc_dapm_widget *w, static const struct snd_soc_dapm_widget tpa6130a2_dapm_widgets[] = { SND_SOC_DAPM_PGA_E("TPA6130A2 Left", SND_SOC_NOPM, - 0, 0, NULL, 0, tpa6130a2_left_event, + TPA6130A2_HP_EN_L, 0, NULL, 0, tpa6130a2_pga_event, SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD), SND_SOC_DAPM_PGA_E("TPA6130A2 Right", SND_SOC_NOPM, - 0, 0, NULL, 0, tpa6130a2_right_event, + TPA6130A2_HP_EN_R, 0, NULL, 0, tpa6130a2_pga_event, SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD), SND_SOC_DAPM_SUPPLY("TPA6130A2 Enable", SND_SOC_NOPM, 0, 0, tpa6130a2_supply_event, -- cgit v1.2.2 From 1bb5ec6a6a0e094c84cc4fa2ba4a6d7cf8e9e8c6 Mon Sep 17 00:00:00 2001 From: Peter Ujfalusi Date: Tue, 30 Nov 2010 16:00:03 +0200 Subject: ASoC: tpa6130a2: Add stereo DAPM path New DAPM widgets, and paths to enable both channels at the same time (for stereo output). With this path the switch time difference can be avoided between left and right channels. The original DAPM paths can be still used, if only one of TPA's output has been connected to a speaker, but for most of the cases, switching to the stereo path is better. Signed-off-by: Peter Ujfalusi Acked-by: Mark Brown Signed-off-by: Liam Girdwood --- sound/soc/codecs/tpa6130a2.c | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'sound/soc/codecs') diff --git a/sound/soc/codecs/tpa6130a2.c b/sound/soc/codecs/tpa6130a2.c index 4c77a82d9780..c97badfac540 100644 --- a/sound/soc/codecs/tpa6130a2.c +++ b/sound/soc/codecs/tpa6130a2.c @@ -354,20 +354,27 @@ static const struct snd_soc_dapm_widget tpa6130a2_dapm_widgets[] = { SND_SOC_DAPM_PGA_E("TPA6130A2 Right", SND_SOC_NOPM, TPA6130A2_HP_EN_R, 0, NULL, 0, tpa6130a2_pga_event, SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD), + SND_SOC_DAPM_PGA_E("TPA6130A2 Stereo", SND_SOC_NOPM, + TPA6130A2_HP_EN_L | TPA6130A2_HP_EN_R, 0, NULL, 0, + tpa6130a2_pga_event, + SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD), SND_SOC_DAPM_SUPPLY("TPA6130A2 Enable", SND_SOC_NOPM, 0, 0, tpa6130a2_supply_event, SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD), /* Outputs */ SND_SOC_DAPM_OUTPUT("TPA6130A2 Headphone Left"), SND_SOC_DAPM_OUTPUT("TPA6130A2 Headphone Right"), + SND_SOC_DAPM_OUTPUT("TPA6130A2 Headphone Stereo"), }; static const struct snd_soc_dapm_route audio_map[] = { {"TPA6130A2 Headphone Left", NULL, "TPA6130A2 Left"}, {"TPA6130A2 Headphone Right", NULL, "TPA6130A2 Right"}, + {"TPA6130A2 Headphone Stereo", NULL, "TPA6130A2 Stereo"}, {"TPA6130A2 Headphone Left", NULL, "TPA6130A2 Enable"}, {"TPA6130A2 Headphone Right", NULL, "TPA6130A2 Enable"}, + {"TPA6130A2 Headphone Stereo", NULL, "TPA6130A2 Enable"}, }; int tpa6130a2_add_controls(struct snd_soc_codec *codec) -- cgit v1.2.2 From b2822a8c22d13bc8c441e1c0492baa40ae974b51 Mon Sep 17 00:00:00 2001 From: Mark Brown Date: Tue, 30 Nov 2010 16:59:29 +0000 Subject: ASoC: Correct event flags for WM8958 AIF DACs We need a post notification as we need to shut down the MBC after the data stops flowing rather than before. Signed-off-by: Mark Brown Acked-by: Liam Girdwood --- sound/soc/codecs/wm8994.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'sound/soc/codecs') diff --git a/sound/soc/codecs/wm8994.c b/sound/soc/codecs/wm8994.c index bfd4cf4fde5f..51f5cf16b425 100644 --- a/sound/soc/codecs/wm8994.c +++ b/sound/soc/codecs/wm8994.c @@ -1205,10 +1205,10 @@ SND_SOC_DAPM_AIF_OUT("AIF1ADC1R", "AIF1 Capture", 0, WM8994_POWER_MANAGEMENT_4, 8, 0), SND_SOC_DAPM_AIF_IN_E("AIF1DAC1L", NULL, 0, WM8994_POWER_MANAGEMENT_5, 9, 0, wm8958_aif_ev, - SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), + SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), SND_SOC_DAPM_AIF_IN_E("AIF1DAC1R", NULL, 0, WM8994_POWER_MANAGEMENT_5, 8, 0, wm8958_aif_ev, - SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), + SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), SND_SOC_DAPM_AIF_OUT("AIF1ADC2L", "AIF1 Capture", 0, WM8994_POWER_MANAGEMENT_4, 11, 0), @@ -1216,10 +1216,10 @@ SND_SOC_DAPM_AIF_OUT("AIF1ADC2R", "AIF1 Capture", 0, WM8994_POWER_MANAGEMENT_4, 10, 0), SND_SOC_DAPM_AIF_IN_E("AIF1DAC2L", NULL, 0, WM8994_POWER_MANAGEMENT_5, 11, 0, wm8958_aif_ev, - SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), + SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), SND_SOC_DAPM_AIF_IN_E("AIF1DAC2R", NULL, 0, WM8994_POWER_MANAGEMENT_5, 10, 0, wm8958_aif_ev, - SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), + SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), SND_SOC_DAPM_MIXER("AIF1ADC1L Mixer", SND_SOC_NOPM, 0, 0, aif1adc1l_mix, ARRAY_SIZE(aif1adc1l_mix)), -- cgit v1.2.2 From 131d81061eba5ffd436b5d132530ac5205b16892 Mon Sep 17 00:00:00 2001 From: Mark Brown Date: Tue, 30 Nov 2010 17:03:39 +0000 Subject: ASoC: Allow user-specified WM8958 multiband compressor configurations The paramters of the WM8958 multiband compressor can be tuned by the user for their system using a graphical configuration tool on the host. Allow the user to specify a set of such paramters in platform data and select between them at runtime. Signed-off-by: Mark Brown Acked-by: Liam Girdwood --- sound/soc/codecs/wm8994.c | 84 +++++++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 82 insertions(+), 2 deletions(-) (limited to 'sound/soc/codecs') diff --git a/sound/soc/codecs/wm8994.c b/sound/soc/codecs/wm8994.c index 51f5cf16b425..59d361145b15 100644 --- a/sound/soc/codecs/wm8994.c +++ b/sound/soc/codecs/wm8994.c @@ -92,6 +92,11 @@ struct wm8994_priv { int retune_mobile_cfg[WM8994_NUM_EQ]; struct soc_enum retune_mobile_enum; + /* Platform dependant MBC configuration */ + int mbc_cfg; + const char **mbc_texts; + struct soc_enum mbc_enum; + struct wm8994_micdet micdet[2]; wm8958_micdet_cb jack_cb; @@ -543,8 +548,9 @@ static const struct soc_enum aif2dacr_src = static void wm8958_mbc_apply(struct snd_soc_codec *codec, int mbc, int start) { struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); + struct wm8994_pdata *pdata = wm8994->pdata; int pwr_reg = snd_soc_read(codec, WM8994_POWER_MANAGEMENT_5); - int ena, reg, aif; + int ena, reg, aif, i; switch (mbc) { case 0: @@ -587,7 +593,20 @@ static void wm8958_mbc_apply(struct snd_soc_codec *codec, int mbc, int start) snd_soc_update_bits(codec, WM8958_DSP2_PROGRAM, WM8958_DSP2_ENA, WM8958_DSP2_ENA); - /* TODO: Apply any user specified MBC settings */ + /* If we've got user supplied MBC settings use them */ + if (pdata && pdata->num_mbc_cfgs) { + struct wm8958_mbc_cfg *cfg + = &pdata->mbc_cfgs[wm8994->mbc_cfg]; + + for (i = 0; i < ARRAY_SIZE(cfg->coeff_regs); i++) + snd_soc_write(codec, i + WM8958_MBC_BAND_1_K_1, + cfg->coeff_regs[i]); + + for (i = 0; i < ARRAY_SIZE(cfg->cutoff_regs); i++) + snd_soc_write(codec, + i + WM8958_MBC_BAND_2_LOWER_CUTOFF_C1_1, + cfg->cutoff_regs[i]); + } /* Run the DSP */ snd_soc_write(codec, WM8958_DSP2_EXECCONTROL, @@ -648,6 +667,39 @@ static int wm8958_aif_ev(struct snd_soc_dapm_widget *w, return 0; } +static int wm8958_put_mbc_enum(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); + struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); + struct wm8994_pdata *pdata = wm8994->pdata; + int value = ucontrol->value.integer.value[0]; + int reg; + + /* Don't allow on the fly reconfiguration */ + reg = snd_soc_read(codec, WM8994_CLOCKING_1); + if (reg < 0 || reg & WM8958_DSP2CLK_ENA) + return -EBUSY; + + if (value >= pdata->num_mbc_cfgs) + return -EINVAL; + + wm8994->mbc_cfg = value; + + return 0; +} + +static int wm8958_get_mbc_enum(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); + struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); + + ucontrol->value.enumerated.item[0] = wm8994->mbc_cfg; + + return 0; +} + static int wm8958_mbc_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) { @@ -2539,6 +2591,34 @@ static void wm8994_handle_pdata(struct wm8994_priv *wm8994) dev_dbg(codec->dev, "%d ReTune Mobile configurations\n", pdata->num_retune_mobile_cfgs); + if (pdata->num_mbc_cfgs) { + struct snd_kcontrol_new control[] = { + SOC_ENUM_EXT("MBC Mode", wm8994->mbc_enum, + wm8958_get_mbc_enum, wm8958_put_mbc_enum), + }; + + /* We need an array of texts for the enum API */ + wm8994->mbc_texts = kmalloc(sizeof(char *) + * pdata->num_mbc_cfgs, GFP_KERNEL); + if (!wm8994->mbc_texts) { + dev_err(wm8994->codec->dev, + "Failed to allocate %d MBC config texts\n", + pdata->num_mbc_cfgs); + return; + } + + for (i = 0; i < pdata->num_mbc_cfgs; i++) + wm8994->mbc_texts[i] = pdata->mbc_cfgs[i].name; + + wm8994->mbc_enum.max = pdata->num_mbc_cfgs; + wm8994->mbc_enum.texts = wm8994->mbc_texts; + + ret = snd_soc_add_controls(wm8994->codec, control, 1); + if (ret != 0) + dev_err(wm8994->codec->dev, + "Failed to add MBC mode controls: %d\n", ret); + } + if (pdata->num_retune_mobile_cfgs) wm8994_handle_retune_mobile_pdata(wm8994); else -- cgit v1.2.2 From cca67a3668392857641e9440ca6dc16a48b12e37 Mon Sep 17 00:00:00 2001 From: Axel Lin Date: Wed, 1 Dec 2010 17:22:34 +0800 Subject: ASoC: ak4535: Improve readability for setting mute The mute/unmute is controled by SMUTE (Soft Mute Control bit): 0: Normal Operation (Default) 1: DAC outputs soft-muted I think this change improves readability. Signed-off-by: Axel Lin Acked-by: Liam Girdwood Signed-off-by: Mark Brown --- sound/soc/codecs/ak4535.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) (limited to 'sound/soc/codecs') diff --git a/sound/soc/codecs/ak4535.c b/sound/soc/codecs/ak4535.c index 73675458076d..8b38739c88f8 100644 --- a/sound/soc/codecs/ak4535.c +++ b/sound/soc/codecs/ak4535.c @@ -366,9 +366,9 @@ static int ak4535_set_dai_fmt(struct snd_soc_dai *codec_dai, static int ak4535_mute(struct snd_soc_dai *dai, int mute) { struct snd_soc_codec *codec = dai->codec; - u16 mute_reg = ak4535_read_reg_cache(codec, AK4535_DAC) & 0xffdf; + u16 mute_reg = ak4535_read_reg_cache(codec, AK4535_DAC); if (!mute) - ak4535_write(codec, AK4535_DAC, mute_reg); + ak4535_write(codec, AK4535_DAC, mute_reg & ~0x20); else ak4535_write(codec, AK4535_DAC, mute_reg | 0x20); return 0; @@ -381,11 +381,11 @@ static int ak4535_set_bias_level(struct snd_soc_codec *codec, switch (level) { case SND_SOC_BIAS_ON: - mute_reg = ak4535_read_reg_cache(codec, AK4535_DAC) & 0xffdf; - ak4535_write(codec, AK4535_DAC, mute_reg); + mute_reg = ak4535_read_reg_cache(codec, AK4535_DAC); + ak4535_write(codec, AK4535_DAC, mute_reg & ~0x20); break; case SND_SOC_BIAS_PREPARE: - mute_reg = ak4535_read_reg_cache(codec, AK4535_DAC) & 0xffdf; + mute_reg = ak4535_read_reg_cache(codec, AK4535_DAC); ak4535_write(codec, AK4535_DAC, mute_reg | 0x20); break; case SND_SOC_BIAS_STANDBY: -- cgit v1.2.2 From 39646871a47fd8808c08de0ce7d7ca8393af2805 Mon Sep 17 00:00:00 2001 From: Peter Ujfalusi Date: Thu, 2 Dec 2010 09:29:56 +0200 Subject: ASoC: tpa6130a2: Replace DAPM code with direct interface The use of DAPM widgets, and extra routing can cause ordering problems in the system. Machine drivers should use the exported direct interface with SND_SOC_DAPM_HP's event callback to manage the state of the amplifier. Signed-off-by: Peter Ujfalusi Acked-by: Mark Brown Signed-off-by: Liam Girdwood --- sound/soc/codecs/tpa6130a2.c | 69 +++++++------------------------------------- sound/soc/codecs/tpa6130a2.h | 1 + 2 files changed, 12 insertions(+), 58 deletions(-) (limited to 'sound/soc/codecs') diff --git a/sound/soc/codecs/tpa6130a2.c b/sound/soc/codecs/tpa6130a2.c index c97badfac540..0a99f313e218 100644 --- a/sound/soc/codecs/tpa6130a2.c +++ b/sound/soc/codecs/tpa6130a2.c @@ -317,65 +317,24 @@ static void tpa6130a2_channel_enable(u8 channel, int enable) } } -static int tpa6130a2_pga_event(struct snd_soc_dapm_widget *w, - struct snd_kcontrol *kcontrol, int event) -{ - switch (event) { - case SND_SOC_DAPM_POST_PMU: - tpa6130a2_channel_enable(w->shift, 1); - break; - case SND_SOC_DAPM_POST_PMD: - tpa6130a2_channel_enable(w->shift, 0); - break; - } - return 0; -} - -static int tpa6130a2_supply_event(struct snd_soc_dapm_widget *w, - struct snd_kcontrol *kcontrol, int event) +int tpa6130a2_stereo_enable(struct snd_soc_codec *codec, int enable) { int ret = 0; - - switch (event) { - case SND_SOC_DAPM_POST_PMU: + if (enable) { ret = tpa6130a2_power(1); - break; - case SND_SOC_DAPM_POST_PMD: + if (ret < 0) + return ret; + tpa6130a2_channel_enable(TPA6130A2_HP_EN_R | TPA6130A2_HP_EN_L, + 1); + } else { + tpa6130a2_channel_enable(TPA6130A2_HP_EN_R | TPA6130A2_HP_EN_L, + 0); ret = tpa6130a2_power(0); - break; } + return ret; } - -static const struct snd_soc_dapm_widget tpa6130a2_dapm_widgets[] = { - SND_SOC_DAPM_PGA_E("TPA6130A2 Left", SND_SOC_NOPM, - TPA6130A2_HP_EN_L, 0, NULL, 0, tpa6130a2_pga_event, - SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD), - SND_SOC_DAPM_PGA_E("TPA6130A2 Right", SND_SOC_NOPM, - TPA6130A2_HP_EN_R, 0, NULL, 0, tpa6130a2_pga_event, - SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD), - SND_SOC_DAPM_PGA_E("TPA6130A2 Stereo", SND_SOC_NOPM, - TPA6130A2_HP_EN_L | TPA6130A2_HP_EN_R, 0, NULL, 0, - tpa6130a2_pga_event, - SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD), - SND_SOC_DAPM_SUPPLY("TPA6130A2 Enable", SND_SOC_NOPM, - 0, 0, tpa6130a2_supply_event, - SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD), - /* Outputs */ - SND_SOC_DAPM_OUTPUT("TPA6130A2 Headphone Left"), - SND_SOC_DAPM_OUTPUT("TPA6130A2 Headphone Right"), - SND_SOC_DAPM_OUTPUT("TPA6130A2 Headphone Stereo"), -}; - -static const struct snd_soc_dapm_route audio_map[] = { - {"TPA6130A2 Headphone Left", NULL, "TPA6130A2 Left"}, - {"TPA6130A2 Headphone Right", NULL, "TPA6130A2 Right"}, - {"TPA6130A2 Headphone Stereo", NULL, "TPA6130A2 Stereo"}, - - {"TPA6130A2 Headphone Left", NULL, "TPA6130A2 Enable"}, - {"TPA6130A2 Headphone Right", NULL, "TPA6130A2 Enable"}, - {"TPA6130A2 Headphone Stereo", NULL, "TPA6130A2 Enable"}, -}; +EXPORT_SYMBOL_GPL(tpa6130a2_stereo_enable); int tpa6130a2_add_controls(struct snd_soc_codec *codec) { @@ -387,18 +346,12 @@ int tpa6130a2_add_controls(struct snd_soc_codec *codec) data = i2c_get_clientdata(tpa6130a2_client); - snd_soc_dapm_new_controls(dapm, tpa6130a2_dapm_widgets, - ARRAY_SIZE(tpa6130a2_dapm_widgets)); - - snd_soc_dapm_add_routes(dapm, audio_map, ARRAY_SIZE(audio_map)); - if (data->id == TPA6140A2) return snd_soc_add_controls(codec, tpa6140a2_controls, ARRAY_SIZE(tpa6140a2_controls)); else return snd_soc_add_controls(codec, tpa6130a2_controls, ARRAY_SIZE(tpa6130a2_controls)); - } EXPORT_SYMBOL_GPL(tpa6130a2_add_controls); diff --git a/sound/soc/codecs/tpa6130a2.h b/sound/soc/codecs/tpa6130a2.h index 57e867fd86d1..5df49c8756b2 100644 --- a/sound/soc/codecs/tpa6130a2.h +++ b/sound/soc/codecs/tpa6130a2.h @@ -57,5 +57,6 @@ #define TPA6130A2_VERSION_MASK (0x0f) extern int tpa6130a2_add_controls(struct snd_soc_codec *codec); +extern int tpa6130a2_stereo_enable(struct snd_soc_codec *codec, int enable); #endif /* __TPA6130A2_H__ */ -- cgit v1.2.2 From fbe609e41b48f2e7da7c053ca835ba1277d3bed2 Mon Sep 17 00:00:00 2001 From: Axel Lin Date: Wed, 1 Dec 2010 14:38:24 +0800 Subject: ASoC: Remove unused aic3x_i2c_init and aic3x_i2c_exit functions Signed-off-by: Axel Lin Acked-by: Mark Brown Acked-by: Jarkko Nikula Signed-off-by: Liam Girdwood --- sound/soc/codecs/tlv320aic3x.c | 15 --------------- 1 file changed, 15 deletions(-) (limited to 'sound/soc/codecs') diff --git a/sound/soc/codecs/tlv320aic3x.c b/sound/soc/codecs/tlv320aic3x.c index fc5abdf0bcb0..8cd4cf5c44dc 100644 --- a/sound/soc/codecs/tlv320aic3x.c +++ b/sound/soc/codecs/tlv320aic3x.c @@ -1545,21 +1545,6 @@ static struct i2c_driver aic3x_i2c_driver = { .remove = aic3x_i2c_remove, .id_table = aic3x_i2c_id, }; - -static inline void aic3x_i2c_init(void) -{ - int ret; - - ret = i2c_add_driver(&aic3x_i2c_driver); - if (ret) - printk(KERN_ERR "%s: error regsitering i2c driver, %d\n", - __func__, ret); -} - -static inline void aic3x_i2c_exit(void) -{ - i2c_del_driver(&aic3x_i2c_driver); -} #endif static int __init aic3x_modinit(void) -- cgit v1.2.2 From d921184e82e828e9c0bc3958f838decaaa9191a8 Mon Sep 17 00:00:00 2001 From: Mark Brown Date: Tue, 30 Nov 2010 21:03:09 +0000 Subject: ASoC: Provide WM8731 microphone boost TLV information Signed-off-by: Mark Brown Acked-by: Liam Girdwood --- sound/soc/codecs/wm8731.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'sound/soc/codecs') diff --git a/sound/soc/codecs/wm8731.c b/sound/soc/codecs/wm8731.c index 94e0cf3a66a1..c90e0252972f 100644 --- a/sound/soc/codecs/wm8731.c +++ b/sound/soc/codecs/wm8731.c @@ -74,6 +74,7 @@ static const struct soc_enum wm8731_enum[] = { static const DECLARE_TLV_DB_SCALE(in_tlv, -3450, 150, 0); static const DECLARE_TLV_DB_SCALE(sidetone_tlv, -1500, 300, 0); static const DECLARE_TLV_DB_SCALE(out_tlv, -12100, 100, 1); +static const DECLARE_TLV_DB_SCALE(mic_tlv, 0, 2000, 0); static const struct snd_kcontrol_new wm8731_snd_controls[] = { @@ -86,7 +87,7 @@ SOC_DOUBLE_R_TLV("Capture Volume", WM8731_LINVOL, WM8731_RINVOL, 0, 31, 0, in_tlv), SOC_DOUBLE_R("Line Capture Switch", WM8731_LINVOL, WM8731_RINVOL, 7, 1, 1), -SOC_SINGLE("Mic Boost (+20dB)", WM8731_APANA, 0, 1, 0), +SOC_SINGLE_TLV("Mic Boost Volume", WM8731_APANA, 0, 1, 0, mic_tlv), SOC_SINGLE("Mic Capture Switch", WM8731_APANA, 1, 1, 1), SOC_SINGLE_TLV("Sidetone Playback Volume", WM8731_APANA, 6, 3, 1, -- cgit v1.2.2 From 59f7297014b7e96779493f132eed04a3d44565df Mon Sep 17 00:00:00 2001 From: Mark Brown Date: Tue, 30 Nov 2010 21:03:44 +0000 Subject: ASoC: Split WM8731 enumeration array into individual enums This is much more maintainable than the array. Signed-off-by: Mark Brown Acked-by: Liam Girdwood --- sound/soc/codecs/wm8731.c | 15 +++++++++------ 1 file changed, 9 insertions(+), 6 deletions(-) (limited to 'sound/soc/codecs') diff --git a/sound/soc/codecs/wm8731.c b/sound/soc/codecs/wm8731.c index c90e0252972f..8003761a8e02 100644 --- a/sound/soc/codecs/wm8731.c +++ b/sound/soc/codecs/wm8731.c @@ -64,12 +64,15 @@ static const u16 wm8731_reg[WM8731_CACHEREGNUM] = { #define wm8731_reset(c) snd_soc_write(c, WM8731_RESET, 0) static const char *wm8731_input_select[] = {"Line In", "Mic"}; + static const char *wm8731_deemph[] = {"None", "32Khz", "44.1Khz", "48Khz"}; -static const struct soc_enum wm8731_enum[] = { - SOC_ENUM_SINGLE(WM8731_APANA, 2, 2, wm8731_input_select), - SOC_ENUM_SINGLE(WM8731_APDIGI, 1, 4, wm8731_deemph), -}; +static const struct soc_enum wm8731_insel_enum = + SOC_ENUM_SINGLE(WM8731_APANA, 2, 2, wm8731_input_select); + +static const struct soc_enum wm8731_deemph_enum = + SOC_ENUM_SINGLE(WM8731_APDIGI, 1, 4, wm8731_deemph); + static const DECLARE_TLV_DB_SCALE(in_tlv, -3450, 150, 0); static const DECLARE_TLV_DB_SCALE(sidetone_tlv, -1500, 300, 0); @@ -96,7 +99,7 @@ SOC_SINGLE_TLV("Sidetone Playback Volume", WM8731_APANA, 6, 3, 1, SOC_SINGLE("ADC High Pass Filter Switch", WM8731_APDIGI, 0, 1, 1), SOC_SINGLE("Store DC Offset Switch", WM8731_APDIGI, 4, 1, 0), -SOC_ENUM("Playback De-emphasis", wm8731_enum[1]), +SOC_ENUM("Playback De-emphasis", wm8731_deemph_enum), }; /* Output Mixer */ @@ -108,7 +111,7 @@ SOC_DAPM_SINGLE("HiFi Playback Switch", WM8731_APANA, 4, 1, 0), /* Input mux */ static const struct snd_kcontrol_new wm8731_input_mux_controls = -SOC_DAPM_ENUM("Input Select", wm8731_enum[0]); +SOC_DAPM_ENUM("Input Select", wm8731_insel_enum); static const struct snd_soc_dapm_widget wm8731_dapm_widgets[] = { SND_SOC_DAPM_SUPPLY("OSC", WM8731_PWR, 5, 1, NULL, 0), -- cgit v1.2.2 From dd31b310b9104327fb6bf7d2fe3b0f0f6fde4dd7 Mon Sep 17 00:00:00 2001 From: Mark Brown Date: Thu, 2 Dec 2010 11:44:00 +0000 Subject: ASoC: Automatically manage WM8731 deemphasis The deemphasis filter should be selected based on sample rate for optimal performance. Signed-off-by: Mark Brown Acked-by: Liam Girdwood --- sound/soc/codecs/wm8731.c | 76 +++++++++++++++++++++++++++++++++++++++++++---- 1 file changed, 71 insertions(+), 5 deletions(-) (limited to 'sound/soc/codecs') diff --git a/sound/soc/codecs/wm8731.c b/sound/soc/codecs/wm8731.c index 8003761a8e02..71122dc36826 100644 --- a/sound/soc/codecs/wm8731.c +++ b/sound/soc/codecs/wm8731.c @@ -46,6 +46,8 @@ struct wm8731_priv { u16 reg_cache[WM8731_CACHEREGNUM]; unsigned int sysclk; int sysclk_type; + int playback_fs; + bool deemph; }; @@ -65,14 +67,73 @@ static const u16 wm8731_reg[WM8731_CACHEREGNUM] = { static const char *wm8731_input_select[] = {"Line In", "Mic"}; -static const char *wm8731_deemph[] = {"None", "32Khz", "44.1Khz", "48Khz"}; - static const struct soc_enum wm8731_insel_enum = SOC_ENUM_SINGLE(WM8731_APANA, 2, 2, wm8731_input_select); -static const struct soc_enum wm8731_deemph_enum = - SOC_ENUM_SINGLE(WM8731_APDIGI, 1, 4, wm8731_deemph); +static int wm8731_deemph[] = { 0, 32000, 44100, 48000 }; + +static int wm8731_set_deemph(struct snd_soc_codec *codec) +{ + struct wm8731_priv *wm8731 = snd_soc_codec_get_drvdata(codec); + int val, i, best; + + /* If we're using deemphasis select the nearest available sample + * rate. + */ + if (wm8731->deemph) { + best = 1; + for (i = 2; i < ARRAY_SIZE(wm8731_deemph); i++) { + if (abs(wm8731_deemph[i] - wm8731->playback_fs) < + abs(wm8731_deemph[best] - wm8731->playback_fs)) + best = i; + } + + val = best << 1; + } else { + best = 0; + val = 0; + } + + dev_dbg(codec->dev, "Set deemphasis %d (%dHz)\n", + best, wm8731_deemph[best]); + return snd_soc_update_bits(codec, WM8731_APDIGI, 0x6, val); +} + +static int wm8731_get_deemph(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); + struct wm8731_priv *wm8731 = snd_soc_codec_get_drvdata(codec); + + ucontrol->value.enumerated.item[0] = wm8731->deemph; + + return 0; +} + +static int wm8731_put_deemph(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); + struct wm8731_priv *wm8731 = snd_soc_codec_get_drvdata(codec); + int deemph = ucontrol->value.enumerated.item[0]; + int ret = 0; + + if (deemph > 1) + return -EINVAL; + + mutex_lock(&codec->mutex); + if (wm8731->deemph != deemph) { + wm8731->deemph = deemph; + + wm8731_set_deemph(codec); + + ret = 1; + } + mutex_unlock(&codec->mutex); + + return ret; +} static const DECLARE_TLV_DB_SCALE(in_tlv, -3450, 150, 0); static const DECLARE_TLV_DB_SCALE(sidetone_tlv, -1500, 300, 0); @@ -99,7 +160,8 @@ SOC_SINGLE_TLV("Sidetone Playback Volume", WM8731_APANA, 6, 3, 1, SOC_SINGLE("ADC High Pass Filter Switch", WM8731_APDIGI, 0, 1, 1), SOC_SINGLE("Store DC Offset Switch", WM8731_APDIGI, 4, 1, 0), -SOC_ENUM("Playback De-emphasis", wm8731_deemph_enum), +SOC_SINGLE_BOOL_EXT("Playback Deemphasis Switch", 0, + wm8731_get_deemph, wm8731_put_deemph), }; /* Output Mixer */ @@ -243,6 +305,8 @@ static int wm8731_hw_params(struct snd_pcm_substream *substream, u16 srate = (coeff_div[i].sr << 2) | (coeff_div[i].bosr << 1) | coeff_div[i].usb; + wm8731->playback_fs = params_rate(params); + snd_soc_write(codec, WM8731_SRATE, srate); /* bit size */ @@ -257,6 +321,8 @@ static int wm8731_hw_params(struct snd_pcm_substream *substream, break; } + wm8731_set_deemph(codec); + snd_soc_write(codec, WM8731_IFACE, iface); return 0; } -- cgit v1.2.2 From 8bc3c2c207dc82d47ffc6ef7b788e04ea637d3f1 Mon Sep 17 00:00:00 2001 From: Mark Brown Date: Tue, 30 Nov 2010 14:56:18 +0000 Subject: ASoC: Tune performance of WM8958 revision A Update some of the default configuration for the device to improve the performance. Signed-off-by: Mark Brown Acked-by: Liam Girdwood --- sound/soc/codecs/wm8994.c | 36 +++++++++++++++++++++++++++--------- 1 file changed, 27 insertions(+), 9 deletions(-) (limited to 'sound/soc/codecs') diff --git a/sound/soc/codecs/wm8994.c b/sound/soc/codecs/wm8994.c index 59d361145b15..af3a98ae0579 100644 --- a/sound/soc/codecs/wm8994.c +++ b/sound/soc/codecs/wm8994.c @@ -1858,15 +1858,33 @@ static int wm8994_set_bias_level(struct snd_soc_codec *codec, if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) { pm_runtime_get_sync(codec->dev); - /* Tweak DC servo and DSP configuration for - * improved performance. */ - if (control->type == WM8994 && wm8994->revision < 4) { - /* Tweak DC servo and DSP configuration for - * improved performance. */ - snd_soc_write(codec, 0x102, 0x3); - snd_soc_write(codec, 0x56, 0x3); - snd_soc_write(codec, 0x817, 0); - snd_soc_write(codec, 0x102, 0); + switch (control->type) { + case WM8994: + if (wm8994->revision < 4) { + /* Tweak DC servo and DSP + * configuration for improved + * performance. */ + snd_soc_write(codec, 0x102, 0x3); + snd_soc_write(codec, 0x56, 0x3); + snd_soc_write(codec, 0x817, 0); + snd_soc_write(codec, 0x102, 0); + } + break; + + case WM8958: + if (wm8994->revision == 0) { + /* Optimise performance for rev A */ + snd_soc_write(codec, 0x102, 0x3); + snd_soc_write(codec, 0xcb, 0x81); + snd_soc_write(codec, 0x817, 0); + snd_soc_write(codec, 0x102, 0); + + snd_soc_update_bits(codec, + WM8958_CHARGE_PUMP_2, + WM8958_CP_DISCH, + WM8958_CP_DISCH); + } + break; } /* Discharge LINEOUT1 & 2 */ -- cgit v1.2.2 From 4bd3a1f415affa4729856dca7e39c5093a9a954f Mon Sep 17 00:00:00 2001 From: Axel Lin Date: Fri, 3 Dec 2010 17:25:57 +0800 Subject: ASoC: Fix inconsistent meaning of default case while checking alc5623->id In alc5623_i2c_probe(), the default case for checking alc5623->id behaves the same as case 0x23. However, In alc5623_probe() the default case for checking alc5623->id becomes to be the same as case 0x21. This makes the meaning of default case inconsistent. Since we have checked codec id in alc5623_i2c_probe() by comparing vid2 with id->driver_data, it is not possible to run into the default case now. In case we may add more supported devices to alc5623_i2c_table in the future, this patch changes the default case return -EINVAL to let people know that they should not run into this case. They should also add a new case accordingly for the new id. Signed-off-by: Axel Lin Acked-by: Arnaud Patard Acked-by: Liam Girdwood Signed-off-by: Mark Brown --- sound/soc/codecs/alc5623.c | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) (limited to 'sound/soc/codecs') diff --git a/sound/soc/codecs/alc5623.c b/sound/soc/codecs/alc5623.c index 9783e7e2eb93..4f377c9e868d 100644 --- a/sound/soc/codecs/alc5623.c +++ b/sound/soc/codecs/alc5623.c @@ -925,7 +925,6 @@ static int alc5623_probe(struct snd_soc_codec *codec) } switch (alc5623->id) { - default: case 0x21: snd_soc_add_controls(codec, rt5621_vol_snd_controls, ARRAY_SIZE(rt5621_vol_snd_controls)); @@ -938,6 +937,8 @@ static int alc5623_probe(struct snd_soc_codec *codec) snd_soc_add_controls(codec, alc5623_vol_snd_controls, ARRAY_SIZE(alc5623_vol_snd_controls)); break; + default: + return -EINVAL; } snd_soc_add_controls(codec, alc5623_snd_controls, @@ -950,7 +951,6 @@ static int alc5623_probe(struct snd_soc_codec *codec) snd_soc_dapm_add_routes(dapm, intercon, ARRAY_SIZE(intercon)); switch (alc5623->id) { - default: case 0x21: case 0x22: snd_soc_dapm_new_controls(dapm, alc5623_dapm_amp_widgets, @@ -962,6 +962,8 @@ static int alc5623_probe(struct snd_soc_codec *codec) snd_soc_dapm_add_routes(dapm, intercon_spk, ARRAY_SIZE(intercon_spk)); break; + default: + return -EINVAL; } return ret; @@ -1039,10 +1041,12 @@ static int alc5623_i2c_probe(struct i2c_client *client, case 0x22: alc5623_dai.name = "alc5622-hifi"; break; - default: case 0x23: alc5623_dai.name = "alc5623-hifi"; break; + default: + kfree(alc5623); + return -EINVAL; } i2c_set_clientdata(client, alc5623); -- cgit v1.2.2 From 062869382bb2821bb8482db1e67850dfd11296fb Mon Sep 17 00:00:00 2001 From: Jassi Brar Date: Fri, 3 Dec 2010 10:34:25 +0900 Subject: ASoC: WM8580: Debug interface index We want the index of DAI's driver here. Signed-off-by: Jassi Brar Acked-by: Liam Girdwood Signed-off-by: Mark Brown --- sound/soc/codecs/wm8580.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'sound/soc/codecs') diff --git a/sound/soc/codecs/wm8580.c b/sound/soc/codecs/wm8580.c index e2a927684b48..cb7765f7687d 100644 --- a/sound/soc/codecs/wm8580.c +++ b/sound/soc/codecs/wm8580.c @@ -507,13 +507,13 @@ static int wm8580_paif_hw_params(struct snd_pcm_substream *substream, } /* Look up the SYSCLK ratio; accept only exact matches */ - ratio = wm8580->sysclk[dai->id] / params_rate(params); + ratio = wm8580->sysclk[dai->driver->id] / params_rate(params); for (i = 0; i < ARRAY_SIZE(wm8580_sysclk_ratios); i++) if (ratio == wm8580_sysclk_ratios[i]) break; if (i == ARRAY_SIZE(wm8580_sysclk_ratios)) { dev_err(codec->dev, "Invalid clock ratio %d/%d\n", - wm8580->sysclk[dai->id], params_rate(params)); + wm8580->sysclk[dai->driver->id], params_rate(params)); return -EINVAL; } paifa |= i; @@ -716,7 +716,7 @@ static int wm8580_set_sysclk(struct snd_soc_dai *dai, int clk_id, switch (clk_id) { case WM8580_CLKSRC_ADCMCLK: - if (dai->id != WM8580_DAI_PAIFTX) + if (dai->driver->id != WM8580_DAI_PAIFTX) return -EINVAL; sel = 0 << sel_shift; break; @@ -735,7 +735,7 @@ static int wm8580_set_sysclk(struct snd_soc_dai *dai, int clk_id, } /* We really should validate PLL settings but not yet */ - wm8580->sysclk[dai->id] = freq; + wm8580->sysclk[dai->driver->id] = freq; return snd_soc_update_bits(codec, WM8580_CLKSEL, sel_mask, sel); } -- cgit v1.2.2 From 4514e8997fbefd5befd6176ac9785e287b4daed4 Mon Sep 17 00:00:00 2001 From: Mark Brown Date: Fri, 3 Dec 2010 16:02:10 +0000 Subject: ASoC: When disabling WM8994 FLL force a source selection When we disable the WM8994 FLL code path sharing means that we end up writing out a configuration. Currently this is the currently active input and output frequency (which causes snd_soc_update_bits() to suppress actual writes both immediately and in the common case where we reenable the same configuration later) but we allow machine drivers to pass through a source of zero. Since the register values written are one less than the source constants this causes corruption of other bitfields in the register. Fix this by using the most recently configured FLL source when none is provided. Signed-off-by: Mark Brown Acked-by: Liam Girdwood Cc: stable@kernel.org --- sound/soc/codecs/wm8994.c | 1 + 1 file changed, 1 insertion(+) (limited to 'sound/soc/codecs') diff --git a/sound/soc/codecs/wm8994.c b/sound/soc/codecs/wm8994.c index af3a98ae0579..b37e95c4e7c7 100644 --- a/sound/soc/codecs/wm8994.c +++ b/sound/soc/codecs/wm8994.c @@ -1677,6 +1677,7 @@ static int _wm8994_set_fll(struct snd_soc_codec *codec, int id, int src, /* Allow no source specification when stopping */ if (freq_out) return -EINVAL; + src = wm8994->fll[id].src; break; case WM8994_FLL_SRC_MCLK1: case WM8994_FLL_SRC_MCLK2: -- cgit v1.2.2 From b1e43d933a3f1183e15d91b1737ecafb7de153eb Mon Sep 17 00:00:00 2001 From: Mark Brown Date: Tue, 7 Dec 2010 17:14:56 +0000 Subject: ASoC: Support WM8994 mono AIF configurations The WM8994 supports mono signals - enable this in the driver. With DSP mode an automatic data channel selector is available, activate this when in mono mode. Signed-off-by: Mark Brown Acked-by: Liam Girdwood --- sound/soc/codecs/wm8994.c | 21 +++++++++++++++------ 1 file changed, 15 insertions(+), 6 deletions(-) (limited to 'sound/soc/codecs') diff --git a/sound/soc/codecs/wm8994.c b/sound/soc/codecs/wm8994.c index b37e95c4e7c7..997fd178563f 100644 --- a/sound/soc/codecs/wm8994.c +++ b/sound/soc/codecs/wm8994.c @@ -2099,10 +2099,12 @@ static int wm8994_hw_params(struct snd_pcm_substream *substream, struct wm8994 *control = codec->control_data; struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); int aif1_reg; + int aif2_reg; int bclk_reg; int lrclk_reg; int rate_reg; int aif1 = 0; + int aif2 = 0; int bclk = 0; int lrclk = 0; int rate_val = 0; @@ -2113,6 +2115,7 @@ static int wm8994_hw_params(struct snd_pcm_substream *substream, switch (dai->id) { case 1: aif1_reg = WM8994_AIF1_CONTROL_1; + aif2_reg = WM8994_AIF1_CONTROL_2; bclk_reg = WM8994_AIF1_BCLK; rate_reg = WM8994_AIF1_RATE; if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK || @@ -2125,6 +2128,7 @@ static int wm8994_hw_params(struct snd_pcm_substream *substream, break; case 2: aif1_reg = WM8994_AIF2_CONTROL_1; + aif2_reg = WM8994_AIF2_CONTROL_2; bclk_reg = WM8994_AIF2_BCLK; rate_reg = WM8994_AIF2_RATE; if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK || @@ -2180,6 +2184,10 @@ static int wm8994_hw_params(struct snd_pcm_substream *substream, dev_dbg(dai->dev, "AIF%dCLK is %dHz, target BCLK %dHz\n", dai->id, wm8994->aifclk[id], bclk_rate); + if (params_channels(params) == 1 && + (snd_soc_read(codec, aif1_reg) & 0x18) == 0x18) + aif2 |= WM8994_AIF1_MONO; + if (wm8994->aifclk[id] == 0) { dev_err(dai->dev, "AIF%dCLK not configured\n", dai->id); return -EINVAL; @@ -2223,6 +2231,7 @@ static int wm8994_hw_params(struct snd_pcm_substream *substream, lrclk, bclk_rate / lrclk); snd_soc_update_bits(codec, aif1_reg, WM8994_AIF1_WL_MASK, aif1); + snd_soc_update_bits(codec, aif2_reg, WM8994_AIF1_MONO, aif2); snd_soc_update_bits(codec, bclk_reg, WM8994_AIF1_BCLK_DIV_MASK, bclk); snd_soc_update_bits(codec, lrclk_reg, WM8994_AIF1DAC_RATE_MASK, lrclk); @@ -2378,14 +2387,14 @@ static struct snd_soc_dai_driver wm8994_dai[] = { .id = 1, .playback = { .stream_name = "AIF1 Playback", - .channels_min = 2, + .channels_min = 1, .channels_max = 2, .rates = WM8994_RATES, .formats = WM8994_FORMATS, }, .capture = { .stream_name = "AIF1 Capture", - .channels_min = 2, + .channels_min = 1, .channels_max = 2, .rates = WM8994_RATES, .formats = WM8994_FORMATS, @@ -2397,14 +2406,14 @@ static struct snd_soc_dai_driver wm8994_dai[] = { .id = 2, .playback = { .stream_name = "AIF2 Playback", - .channels_min = 2, + .channels_min = 1, .channels_max = 2, .rates = WM8994_RATES, .formats = WM8994_FORMATS, }, .capture = { .stream_name = "AIF2 Capture", - .channels_min = 2, + .channels_min = 1, .channels_max = 2, .rates = WM8994_RATES, .formats = WM8994_FORMATS, @@ -2416,14 +2425,14 @@ static struct snd_soc_dai_driver wm8994_dai[] = { .id = 3, .playback = { .stream_name = "AIF3 Playback", - .channels_min = 2, + .channels_min = 1, .channels_max = 2, .rates = WM8994_RATES, .formats = WM8994_FORMATS, }, .capture = { .stream_name = "AIF3 Capture", - .channels_min = 2, + .channels_min = 1, .channels_max = 2, .rates = WM8994_RATES, .formats = WM8994_FORMATS, -- cgit v1.2.2 From 146fd574ec06b1c593805738b1c2c8c5a4128681 Mon Sep 17 00:00:00 2001 From: Uk Kim Date: Tue, 7 Dec 2010 13:58:40 +0000 Subject: ASoC: Add ADC high pass filter support to WM8994 Signed-off-by: Uk Kim Acked-by: Liam Girdwood Signed-off-by: Mark Brown --- sound/soc/codecs/wm8994.c | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) (limited to 'sound/soc/codecs') diff --git a/sound/soc/codecs/wm8994.c b/sound/soc/codecs/wm8994.c index 997fd178563f..da48802340fc 100644 --- a/sound/soc/codecs/wm8994.c +++ b/sound/soc/codecs/wm8994.c @@ -310,6 +310,19 @@ static const char *sidetone_hpf_text[] = { static const struct soc_enum sidetone_hpf = SOC_ENUM_SINGLE(WM8994_SIDETONE, 7, 7, sidetone_hpf_text); +static const char *adc_hpf_text[] = { + "HiFi", "Voice 1", "Voice 2", "Voice 3" +}; + +static const struct soc_enum aif1adc1_hpf = + SOC_ENUM_SINGLE(WM8994_AIF1_ADC1_FILTERS, 13, 4, adc_hpf_text); + +static const struct soc_enum aif1adc2_hpf = + SOC_ENUM_SINGLE(WM8994_AIF1_ADC2_FILTERS, 13, 4, adc_hpf_text); + +static const struct soc_enum aif2adc_hpf = + SOC_ENUM_SINGLE(WM8994_AIF2_ADC_FILTERS, 13, 4, adc_hpf_text); + static const DECLARE_TLV_DB_SCALE(aif_tlv, 0, 600, 0); static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1); static const DECLARE_TLV_DB_SCALE(st_tlv, -3600, 300, 0); @@ -812,6 +825,15 @@ SOC_SINGLE_TLV("DAC2 Left Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES, SOC_ENUM("Sidetone HPF Mux", sidetone_hpf), SOC_SINGLE("Sidetone HPF Switch", WM8994_SIDETONE, 6, 1, 0), +SOC_ENUM("AIF1ADC1 HPF Mode", aif1adc1_hpf), +SOC_DOUBLE("AIF1ADC1 HPF Switch", WM8994_AIF1_ADC1_FILTERS, 12, 11, 1, 0), + +SOC_ENUM("AIF1ADC2 HPF Mode", aif1adc2_hpf), +SOC_DOUBLE("AIF1ADC2 HPF Switch", WM8994_AIF1_ADC2_FILTERS, 12, 11, 1, 0), + +SOC_ENUM("AIF2ADC HPF Mode", aif2adc_hpf), +SOC_DOUBLE("AIF2ADC HPF Switch", WM8994_AIF2_ADC_FILTERS, 12, 11, 1, 0), + SOC_DOUBLE_R_TLV("DAC1 Volume", WM8994_DAC1_LEFT_VOLUME, WM8994_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv), SOC_DOUBLE_R("DAC1 Switch", WM8994_DAC1_LEFT_VOLUME, -- cgit v1.2.2 From 9e87186fff939924da58b8f562ec275757e29776 Mon Sep 17 00:00:00 2001 From: Peter Ujfalusi Date: Wed, 8 Dec 2010 16:04:32 +0200 Subject: ASoC: tlv320dac33: Rename outpup amplifier widget Use better name for the widget, and remove the 'Power' from it's name. Signed-off-by: Peter Ujfalusi Acked-by: Mark Brown Signed-off-by: Liam Girdwood --- sound/soc/codecs/tlv320dac33.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) (limited to 'sound/soc/codecs') diff --git a/sound/soc/codecs/tlv320dac33.c b/sound/soc/codecs/tlv320dac33.c index a0ba5d1be1b3..e2e873ee47de 100644 --- a/sound/soc/codecs/tlv320dac33.c +++ b/sound/soc/codecs/tlv320dac33.c @@ -599,9 +599,9 @@ static const struct snd_soc_dapm_widget dac33_dapm_widgets[] = { SND_SOC_DAPM_SWITCH("Analog Right Bypass", SND_SOC_NOPM, 0, 0, &dac33_dapm_abypassr_control), - SND_SOC_DAPM_REG(snd_soc_dapm_mixer, "Output Left Amp Power", + SND_SOC_DAPM_REG(snd_soc_dapm_mixer, "Output Left Amplifier", DAC33_OUT_AMP_PWR_CTRL, 6, 3, 3, 0), - SND_SOC_DAPM_REG(snd_soc_dapm_mixer, "Output Right Amp Power", + SND_SOC_DAPM_REG(snd_soc_dapm_mixer, "Output Right Amplifier", DAC33_OUT_AMP_PWR_CTRL, 4, 3, 3, 0), SND_SOC_DAPM_PRE("Prepare Playback", playback_event), @@ -612,15 +612,15 @@ static const struct snd_soc_dapm_route audio_map[] = { {"Analog Left Bypass", "Switch", "LINEL"}, {"Analog Right Bypass", "Switch", "LINER"}, - {"Output Left Amp Power", NULL, "DACL"}, - {"Output Right Amp Power", NULL, "DACR"}, + {"Output Left Amplifier", NULL, "DACL"}, + {"Output Right Amplifier", NULL, "DACR"}, - {"Output Left Amp Power", NULL, "Analog Left Bypass"}, - {"Output Right Amp Power", NULL, "Analog Right Bypass"}, + {"Output Left Amplifier", NULL, "Analog Left Bypass"}, + {"Output Right Amplifier", NULL, "Analog Right Bypass"}, /* output */ - {"LEFT_LO", NULL, "Output Left Amp Power"}, - {"RIGHT_LO", NULL, "Output Right Amp Power"}, + {"LEFT_LO", NULL, "Output Left Amplifier"}, + {"RIGHT_LO", NULL, "Output Right Amplifier"}, }; static int dac33_add_widgets(struct snd_soc_codec *codec) -- cgit v1.2.2 From 76eac39ce5f64b95931a6026812e902cb8863a6c Mon Sep 17 00:00:00 2001 From: Peter Ujfalusi Date: Wed, 8 Dec 2010 16:04:33 +0200 Subject: ASoC: tlv320dac33: Move DAC LR power on to a supply widget The power for the DACs need to be enabled, even when only the analog bypass is in use with the codec, otherwise the audio is going to be distorted. Make sure that the DACs are powered all the time, when there is audio activity. Signed-off-by: Peter Ujfalusi Acked-by: Mark Brown Signed-off-by: Liam Girdwood --- sound/soc/codecs/tlv320dac33.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) (limited to 'sound/soc/codecs') diff --git a/sound/soc/codecs/tlv320dac33.c b/sound/soc/codecs/tlv320dac33.c index e2e873ee47de..cee0f9912408 100644 --- a/sound/soc/codecs/tlv320dac33.c +++ b/sound/soc/codecs/tlv320dac33.c @@ -590,8 +590,8 @@ static const struct snd_soc_dapm_widget dac33_dapm_widgets[] = { SND_SOC_DAPM_INPUT("LINEL"), SND_SOC_DAPM_INPUT("LINER"), - SND_SOC_DAPM_DAC("DACL", "Left Playback", DAC33_LDAC_PWR_CTRL, 2, 0), - SND_SOC_DAPM_DAC("DACR", "Right Playback", DAC33_RDAC_PWR_CTRL, 2, 0), + SND_SOC_DAPM_DAC("DACL", "Left Playback", SND_SOC_NOPM, 0, 0), + SND_SOC_DAPM_DAC("DACR", "Right Playback", SND_SOC_NOPM, 0, 0), /* Analog bypass */ SND_SOC_DAPM_SWITCH("Analog Left Bypass", SND_SOC_NOPM, 0, 0, @@ -604,6 +604,11 @@ static const struct snd_soc_dapm_widget dac33_dapm_widgets[] = { SND_SOC_DAPM_REG(snd_soc_dapm_mixer, "Output Right Amplifier", DAC33_OUT_AMP_PWR_CTRL, 4, 3, 3, 0), + SND_SOC_DAPM_SUPPLY("Left DAC Power", + DAC33_LDAC_PWR_CTRL, 2, 0, NULL, 0), + SND_SOC_DAPM_SUPPLY("Right DAC Power", + DAC33_RDAC_PWR_CTRL, 2, 0, NULL, 0), + SND_SOC_DAPM_PRE("Prepare Playback", playback_event), }; @@ -618,6 +623,9 @@ static const struct snd_soc_dapm_route audio_map[] = { {"Output Left Amplifier", NULL, "Analog Left Bypass"}, {"Output Right Amplifier", NULL, "Analog Right Bypass"}, + {"Output Left Amplifier", NULL, "Left DAC Power"}, + {"Output Right Amplifier", NULL, "Right DAC Power"}, + /* output */ {"LEFT_LO", NULL, "Output Left Amplifier"}, {"RIGHT_LO", NULL, "Output Right Amplifier"}, -- cgit v1.2.2 From 3ee4fe15aba7531f75be4dcc331caa8f0c6369ec Mon Sep 17 00:00:00 2001 From: Peter Ujfalusi Date: Wed, 8 Dec 2010 15:12:56 +0200 Subject: ASoC: tlv320dac33: Fix compillation error Fix the compilation error introduced by patch: ASoC: tlv320dac33: Avoid multiple soft power up Signed-off-by: Peter Ujfalusi Acked-by: Mark Brown Signed-off-by: Liam Girdwood --- sound/soc/codecs/tlv320dac33.c | 1 + 1 file changed, 1 insertion(+) (limited to 'sound/soc/codecs') diff --git a/sound/soc/codecs/tlv320dac33.c b/sound/soc/codecs/tlv320dac33.c index cee0f9912408..b3445b362e96 100644 --- a/sound/soc/codecs/tlv320dac33.c +++ b/sound/soc/codecs/tlv320dac33.c @@ -646,6 +646,7 @@ static int dac33_add_widgets(struct snd_soc_codec *codec) static int dac33_set_bias_level(struct snd_soc_codec *codec, enum snd_soc_bias_level level) { + struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec); int ret; switch (level) { -- cgit v1.2.2 From 249c5156b8a743e3df5386c5cb7ae3df1d754e50 Mon Sep 17 00:00:00 2001 From: Mario Becroft Date: Sat, 4 Dec 2010 11:51:34 +1300 Subject: ASoC: Optimise WM9081 FLL performance Tune the FLL gain for optimal performance according to evaluation results. Signed-off-by: Mario Becroft Acked-by: Liam Girdwood Signed-off-by: Mark Brown --- sound/soc/codecs/wm9081.c | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'sound/soc/codecs') diff --git a/sound/soc/codecs/wm9081.c b/sound/soc/codecs/wm9081.c index c7060775e88b..e5055b28c638 100644 --- a/sound/soc/codecs/wm9081.c +++ b/sound/soc/codecs/wm9081.c @@ -590,6 +590,10 @@ static int wm9081_set_fll(struct snd_soc_codec *codec, int fll_id, reg5 |= fll_div.fll_clk_ref_div << WM9081_FLL_CLK_REF_DIV_SHIFT; snd_soc_write(codec, WM9081_FLL_CONTROL_5, reg5); + /* Set gain to the recommended value */ + snd_soc_update_bits(codec, WM9081_FLL_CONTROL_4, + WM9081_FLL_GAIN_MASK, 0); + /* Enable the FLL */ snd_soc_write(codec, WM9081_FLL_CONTROL_1, reg1 | WM9081_FLL_ENA); -- cgit v1.2.2 From 154b26aa9ec4aaeaa7258fe85a036613f3713a59 Mon Sep 17 00:00:00 2001 From: Mark Brown Date: Thu, 9 Dec 2010 12:07:44 +0000 Subject: ASoC: Implement WM8994/58 DAC and ADC oversampling control The oversampling rate of the DAC and ADC can be controlled to optimise for either low power consumption or maximum performance. Signed-off-by: Mark Brown Acked-by: Liam Girdwood --- sound/soc/codecs/wm8994.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) (limited to 'sound/soc/codecs') diff --git a/sound/soc/codecs/wm8994.c b/sound/soc/codecs/wm8994.c index da48802340fc..e59691a7b342 100644 --- a/sound/soc/codecs/wm8994.c +++ b/sound/soc/codecs/wm8994.c @@ -558,6 +558,16 @@ static const struct soc_enum aif2dacl_src = static const struct soc_enum aif2dacr_src = SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_2, 14, 2, aif_chan_src_text); +static const char *osr_text[] = { + "Low Power", "High Performance", +}; + +static const struct soc_enum dac_osr = + SOC_ENUM_SINGLE(WM8994_OVERSAMPLING, 0, 2, osr_text); + +static const struct soc_enum adc_osr = + SOC_ENUM_SINGLE(WM8994_OVERSAMPLING, 1, 2, osr_text); + static void wm8958_mbc_apply(struct snd_soc_codec *codec, int mbc, int start) { struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); @@ -834,6 +844,9 @@ SOC_DOUBLE("AIF1ADC2 HPF Switch", WM8994_AIF1_ADC2_FILTERS, 12, 11, 1, 0), SOC_ENUM("AIF2ADC HPF Mode", aif2adc_hpf), SOC_DOUBLE("AIF2ADC HPF Switch", WM8994_AIF2_ADC_FILTERS, 12, 11, 1, 0), +SOC_ENUM("ADC OSR", adc_osr), +SOC_ENUM("DAC OSR", dac_osr), + SOC_DOUBLE_R_TLV("DAC1 Volume", WM8994_DAC1_LEFT_VOLUME, WM8994_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv), SOC_DOUBLE_R("DAC1 Switch", WM8994_DAC1_LEFT_VOLUME, -- cgit v1.2.2 From a6cea9655bfa821dbf53c6fffb9b2b99fe77367c Mon Sep 17 00:00:00 2001 From: Peter Ujfalusi Date: Fri, 10 Dec 2010 13:26:31 +0200 Subject: ASoC: tlv320dac33: Power down digital parts, when not needed If the following scenario has been followed: 1. Enable analog bypass amixer sset 'Analog Left Bypass' on amixer sset 'Analog Right Bypass' on 2. Start playback aplay -fdat -d3 /dev/zero After the playback stopped (3 sec), and the soc timeout (5 sec), the digital parts of the codec will remain powered up. This means that the DAI clocks are continue to run, the oscillator remain operational, etc. Use the SND_SOC_DAPM_POST_PMD widget to get notification about the stopped stream, and power down the digital part of the codec. If the analog bypass is enabled, than the codec will remain in BIAS_ON level, and things will work correctly. In case, if the bypass is disabled, than the codec will fall to BIAS_STANDBY than to BIAS_OFF level, as it used to. The digital part of DAC33 is initialized at every stream start (DAPM_PRE:PRE_PMU event), so subsequent streams (within 5 sec) will have working DAI. When the codec is coming out from BIAS_OFF, the full power-up sequence followed by the same DAPM_PRE widget event will power up the digital part. Signed-off-by: Peter Ujfalusi Acked-by: Mark Brown Signed-off-by: Liam Girdwood --- sound/soc/codecs/tlv320dac33.c | 23 +++++++++++++++++++++-- 1 file changed, 21 insertions(+), 2 deletions(-) (limited to 'sound/soc/codecs') diff --git a/sound/soc/codecs/tlv320dac33.c b/sound/soc/codecs/tlv320dac33.c index b3445b362e96..776ac80cc1a8 100644 --- a/sound/soc/codecs/tlv320dac33.c +++ b/sound/soc/codecs/tlv320dac33.c @@ -354,6 +354,21 @@ static inline void dac33_soft_power(struct snd_soc_codec *codec, int power) dac33_write(codec, DAC33_PWR_CTRL, reg); } +static inline void dac33_disable_digital(struct snd_soc_codec *codec) +{ + u8 reg; + + /* Stop the DAI clock */ + reg = dac33_read_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_B); + reg &= ~DAC33_BCLKON; + dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_B, reg); + + /* Power down the Oscillator, and DACs */ + reg = dac33_read_reg_cache(codec, DAC33_PWR_CTRL); + reg &= ~(DAC33_OSCPDNB | DAC33_DACRPDNB | DAC33_DACLPDNB); + dac33_write(codec, DAC33_PWR_CTRL, reg); +} + static int dac33_hard_power(struct snd_soc_codec *codec, int power) { struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec); @@ -402,7 +417,7 @@ exit: return ret; } -static int playback_event(struct snd_soc_dapm_widget *w, +static int dac33_playback_event(struct snd_soc_dapm_widget *w, struct snd_kcontrol *kcontrol, int event) { struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(w->codec); @@ -414,6 +429,9 @@ static int playback_event(struct snd_soc_dapm_widget *w, dac33_prepare_chip(dac33->substream); } break; + case SND_SOC_DAPM_POST_PMD: + dac33_disable_digital(w->codec); + break; } return 0; } @@ -609,7 +627,8 @@ static const struct snd_soc_dapm_widget dac33_dapm_widgets[] = { SND_SOC_DAPM_SUPPLY("Right DAC Power", DAC33_RDAC_PWR_CTRL, 2, 0, NULL, 0), - SND_SOC_DAPM_PRE("Prepare Playback", playback_event), + SND_SOC_DAPM_PRE("Pre Playback", dac33_playback_event), + SND_SOC_DAPM_POST("Post Playback", dac33_playback_event), }; static const struct snd_soc_dapm_route audio_map[] = { -- cgit v1.2.2 From 460f4aae8f9c6e414f17bfaaf9b89942ed5984a6 Mon Sep 17 00:00:00 2001 From: Mark Brown Date: Fri, 10 Dec 2010 18:42:58 +0000 Subject: ASoC: Implement WM8903 high pass filter support Signed-off-by: Mark Brown Acked-by: Liam Girdwood --- sound/soc/codecs/wm8903.c | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'sound/soc/codecs') diff --git a/sound/soc/codecs/wm8903.c b/sound/soc/codecs/wm8903.c index 620793e51666..797992c09342 100644 --- a/sound/soc/codecs/wm8903.c +++ b/sound/soc/codecs/wm8903.c @@ -474,6 +474,13 @@ static const DECLARE_TLV_DB_SCALE(drc_tlv_min, 0, 600, 0); static const DECLARE_TLV_DB_SCALE(drc_tlv_max, 1200, 600, 0); static const DECLARE_TLV_DB_SCALE(drc_tlv_startup, -300, 50, 0); +static const char *hpf_mode_text[] = { + "Hi-fi", "Voice 1", "Voice 2", "Voice 3" +}; + +static const struct soc_enum hpf_mode = + SOC_ENUM_SINGLE(WM8903_ADC_DIGITAL_0, 5, 4, hpf_mode_text); + static const char *drc_slope_text[] = { "1", "1/2", "1/4", "1/8", "1/16", "0" }; @@ -612,6 +619,8 @@ SOC_SINGLE("Right Input PGA Common Mode Switch", WM8903_ANALOGUE_RIGHT_INPUT_1, 6, 1, 0), /* ADCs */ +SOC_SINGLE("HPF Switch", WM8903_ADC_DIGITAL_0, 4, 1, 0), +SOC_ENUM("HPF Mode", hpf_mode), SOC_SINGLE("DRC Switch", WM8903_DRC_0, 15, 1, 0), SOC_ENUM("DRC Compressor Slope R0", drc_slope_r0), SOC_ENUM("DRC Compressor Slope R1", drc_slope_r1), -- cgit v1.2.2 From dcf9ada3bce67feab4482845f5e8e78fd278a176 Mon Sep 17 00:00:00 2001 From: Mark Brown Date: Fri, 10 Dec 2010 19:17:06 +0000 Subject: ASoC: Implement WM8903 oversampling rate controls Signed-off-by: Mark Brown Acked-by: Liam Girdwood --- sound/soc/codecs/wm8903.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'sound/soc/codecs') diff --git a/sound/soc/codecs/wm8903.c b/sound/soc/codecs/wm8903.c index 797992c09342..542c7c4868ba 100644 --- a/sound/soc/codecs/wm8903.c +++ b/sound/soc/codecs/wm8903.c @@ -481,6 +481,16 @@ static const char *hpf_mode_text[] = { static const struct soc_enum hpf_mode = SOC_ENUM_SINGLE(WM8903_ADC_DIGITAL_0, 5, 4, hpf_mode_text); +static const char *osr_text[] = { + "Low power", "High performance" +}; + +static const struct soc_enum adc_osr = + SOC_ENUM_SINGLE(WM8903_ANALOGUE_ADC_0, 0, 2, osr_text); + +static const struct soc_enum dac_osr = + SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_1, 0, 2, osr_text); + static const char *drc_slope_text[] = { "1", "1/2", "1/4", "1/8", "1/16", "0" }; @@ -619,6 +629,7 @@ SOC_SINGLE("Right Input PGA Common Mode Switch", WM8903_ANALOGUE_RIGHT_INPUT_1, 6, 1, 0), /* ADCs */ +SOC_ENUM("ADC OSR", adc_osr), SOC_SINGLE("HPF Switch", WM8903_ADC_DIGITAL_0, 4, 1, 0), SOC_ENUM("HPF Mode", hpf_mode), SOC_SINGLE("DRC Switch", WM8903_DRC_0, 15, 1, 0), @@ -650,6 +661,7 @@ SOC_DOUBLE_TLV("Digital Sidetone Volume", WM8903_DAC_DIGITAL_0, 4, 8, 12, 0, digital_sidetone_tlv), /* DAC */ +SOC_ENUM("DAC OSR", dac_osr), SOC_DOUBLE_R_TLV("Digital Playback Volume", WM8903_DAC_DIGITAL_VOLUME_LEFT, WM8903_DAC_DIGITAL_VOLUME_RIGHT, 1, 120, 0, digital_tlv), SOC_ENUM("DAC Soft Mute Rate", soft_mute), -- cgit v1.2.2 From f2c1fe090093ed62271473342f093df53c4f8a59 Mon Sep 17 00:00:00 2001 From: Mark Brown Date: Fri, 10 Dec 2010 19:17:07 +0000 Subject: ASoC: Remove open coded symmetry implementation from WM8903 We're already flagged as using symmetric rates so we don't need to have a custom implementation. Signed-off-by: Mark Brown Acked-by: Liam Girdwood --- sound/soc/codecs/wm8903.c | 79 +---------------------------------------------- 1 file changed, 1 insertion(+), 78 deletions(-) (limited to 'sound/soc/codecs') diff --git a/sound/soc/codecs/wm8903.c b/sound/soc/codecs/wm8903.c index 542c7c4868ba..f9ae403715c6 100644 --- a/sound/soc/codecs/wm8903.c +++ b/sound/soc/codecs/wm8903.c @@ -218,10 +218,8 @@ struct wm8903_priv { int sysclk; int irq; - /* Reference counts */ + /* Reference count */ int class_w_users; - int playback_active; - int capture_active; struct completion wseq; @@ -230,9 +228,6 @@ struct wm8903_priv { int mic_short; int mic_last_report; int mic_delay; - - struct snd_pcm_substream *master_substream; - struct snd_pcm_substream *slave_substream; }; static int wm8903_volatile_register(unsigned int reg) @@ -1243,58 +1238,6 @@ static struct { { 0, 0 }, }; -static int wm8903_startup(struct snd_pcm_substream *substream, - struct snd_soc_dai *dai) -{ - struct snd_soc_pcm_runtime *rtd = substream->private_data; - struct snd_soc_codec *codec = rtd->codec; - struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec); - struct snd_pcm_runtime *master_runtime; - - if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) - wm8903->playback_active++; - else - wm8903->capture_active++; - - /* The DAI has shared clocks so if we already have a playback or - * capture going then constrain this substream to match it. - */ - if (wm8903->master_substream) { - master_runtime = wm8903->master_substream->runtime; - - dev_dbg(codec->dev, "Constraining to %d bits\n", - master_runtime->sample_bits); - - snd_pcm_hw_constraint_minmax(substream->runtime, - SNDRV_PCM_HW_PARAM_SAMPLE_BITS, - master_runtime->sample_bits, - master_runtime->sample_bits); - - wm8903->slave_substream = substream; - } else - wm8903->master_substream = substream; - - return 0; -} - -static void wm8903_shutdown(struct snd_pcm_substream *substream, - struct snd_soc_dai *dai) -{ - struct snd_soc_pcm_runtime *rtd = substream->private_data; - struct snd_soc_codec *codec = rtd->codec; - struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec); - - if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) - wm8903->playback_active--; - else - wm8903->capture_active--; - - if (wm8903->master_substream == substream) - wm8903->master_substream = wm8903->slave_substream; - - wm8903->slave_substream = NULL; -} - static int wm8903_hw_params(struct snd_pcm_substream *substream, struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) @@ -1319,11 +1262,6 @@ static int wm8903_hw_params(struct snd_pcm_substream *substream, u16 clock1 = snd_soc_read(codec, WM8903_CLOCK_RATES_1); u16 dac_digital1 = snd_soc_read(codec, WM8903_DAC_DIGITAL_1); - if (substream == wm8903->slave_substream) { - dev_dbg(codec->dev, "Ignoring hw_params for slave substream\n"); - return 0; - } - /* Enable sloping stopband filter for low sample rates */ if (fs <= 24000) dac_digital1 |= WM8903_DAC_SB_FILT; @@ -1341,19 +1279,6 @@ static int wm8903_hw_params(struct snd_pcm_substream *substream, } } - /* Constraints should stop us hitting this but let's make sure */ - if (wm8903->capture_active) - switch (sample_rates[dsp_config].rate) { - case 88200: - case 96000: - dev_err(codec->dev, "%dHz unsupported by ADC\n", - fs); - return -EINVAL; - - default: - break; - } - dev_dbg(codec->dev, "DSP fs = %dHz\n", sample_rates[dsp_config].rate); clock1 &= ~WM8903_SAMPLE_RATE_MASK; clock1 |= sample_rates[dsp_config].value; @@ -1592,8 +1517,6 @@ static irqreturn_t wm8903_irq(int irq, void *data) SNDRV_PCM_FMTBIT_S24_LE) static struct snd_soc_dai_ops wm8903_dai_ops = { - .startup = wm8903_startup, - .shutdown = wm8903_shutdown, .hw_params = wm8903_hw_params, .digital_mute = wm8903_digital_mute, .set_fmt = wm8903_set_dai_fmt, -- cgit v1.2.2 From 69fff9bbbc4d214ed22c8f89681af3871a128e35 Mon Sep 17 00:00:00 2001 From: Mark Brown Date: Fri, 10 Dec 2010 19:17:08 +0000 Subject: ASoC: Automatically manage WM8903 deemphasis rate Provide the user with a boolean control then automatically select the deemphasis filter most closely matching the sample rate. Signed-off-by: Mark Brown Acked-by: Liam Girdwood --- sound/soc/codecs/wm8903.c | 82 ++++++++++++++++++++++++++++++++++++++++++----- 1 file changed, 74 insertions(+), 8 deletions(-) (limited to 'sound/soc/codecs') diff --git a/sound/soc/codecs/wm8903.c b/sound/soc/codecs/wm8903.c index f9ae403715c6..d015745a886b 100644 --- a/sound/soc/codecs/wm8903.c +++ b/sound/soc/codecs/wm8903.c @@ -218,6 +218,9 @@ struct wm8903_priv { int sysclk; int irq; + int fs; + int deemph; + /* Reference count */ int class_w_users; @@ -457,6 +460,72 @@ static int wm8903_class_w_put(struct snd_kcontrol *kcontrol, .private_value = SOC_SINGLE_VALUE(reg, shift, max, invert) } +static int wm8903_deemph[] = { 0, 32000, 44100, 48000 }; + +static int wm8903_set_deemph(struct snd_soc_codec *codec) +{ + struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec); + int val, i, best; + + /* If we're using deemphasis select the nearest available sample + * rate. + */ + if (wm8903->deemph) { + best = 1; + for (i = 2; i < ARRAY_SIZE(wm8903_deemph); i++) { + if (abs(wm8903_deemph[i] - wm8903->fs) < + abs(wm8903_deemph[best] - wm8903->fs)) + best = i; + } + + val = best << WM8903_DEEMPH_SHIFT; + } else { + best = 0; + val = 0; + } + + dev_dbg(codec->dev, "Set deemphasis %d (%dHz)\n", + best, wm8903_deemph[best]); + + return snd_soc_update_bits(codec, WM8903_DAC_DIGITAL_1, + WM8903_DEEMPH_MASK, val); +} + +static int wm8903_get_deemph(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); + struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec); + + ucontrol->value.enumerated.item[0] = wm8903->deemph; + + return 0; +} + +static int wm8903_put_deemph(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); + struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec); + int deemph = ucontrol->value.enumerated.item[0]; + int ret = 0; + + if (deemph > 1) + return -EINVAL; + + mutex_lock(&codec->mutex); + if (wm8903->deemph != deemph) { + wm8903->deemph = deemph; + + wm8903_set_deemph(codec); + + ret = 1; + } + mutex_unlock(&codec->mutex); + + return ret; +} + /* ALSA can only do steps of .01dB */ static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1); @@ -548,13 +617,6 @@ static const char *mute_mode_text[] = { static const struct soc_enum mute_mode = SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_1, 9, 2, mute_mode_text); -static const char *dac_deemphasis_text[] = { - "Disabled", "32kHz", "44.1kHz", "48kHz" -}; - -static const struct soc_enum dac_deemphasis = - SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_1, 1, 4, dac_deemphasis_text); - static const char *companding_text[] = { "ulaw", "alaw" }; @@ -662,9 +724,10 @@ SOC_DOUBLE_R_TLV("Digital Playback Volume", WM8903_DAC_DIGITAL_VOLUME_LEFT, SOC_ENUM("DAC Soft Mute Rate", soft_mute), SOC_ENUM("DAC Mute Mode", mute_mode), SOC_SINGLE("DAC Mono Switch", WM8903_DAC_DIGITAL_1, 12, 1, 0), -SOC_ENUM("DAC De-emphasis", dac_deemphasis), SOC_ENUM("DAC Companding Mode", dac_companding), SOC_SINGLE("DAC Companding Switch", WM8903_AUDIO_INTERFACE_0, 1, 1, 0), +SOC_SINGLE_BOOL_EXT("Playback Deemphasis Switch", 0, + wm8903_get_deemph, wm8903_put_deemph), /* Headphones */ SOC_DOUBLE_R("Headphone Switch", @@ -1374,6 +1437,9 @@ static int wm8903_hw_params(struct snd_pcm_substream *substream, aif2 |= bclk_divs[bclk_div].div; aif3 |= bclk / fs; + wm8903->fs = params_rate(params); + wm8903_set_deemph(codec); + snd_soc_write(codec, WM8903_CLOCK_RATES_0, clock0); snd_soc_write(codec, WM8903_CLOCK_RATES_1, clock1); snd_soc_write(codec, WM8903_AUDIO_INTERFACE_1, aif1); -- cgit v1.2.2 From 49db7e7b995f5c61c5e24198f833ed01d99f5e7d Mon Sep 17 00:00:00 2001 From: Mark Brown Date: Wed, 8 Dec 2010 13:49:43 +0000 Subject: ASoC: Fix widgets for WM8994/58 AIF2 source control The compiler really ought to have been warning about unreferenced variables... Signed-off-by: Mark Brown Acked-by: Liam Girdwood --- sound/soc/codecs/wm8994.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'sound/soc/codecs') diff --git a/sound/soc/codecs/wm8994.c b/sound/soc/codecs/wm8994.c index e59691a7b342..af104acd75f8 100644 --- a/sound/soc/codecs/wm8994.c +++ b/sound/soc/codecs/wm8994.c @@ -790,13 +790,13 @@ SOC_DOUBLE_R_TLV("AIF2ADC Volume", WM8994_AIF2_ADC_LEFT_VOLUME, SOC_ENUM("AIF1ADCL Source", aif1adcl_src), SOC_ENUM("AIF1ADCR Source", aif1adcr_src), -SOC_ENUM("AIF2ADCL Source", aif1adcl_src), -SOC_ENUM("AIF2ADCR Source", aif1adcr_src), +SOC_ENUM("AIF2ADCL Source", aif2adcl_src), +SOC_ENUM("AIF2ADCR Source", aif2adcr_src), SOC_ENUM("AIF1DACL Source", aif1dacl_src), SOC_ENUM("AIF1DACR Source", aif1dacr_src), -SOC_ENUM("AIF2DACL Source", aif1dacl_src), -SOC_ENUM("AIF2DACR Source", aif1dacr_src), +SOC_ENUM("AIF2DACL Source", aif2dacl_src), +SOC_ENUM("AIF2DACR Source", aif2dacr_src), SOC_DOUBLE_R_TLV("AIF1DAC1 Volume", WM8994_AIF1_DAC1_LEFT_VOLUME, WM8994_AIF1_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv), -- cgit v1.2.2 From fdea0571ddca8e3f22448f66d72a034575abea28 Mon Sep 17 00:00:00 2001 From: Takashi Iwai Date: Mon, 13 Dec 2010 12:55:39 +0100 Subject: ASoC: Fix merge errors with flush_scheduled_work() removal delayed_work was moved to dapm in the commit ce6120cca2589ede530200c7cfe11ac9f144333c ASoC: Decouple DAPM from CODECs Signed-off-by: Takashi Iwai --- sound/soc/codecs/wm8350.c | 2 +- sound/soc/codecs/wm8753.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'sound/soc/codecs') diff --git a/sound/soc/codecs/wm8350.c b/sound/soc/codecs/wm8350.c index f8a8a6944e65..07ba7e3f6a8c 100644 --- a/sound/soc/codecs/wm8350.c +++ b/sound/soc/codecs/wm8350.c @@ -1643,7 +1643,7 @@ static int wm8350_codec_remove(struct snd_soc_codec *codec) /* if there was any work waiting then we run it now and * wait for its completion */ - flush_delayed_work_sync(&codec->delayed_work); + flush_delayed_work_sync(&codec->dapm.delayed_work); wm8350_set_bias_level(codec, SND_SOC_BIAS_OFF); diff --git a/sound/soc/codecs/wm8753.c b/sound/soc/codecs/wm8753.c index 747457193887..73507e71cb79 100644 --- a/sound/soc/codecs/wm8753.c +++ b/sound/soc/codecs/wm8753.c @@ -1587,7 +1587,7 @@ static int wm8753_probe(struct snd_soc_codec *codec) /* power down chip */ static int wm8753_remove(struct snd_soc_codec *codec) { - flush_delayed_work_sync(&codec->delayed_work); + flush_delayed_work_sync(&codec->dapm.delayed_work); wm8753_set_bias_level(codec, SND_SOC_BIAS_OFF); return 0; -- cgit v1.2.2 From 83b6542533859d6ed6c95f8b869291e885eab5bd Mon Sep 17 00:00:00 2001 From: Mark Brown Date: Tue, 14 Dec 2010 11:25:18 +0000 Subject: ASoC: Explicitly clear WM8993 ramp controls on power down This helps ensure that the ramp logic is reset when powering back up. Signed-off-by: Mark Brown Acked-by: Liam Girdwood --- sound/soc/codecs/wm8993.c | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'sound/soc/codecs') diff --git a/sound/soc/codecs/wm8993.c b/sound/soc/codecs/wm8993.c index 77b1d441c3d0..15f34a26debf 100644 --- a/sound/soc/codecs/wm8993.c +++ b/sound/soc/codecs/wm8993.c @@ -1030,6 +1030,12 @@ static int wm8993_set_bias_level(struct snd_soc_codec *codec, WM8993_VMID_SEL_MASK | WM8993_BIAS_ENA, 0); + snd_soc_update_bits(codec, WM8993_ANTIPOP2, + WM8993_STARTUP_BIAS_ENA | + WM8993_VMID_BUF_ENA | + WM8993_VMID_RAMP_MASK | + WM8993_BIAS_SRC, 0); + #ifdef CONFIG_REGULATOR /* Post 2.6.34 we will be able to get a callback when * the regulators are disabled which we can use but -- cgit v1.2.2 From dcdeda4a60b2046dd18d3dd20cbd888f25d8916b Mon Sep 17 00:00:00 2001 From: Peter Ujfalusi Date: Tue, 14 Dec 2010 13:45:29 +0200 Subject: ASoC: TWL4030: Fix 24bit support twl4030 series of codecs supports S32_LE with msbits=24. Replace the S24_LE with S32_LE format, and add constraint for 24msbit in case of 32 S32_LE format. Signed-off-by: Peter Ujfalusi Acked-by: Mark Brown Signed-off-by: Liam Girdwood --- sound/soc/codecs/twl4030.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'sound/soc/codecs') diff --git a/sound/soc/codecs/twl4030.c b/sound/soc/codecs/twl4030.c index c173cf00f5cb..e4d464b937d6 100644 --- a/sound/soc/codecs/twl4030.c +++ b/sound/soc/codecs/twl4030.c @@ -1724,6 +1724,7 @@ static int twl4030_startup(struct snd_pcm_substream *substream, struct snd_soc_codec *codec = rtd->codec; struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec); + snd_pcm_hw_constraint_msbits(substream->runtime, 0, 32, 24); if (twl4030->master_substream) { twl4030->slave_substream = substream; /* The DAI has one configuration for playback and capture, so @@ -1848,7 +1849,7 @@ static int twl4030_hw_params(struct snd_pcm_substream *substream, case SNDRV_PCM_FORMAT_S16_LE: format |= TWL4030_DATA_WIDTH_16S_16W; break; - case SNDRV_PCM_FORMAT_S24_LE: + case SNDRV_PCM_FORMAT_S32_LE: format |= TWL4030_DATA_WIDTH_32S_24W; break; default: @@ -2181,7 +2182,7 @@ static int twl4030_voice_set_tristate(struct snd_soc_dai *dai, int tristate) } #define TWL4030_RATES (SNDRV_PCM_RATE_8000_48000) -#define TWL4030_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FORMAT_S24_LE) +#define TWL4030_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE) static struct snd_soc_dai_ops twl4030_dai_hifi_ops = { .startup = twl4030_startup, -- cgit v1.2.2 From a2d2362edf9f068bdee7d0411e0603b322f8415d Mon Sep 17 00:00:00 2001 From: Jorge Eduardo Candelaria Date: Fri, 10 Dec 2010 20:45:17 -0600 Subject: ASoC: twl6040: Add jack support for headset and handset This patch adds support for reporting twl6040 headset and handset jack events. The machine driver retrieves and report the status through twl6040_hs_jack_detect. A workq is used to debounce of the irq. Signed-off-by: Jorge Eduardo Candelaria Signed-off-by: Misael Lopez Cruz Signed-off-by: Margarita Olaya Cabrera Signed-off-by: Liam Girdwood --- sound/soc/codecs/twl6040.c | 67 ++++++++++++++++++++++++++++++++++++++++++++++ sound/soc/codecs/twl6040.h | 7 +++++ 2 files changed, 74 insertions(+) (limited to 'sound/soc/codecs') diff --git a/sound/soc/codecs/twl6040.c b/sound/soc/codecs/twl6040.c index b92f2b737e4c..5d7e2f7b194c 100644 --- a/sound/soc/codecs/twl6040.c +++ b/sound/soc/codecs/twl6040.c @@ -42,6 +42,11 @@ #define TWL6040_RATES (SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000) #define TWL6040_FORMATS (SNDRV_PCM_FMTBIT_S32_LE) +struct twl6040_jack_data { + struct snd_soc_jack *jack; + int report; +}; + /* codec private data */ struct twl6040_data { int audpwron; @@ -52,6 +57,11 @@ struct twl6040_data { unsigned int sysclk; struct snd_pcm_hw_constraint_list *sysclk_constraints; struct completion ready; + struct twl6040_jack_data hs_jack; + struct snd_soc_codec *codec; + struct workqueue_struct *workqueue; + struct delayed_work delayed_work; + struct mutex mutex; }; /* @@ -381,6 +391,47 @@ static int twl6040_power_mode_event(struct snd_soc_dapm_widget *w, return 0; } +void twl6040_hs_jack_report(struct snd_soc_codec *codec, + struct snd_soc_jack *jack, int report) +{ + struct twl6040_data *priv = snd_soc_codec_get_drvdata(codec); + int status; + + mutex_lock(&priv->mutex); + + /* Sync status */ + status = twl6040_read_reg_volatile(codec, TWL6040_REG_STATUS); + if (status & TWL6040_PLUGCOMP) + snd_soc_jack_report(jack, report, report); + else + snd_soc_jack_report(jack, 0, report); + + mutex_unlock(&priv->mutex); +} + +void twl6040_hs_jack_detect(struct snd_soc_codec *codec, + struct snd_soc_jack *jack, int report) +{ + struct twl6040_data *priv = snd_soc_codec_get_drvdata(codec); + struct twl6040_jack_data *hs_jack = &priv->hs_jack; + + hs_jack->jack = jack; + hs_jack->report = report; + + twl6040_hs_jack_report(codec, hs_jack->jack, hs_jack->report); +} +EXPORT_SYMBOL_GPL(twl6040_hs_jack_detect); + +static void twl6040_accessory_work(struct work_struct *work) +{ + struct twl6040_data *priv = container_of(work, + struct twl6040_data, delayed_work.work); + struct snd_soc_codec *codec = priv->codec; + struct twl6040_jack_data *hs_jack = &priv->hs_jack; + + twl6040_hs_jack_report(codec, hs_jack->jack, hs_jack->report); +} + /* audio interrupt handler */ static irqreturn_t twl6040_naudint_handler(int irq, void *data) { @@ -396,6 +447,9 @@ static irqreturn_t twl6040_naudint_handler(int irq, void *data) break; case TWL6040_PLUGINT: case TWL6040_UNPLUGINT: + queue_delayed_work(priv->workqueue, &priv->delayed_work, + msecs_to_jiffies(200)); + break; case TWL6040_HOOKINT: break; case TWL6040_HFINT: @@ -1023,6 +1077,8 @@ static int twl6040_probe(struct snd_soc_codec *codec) return -ENOMEM; snd_soc_codec_set_drvdata(codec, priv); + priv->codec = codec; + if (twl_codec) { audpwron = twl_codec->audpwron_gpio; naudint = twl_codec->naudint_irq; @@ -1033,6 +1089,14 @@ static int twl6040_probe(struct snd_soc_codec *codec) priv->audpwron = audpwron; priv->naudint = naudint; + priv->workqueue = create_singlethread_workqueue("twl6040-codec"); + + if (!priv->workqueue) + goto work_err; + + INIT_DELAYED_WORK(&priv->delayed_work, twl6040_accessory_work); + + mutex_init(&priv->mutex); init_completion(&priv->ready); @@ -1089,6 +1153,8 @@ gpio2_err: if (gpio_is_valid(audpwron)) gpio_free(audpwron); gpio1_err: + destroy_workqueue(priv->workqueue); +work_err: kfree(priv); return ret; } @@ -1107,6 +1173,7 @@ static int twl6040_remove(struct snd_soc_codec *codec) if (naudint) free_irq(naudint, codec); + destroy_workqueue(priv->workqueue); kfree(priv); return 0; diff --git a/sound/soc/codecs/twl6040.h b/sound/soc/codecs/twl6040.h index f7c77fa58a3c..67396f63c1ec 100644 --- a/sound/soc/codecs/twl6040.h +++ b/sound/soc/codecs/twl6040.h @@ -135,4 +135,11 @@ #define TWL6040_HPPLL_ID 1 #define TWL6040_LPPLL_ID 2 +/* STATUS (0x2E) fields */ + +#define TWL6040_PLUGCOMP 0x02 + +void twl6040_hs_jack_detect(struct snd_soc_codec *codec, + struct snd_soc_jack *jack, int report); + #endif /* End of __TWL6040_H__ */ -- cgit v1.2.2 From 0dec1ec72317caa64f0174f8190c714ae4d51040 Mon Sep 17 00:00:00 2001 From: "Olaya, Margarita" Date: Fri, 10 Dec 2010 21:05:24 -0600 Subject: ASoC: twl6040: Update twl IO macro Update the codec to use the new twl core register macros Signed-off-by: Margarita Olaya Cabrera Acked-by: Mark Brown Signed-off-by: Liam Girdwood --- sound/soc/codecs/twl6040.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'sound/soc/codecs') diff --git a/sound/soc/codecs/twl6040.c b/sound/soc/codecs/twl6040.c index 5d7e2f7b194c..d33d2b4769f3 100644 --- a/sound/soc/codecs/twl6040.c +++ b/sound/soc/codecs/twl6040.c @@ -210,7 +210,7 @@ static int twl6040_read_reg_volatile(struct snd_soc_codec *codec, if (reg >= TWL6040_CACHEREGNUM) return -EIO; - twl_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &value, reg); + twl_i2c_read_u8(TWL_MODULE_AUDIO_VOICE, &value, reg); twl6040_write_reg_cache(codec, reg, value); return value; @@ -226,7 +226,7 @@ static int twl6040_write(struct snd_soc_codec *codec, return -EIO; twl6040_write_reg_cache(codec, reg, value); - return twl_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, value, reg); + return twl_i2c_write_u8(TWL_MODULE_AUDIO_VOICE, value, reg); } static void twl6040_init_vio_regs(struct snd_soc_codec *codec) @@ -439,7 +439,7 @@ static irqreturn_t twl6040_naudint_handler(int irq, void *data) struct twl6040_data *priv = snd_soc_codec_get_drvdata(codec); u8 intid; - twl_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &intid, TWL6040_REG_INTID); + twl_i2c_read_u8(TWL_MODULE_AUDIO_VOICE, &intid, TWL6040_REG_INTID); switch (intid) { case TWL6040_THINT: @@ -715,7 +715,7 @@ static int twl6040_power_up_completion(struct snd_soc_codec *codec, msecs_to_jiffies(48)); if (!time_left) { - twl_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &intid, + twl_i2c_read_u8(TWL_MODULE_AUDIO_VOICE, &intid, TWL6040_REG_INTID); if (!(intid & TWL6040_READYINT)) { dev_err(codec->dev, "timeout waiting for READYINT\n"); -- cgit v1.2.2 From cf370a5a0e9d3b111f93216a55f275d66daed952 Mon Sep 17 00:00:00 2001 From: "Olaya, Margarita" Date: Fri, 10 Dec 2010 21:05:30 -0600 Subject: ASoC: twl6040: Modify the IRQ handler Multiples interrupts can be received. The irq handler is modified to attend all of them. Signed-off-by: Margarita Olaya Cabrera Acked-by: Mark Brown Signed-off-by: Liam Girdwood --- sound/soc/codecs/twl6040.c | 30 ++++++++++++------------------ 1 file changed, 12 insertions(+), 18 deletions(-) (limited to 'sound/soc/codecs') diff --git a/sound/soc/codecs/twl6040.c b/sound/soc/codecs/twl6040.c index d33d2b4769f3..8a6c62339e39 100644 --- a/sound/soc/codecs/twl6040.c +++ b/sound/soc/codecs/twl6040.c @@ -441,30 +441,24 @@ static irqreturn_t twl6040_naudint_handler(int irq, void *data) twl_i2c_read_u8(TWL_MODULE_AUDIO_VOICE, &intid, TWL6040_REG_INTID); - switch (intid) { - case TWL6040_THINT: + if (intid & TWL6040_THINT) dev_alert(codec->dev, "die temp over-limit detection\n"); - break; - case TWL6040_PLUGINT: - case TWL6040_UNPLUGINT: + + if ((intid & TWL6040_PLUGINT) || (intid & TWL6040_UNPLUGINT)) queue_delayed_work(priv->workqueue, &priv->delayed_work, msecs_to_jiffies(200)); - break; - case TWL6040_HOOKINT: - break; - case TWL6040_HFINT: + + if (intid & TWL6040_HOOKINT) + dev_info(codec->dev, "hook detection\n"); + + if (intid & TWL6040_HFINT) dev_alert(codec->dev, "hf drivers over current detection\n"); - break; - case TWL6040_VIBINT: + + if (intid & TWL6040_VIBINT) dev_alert(codec->dev, "vib drivers over current detection\n"); - break; - case TWL6040_READYINT: + + if (intid & TWL6040_READYINT) complete(&priv->ready); - break; - default: - dev_err(codec->dev, "unknown audio interrupt %d\n", intid); - break; - } return IRQ_HANDLED; } -- cgit v1.2.2 From 370a0314ff3e1315e7fdec32a88a7ae49ccd22c8 Mon Sep 17 00:00:00 2001 From: Jorge Eduardo Candelaria Date: Fri, 10 Dec 2010 21:05:32 -0600 Subject: ASoC: twl6040: Add headset and handset mux controls This patch adds support for the twl6040 headset and handset MUX controls. Signed-off-by: Jorge Eduardo Candelaria Signed-off-by: Margarita Olaya Cabrera Acked-by: Mark Brown Signed-off-by: Liam Girdwood --- sound/soc/codecs/twl6040.c | 100 +++++++++++++++++++++++++++++++++------------ 1 file changed, 73 insertions(+), 27 deletions(-) (limited to 'sound/soc/codecs') diff --git a/sound/soc/codecs/twl6040.c b/sound/soc/codecs/twl6040.c index 8a6c62339e39..b575fd3ba3fb 100644 --- a/sound/soc/codecs/twl6040.c +++ b/sound/soc/codecs/twl6040.c @@ -475,6 +475,12 @@ static DECLARE_TLV_DB_SCALE(mic_preamp_tlv, -600, 600, 0); */ static DECLARE_TLV_DB_SCALE(mic_amp_tlv, 600, 600, 0); +/* + * AFMGAIN volume control: + * from 18 to 24 dB in 6 dB steps + */ +static DECLARE_TLV_DB_SCALE(afm_amp_tlv, 1800, 600, 0); + /* * HSGAIN volume control: * from -30 to 0 dB in 2 dB steps @@ -506,6 +512,28 @@ static const struct soc_enum twl6040_enum[] = { SOC_ENUM_SINGLE(TWL6040_REG_MICRCTL, 3, 3, twl6040_amicr_texts), }; +static const char *twl6040_hs_texts[] = { + "Off", "HS DAC", "Line-In amp" +}; + +static const struct soc_enum twl6040_hs_enum[] = { + SOC_ENUM_SINGLE(TWL6040_REG_HSLCTL, 5, ARRAY_SIZE(twl6040_hs_texts), + twl6040_hs_texts), + SOC_ENUM_SINGLE(TWL6040_REG_HSRCTL, 5, ARRAY_SIZE(twl6040_hs_texts), + twl6040_hs_texts), +}; + +static const char *twl6040_hf_texts[] = { + "Off", "HF DAC", "Line-In amp" +}; + +static const struct soc_enum twl6040_hf_enum[] = { + SOC_ENUM_SINGLE(TWL6040_REG_HFLCTL, 2, ARRAY_SIZE(twl6040_hf_texts), + twl6040_hf_texts), + SOC_ENUM_SINGLE(TWL6040_REG_HFRCTL, 2, ARRAY_SIZE(twl6040_hf_texts), + twl6040_hf_texts), +}; + static const struct snd_kcontrol_new amicl_control = SOC_DAPM_ENUM("Route", twl6040_enum[0]); @@ -513,18 +541,18 @@ static const struct snd_kcontrol_new amicr_control = SOC_DAPM_ENUM("Route", twl6040_enum[1]); /* Headset DAC playback switches */ -static const struct snd_kcontrol_new hsdacl_switch_controls = - SOC_DAPM_SINGLE("Switch", TWL6040_REG_HSLCTL, 5, 1, 0); +static const struct snd_kcontrol_new hsl_mux_controls = + SOC_DAPM_ENUM("Route", twl6040_hs_enum[0]); -static const struct snd_kcontrol_new hsdacr_switch_controls = - SOC_DAPM_SINGLE("Switch", TWL6040_REG_HSRCTL, 5, 1, 0); +static const struct snd_kcontrol_new hsr_mux_controls = + SOC_DAPM_ENUM("Route", twl6040_hs_enum[1]); /* Handsfree DAC playback switches */ -static const struct snd_kcontrol_new hfdacl_switch_controls = - SOC_DAPM_SINGLE("Switch", TWL6040_REG_HFLCTL, 2, 1, 0); +static const struct snd_kcontrol_new hfl_mux_controls = + SOC_DAPM_ENUM("Route", twl6040_hf_enum[0]); -static const struct snd_kcontrol_new hfdacr_switch_controls = - SOC_DAPM_SINGLE("Switch", TWL6040_REG_HFRCTL, 2, 1, 0); +static const struct snd_kcontrol_new hfr_mux_controls = + SOC_DAPM_ENUM("Route", twl6040_hf_enum[1]); static const struct snd_kcontrol_new ep_driver_switch_controls = SOC_DAPM_SINGLE("Switch", TWL6040_REG_EARCTL, 0, 1, 0); @@ -536,6 +564,10 @@ static const struct snd_kcontrol_new twl6040_snd_controls[] = { SOC_DOUBLE_TLV("Capture Volume", TWL6040_REG_MICGAIN, 0, 3, 4, 0, mic_amp_tlv), + /* AFM gains */ + SOC_DOUBLE_TLV("Aux FM Volume", + TWL6040_REG_LINEGAIN, 0, 5, 0xF, 0, afm_amp_tlv), + /* Playback gains */ SOC_DOUBLE_TLV("Headset Playback Volume", TWL6040_REG_HSGAIN, 0, 4, 0xF, 1, hs_tlv), @@ -572,6 +604,12 @@ static const struct snd_soc_dapm_widget twl6040_dapm_widgets[] = { SND_SOC_DAPM_PGA("MicAmpR", TWL6040_REG_MICRCTL, 0, 0, NULL, 0), + /* Auxiliary FM PGAs */ + SND_SOC_DAPM_PGA("AFMAmpL", + TWL6040_REG_MICLCTL, 1, 0, NULL, 0), + SND_SOC_DAPM_PGA("AFMAmpR", + TWL6040_REG_MICRCTL, 1, 0, NULL, 0), + /* ADCs */ SND_SOC_DAPM_ADC("ADC Left", "Left Front Capture", TWL6040_REG_MICLCTL, 2, 0), @@ -606,15 +644,15 @@ static const struct snd_soc_dapm_widget twl6040_dapm_widgets[] = { twl6040_power_mode_event, SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), - /* Analog playback switches */ - SND_SOC_DAPM_SWITCH("HSDAC Left Playback", - SND_SOC_NOPM, 0, 0, &hsdacl_switch_controls), - SND_SOC_DAPM_SWITCH("HSDAC Right Playback", - SND_SOC_NOPM, 0, 0, &hsdacr_switch_controls), - SND_SOC_DAPM_SWITCH("HFDAC Left Playback", - SND_SOC_NOPM, 0, 0, &hfdacl_switch_controls), - SND_SOC_DAPM_SWITCH("HFDAC Right Playback", - SND_SOC_NOPM, 0, 0, &hfdacr_switch_controls), + SND_SOC_DAPM_MUX("HF Left Playback", + SND_SOC_NOPM, 0, 0, &hfl_mux_controls), + SND_SOC_DAPM_MUX("HF Right Playback", + SND_SOC_NOPM, 0, 0, &hfr_mux_controls), + /* Analog playback Muxes */ + SND_SOC_DAPM_MUX("HS Left Playback", + SND_SOC_NOPM, 0, 0, &hsl_mux_controls), + SND_SOC_DAPM_MUX("HS Right Playback", + SND_SOC_NOPM, 0, 0, &hsr_mux_controls), /* Analog playback drivers */ SND_SOC_DAPM_PGA_E("Handsfree Left Driver", @@ -658,12 +696,18 @@ static const struct snd_soc_dapm_route intercon[] = { {"ADC Left", NULL, "MicAmpL"}, {"ADC Right", NULL, "MicAmpR"}, - /* Headset playback path */ - {"HSDAC Left Playback", "Switch", "HSDAC Left"}, - {"HSDAC Right Playback", "Switch", "HSDAC Right"}, + /* AFM path */ + {"AFMAmpL", "NULL", "AFML"}, + {"AFMAmpR", "NULL", "AFMR"}, + + {"HS Left Playback", "HS DAC", "HSDAC Left"}, + {"HS Left Playback", "Line-In amp", "AFMAmpL"}, - {"Headset Left Driver", NULL, "HSDAC Left Playback"}, - {"Headset Right Driver", NULL, "HSDAC Right Playback"}, + {"HS Right Playback", "HS DAC", "HSDAC Right"}, + {"HS Right Playback", "Line-In amp", "AFMAmpR"}, + + {"Headset Left Driver", "NULL", "HS Left Playback"}, + {"Headset Right Driver", "NULL", "HS Right Playback"}, {"HSOL", NULL, "Headset Left Driver"}, {"HSOR", NULL, "Headset Right Driver"}, @@ -672,12 +716,14 @@ static const struct snd_soc_dapm_route intercon[] = { {"Earphone Driver", "Switch", "HSDAC Left"}, {"EP", NULL, "Earphone Driver"}, - /* Handsfree playback path */ - {"HFDAC Left Playback", "Switch", "HFDAC Left"}, - {"HFDAC Right Playback", "Switch", "HFDAC Right"}, + {"HF Left Playback", "HF DAC", "HFDAC Left"}, + {"HF Left Playback", "Line-In amp", "AFMAmpL"}, + + {"HF Right Playback", "HF DAC", "HFDAC Right"}, + {"HF Right Playback", "Line-In amp", "AFMAmpR"}, - {"HFDAC Left PGA", NULL, "HFDAC Left Playback"}, - {"HFDAC Right PGA", NULL, "HFDAC Right Playback"}, + {"HFDAC Left PGA", NULL, "HF Left Playback"}, + {"HFDAC Right PGA", NULL, "HF Right Playback"}, {"Handsfree Left Driver", "Switch", "HFDAC Left PGA"}, {"Handsfree Right Driver", "Switch", "HFDAC Right PGA"}, -- cgit v1.2.2 From 6c311041c1d3d0b9d1fc6ddacd49e50d83ba158a Mon Sep 17 00:00:00 2001 From: "Olaya, Margarita" Date: Fri, 10 Dec 2010 21:05:46 -0600 Subject: ASoC: twl6040: Restore bias level at resume This patch restores the CODEC bias level at resume(). Signed-off-by: Margarita Olaya Cabrera Acked-by: Mark Brown Signed-off-by: Liam Girdwood --- sound/soc/codecs/twl6040.c | 1 + 1 file changed, 1 insertion(+) (limited to 'sound/soc/codecs') diff --git a/sound/soc/codecs/twl6040.c b/sound/soc/codecs/twl6040.c index b575fd3ba3fb..3973bf6889c0 100644 --- a/sound/soc/codecs/twl6040.c +++ b/sound/soc/codecs/twl6040.c @@ -1097,6 +1097,7 @@ static int twl6040_suspend(struct snd_soc_codec *codec, pm_message_t state) static int twl6040_resume(struct snd_soc_codec *codec) { twl6040_set_bias_level(codec, SND_SOC_BIAS_STANDBY); + twl6040_set_bias_level(codec, codec->dapm.suspend_bias_level); return 0; } -- cgit v1.2.2 From 4e624d0609081e4394695fba3d7c3b7ebb6171ce Mon Sep 17 00:00:00 2001 From: "Olaya, Margarita" Date: Fri, 10 Dec 2010 21:05:54 -0600 Subject: ASoC: twl6040: Fix PCM error handling ops This patch moves all the PCM error handling for clock config out of trigger() and startup() and into prepare(). Signed-off-by: Margarita Olaya Cabrera Acked-by: Mark Brown Signed-off-by: Liam Girdwood --- sound/soc/codecs/twl6040.c | 55 +++++++++++++++++++--------------------------- 1 file changed, 22 insertions(+), 33 deletions(-) (limited to 'sound/soc/codecs') diff --git a/sound/soc/codecs/twl6040.c b/sound/soc/codecs/twl6040.c index 3973bf6889c0..fd9a3ab91a19 100644 --- a/sound/soc/codecs/twl6040.c +++ b/sound/soc/codecs/twl6040.c @@ -865,23 +865,6 @@ static int twl6040_startup(struct snd_pcm_substream *substream, struct snd_soc_codec *codec = rtd->codec; struct twl6040_data *priv = snd_soc_codec_get_drvdata(codec); - if (!priv->sysclk) { - dev_err(codec->dev, - "no mclk configured, call set_sysclk() on init\n"); - return -EINVAL; - } - - /* - * capture is not supported at 17.64 MHz, - * it's reserved for headset low-power playback scenario - */ - if ((priv->sysclk == 17640000) && substream->stream) { - dev_err(codec->dev, - "capture mode is not supported at %dHz\n", - priv->sysclk); - return -EINVAL; - } - snd_pcm_hw_constraint_list(substream->runtime, 0, SNDRV_PCM_HW_PARAM_RATE, priv->sysclk_constraints); @@ -925,31 +908,37 @@ static int twl6040_hw_params(struct snd_pcm_substream *substream, return 0; } -static int twl6040_trigger(struct snd_pcm_substream *substream, - int cmd, struct snd_soc_dai *dai) +static int twl6040_prepare(struct snd_pcm_substream *substream, + struct snd_soc_dai *dai) { struct snd_soc_pcm_runtime *rtd = substream->private_data; struct snd_soc_codec *codec = rtd->codec; struct twl6040_data *priv = snd_soc_codec_get_drvdata(codec); - switch (cmd) { - case SNDRV_PCM_TRIGGER_START: - case SNDRV_PCM_TRIGGER_RESUME: - /* - * low-power playback mode is restricted - * for headset path only - */ - if ((priv->sysclk == 17640000) && priv->non_lp) { + if (!priv->sysclk) { + dev_err(codec->dev, + "no mclk configured, call set_sysclk() on init\n"); + return -EINVAL; + } + + /* + * capture is not supported at 17.64 MHz, + * it's reserved for headset low-power playback scenario + */ + if ((priv->sysclk == 17640000) && + substream->stream == SNDRV_PCM_STREAM_CAPTURE) { + dev_err(codec->dev, + "capture mode is not supported at %dHz\n", + priv->sysclk); + return -EINVAL; + } + + if ((priv->sysclk == 17640000) && priv->non_lp) { dev_err(codec->dev, "some enabled paths aren't supported at %dHz\n", priv->sysclk); return -EPERM; - } - break; - default: - break; } - return 0; } @@ -1063,7 +1052,7 @@ static int twl6040_set_dai_sysclk(struct snd_soc_dai *codec_dai, static struct snd_soc_dai_ops twl6040_dai_ops = { .startup = twl6040_startup, .hw_params = twl6040_hw_params, - .trigger = twl6040_trigger, + .prepare = twl6040_prepare, .set_sysclk = twl6040_set_dai_sysclk, }; -- cgit v1.2.2 From 60ea4cecddd03ed86b91bc8c057d3d305dc678be Mon Sep 17 00:00:00 2001 From: "Olaya, Margarita" Date: Fri, 10 Dec 2010 21:05:58 -0600 Subject: ASoC: twl6040: Support other sample rates. The twl6040 can support more sample rates other than 88.2 and 96k. Signed-off-by: Margarita Olaya Cabrera Acked-by: Mark Brown Signed-off-by: Liam Girdwood --- sound/soc/codecs/twl6040.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) (limited to 'sound/soc/codecs') diff --git a/sound/soc/codecs/twl6040.c b/sound/soc/codecs/twl6040.c index fd9a3ab91a19..b59d947d0bfe 100644 --- a/sound/soc/codecs/twl6040.c +++ b/sound/soc/codecs/twl6040.c @@ -39,7 +39,7 @@ #include "twl6040.h" -#define TWL6040_RATES (SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000) +#define TWL6040_RATES SNDRV_PCM_RATE_8000_96000 #define TWL6040_FORMATS (SNDRV_PCM_FMTBIT_S32_LE) struct twl6040_jack_data { @@ -890,10 +890,17 @@ static int twl6040_hw_params(struct snd_pcm_substream *substream, rate = params_rate(params); switch (rate) { + case 11250: + case 22500: + case 44100: case 88200: lppllctl |= TWL6040_LPLLFIN; priv->sysclk = 17640000; break; + case 8000: + case 16000: + case 32000: + case 48000: case 96000: lppllctl &= ~TWL6040_LPLLFIN; priv->sysclk = 19200000; -- cgit v1.2.2 From cb973d78f82f038c7d8d78d469fb89842d246871 Mon Sep 17 00:00:00 2001 From: Francois Mazard Date: Fri, 10 Dec 2010 21:06:03 -0600 Subject: ASoC: twl6040: Fix analog Mic L & R mux controls The mux control has 4 elements not 3 Signed-off-by: Margarita Olaya Cabrera Acked-by: Mark Brown Signed-off-by: Liam Girdwood --- sound/soc/codecs/twl6040.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'sound/soc/codecs') diff --git a/sound/soc/codecs/twl6040.c b/sound/soc/codecs/twl6040.c index b59d947d0bfe..5081e812c528 100644 --- a/sound/soc/codecs/twl6040.c +++ b/sound/soc/codecs/twl6040.c @@ -508,8 +508,8 @@ static const char *twl6040_amicr_texts[] = {"Headset Mic", "Sub Mic", "Aux/FM Right", "Off"}; static const struct soc_enum twl6040_enum[] = { - SOC_ENUM_SINGLE(TWL6040_REG_MICLCTL, 3, 3, twl6040_amicl_texts), - SOC_ENUM_SINGLE(TWL6040_REG_MICRCTL, 3, 3, twl6040_amicr_texts), + SOC_ENUM_SINGLE(TWL6040_REG_MICLCTL, 3, 4, twl6040_amicl_texts), + SOC_ENUM_SINGLE(TWL6040_REG_MICRCTL, 3, 4, twl6040_amicr_texts), }; static const char *twl6040_hs_texts[] = { -- cgit v1.2.2 From 99903ea23655a43ce4f75b64fef69e341fd0b7df Mon Sep 17 00:00:00 2001 From: "Olaya, Margarita" Date: Fri, 10 Dec 2010 21:06:07 -0600 Subject: ASoC: twl6040: Enable automatic power for phoenix 1.1 Phoenix 1.1 supports automatic power on sequence, a verification is added to use it with new revision of the chip. Signed-off-by: Margarita Olaya Cabrera Acked-by: Mark Brown Signed-off-by: Liam Girdwood --- sound/soc/codecs/twl6040.c | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) (limited to 'sound/soc/codecs') diff --git a/sound/soc/codecs/twl6040.c b/sound/soc/codecs/twl6040.c index 5081e812c528..c54350445d0c 100644 --- a/sound/soc/codecs/twl6040.c +++ b/sound/soc/codecs/twl6040.c @@ -1108,6 +1108,7 @@ static int twl6040_probe(struct snd_soc_codec *codec) struct twl6040_data *priv; int audpwron, naudint; int ret = 0; + u8 icrev; priv = kzalloc(sizeof(struct twl6040_data), GFP_KERNEL); if (priv == NULL) @@ -1116,13 +1117,17 @@ static int twl6040_probe(struct snd_soc_codec *codec) priv->codec = codec; - if (twl_codec) { + twl_i2c_read_u8(TWL_MODULE_AUDIO_VOICE, &icrev, TWL6040_REG_ASICREV); + + if (twl_codec && (icrev > 0)) audpwron = twl_codec->audpwron_gpio; - naudint = twl_codec->naudint_irq; - } else { + else audpwron = -EINVAL; + + if (twl_codec) + naudint = twl_codec->naudint_irq; + else naudint = 0; - } priv->audpwron = audpwron; priv->naudint = naudint; -- cgit v1.2.2 From f1f489a6aa89993892cd7b4d08f67e7e110492cb Mon Sep 17 00:00:00 2001 From: Jorge Eduardo Candelaria Date: Fri, 10 Dec 2010 21:06:13 -0600 Subject: ASoC: twl6040: Clear interrupt status at boot time On Phoenix 1.1, the INTID register default value is an invalid one, causing the interrupt handler to think the phoenix power on sequence is ready before it actually finishes. This causes some i2c errors when trying to configure twl. Signed-off-by: Jorge Eduardo Candelaria Signed-off-by: Margarita Olaya Cabrera Acked-by: Mark Brown Signed-off-by: Liam Girdwood --- sound/soc/codecs/twl6040.c | 21 +++++++++++---------- 1 file changed, 11 insertions(+), 10 deletions(-) (limited to 'sound/soc/codecs') diff --git a/sound/soc/codecs/twl6040.c b/sound/soc/codecs/twl6040.c index c54350445d0c..f5d5f89a2216 100644 --- a/sound/soc/codecs/twl6040.c +++ b/sound/soc/codecs/twl6040.c @@ -1152,6 +1152,17 @@ static int twl6040_probe(struct snd_soc_codec *codec) goto gpio2_err; priv->codec_powered = 0; + + /* enable only codec ready interrupt */ + twl6040_write(codec, TWL6040_REG_INTMR, + ~TWL6040_READYMSK & TWL6040_ALLINT_MSK); + + /* reset interrupt status to allow correct power up sequence */ + twl6040_read_reg_volatile(codec, TWL6040_REG_INTID); + } else { + /* no interrupts at all */ + twl6040_write_reg_cache(codec, TWL6040_REG_INTMR, + TWL6040_ALLINT_MSK); } if (naudint) { @@ -1162,16 +1173,6 @@ static int twl6040_probe(struct snd_soc_codec *codec) "twl6040_codec", codec); if (ret) goto gpio2_err; - } else { - if (gpio_is_valid(audpwron)) { - /* enable only codec ready interrupt */ - twl6040_write_reg_cache(codec, TWL6040_REG_INTMR, - ~TWL6040_READYMSK & TWL6040_ALLINT_MSK); - } else { - /* no interrupts at all */ - twl6040_write_reg_cache(codec, TWL6040_REG_INTMR, - TWL6040_ALLINT_MSK); - } } /* init vio registers */ -- cgit v1.2.2 From 4f44ee1f494edef1fea3db20565b2e209bef6280 Mon Sep 17 00:00:00 2001 From: Misael Lopez Cruz Date: Fri, 10 Dec 2010 21:06:24 -0600 Subject: ASoC: twl6040: Enable plug detection interrupts Enable plug detection interrupt mask in order to get headset PLUGINT/UNPLUGINT interrupts. Signed-off-by: Misael Lopez Cruz Signed-off-by: Margarita Olaya Cabrera Acked-by: Mark Brown Signed-off-by: Liam Girdwood --- sound/soc/codecs/twl6040.c | 10 +++------- sound/soc/codecs/twl6040.h | 1 + 2 files changed, 4 insertions(+), 7 deletions(-) (limited to 'sound/soc/codecs') diff --git a/sound/soc/codecs/twl6040.c b/sound/soc/codecs/twl6040.c index f5d5f89a2216..a8ec9113cc33 100644 --- a/sound/soc/codecs/twl6040.c +++ b/sound/soc/codecs/twl6040.c @@ -1108,7 +1108,7 @@ static int twl6040_probe(struct snd_soc_codec *codec) struct twl6040_data *priv; int audpwron, naudint; int ret = 0; - u8 icrev; + u8 icrev, intmr = TWL6040_ALLINT_MSK; priv = kzalloc(sizeof(struct twl6040_data), GFP_KERNEL); if (priv == NULL) @@ -1154,16 +1154,12 @@ static int twl6040_probe(struct snd_soc_codec *codec) priv->codec_powered = 0; /* enable only codec ready interrupt */ - twl6040_write(codec, TWL6040_REG_INTMR, - ~TWL6040_READYMSK & TWL6040_ALLINT_MSK); + intmr &= ~(TWL6040_READYMSK | TWL6040_PLUGMSK); /* reset interrupt status to allow correct power up sequence */ twl6040_read_reg_volatile(codec, TWL6040_REG_INTID); - } else { - /* no interrupts at all */ - twl6040_write_reg_cache(codec, TWL6040_REG_INTMR, - TWL6040_ALLINT_MSK); } + twl6040_write(codec, TWL6040_REG_INTMR, intmr); if (naudint) { /* audio interrupt */ diff --git a/sound/soc/codecs/twl6040.h b/sound/soc/codecs/twl6040.h index 67396f63c1ec..23aeed0963e6 100644 --- a/sound/soc/codecs/twl6040.h +++ b/sound/soc/codecs/twl6040.h @@ -79,6 +79,7 @@ /* INTMR (0x04) fields */ +#define TWL6040_PLUGMSK 0x02 #define TWL6040_READYMSK 0x40 #define TWL6040_ALLINT_MSK 0x7B -- cgit v1.2.2 From cbd9cb5de3182d688544611c019b06bf04e2ad06 Mon Sep 17 00:00:00 2001 From: Jorge Eduardo Candelaria Date: Fri, 10 Dec 2010 21:06:30 -0600 Subject: ASoC: twl6040: Increase timeout for power up After coming back from suspend, the timeout waiting for Phoenix chip to complete its power up sequence is not enough, which leaves the codec cache value for some registers in an outdated state. Increase the timeout value to wait for the power up sequence to correclty complete. Signed-off-by: Jorge Eduardo Candelaria Signed-off-by: Margarita Olaya Cabrera Acked-by: Mark Brown Signed-off-by: Liam Girdwood --- sound/soc/codecs/twl6040.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'sound/soc/codecs') diff --git a/sound/soc/codecs/twl6040.c b/sound/soc/codecs/twl6040.c index a8ec9113cc33..39f0bc5145c0 100644 --- a/sound/soc/codecs/twl6040.c +++ b/sound/soc/codecs/twl6040.c @@ -752,7 +752,7 @@ static int twl6040_power_up_completion(struct snd_soc_codec *codec, u8 intid; time_left = wait_for_completion_timeout(&priv->ready, - msecs_to_jiffies(48)); + msecs_to_jiffies(144)); if (!time_left) { twl_i2c_read_u8(TWL_MODULE_AUDIO_VOICE, &intid, -- cgit v1.2.2 From 9020808b4d9ff6b7eebb026492dba6a805309df8 Mon Sep 17 00:00:00 2001 From: "Olaya, Margarita" Date: Fri, 10 Dec 2010 21:06:39 -0600 Subject: ASoC: twl6040: Fix TLV dB step values for gains Some gains were incorrectly configured for dB values. Signed-off-by: Margarita Olaya Cabrera Acked-by: Mark Brown Signed-off-by: Liam Girdwood --- sound/soc/codecs/twl6040.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'sound/soc/codecs') diff --git a/sound/soc/codecs/twl6040.c b/sound/soc/codecs/twl6040.c index 39f0bc5145c0..b0ca9f9b70f7 100644 --- a/sound/soc/codecs/twl6040.c +++ b/sound/soc/codecs/twl6040.c @@ -471,9 +471,9 @@ static DECLARE_TLV_DB_SCALE(mic_preamp_tlv, -600, 600, 0); /* * MICGAIN volume control: - * from 6 to 30 dB in 6 dB steps + * from -6 to 30 dB in 6 dB steps */ -static DECLARE_TLV_DB_SCALE(mic_amp_tlv, 600, 600, 0); +static DECLARE_TLV_DB_SCALE(mic_amp_tlv, -600, 600, 0); /* * AFMGAIN volume control: -- cgit v1.2.2 From 53a9ef15df8c0dc688fae33277a252f0dd2faf2d Mon Sep 17 00:00:00 2001 From: Misael Lopez Cruz Date: Fri, 10 Dec 2010 21:06:34 -0600 Subject: ASoC: twl6040: Use correct offset for LineInAmp Right Gain for LineInAmp Right uses LINEGAIN[5:3], which means that offset for right channel should be 4. Signed-off-by: Misael Lopez Cruz Signed-off-by: Margarita Olaya Cabrera Acked-by: Mark Brown Signed-off-by: Liam Girdwood --- sound/soc/codecs/twl6040.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'sound/soc/codecs') diff --git a/sound/soc/codecs/twl6040.c b/sound/soc/codecs/twl6040.c index b0ca9f9b70f7..9dfe208e6539 100644 --- a/sound/soc/codecs/twl6040.c +++ b/sound/soc/codecs/twl6040.c @@ -566,7 +566,7 @@ static const struct snd_kcontrol_new twl6040_snd_controls[] = { /* AFM gains */ SOC_DOUBLE_TLV("Aux FM Volume", - TWL6040_REG_LINEGAIN, 0, 5, 0xF, 0, afm_amp_tlv), + TWL6040_REG_LINEGAIN, 0, 4, 0xF, 0, afm_amp_tlv), /* Playback gains */ SOC_DOUBLE_TLV("Headset Playback Volume", -- cgit v1.2.2 From 8ddab3f5107c3955e70e87a632d4d179ddba1189 Mon Sep 17 00:00:00 2001 From: Jarkko Nikula Date: Tue, 14 Dec 2010 12:18:30 +0200 Subject: ASoC: Move DAPM paths from DAPM context to snd_soc_card Decoupling DAPM paths from DAPM context is a first prerequisite when extending ASoC core to cross-device paths. This patch is almost a nullop and does not allow to construct cross-device setup but the path clean-up part in dapm_free_widgets is prepared to remove cross-device paths between a device being removed and others. Signed-off-by: Jarkko Nikula Acked-by: Liam Girdwood Signed-off-by: Mark Brown --- sound/soc/codecs/tlv320aic3x.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'sound/soc/codecs') diff --git a/sound/soc/codecs/tlv320aic3x.c b/sound/soc/codecs/tlv320aic3x.c index fc5abdf0bcb0..899af41787c1 100644 --- a/sound/soc/codecs/tlv320aic3x.c +++ b/sound/soc/codecs/tlv320aic3x.c @@ -185,7 +185,7 @@ static int snd_soc_dapm_put_volsw_aic3x(struct snd_kcontrol *kcontrol, if (snd_soc_test_bits(widget->codec, reg, val_mask, val)) { /* find dapm widget path assoc with kcontrol */ - list_for_each_entry(path, &widget->dapm->paths, list) { + list_for_each_entry(path, &widget->dapm->card->paths, list) { if (path->kcontrol != kcontrol) continue; -- cgit v1.2.2 From 97c866defc0fc6e18b49603ac19f732f53e79c46 Mon Sep 17 00:00:00 2001 From: Jarkko Nikula Date: Tue, 14 Dec 2010 12:18:31 +0200 Subject: ASoC: Move widgets from DAPM context to snd_soc_card Decoupling widgets from DAPM context is required when extending the ASoC core to cross-device paths. Even the list of widgets are now kept in struct snd_soc_card, the widget listing in sysfs and debugs remain sorted per device. This patch makes possible to build cross-device paths but does not extend yet the DAPM to handle codec bias and widget power changes of an another device. Cross-device paths are registered by listing the widgets from device A in a map for device B. In case of conflicting widget names between the devices, a uniform name prefix is needed to separate them. See commit ead9b91 "ASoC: Add optional name_prefix for kcontrol, widget and route names" for help. An example below shows a path that connects MONO out of A into Line In of B: static const struct snd_soc_dapm_route mapA[] = { {"MONO", NULL, "DAC"}, }; static const struct snd_soc_dapm_route mapB[] = { {"Line In", NULL, "MONO"}, }; Signed-off-by: Jarkko Nikula Acked-by: Liam Girdwood Signed-off-by: Mark Brown --- sound/soc/codecs/wm8960.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'sound/soc/codecs') diff --git a/sound/soc/codecs/wm8960.c b/sound/soc/codecs/wm8960.c index 2c5712dce1d5..054f5737319c 100644 --- a/sound/soc/codecs/wm8960.c +++ b/sound/soc/codecs/wm8960.c @@ -418,7 +418,9 @@ static int wm8960_add_widgets(struct snd_soc_codec *codec) * list each time to find the desired power state do so now * and save the result. */ - list_for_each_entry(w, &codec->dapm.widgets, list) { + list_for_each_entry(w, &codec->card->widgets, list) { + if (w->dapm != &codec->dapm) + continue; if (strcmp(w->name, "LOUT1 PGA") == 0) wm8960->lout1 = w; if (strcmp(w->name, "ROUT1 PGA") == 0) -- cgit v1.2.2 From 65b7cecc85b9bb7bb8ce74c6a3b280464b00c86c Mon Sep 17 00:00:00 2001 From: "Olaya, Margarita" Date: Tue, 14 Dec 2010 19:18:36 -0600 Subject: ASoC: twl6040: Set default gains to minimun value Updated default values to improve power consumption. Signed-off-by: Jorge Eduardo Candelaria Signed-off-by: Margarita Olaya Cabrera Acked-by: Mark Brown Signed-off-by: Liam Girdwood --- sound/soc/codecs/twl6040.c | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'sound/soc/codecs') diff --git a/sound/soc/codecs/twl6040.c b/sound/soc/codecs/twl6040.c index 9dfe208e6539..b252cf8f0ce1 100644 --- a/sound/soc/codecs/twl6040.c +++ b/sound/soc/codecs/twl6040.c @@ -806,6 +806,15 @@ static int twl6040_set_bias_level(struct snd_soc_codec *codec, /* initialize vdd/vss registers with reg_cache */ twl6040_init_vdd_regs(codec); + + /* Set external boost GPO */ + twl6040_write(codec, TWL6040_REG_GPOCTL, 0x02); + + /* Set initial minimal gain values */ + twl6040_write(codec, TWL6040_REG_HSGAIN, 0xFF); + twl6040_write(codec, TWL6040_REG_EARCTL, 0x1E); + twl6040_write(codec, TWL6040_REG_HFLGAIN, 0x1D); + twl6040_write(codec, TWL6040_REG_HFRGAIN, 0x1D); break; case SND_SOC_BIAS_OFF: if (!priv->codec_powered) -- cgit v1.2.2 From 1bf84759bdcc08933b22ee70722f1575ad84f9b9 Mon Sep 17 00:00:00 2001 From: Margarita Olaya Cabrera Date: Tue, 14 Dec 2010 19:00:21 -0600 Subject: ASoC: twl6040: Add ramp up/down volume for HS and HF Add ramp functions for the headset and handsfree outputs in order to reduce the pops during power on/off sequences. In order to give more control to volume ramp, step size and delay between steps can be specified. The patches are based on wm8350 implementation from Liam Girdwood. Signed-off-by: Margarita Olaya Cabrera Signed-off-by: Misael Lopez Cruz Acked-by: Mark Brown Signed-off-by: Liam Girdwood --- sound/soc/codecs/twl6040.c | 533 ++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 521 insertions(+), 12 deletions(-) (limited to 'sound/soc/codecs') diff --git a/sound/soc/codecs/twl6040.c b/sound/soc/codecs/twl6040.c index b252cf8f0ce1..2f68f5949a63 100644 --- a/sound/soc/codecs/twl6040.c +++ b/sound/soc/codecs/twl6040.c @@ -40,7 +40,35 @@ #include "twl6040.h" #define TWL6040_RATES SNDRV_PCM_RATE_8000_96000 -#define TWL6040_FORMATS (SNDRV_PCM_FMTBIT_S32_LE) +#define TWL6040_FORMATS (SNDRV_PCM_FMTBIT_S32_LE) + +#define TWL6040_OUTHS_0dB 0x00 +#define TWL6040_OUTHS_M30dB 0x0F +#define TWL6040_OUTHF_0dB 0x03 +#define TWL6040_OUTHF_M52dB 0x1D + +#define TWL6040_RAMP_NONE 0 +#define TWL6040_RAMP_UP 1 +#define TWL6040_RAMP_DOWN 2 + +#define TWL6040_HSL_VOL_MASK 0x0F +#define TWL6040_HSL_VOL_SHIFT 0 +#define TWL6040_HSR_VOL_MASK 0xF0 +#define TWL6040_HSR_VOL_SHIFT 4 +#define TWL6040_HF_VOL_MASK 0x1F +#define TWL6040_HF_VOL_SHIFT 0 + +struct twl6040_output { + u16 active; + u16 left_vol; + u16 right_vol; + u16 left_step; + u16 right_step; + unsigned int step_delay; + u16 ramp; + u16 mute; + struct completion ramp_done; +}; struct twl6040_jack_data { struct snd_soc_jack *jack; @@ -62,6 +90,12 @@ struct twl6040_data { struct workqueue_struct *workqueue; struct delayed_work delayed_work; struct mutex mutex; + struct twl6040_output headset; + struct twl6040_output handsfree; + struct workqueue_struct *hf_workqueue; + struct workqueue_struct *hs_workqueue; + struct delayed_work hs_delayed_work; + struct delayed_work hf_delayed_work; }; /* @@ -263,6 +297,305 @@ static void twl6040_init_vdd_regs(struct snd_soc_codec *codec) } } +/* + * Ramp HS PGA volume to minimise pops at stream startup and shutdown. + */ +static inline int twl6040_hs_ramp_step(struct snd_soc_codec *codec, + unsigned int left_step, unsigned int right_step) +{ + + struct twl6040_data *priv = snd_soc_codec_get_drvdata(codec); + struct twl6040_output *headset = &priv->headset; + int left_complete = 0, right_complete = 0; + u8 reg, val; + + /* left channel */ + left_step = (left_step > 0xF) ? 0xF : left_step; + reg = twl6040_read_reg_cache(codec, TWL6040_REG_HSGAIN); + val = (~reg & TWL6040_HSL_VOL_MASK); + + if (headset->ramp == TWL6040_RAMP_UP) { + /* ramp step up */ + if (val < headset->left_vol) { + val += left_step; + reg &= ~TWL6040_HSL_VOL_MASK; + twl6040_write(codec, TWL6040_REG_HSGAIN, + (reg | (~val & TWL6040_HSL_VOL_MASK))); + } else { + left_complete = 1; + } + } else if (headset->ramp == TWL6040_RAMP_DOWN) { + /* ramp step down */ + if (val > 0x0) { + val -= left_step; + reg &= ~TWL6040_HSL_VOL_MASK; + twl6040_write(codec, TWL6040_REG_HSGAIN, reg | + (~val & TWL6040_HSL_VOL_MASK)); + } else { + left_complete = 1; + } + } + + /* right channel */ + right_step = (right_step > 0xF) ? 0xF : right_step; + reg = twl6040_read_reg_cache(codec, TWL6040_REG_HSGAIN); + val = (~reg & TWL6040_HSR_VOL_MASK) >> TWL6040_HSR_VOL_SHIFT; + + if (headset->ramp == TWL6040_RAMP_UP) { + /* ramp step up */ + if (val < headset->right_vol) { + val += right_step; + reg &= ~TWL6040_HSR_VOL_MASK; + twl6040_write(codec, TWL6040_REG_HSGAIN, + (reg | (~val << TWL6040_HSR_VOL_SHIFT))); + } else { + right_complete = 1; + } + } else if (headset->ramp == TWL6040_RAMP_DOWN) { + /* ramp step down */ + if (val > 0x0) { + val -= right_step; + reg &= ~TWL6040_HSR_VOL_MASK; + twl6040_write(codec, TWL6040_REG_HSGAIN, + reg | (~val << TWL6040_HSR_VOL_SHIFT)); + } else { + right_complete = 1; + } + } + + return left_complete & right_complete; +} + +/* + * Ramp HF PGA volume to minimise pops at stream startup and shutdown. + */ +static inline int twl6040_hf_ramp_step(struct snd_soc_codec *codec, + unsigned int left_step, unsigned int right_step) +{ + struct twl6040_data *priv = snd_soc_codec_get_drvdata(codec); + struct twl6040_output *handsfree = &priv->handsfree; + int left_complete = 0, right_complete = 0; + u16 reg, val; + + /* left channel */ + left_step = (left_step > 0x1D) ? 0x1D : left_step; + reg = twl6040_read_reg_cache(codec, TWL6040_REG_HFLGAIN); + reg = 0x1D - reg; + val = (reg & TWL6040_HF_VOL_MASK); + if (handsfree->ramp == TWL6040_RAMP_UP) { + /* ramp step up */ + if (val < handsfree->left_vol) { + val += left_step; + reg &= ~TWL6040_HF_VOL_MASK; + twl6040_write(codec, TWL6040_REG_HFLGAIN, + reg | (0x1D - val)); + } else { + left_complete = 1; + } + } else if (handsfree->ramp == TWL6040_RAMP_DOWN) { + /* ramp step down */ + if (val > 0) { + val -= left_step; + reg &= ~TWL6040_HF_VOL_MASK; + twl6040_write(codec, TWL6040_REG_HFLGAIN, + reg | (0x1D - val)); + } else { + left_complete = 1; + } + } + + /* right channel */ + right_step = (right_step > 0x1D) ? 0x1D : right_step; + reg = twl6040_read_reg_cache(codec, TWL6040_REG_HFRGAIN); + reg = 0x1D - reg; + val = (reg & TWL6040_HF_VOL_MASK); + if (handsfree->ramp == TWL6040_RAMP_UP) { + /* ramp step up */ + if (val < handsfree->right_vol) { + val += right_step; + reg &= ~TWL6040_HF_VOL_MASK; + twl6040_write(codec, TWL6040_REG_HFRGAIN, + reg | (0x1D - val)); + } else { + right_complete = 1; + } + } else if (handsfree->ramp == TWL6040_RAMP_DOWN) { + /* ramp step down */ + if (val > 0) { + val -= right_step; + reg &= ~TWL6040_HF_VOL_MASK; + twl6040_write(codec, TWL6040_REG_HFRGAIN, + reg | (0x1D - val)); + } + } + + return left_complete & right_complete; +} + +/* + * This work ramps both output PGAs at stream start/stop time to + * minimise pop associated with DAPM power switching. + */ +static void twl6040_pga_hs_work(struct work_struct *work) +{ + struct twl6040_data *priv = + container_of(work, struct twl6040_data, hs_delayed_work.work); + struct snd_soc_codec *codec = priv->codec; + struct twl6040_output *headset = &priv->headset; + unsigned int delay = headset->step_delay; + int i, headset_complete; + + /* do we need to ramp at all ? */ + if (headset->ramp == TWL6040_RAMP_NONE) + return; + + /* HS PGA volumes have 4 bits of resolution to ramp */ + for (i = 0; i <= 16; i++) { + headset_complete = 1; + if (headset->ramp != TWL6040_RAMP_NONE) + headset_complete = twl6040_hs_ramp_step(codec, + headset->left_step, + headset->right_step); + + /* ramp finished ? */ + if (headset_complete) + break; + + /* + * TODO: tune: delay is longer over 0dB + * as increases are larger. + */ + if (i >= 8) + schedule_timeout_interruptible(msecs_to_jiffies(delay + + (delay >> 1))); + else + schedule_timeout_interruptible(msecs_to_jiffies(delay)); + } + + if (headset->ramp == TWL6040_RAMP_DOWN) { + headset->active = 0; + complete(&headset->ramp_done); + } else { + headset->active = 1; + } + headset->ramp = TWL6040_RAMP_NONE; +} + +static void twl6040_pga_hf_work(struct work_struct *work) +{ + struct twl6040_data *priv = + container_of(work, struct twl6040_data, hf_delayed_work.work); + struct snd_soc_codec *codec = priv->codec; + struct twl6040_output *handsfree = &priv->handsfree; + unsigned int delay = handsfree->step_delay; + int i, handsfree_complete; + + /* do we need to ramp at all ? */ + if (handsfree->ramp == TWL6040_RAMP_NONE) + return; + + /* HF PGA volumes have 5 bits of resolution to ramp */ + for (i = 0; i <= 32; i++) { + handsfree_complete = 1; + if (handsfree->ramp != TWL6040_RAMP_NONE) + handsfree_complete = twl6040_hf_ramp_step(codec, + handsfree->left_step, + handsfree->right_step); + + /* ramp finished ? */ + if (handsfree_complete) + break; + + /* + * TODO: tune: delay is longer over 0dB + * as increases are larger. + */ + if (i >= 16) + schedule_timeout_interruptible(msecs_to_jiffies(delay + + (delay >> 1))); + else + schedule_timeout_interruptible(msecs_to_jiffies(delay)); + } + + + if (handsfree->ramp == TWL6040_RAMP_DOWN) { + handsfree->active = 0; + complete(&handsfree->ramp_done); + } else + handsfree->active = 1; + handsfree->ramp = TWL6040_RAMP_NONE; +} + +static int pga_event(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, int event) +{ + struct snd_soc_codec *codec = w->codec; + struct twl6040_data *priv = snd_soc_codec_get_drvdata(codec); + struct twl6040_output *out; + struct delayed_work *work; + struct workqueue_struct *queue; + + switch (w->shift) { + case 2: + case 3: + out = &priv->headset; + work = &priv->hs_delayed_work; + queue = priv->hs_workqueue; + out->step_delay = 5; /* 5 ms between volume ramp steps */ + break; + case 4: + out = &priv->handsfree; + work = &priv->hf_delayed_work; + queue = priv->hf_workqueue; + out->step_delay = 5; /* 5 ms between volume ramp steps */ + if (SND_SOC_DAPM_EVENT_ON(event)) + priv->non_lp++; + else + priv->non_lp--; + break; + default: + return -1; + } + + switch (event) { + case SND_SOC_DAPM_POST_PMU: + if (out->active) + break; + + /* don't use volume ramp for power-up */ + out->left_step = out->left_vol; + out->right_step = out->right_vol; + + if (!delayed_work_pending(work)) { + out->ramp = TWL6040_RAMP_UP; + queue_delayed_work(queue, work, + msecs_to_jiffies(1)); + } + break; + + case SND_SOC_DAPM_PRE_PMD: + if (!out->active) + break; + + if (!delayed_work_pending(work)) { + /* use volume ramp for power-down */ + out->left_step = 1; + out->right_step = 1; + out->ramp = TWL6040_RAMP_DOWN; + INIT_COMPLETION(out->ramp_done); + + queue_delayed_work(queue, work, + msecs_to_jiffies(1)); + + wait_for_completion_timeout(&out->ramp_done, + msecs_to_jiffies(2000)); + } + break; + } + + return 0; +} + /* twl6040 codec manual power-up sequence */ static void twl6040_power_up(struct snd_soc_codec *codec) { @@ -463,6 +796,156 @@ static irqreturn_t twl6040_naudint_handler(int irq, void *data) return IRQ_HANDLED; } +static int twl6040_put_volsw(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); + struct twl6040_data *twl6040_priv = snd_soc_codec_get_drvdata(codec); + struct twl6040_output *out = NULL; + struct soc_mixer_control *mc = + (struct soc_mixer_control *)kcontrol->private_value; + int ret; + unsigned int reg = mc->reg; + + /* For HS and HF we shadow the values and only actually write + * them out when active in order to ensure the amplifier comes on + * as quietly as possible. */ + switch (reg) { + case TWL6040_REG_HSGAIN: + out = &twl6040_priv->headset; + break; + default: + break; + } + + if (out) { + out->left_vol = ucontrol->value.integer.value[0]; + out->right_vol = ucontrol->value.integer.value[1]; + if (!out->active) + return 1; + } + + ret = snd_soc_put_volsw(kcontrol, ucontrol); + if (ret < 0) + return ret; + + return 1; +} + +static int twl6040_get_volsw(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); + struct twl6040_data *twl6040_priv = snd_soc_codec_get_drvdata(codec); + struct twl6040_output *out = &twl6040_priv->headset; + struct soc_mixer_control *mc = + (struct soc_mixer_control *)kcontrol->private_value; + unsigned int reg = mc->reg; + + switch (reg) { + case TWL6040_REG_HSGAIN: + out = &twl6040_priv->headset; + ucontrol->value.integer.value[0] = out->left_vol; + ucontrol->value.integer.value[1] = out->right_vol; + return 0; + + default: + break; + } + + return snd_soc_get_volsw(kcontrol, ucontrol); +} + +static int twl6040_put_volsw_2r_vu(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); + struct twl6040_data *twl6040_priv = snd_soc_codec_get_drvdata(codec); + struct twl6040_output *out = NULL; + struct soc_mixer_control *mc = + (struct soc_mixer_control *)kcontrol->private_value; + int ret; + unsigned int reg = mc->reg; + + /* For HS and HF we shadow the values and only actually write + * them out when active in order to ensure the amplifier comes on + * as quietly as possible. */ + switch (reg) { + case TWL6040_REG_HFLGAIN: + case TWL6040_REG_HFRGAIN: + out = &twl6040_priv->handsfree; + break; + default: + break; + } + + if (out) { + out->left_vol = ucontrol->value.integer.value[0]; + out->right_vol = ucontrol->value.integer.value[1]; + if (!out->active) + return 1; + } + + ret = snd_soc_put_volsw_2r(kcontrol, ucontrol); + if (ret < 0) + return ret; + + return 1; +} + +static int twl6040_get_volsw_2r(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); + struct twl6040_data *twl6040_priv = snd_soc_codec_get_drvdata(codec); + struct twl6040_output *out = &twl6040_priv->handsfree; + struct soc_mixer_control *mc = + (struct soc_mixer_control *)kcontrol->private_value; + unsigned int reg = mc->reg; + + /* If these are cached registers use the cache */ + switch (reg) { + case TWL6040_REG_HFLGAIN: + case TWL6040_REG_HFRGAIN: + out = &twl6040_priv->handsfree; + ucontrol->value.integer.value[0] = out->left_vol; + ucontrol->value.integer.value[1] = out->right_vol; + return 0; + + default: + break; + } + + return snd_soc_get_volsw_2r(kcontrol, ucontrol); +} + +/* double control with volume update */ +#define SOC_TWL6040_DOUBLE_TLV(xname, xreg, shift_left, shift_right, xmax,\ + xinvert, tlv_array)\ +{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname),\ + .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\ + SNDRV_CTL_ELEM_ACCESS_READWRITE,\ + .tlv.p = (tlv_array), \ + .info = snd_soc_info_volsw, .get = twl6040_get_volsw, \ + .put = twl6040_put_volsw, \ + .private_value = (unsigned long)&(struct soc_mixer_control) \ + {.reg = xreg, .shift = shift_left, .rshift = shift_right,\ + .max = xmax, .platform_max = xmax, .invert = xinvert} } + +/* double control with volume update */ +#define SOC_TWL6040_DOUBLE_R_TLV(xname, reg_left, reg_right, xshift, xmax,\ + xinvert, tlv_array)\ +{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname),\ + .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ | \ + SNDRV_CTL_ELEM_ACCESS_READWRITE | \ + SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ + .tlv.p = (tlv_array), \ + .info = snd_soc_info_volsw_2r, \ + .get = twl6040_get_volsw_2r, .put = twl6040_put_volsw_2r_vu, \ + .private_value = (unsigned long)&(struct soc_mixer_control) \ + {.reg = reg_left, .rreg = reg_right, .shift = xshift, \ + .rshift = xshift, .max = xmax, .invert = xinvert}, } + /* * MICATT volume control: * from -6 to 0 dB in 6 dB steps @@ -569,9 +1052,9 @@ static const struct snd_kcontrol_new twl6040_snd_controls[] = { TWL6040_REG_LINEGAIN, 0, 4, 0xF, 0, afm_amp_tlv), /* Playback gains */ - SOC_DOUBLE_TLV("Headset Playback Volume", + SOC_TWL6040_DOUBLE_TLV("Headset Playback Volume", TWL6040_REG_HSGAIN, 0, 4, 0xF, 1, hs_tlv), - SOC_DOUBLE_R_TLV("Handsfree Playback Volume", + SOC_TWL6040_DOUBLE_R_TLV("Handsfree Playback Volume", TWL6040_REG_HFLGAIN, TWL6040_REG_HFRGAIN, 0, 0x1D, 1, hf_tlv), SOC_SINGLE_TLV("Earphone Playback Volume", TWL6040_REG_EARCTL, 1, 0xF, 1, ep_tlv), @@ -657,16 +1140,20 @@ static const struct snd_soc_dapm_widget twl6040_dapm_widgets[] = { /* Analog playback drivers */ SND_SOC_DAPM_PGA_E("Handsfree Left Driver", TWL6040_REG_HFLCTL, 4, 0, NULL, 0, - twl6040_power_mode_event, - SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), + pga_event, + SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), SND_SOC_DAPM_PGA_E("Handsfree Right Driver", TWL6040_REG_HFRCTL, 4, 0, NULL, 0, - twl6040_power_mode_event, - SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), - SND_SOC_DAPM_PGA("Headset Left Driver", - TWL6040_REG_HSLCTL, 2, 0, NULL, 0), - SND_SOC_DAPM_PGA("Headset Right Driver", - TWL6040_REG_HSRCTL, 2, 0, NULL, 0), + pga_event, + SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), + SND_SOC_DAPM_PGA_E("Headset Left Driver", + TWL6040_REG_HSLCTL, 2, 0, NULL, 0, + pga_event, + SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), + SND_SOC_DAPM_PGA_E("Headset Right Driver", + TWL6040_REG_HSRCTL, 2, 0, NULL, 0, + pga_event, + SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), SND_SOC_DAPM_SWITCH_E("Earphone Driver", SND_SOC_NOPM, 0, 0, &ep_driver_switch_controls, twl6040_power_mode_event, @@ -1150,6 +1637,8 @@ static int twl6040_probe(struct snd_soc_codec *codec) mutex_init(&priv->mutex); init_completion(&priv->ready); + init_completion(&priv->headset.ramp_done); + init_completion(&priv->handsfree.ramp_done); if (gpio_is_valid(audpwron)) { ret = gpio_request(audpwron, "audpwron"); @@ -1183,10 +1672,24 @@ static int twl6040_probe(struct snd_soc_codec *codec) /* init vio registers */ twl6040_init_vio_regs(codec); + priv->hf_workqueue = create_singlethread_workqueue("twl6040-hf"); + if (priv->hf_workqueue == NULL) { + ret = -ENOMEM; + goto irq_err; + } + priv->hs_workqueue = create_singlethread_workqueue("twl6040-hs"); + if (priv->hs_workqueue == NULL) { + ret = -ENOMEM; + goto wq_err; + } + + INIT_DELAYED_WORK(&priv->hs_delayed_work, twl6040_pga_hs_work); + INIT_DELAYED_WORK(&priv->hf_delayed_work, twl6040_pga_hf_work); + /* power on device */ ret = twl6040_set_bias_level(codec, SND_SOC_BIAS_STANDBY); if (ret) - goto irq_err; + goto bias_err; snd_soc_add_controls(codec, twl6040_snd_controls, ARRAY_SIZE(twl6040_snd_controls)); @@ -1194,6 +1697,10 @@ static int twl6040_probe(struct snd_soc_codec *codec) return 0; +bias_err: + destroy_workqueue(priv->hs_workqueue); +wq_err: + destroy_workqueue(priv->hf_workqueue); irq_err: if (naudint) free_irq(naudint, codec); @@ -1222,6 +1729,8 @@ static int twl6040_remove(struct snd_soc_codec *codec) free_irq(naudint, codec); destroy_workqueue(priv->workqueue); + destroy_workqueue(priv->hf_workqueue); + destroy_workqueue(priv->hs_workqueue); kfree(priv); return 0; -- cgit v1.2.2 From 0bb140f8d94dd683fab248a3216dd5d0e792d41f Mon Sep 17 00:00:00 2001 From: Mark Brown Date: Mon, 20 Dec 2010 20:53:25 +0000 Subject: ASoC: Remove some unused defines from WM8903 These would have been used if we'd done manual clock divider setup, but we didn't. Signed-off-by: Mark Brown Acked-by: Liam Girdwood --- sound/soc/codecs/wm8903.h | 4 ---- 1 file changed, 4 deletions(-) (limited to 'sound/soc/codecs') diff --git a/sound/soc/codecs/wm8903.h b/sound/soc/codecs/wm8903.h index 996435e681e5..e47b8c8be921 100644 --- a/sound/soc/codecs/wm8903.h +++ b/sound/soc/codecs/wm8903.h @@ -19,10 +19,6 @@ extern int wm8903_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack, int det, int shrt); -#define WM8903_MCLK_DIV_2 1 -#define WM8903_CLK_SYS 2 -#define WM8903_BCLK 3 -#define WM8903_LRCLK 4 /* * Register values. -- cgit v1.2.2 From 458350b31f4f7a4d1db0c268cf1cced5afeeb8a5 Mon Sep 17 00:00:00 2001 From: Mark Brown Date: Mon, 20 Dec 2010 14:35:09 +0000 Subject: ASoC: Fix WM8994/58 3D stereo control definitions Cut'n'paste in the register names. Signed-off-by: Mark Brown Acked-by: Liam Girdwood --- sound/soc/codecs/wm8994.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'sound/soc/codecs') diff --git a/sound/soc/codecs/wm8994.c b/sound/soc/codecs/wm8994.c index af104acd75f8..e1a775bd83fa 100644 --- a/sound/soc/codecs/wm8994.c +++ b/sound/soc/codecs/wm8994.c @@ -869,15 +869,15 @@ SOC_SINGLE_TLV("SPKR DAC1 Volume", WM8994_SPKMIXR_ATTENUATION, SOC_SINGLE_TLV("AIF1DAC1 3D Stereo Volume", WM8994_AIF1_DAC1_FILTERS_2, 10, 15, 0, wm8994_3d_tlv), -SOC_SINGLE("AIF1DAC1 3D Stereo Switch", WM8994_AIF1_DAC2_FILTERS_2, +SOC_SINGLE("AIF1DAC1 3D Stereo Switch", WM8994_AIF1_DAC1_FILTERS_2, 8, 1, 0), SOC_SINGLE_TLV("AIF1DAC2 3D Stereo Volume", WM8994_AIF1_DAC2_FILTERS_2, 10, 15, 0, wm8994_3d_tlv), SOC_SINGLE("AIF1DAC2 3D Stereo Switch", WM8994_AIF1_DAC2_FILTERS_2, 8, 1, 0), -SOC_SINGLE_TLV("AIF2DAC 3D Stereo Volume", WM8994_AIF1_DAC1_FILTERS_2, +SOC_SINGLE_TLV("AIF2DAC 3D Stereo Volume", WM8994_AIF2_DAC_FILTERS_2, 10, 15, 0, wm8994_3d_tlv), -SOC_SINGLE("AIF2DAC 3D Stereo Switch", WM8994_AIF1_DAC2_FILTERS_2, +SOC_SINGLE("AIF2DAC 3D Stereo Switch", WM8994_AIF2_DAC_FILTERS_2, 8, 1, 0), }; -- cgit v1.2.2 From 6d3c26bcb7a129a11a54d78644e264ec872547e1 Mon Sep 17 00:00:00 2001 From: Mark Brown Date: Sun, 5 Dec 2010 12:41:52 +0000 Subject: ASoC: Use delayed work to debounce WM8350 jack IRQs This avoids blocking the IRQ thread and allows further bounces to extend the debounce time. Signed-off-by: Mark Brown Acked-by: Liam Girdwood --- sound/soc/codecs/wm8350.c | 62 ++++++++++++++++++++++++++++++++--------------- 1 file changed, 43 insertions(+), 19 deletions(-) (limited to 'sound/soc/codecs') diff --git a/sound/soc/codecs/wm8350.c b/sound/soc/codecs/wm8350.c index 07ba7e3f6a8c..3e0362e62f8f 100644 --- a/sound/soc/codecs/wm8350.c +++ b/sound/soc/codecs/wm8350.c @@ -53,6 +53,7 @@ struct wm8350_output { struct wm8350_jack_data { struct snd_soc_jack *jack; + struct delayed_work work; int report; int short_report; }; @@ -1335,45 +1336,63 @@ static int wm8350_resume(struct snd_soc_codec *codec) return 0; } -static irqreturn_t wm8350_hp_jack_handler(int irq, void *data) +static void wm8350_hp_work(struct wm8350_data *priv, + struct wm8350_jack_data *jack, + u16 mask) { - struct wm8350_data *priv = data; struct wm8350 *wm8350 = priv->codec.control_data; u16 reg; int report; - int mask; + + reg = wm8350_reg_read(wm8350, WM8350_JACK_PIN_STATUS); + if (reg & mask) + report = jack->report; + else + report = 0; + + snd_soc_jack_report(jack->jack, report, jack->report); + +} + +static void wm8350_hpl_work(struct work_struct *work) +{ + struct wm8350_data *priv = + container_of(work, struct wm8350_data, hpl.work.work); + + wm8350_hp_work(priv, &priv->hpl, WM8350_JACK_L_LVL); +} + +static void wm8350_hpr_work(struct work_struct *work) +{ + struct wm8350_data *priv = + container_of(work, struct wm8350_data, hpr.work.work); + + wm8350_hp_work(priv, &priv->hpr, WM8350_JACK_R_LVL); +} + +static irqreturn_t wm8350_hp_jack_handler(int irq, void *data) +{ + struct wm8350_data *priv = data; + struct wm8350 *wm8350 = priv->codec.control_data; struct wm8350_jack_data *jack = NULL; switch (irq - wm8350->irq_base) { case WM8350_IRQ_CODEC_JCK_DET_L: jack = &priv->hpl; - mask = WM8350_JACK_L_LVL; break; case WM8350_IRQ_CODEC_JCK_DET_R: jack = &priv->hpr; - mask = WM8350_JACK_R_LVL; break; default: BUG(); } - if (!jack->jack) { - dev_warn(wm8350->dev, "Jack interrupt called with no jack\n"); - return IRQ_NONE; - } + if (device_may_wakeup(wm8350->dev)) + pm_wakeup_event(wm8350->dev, 250); - /* Debounce */ - msleep(200); - - reg = wm8350_reg_read(wm8350, WM8350_JACK_PIN_STATUS); - if (reg & mask) - report = jack->report; - else - report = 0; - - snd_soc_jack_report(jack->jack, report, jack->report); + schedule_delayed_work(&jack->work, 200); return IRQ_HANDLED; } @@ -1552,6 +1571,8 @@ static int wm8350_codec_probe(struct snd_soc_codec *codec) wm8350_clear_bits(wm8350, WM8350_POWER_MGMT_5, WM8350_CODEC_ENA); INIT_DELAYED_WORK(&codec->dapm.delayed_work, wm8350_pga_work); + INIT_DELAYED_WORK(&priv->hpl.work, wm8350_hpl_work); + INIT_DELAYED_WORK(&priv->hpr.work, wm8350_hpr_work); /* Enable the codec */ wm8350_set_bits(wm8350, WM8350_POWER_MGMT_5, WM8350_CODEC_ENA); @@ -1641,6 +1662,9 @@ static int wm8350_codec_remove(struct snd_soc_codec *codec) priv->hpr.jack = NULL; priv->mic.jack = NULL; + cancel_delayed_work_sync(&priv->hpl.work); + cancel_delayed_work_sync(&priv->hpr.work); + /* if there was any work waiting then we run it now and * wait for its completion */ flush_delayed_work_sync(&codec->dapm.delayed_work); -- cgit v1.2.2 From 2bbb5d667958f20ef8e7f7b37f9acced6dac0b98 Mon Sep 17 00:00:00 2001 From: Mark Brown Date: Sun, 5 Dec 2010 12:50:12 +0000 Subject: ASoC: Trace Wolfson jack detection IRQs Add jack detection interrupt trace to Wolfson CODEC drivers. Signed-off-by: Mark Brown Acked-by: Liam Girdwood --- sound/soc/codecs/wm8350.c | 5 +++++ sound/soc/codecs/wm8903.c | 4 ++++ sound/soc/codecs/wm8962.c | 3 +++ sound/soc/codecs/wm8994.c | 5 +++++ 4 files changed, 17 insertions(+) (limited to 'sound/soc/codecs') diff --git a/sound/soc/codecs/wm8350.c b/sound/soc/codecs/wm8350.c index 3e0362e62f8f..82d877df3fb0 100644 --- a/sound/soc/codecs/wm8350.c +++ b/sound/soc/codecs/wm8350.c @@ -26,6 +26,7 @@ #include #include #include +#include #include "wm8350.h" @@ -1378,10 +1379,12 @@ static irqreturn_t wm8350_hp_jack_handler(int irq, void *data) switch (irq - wm8350->irq_base) { case WM8350_IRQ_CODEC_JCK_DET_L: + trace_snd_soc_jack_irq("WM8350 HPL"); jack = &priv->hpl; break; case WM8350_IRQ_CODEC_JCK_DET_R: + trace_snd_soc_jack_irq("WM8350 HPR"); jack = &priv->hpr; break; @@ -1456,6 +1459,8 @@ static irqreturn_t wm8350_mic_handler(int irq, void *data) u16 reg; int report = 0; + trace_snd_soc_jack_irq("WM8350 mic"); + reg = wm8350_reg_read(wm8350, WM8350_JACK_PIN_STATUS); if (reg & WM8350_JACK_MICSCD_LVL) report |= priv->mic.short_report; diff --git a/sound/soc/codecs/wm8903.c b/sound/soc/codecs/wm8903.c index d015745a886b..b32699bc1927 100644 --- a/sound/soc/codecs/wm8903.c +++ b/sound/soc/codecs/wm8903.c @@ -31,6 +31,7 @@ #include #include #include +#include #include "wm8903.h" @@ -1533,6 +1534,9 @@ static irqreturn_t wm8903_irq(int irq, void *data) mic_report = wm8903->mic_last_report; int_pol = snd_soc_read(codec, WM8903_INTERRUPT_POLARITY_1); + if (int_val & (WM8903_MICSHRT_EINT | WM8903_MICDET_EINT)) + trace_snd_soc_jack_irq(dev_name(codec->dev)); + if (int_val & WM8903_MICSHRT_EINT) { dev_dbg(codec->dev, "Microphone short (pol=%x)\n", int_pol); diff --git a/sound/soc/codecs/wm8962.c b/sound/soc/codecs/wm8962.c index f0c9d2691842..a24f83d604c9 100644 --- a/sound/soc/codecs/wm8962.c +++ b/sound/soc/codecs/wm8962.c @@ -32,6 +32,7 @@ #include #include #include +#include #include "wm8962.h" @@ -3353,6 +3354,8 @@ static irqreturn_t wm8962_irq(int irq, void *data) if (active & (WM8962_MICSCD_EINT | WM8962_MICD_EINT)) { dev_dbg(codec->dev, "Microphone event detected\n"); + trace_snd_soc_jack_irq(dev_name(codec->dev)); + pm_wakeup_event(codec->dev, 300); schedule_delayed_work(&wm8962->mic_work, diff --git a/sound/soc/codecs/wm8994.c b/sound/soc/codecs/wm8994.c index e1a775bd83fa..067a532bed15 100644 --- a/sound/soc/codecs/wm8994.c +++ b/sound/soc/codecs/wm8994.c @@ -28,6 +28,7 @@ #include #include #include +#include #include #include @@ -2755,6 +2756,8 @@ static irqreturn_t wm8994_mic_irq(int irq, void *data) int reg; int report; + trace_snd_soc_jack_irq(dev_name(codec->dev)); + reg = snd_soc_read(codec, WM8994_INTERRUPT_RAW_STATUS_2); if (reg < 0) { dev_err(codec->dev, "Failed to read microphone status: %d\n", @@ -2901,6 +2904,8 @@ static irqreturn_t wm8958_mic_irq(int irq, void *data) goto out; } + trace_snd_soc_jack_irq(dev_name(codec->dev)); + if (wm8994->jack_cb) wm8994->jack_cb(reg, wm8994->jack_cb_data); else -- cgit v1.2.2 From 1c9e9795b5e2348df619fd6010d7583dc9b8c811 Mon Sep 17 00:00:00 2001 From: Mark Brown Date: Sun, 5 Dec 2010 12:53:08 +0000 Subject: ASoC: Add jack IRQ trace to 88pm860x driver Signed-off-by: Mark Brown Acked-by: Liam Girdwood --- sound/soc/codecs/88pm860x-codec.c | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'sound/soc/codecs') diff --git a/sound/soc/codecs/88pm860x-codec.c b/sound/soc/codecs/88pm860x-codec.c index 08e15dee9182..a34fb924e77b 100644 --- a/sound/soc/codecs/88pm860x-codec.c +++ b/sound/soc/codecs/88pm860x-codec.c @@ -22,6 +22,7 @@ #include #include #include +#include #include "88pm860x-codec.h" @@ -1262,6 +1263,10 @@ static irqreturn_t pm860x_codec_handler(int irq, void *data) mask = pm860x->det.hs_shrt | pm860x->det.hook_det | pm860x->det.lo_shrt | pm860x->det.hp_det; + if (status & (HEADSET_STATUS | MIC_STATUS | SHORT_HS1 | SHORT_HS2 | + SHORT_LO1 | SHORT_LO2)) + trace_snd_soc_jack_irq(dev_name(pm860x->codec->dev)); + if ((pm860x->det.hp_det & SND_JACK_HEADPHONE) && (status & HEADSET_STATUS)) report |= SND_JACK_HEADPHONE; -- cgit v1.2.2 From 6a504a751124889e0bdbb25963a7edf7aeedb7bd Mon Sep 17 00:00:00 2001 From: Dimitris Papastamos Date: Wed, 22 Dec 2010 11:33:11 +0000 Subject: ASoC: Add initial WM8995 driver The WM8995 is a digital audio hub CODEC designed for smartphones. The current driver supports most of the basic functionality of the WM8995. Signed-off-by: Dimitris Papastamos Acked-by: Liam Girdwood Signed-off-by: Mark Brown --- sound/soc/codecs/Kconfig | 4 + sound/soc/codecs/Makefile | 2 + sound/soc/codecs/wm8995.c | 1818 ++++++++++ sound/soc/codecs/wm8995.h | 8749 +++++++++++++++++++++++++++++++++++++++++++++ 4 files changed, 10573 insertions(+) create mode 100644 sound/soc/codecs/wm8995.c create mode 100644 sound/soc/codecs/wm8995.h (limited to 'sound/soc/codecs') diff --git a/sound/soc/codecs/Kconfig b/sound/soc/codecs/Kconfig index 0f33db2be25a..054191ed08ef 100644 --- a/sound/soc/codecs/Kconfig +++ b/sound/soc/codecs/Kconfig @@ -78,6 +78,7 @@ config SND_SOC_ALL_CODECS select SND_SOC_WM8990 if I2C select SND_SOC_WM8993 if I2C select SND_SOC_WM8994 if MFD_WM8994 + select SND_SOC_WM8995 if SND_SOC_I2C_AND_SPI select SND_SOC_WM9081 if I2C select SND_SOC_WM9090 if I2C select SND_SOC_WM9705 if SND_SOC_AC97_BUS @@ -306,6 +307,9 @@ config SND_SOC_WM8993 config SND_SOC_WM8994 tristate +config SND_SOC_WM8995 + tristate + config SND_SOC_WM9081 tristate diff --git a/sound/soc/codecs/Makefile b/sound/soc/codecs/Makefile index 10e5e099334a..6a1e17bbbf83 100644 --- a/sound/soc/codecs/Makefile +++ b/sound/soc/codecs/Makefile @@ -62,6 +62,7 @@ snd-soc-wm8988-objs := wm8988.o snd-soc-wm8990-objs := wm8990.o snd-soc-wm8993-objs := wm8993.o snd-soc-wm8994-objs := wm8994.o wm8994-tables.o +snd-soc-wm8995-objs := wm8995.o snd-soc-wm9081-objs := wm9081.o snd-soc-wm9705-objs := wm9705.o snd-soc-wm9712-objs := wm9712.o @@ -140,6 +141,7 @@ obj-$(CONFIG_SND_SOC_WM8988) += snd-soc-wm8988.o obj-$(CONFIG_SND_SOC_WM8990) += snd-soc-wm8990.o obj-$(CONFIG_SND_SOC_WM8993) += snd-soc-wm8993.o obj-$(CONFIG_SND_SOC_WM8994) += snd-soc-wm8994.o +obj-$(CONFIG_SND_SOC_WM8995) += snd-soc-wm8995.o obj-$(CONFIG_SND_SOC_WM9081) += snd-soc-wm9081.o obj-$(CONFIG_SND_SOC_WM9705) += snd-soc-wm9705.o obj-$(CONFIG_SND_SOC_WM9712) += snd-soc-wm9712.o diff --git a/sound/soc/codecs/wm8995.c b/sound/soc/codecs/wm8995.c new file mode 100644 index 000000000000..3d2110c1d81f --- /dev/null +++ b/sound/soc/codecs/wm8995.c @@ -0,0 +1,1818 @@ +/* + * wm8995.c -- WM8995 ALSA SoC Audio driver + * + * Copyright 2010 Wolfson Microelectronics plc + * + * Author: Dimitris Papastamos + * + * Based on wm8994.c and wm_hubs.c by Mark Brown + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "wm8995.h" + +static const u16 wm8995_reg_defs[WM8995_MAX_REGISTER + 1] __devinitconst = { + [0] = 0x8995, [5] = 0x0100, [16] = 0x000b, [17] = 0x000b, + [24] = 0x02c0, [25] = 0x02c0, [26] = 0x02c0, [27] = 0x02c0, + [28] = 0x000f, [32] = 0x0005, [33] = 0x0005, [40] = 0x0003, + [41] = 0x0013, [48] = 0x0004, [56] = 0x09f8, [64] = 0x1f25, + [69] = 0x0004, [82] = 0xaaaa, [84] = 0x2a2a, [146] = 0x0060, + [256] = 0x0002, [257] = 0x8004, [520] = 0x0010, [528] = 0x0083, + [529] = 0x0083, [548] = 0x0c80, [580] = 0x0c80, [768] = 0x4050, + [769] = 0x4000, [771] = 0x0040, [772] = 0x0040, [773] = 0x0040, + [774] = 0x0004, [775] = 0x0100, [784] = 0x4050, [785] = 0x4000, + [787] = 0x0040, [788] = 0x0040, [789] = 0x0040, [1024] = 0x00c0, + [1025] = 0x00c0, [1026] = 0x00c0, [1027] = 0x00c0, [1028] = 0x00c0, + [1029] = 0x00c0, [1030] = 0x00c0, [1031] = 0x00c0, [1056] = 0x0200, + [1057] = 0x0010, [1058] = 0x0200, [1059] = 0x0010, [1088] = 0x0098, + [1089] = 0x0845, [1104] = 0x0098, [1105] = 0x0845, [1152] = 0x6318, + [1153] = 0x6300, [1154] = 0x0fca, [1155] = 0x0400, [1156] = 0x00d8, + [1157] = 0x1eb5, [1158] = 0xf145, [1159] = 0x0b75, [1160] = 0x01c5, + [1161] = 0x1c58, [1162] = 0xf373, [1163] = 0x0a54, [1164] = 0x0558, + [1165] = 0x168e, [1166] = 0xf829, [1167] = 0x07ad, [1168] = 0x1103, + [1169] = 0x0564, [1170] = 0x0559, [1171] = 0x4000, [1184] = 0x6318, + [1185] = 0x6300, [1186] = 0x0fca, [1187] = 0x0400, [1188] = 0x00d8, + [1189] = 0x1eb5, [1190] = 0xf145, [1191] = 0x0b75, [1192] = 0x01c5, + [1193] = 0x1c58, [1194] = 0xf373, [1195] = 0x0a54, [1196] = 0x0558, + [1197] = 0x168e, [1198] = 0xf829, [1199] = 0x07ad, [1200] = 0x1103, + [1201] = 0x0564, [1202] = 0x0559, [1203] = 0x4000, [1280] = 0x00c0, + [1281] = 0x00c0, [1282] = 0x00c0, [1283] = 0x00c0, [1312] = 0x0200, + [1313] = 0x0010, [1344] = 0x0098, [1345] = 0x0845, [1408] = 0x6318, + [1409] = 0x6300, [1410] = 0x0fca, [1411] = 0x0400, [1412] = 0x00d8, + [1413] = 0x1eb5, [1414] = 0xf145, [1415] = 0x0b75, [1416] = 0x01c5, + [1417] = 0x1c58, [1418] = 0xf373, [1419] = 0x0a54, [1420] = 0x0558, + [1421] = 0x168e, [1422] = 0xf829, [1423] = 0x07ad, [1424] = 0x1103, + [1425] = 0x0564, [1426] = 0x0559, [1427] = 0x4000, [1568] = 0x0002, + [1792] = 0xa100, [1793] = 0xa101, [1794] = 0xa101, [1795] = 0xa101, + [1796] = 0xa101, [1797] = 0xa101, [1798] = 0xa101, [1799] = 0xa101, + [1800] = 0xa101, [1801] = 0xa101, [1802] = 0xa101, [1803] = 0xa101, + [1804] = 0xa101, [1805] = 0xa101, [1825] = 0x0055, [1848] = 0x3fff, + [1849] = 0x1fff, [2049] = 0x0001, [2050] = 0x0069, [2056] = 0x0002, + [2057] = 0x0003, [2058] = 0x0069, [12288] = 0x0001, [12289] = 0x0001, + [12291] = 0x0006, [12292] = 0x0040, [12293] = 0x0001, [12294] = 0x000f, + [12295] = 0x0006, [12296] = 0x0001, [12297] = 0x0003, [12298] = 0x0104, + [12300] = 0x0060, [12301] = 0x0011, [12302] = 0x0401, [12304] = 0x0050, + [12305] = 0x0003, [12306] = 0x0100, [12308] = 0x0051, [12309] = 0x0003, + [12310] = 0x0104, [12311] = 0x000a, [12312] = 0x0060, [12313] = 0x003b, + [12314] = 0x0502, [12315] = 0x0100, [12316] = 0x2fff, [12320] = 0x2fff, + [12324] = 0x2fff, [12328] = 0x2fff, [12332] = 0x2fff, [12336] = 0x2fff, + [12340] = 0x2fff, [12344] = 0x2fff, [12348] = 0x2fff, [12352] = 0x0001, + [12353] = 0x0001, [12355] = 0x0006, [12356] = 0x0040, [12357] = 0x0001, + [12358] = 0x000f, [12359] = 0x0006, [12360] = 0x0001, [12361] = 0x0003, + [12362] = 0x0104, [12364] = 0x0060, [12365] = 0x0011, [12366] = 0x0401, + [12368] = 0x0050, [12369] = 0x0003, [12370] = 0x0100, [12372] = 0x0060, + [12373] = 0x003b, [12374] = 0x0502, [12375] = 0x0100, [12376] = 0x2fff, + [12380] = 0x2fff, [12384] = 0x2fff, [12388] = 0x2fff, [12392] = 0x2fff, + [12396] = 0x2fff, [12400] = 0x2fff, [12404] = 0x2fff, [12408] = 0x2fff, + [12412] = 0x2fff, [12416] = 0x0001, [12417] = 0x0001, [12419] = 0x0006, + [12420] = 0x0040, [12421] = 0x0001, [12422] = 0x000f, [12423] = 0x0006, + [12424] = 0x0001, [12425] = 0x0003, [12426] = 0x0106, [12428] = 0x0061, + [12429] = 0x0011, [12430] = 0x0401, [12432] = 0x0050, [12433] = 0x0003, + [12434] = 0x0102, [12436] = 0x0051, [12437] = 0x0003, [12438] = 0x0106, + [12439] = 0x000a, [12440] = 0x0061, [12441] = 0x003b, [12442] = 0x0502, + [12443] = 0x0100, [12444] = 0x2fff, [12448] = 0x2fff, [12452] = 0x2fff, + [12456] = 0x2fff, [12460] = 0x2fff, [12464] = 0x2fff, [12468] = 0x2fff, + [12472] = 0x2fff, [12476] = 0x2fff, [12480] = 0x0001, [12481] = 0x0001, + [12483] = 0x0006, [12484] = 0x0040, [12485] = 0x0001, [12486] = 0x000f, + [12487] = 0x0006, [12488] = 0x0001, [12489] = 0x0003, [12490] = 0x0106, + [12492] = 0x0061, [12493] = 0x0011, [12494] = 0x0401, [12496] = 0x0050, + [12497] = 0x0003, [12498] = 0x0102, [12500] = 0x0061, [12501] = 0x003b, + [12502] = 0x0502, [12503] = 0x0100, [12504] = 0x2fff, [12508] = 0x2fff, + [12512] = 0x2fff, [12516] = 0x2fff, [12520] = 0x2fff, [12524] = 0x2fff, + [12528] = 0x2fff, [12532] = 0x2fff, [12536] = 0x2fff, [12540] = 0x2fff, + [12544] = 0x0060, [12546] = 0x0601, [12548] = 0x0050, [12550] = 0x0100, + [12552] = 0x0001, [12554] = 0x0104, [12555] = 0x0100, [12556] = 0x2fff, + [12560] = 0x2fff, [12564] = 0x2fff, [12568] = 0x2fff, [12572] = 0x2fff, + [12576] = 0x2fff, [12580] = 0x2fff, [12584] = 0x2fff, [12588] = 0x2fff, + [12592] = 0x2fff, [12596] = 0x2fff, [12600] = 0x2fff, [12604] = 0x2fff, + [12608] = 0x0061, [12610] = 0x0601, [12612] = 0x0050, [12614] = 0x0102, + [12616] = 0x0001, [12618] = 0x0106, [12619] = 0x0100, [12620] = 0x2fff, + [12624] = 0x2fff, [12628] = 0x2fff, [12632] = 0x2fff, [12636] = 0x2fff, + [12640] = 0x2fff, [12644] = 0x2fff, [12648] = 0x2fff, [12652] = 0x2fff, + [12656] = 0x2fff, [12660] = 0x2fff, [12664] = 0x2fff, [12668] = 0x2fff, + [12672] = 0x0060, [12674] = 0x0601, [12676] = 0x0061, [12678] = 0x0601, + [12680] = 0x0050, [12682] = 0x0300, [12684] = 0x0001, [12686] = 0x0304, + [12688] = 0x0040, [12690] = 0x000f, [12692] = 0x0001, [12695] = 0x0100 +}; + +struct fll_config { + int src; + int in; + int out; +}; + +struct wm8995_priv { + enum snd_soc_control_type control_type; + int sysclk[2]; + int mclk[2]; + int aifclk[2]; + struct fll_config fll[2], fll_suspend[2]; +}; + +static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1); +static const DECLARE_TLV_DB_SCALE(in1lr_pga_tlv, -1650, 150, 0); +static const DECLARE_TLV_DB_SCALE(in1l_boost_tlv, 0, 600, 0); +static const DECLARE_TLV_DB_SCALE(sidetone_tlv, -3600, 150, 0); + +static const char *in1l_text[] = { + "Differential", "Single-ended IN1LN", "Single-ended IN1LP" +}; + +static const SOC_ENUM_SINGLE_DECL(in1l_enum, WM8995_LEFT_LINE_INPUT_CONTROL, + 2, in1l_text); + +static const char *in1r_text[] = { + "Differential", "Single-ended IN1RN", "Single-ended IN1RP" +}; + +static const SOC_ENUM_SINGLE_DECL(in1r_enum, WM8995_LEFT_LINE_INPUT_CONTROL, + 0, in1r_text); + +static const char *dmic_src_text[] = { + "DMICDAT1", "DMICDAT2", "DMICDAT3" +}; + +static const SOC_ENUM_SINGLE_DECL(dmic_src1_enum, WM8995_POWER_MANAGEMENT_5, + 8, dmic_src_text); +static const SOC_ENUM_SINGLE_DECL(dmic_src2_enum, WM8995_POWER_MANAGEMENT_5, + 6, dmic_src_text); + +static const struct snd_kcontrol_new wm8995_snd_controls[] = { + SOC_DOUBLE_R_TLV("DAC1 Volume", WM8995_DAC1_LEFT_VOLUME, + WM8995_DAC1_RIGHT_VOLUME, 0, 96, 0, digital_tlv), + SOC_DOUBLE_R("DAC1 Switch", WM8995_DAC1_LEFT_VOLUME, + WM8995_DAC1_RIGHT_VOLUME, 9, 1, 1), + + SOC_DOUBLE_R_TLV("DAC2 Volume", WM8995_DAC2_LEFT_VOLUME, + WM8995_DAC2_RIGHT_VOLUME, 0, 96, 0, digital_tlv), + SOC_DOUBLE_R("DAC2 Switch", WM8995_DAC2_LEFT_VOLUME, + WM8995_DAC2_RIGHT_VOLUME, 9, 1, 1), + + SOC_DOUBLE_R_TLV("AIF1DAC1 Volume", WM8995_AIF1_DAC1_LEFT_VOLUME, + WM8995_AIF1_DAC1_RIGHT_VOLUME, 0, 96, 0, digital_tlv), + SOC_DOUBLE_R_TLV("AIF1DAC2 Volume", WM8995_AIF1_DAC2_LEFT_VOLUME, + WM8995_AIF1_DAC2_RIGHT_VOLUME, 0, 96, 0, digital_tlv), + SOC_DOUBLE_R_TLV("AIF2DAC Volume", WM8995_AIF2_DAC_LEFT_VOLUME, + WM8995_AIF2_DAC_RIGHT_VOLUME, 0, 96, 0, digital_tlv), + + SOC_DOUBLE_R_TLV("IN1LR Volume", WM8995_LEFT_LINE_INPUT_1_VOLUME, + WM8995_RIGHT_LINE_INPUT_1_VOLUME, 0, 31, 0, in1lr_pga_tlv), + + SOC_SINGLE_TLV("IN1L Boost", WM8995_LEFT_LINE_INPUT_CONTROL, + 4, 3, 0, in1l_boost_tlv), + + SOC_ENUM("IN1L Mode", in1l_enum), + SOC_ENUM("IN1R Mode", in1r_enum), + + SOC_ENUM("DMIC1 SRC", dmic_src1_enum), + SOC_ENUM("DMIC2 SRC", dmic_src2_enum), + + SOC_DOUBLE_TLV("DAC1 Sidetone Volume", WM8995_DAC1_MIXER_VOLUMES, 0, 5, + 24, 0, sidetone_tlv), + SOC_DOUBLE_TLV("DAC2 Sidetone Volume", WM8995_DAC2_MIXER_VOLUMES, 0, 5, + 24, 0, sidetone_tlv), + + SOC_DOUBLE_R_TLV("AIF1ADC1 Volume", WM8995_AIF1_ADC1_LEFT_VOLUME, + WM8995_AIF1_ADC1_RIGHT_VOLUME, 0, 96, 0, digital_tlv), + SOC_DOUBLE_R_TLV("AIF1ADC2 Volume", WM8995_AIF1_ADC2_LEFT_VOLUME, + WM8995_AIF1_ADC2_RIGHT_VOLUME, 0, 96, 0, digital_tlv), + SOC_DOUBLE_R_TLV("AIF2ADC Volume", WM8995_AIF2_ADC_LEFT_VOLUME, + WM8995_AIF2_ADC_RIGHT_VOLUME, 0, 96, 0, digital_tlv) +}; + +static void wm8995_update_class_w(struct snd_soc_codec *codec) +{ + int enable = 1; + int source = 0; /* GCC flow analysis can't track enable */ + int reg, reg_r; + + /* We also need the same setting for L/R and only one path */ + reg = snd_soc_read(codec, WM8995_DAC1_LEFT_MIXER_ROUTING); + switch (reg) { + case WM8995_AIF2DACL_TO_DAC1L: + dev_dbg(codec->dev, "Class W source AIF2DAC\n"); + source = 2 << WM8995_CP_DYN_SRC_SEL_SHIFT; + break; + case WM8995_AIF1DAC2L_TO_DAC1L: + dev_dbg(codec->dev, "Class W source AIF1DAC2\n"); + source = 1 << WM8995_CP_DYN_SRC_SEL_SHIFT; + break; + case WM8995_AIF1DAC1L_TO_DAC1L: + dev_dbg(codec->dev, "Class W source AIF1DAC1\n"); + source = 0 << WM8995_CP_DYN_SRC_SEL_SHIFT; + break; + default: + dev_dbg(codec->dev, "DAC mixer setting: %x\n", reg); + enable = 0; + break; + } + + reg_r = snd_soc_read(codec, WM8995_DAC1_RIGHT_MIXER_ROUTING); + if (reg_r != reg) { + dev_dbg(codec->dev, "Left and right DAC mixers different\n"); + enable = 0; + } + + if (enable) { + dev_dbg(codec->dev, "Class W enabled\n"); + snd_soc_update_bits(codec, WM8995_CLASS_W_1, + WM8995_CP_DYN_PWR_MASK | + WM8995_CP_DYN_SRC_SEL_MASK, + source | WM8995_CP_DYN_PWR); + } else { + dev_dbg(codec->dev, "Class W disabled\n"); + snd_soc_update_bits(codec, WM8995_CLASS_W_1, + WM8995_CP_DYN_PWR_MASK, 0); + } +} + +static int check_clk_sys(struct snd_soc_dapm_widget *source, + struct snd_soc_dapm_widget *sink) +{ + unsigned int reg; + const char *clk; + + reg = snd_soc_read(source->codec, WM8995_CLOCKING_1); + /* Check what we're currently using for CLK_SYS */ + if (reg & WM8995_SYSCLK_SRC) + clk = "AIF2CLK"; + else + clk = "AIF1CLK"; + return !strcmp(source->name, clk); +} + +static int wm8995_put_class_w(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_dapm_widget *w; + struct snd_soc_codec *codec; + int ret; + + w = snd_kcontrol_chip(kcontrol); + codec = w->codec; + ret = snd_soc_dapm_put_volsw(kcontrol, ucontrol); + wm8995_update_class_w(codec); + return ret; +} + +static int hp_supply_event(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, int event) +{ + struct snd_soc_codec *codec; + struct wm8995_priv *wm8995; + + codec = w->codec; + wm8995 = snd_soc_codec_get_drvdata(codec); + + switch (event) { + case SND_SOC_DAPM_PRE_PMU: + /* Enable the headphone amp */ + snd_soc_update_bits(codec, WM8995_POWER_MANAGEMENT_1, + WM8995_HPOUT1L_ENA_MASK | + WM8995_HPOUT1R_ENA_MASK, + WM8995_HPOUT1L_ENA | + WM8995_HPOUT1R_ENA); + + /* Enable the second stage */ + snd_soc_update_bits(codec, WM8995_ANALOGUE_HP_1, + WM8995_HPOUT1L_DLY_MASK | + WM8995_HPOUT1R_DLY_MASK, + WM8995_HPOUT1L_DLY | + WM8995_HPOUT1R_DLY); + break; + case SND_SOC_DAPM_PRE_PMD: + snd_soc_update_bits(codec, WM8995_CHARGE_PUMP_1, + WM8995_CP_ENA_MASK, 0); + break; + } + + return 0; +} + +static void dc_servo_cmd(struct snd_soc_codec *codec, + unsigned int reg, unsigned int val, unsigned int mask) +{ + int timeout = 10; + + dev_dbg(codec->dev, "%s: reg = %#x, val = %#x, mask = %#x\n", + __func__, reg, val, mask); + + snd_soc_write(codec, reg, val); + while (timeout--) { + msleep(10); + val = snd_soc_read(codec, WM8995_DC_SERVO_READBACK_0); + if ((val & mask) == mask) + return; + } + + dev_err(codec->dev, "Timed out waiting for DC Servo\n"); +} + +static int hp_event(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, int event) +{ + struct snd_soc_codec *codec; + unsigned int reg; + + codec = w->codec; + reg = snd_soc_read(codec, WM8995_ANALOGUE_HP_1); + + switch (event) { + case SND_SOC_DAPM_POST_PMU: + snd_soc_update_bits(codec, WM8995_CHARGE_PUMP_1, + WM8995_CP_ENA_MASK, WM8995_CP_ENA); + + msleep(5); + + snd_soc_update_bits(codec, WM8995_POWER_MANAGEMENT_1, + WM8995_HPOUT1L_ENA_MASK | + WM8995_HPOUT1R_ENA_MASK, + WM8995_HPOUT1L_ENA | WM8995_HPOUT1R_ENA); + + udelay(20); + + reg |= WM8995_HPOUT1L_DLY | WM8995_HPOUT1R_DLY; + snd_soc_write(codec, WM8995_ANALOGUE_HP_1, reg); + + snd_soc_write(codec, WM8995_DC_SERVO_1, WM8995_DCS_ENA_CHAN_0 | + WM8995_DCS_ENA_CHAN_1); + + dc_servo_cmd(codec, WM8995_DC_SERVO_2, + WM8995_DCS_TRIG_STARTUP_0 | + WM8995_DCS_TRIG_STARTUP_1, + WM8995_DCS_TRIG_DAC_WR_0 | + WM8995_DCS_TRIG_DAC_WR_1); + + reg |= WM8995_HPOUT1R_OUTP | WM8995_HPOUT1R_RMV_SHORT | + WM8995_HPOUT1L_OUTP | WM8995_HPOUT1L_RMV_SHORT; + snd_soc_write(codec, WM8995_ANALOGUE_HP_1, reg); + + break; + case SND_SOC_DAPM_PRE_PMD: + snd_soc_update_bits(codec, WM8995_ANALOGUE_HP_1, + WM8995_HPOUT1L_OUTP_MASK | + WM8995_HPOUT1R_OUTP_MASK | + WM8995_HPOUT1L_RMV_SHORT_MASK | + WM8995_HPOUT1R_RMV_SHORT_MASK, 0); + + snd_soc_update_bits(codec, WM8995_ANALOGUE_HP_1, + WM8995_HPOUT1L_DLY_MASK | + WM8995_HPOUT1R_DLY_MASK, 0); + + snd_soc_write(codec, WM8995_DC_SERVO_1, 0); + + snd_soc_update_bits(codec, WM8995_POWER_MANAGEMENT_1, + WM8995_HPOUT1L_ENA_MASK | + WM8995_HPOUT1R_ENA_MASK, + 0); + break; + } + + return 0; +} + +static int configure_aif_clock(struct snd_soc_codec *codec, int aif) +{ + struct wm8995_priv *wm8995; + int rate; + int reg1 = 0; + int offset; + + wm8995 = snd_soc_codec_get_drvdata(codec); + + if (aif) + offset = 4; + else + offset = 0; + + switch (wm8995->sysclk[aif]) { + case WM8995_SYSCLK_MCLK1: + rate = wm8995->mclk[0]; + break; + case WM8995_SYSCLK_MCLK2: + reg1 |= 0x8; + rate = wm8995->mclk[1]; + break; + case WM8995_SYSCLK_FLL1: + reg1 |= 0x10; + rate = wm8995->fll[0].out; + break; + case WM8995_SYSCLK_FLL2: + reg1 |= 0x18; + rate = wm8995->fll[1].out; + break; + default: + return -EINVAL; + } + + if (rate >= 13500000) { + rate /= 2; + reg1 |= WM8995_AIF1CLK_DIV; + + dev_dbg(codec->dev, "Dividing AIF%d clock to %dHz\n", + aif + 1, rate); + } + + wm8995->aifclk[aif] = rate; + + snd_soc_update_bits(codec, WM8995_AIF1_CLOCKING_1 + offset, + WM8995_AIF1CLK_SRC_MASK | WM8995_AIF1CLK_DIV_MASK, + reg1); + return 0; +} + +static int configure_clock(struct snd_soc_codec *codec) +{ + struct wm8995_priv *wm8995; + int old, new; + + wm8995 = snd_soc_codec_get_drvdata(codec); + + /* Bring up the AIF clocks first */ + configure_aif_clock(codec, 0); + configure_aif_clock(codec, 1); + + /* + * Then switch CLK_SYS over to the higher of them; a change + * can only happen as a result of a clocking change which can + * only be made outside of DAPM so we can safely redo the + * clocking. + */ + + /* If they're equal it doesn't matter which is used */ + if (wm8995->aifclk[0] == wm8995->aifclk[1]) + return 0; + + if (wm8995->aifclk[0] < wm8995->aifclk[1]) + new = WM8995_SYSCLK_SRC; + else + new = 0; + + old = snd_soc_read(codec, WM8995_CLOCKING_1) & WM8995_SYSCLK_SRC; + + /* If there's no change then we're done. */ + if (old == new) + return 0; + + snd_soc_update_bits(codec, WM8995_CLOCKING_1, + WM8995_SYSCLK_SRC_MASK, new); + + snd_soc_dapm_sync(&codec->dapm); + + return 0; +} + +static int clk_sys_event(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, int event) +{ + struct snd_soc_codec *codec; + + codec = w->codec; + + switch (event) { + case SND_SOC_DAPM_PRE_PMU: + return configure_clock(codec); + + case SND_SOC_DAPM_POST_PMD: + configure_clock(codec); + break; + } + + return 0; +} + +static const char *sidetone_text[] = { + "ADC/DMIC1", "DMIC2", +}; + +static const struct soc_enum sidetone1_enum = + SOC_ENUM_SINGLE(WM8995_SIDETONE, 0, 2, sidetone_text); + +static const struct snd_kcontrol_new sidetone1_mux = + SOC_DAPM_ENUM("Left Sidetone Mux", sidetone1_enum); + +static const struct soc_enum sidetone2_enum = + SOC_ENUM_SINGLE(WM8995_SIDETONE, 1, 2, sidetone_text); + +static const struct snd_kcontrol_new sidetone2_mux = + SOC_DAPM_ENUM("Right Sidetone Mux", sidetone2_enum); + +static const struct snd_kcontrol_new aif1adc1l_mix[] = { + SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8995_AIF1_ADC1_LEFT_MIXER_ROUTING, + 1, 1, 0), + SOC_DAPM_SINGLE("AIF2 Switch", WM8995_AIF1_ADC1_LEFT_MIXER_ROUTING, + 0, 1, 0), +}; + +static const struct snd_kcontrol_new aif1adc1r_mix[] = { + SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8995_AIF1_ADC1_RIGHT_MIXER_ROUTING, + 1, 1, 0), + SOC_DAPM_SINGLE("AIF2 Switch", WM8995_AIF1_ADC1_RIGHT_MIXER_ROUTING, + 0, 1, 0), +}; + +static const struct snd_kcontrol_new aif1adc2l_mix[] = { + SOC_DAPM_SINGLE("DMIC Switch", WM8995_AIF1_ADC2_LEFT_MIXER_ROUTING, + 1, 1, 0), + SOC_DAPM_SINGLE("AIF2 Switch", WM8995_AIF1_ADC2_LEFT_MIXER_ROUTING, + 0, 1, 0), +}; + +static const struct snd_kcontrol_new aif1adc2r_mix[] = { + SOC_DAPM_SINGLE("DMIC Switch", WM8995_AIF1_ADC2_RIGHT_MIXER_ROUTING, + 1, 1, 0), + SOC_DAPM_SINGLE("AIF2 Switch", WM8995_AIF1_ADC2_RIGHT_MIXER_ROUTING, + 0, 1, 0), +}; + +static const struct snd_kcontrol_new dac1l_mix[] = { + WM8995_CLASS_W_SWITCH("Right Sidetone Switch", WM8995_DAC1_LEFT_MIXER_ROUTING, + 5, 1, 0), + WM8995_CLASS_W_SWITCH("Left Sidetone Switch", WM8995_DAC1_LEFT_MIXER_ROUTING, + 4, 1, 0), + WM8995_CLASS_W_SWITCH("AIF2 Switch", WM8995_DAC1_LEFT_MIXER_ROUTING, + 2, 1, 0), + WM8995_CLASS_W_SWITCH("AIF1.2 Switch", WM8995_DAC1_LEFT_MIXER_ROUTING, + 1, 1, 0), + WM8995_CLASS_W_SWITCH("AIF1.1 Switch", WM8995_DAC1_LEFT_MIXER_ROUTING, + 0, 1, 0), +}; + +static const struct snd_kcontrol_new dac1r_mix[] = { + WM8995_CLASS_W_SWITCH("Right Sidetone Switch", WM8995_DAC1_RIGHT_MIXER_ROUTING, + 5, 1, 0), + WM8995_CLASS_W_SWITCH("Left Sidetone Switch", WM8995_DAC1_RIGHT_MIXER_ROUTING, + 4, 1, 0), + WM8995_CLASS_W_SWITCH("AIF2 Switch", WM8995_DAC1_RIGHT_MIXER_ROUTING, + 2, 1, 0), + WM8995_CLASS_W_SWITCH("AIF1.2 Switch", WM8995_DAC1_RIGHT_MIXER_ROUTING, + 1, 1, 0), + WM8995_CLASS_W_SWITCH("AIF1.1 Switch", WM8995_DAC1_RIGHT_MIXER_ROUTING, + 0, 1, 0), +}; + +static const struct snd_kcontrol_new aif2dac2l_mix[] = { + SOC_DAPM_SINGLE("Right Sidetone Switch", WM8995_DAC2_LEFT_MIXER_ROUTING, + 5, 1, 0), + SOC_DAPM_SINGLE("Left Sidetone Switch", WM8995_DAC2_LEFT_MIXER_ROUTING, + 4, 1, 0), + SOC_DAPM_SINGLE("AIF2 Switch", WM8995_DAC2_LEFT_MIXER_ROUTING, + 2, 1, 0), + SOC_DAPM_SINGLE("AIF1.2 Switch", WM8995_DAC2_LEFT_MIXER_ROUTING, + 1, 1, 0), + SOC_DAPM_SINGLE("AIF1.1 Switch", WM8995_DAC2_LEFT_MIXER_ROUTING, + 0, 1, 0), +}; + +static const struct snd_kcontrol_new aif2dac2r_mix[] = { + SOC_DAPM_SINGLE("Right Sidetone Switch", WM8995_DAC2_RIGHT_MIXER_ROUTING, + 5, 1, 0), + SOC_DAPM_SINGLE("Left Sidetone Switch", WM8995_DAC2_RIGHT_MIXER_ROUTING, + 4, 1, 0), + SOC_DAPM_SINGLE("AIF2 Switch", WM8995_DAC2_RIGHT_MIXER_ROUTING, + 2, 1, 0), + SOC_DAPM_SINGLE("AIF1.2 Switch", WM8995_DAC2_RIGHT_MIXER_ROUTING, + 1, 1, 0), + SOC_DAPM_SINGLE("AIF1.1 Switch", WM8995_DAC2_RIGHT_MIXER_ROUTING, + 0, 1, 0), +}; + +static const struct snd_kcontrol_new in1l_pga = + SOC_DAPM_SINGLE("IN1L Switch", WM8995_POWER_MANAGEMENT_2, 5, 1, 0); + +static const struct snd_kcontrol_new in1r_pga = + SOC_DAPM_SINGLE("IN1R Switch", WM8995_POWER_MANAGEMENT_2, 4, 1, 0); + +static const char *adc_mux_text[] = { + "ADC", + "DMIC", +}; + +static const struct soc_enum adc_enum = + SOC_ENUM_SINGLE(0, 0, 2, adc_mux_text); + +static const struct snd_kcontrol_new adcl_mux = + SOC_DAPM_ENUM_VIRT("ADCL Mux", adc_enum); + +static const struct snd_kcontrol_new adcr_mux = + SOC_DAPM_ENUM_VIRT("ADCR Mux", adc_enum); + +static const char *spk_src_text[] = { + "DAC1L", "DAC1R", "DAC2L", "DAC2R" +}; + +static const SOC_ENUM_SINGLE_DECL(spk1l_src_enum, WM8995_LEFT_PDM_SPEAKER_1, + 0, spk_src_text); +static const SOC_ENUM_SINGLE_DECL(spk1r_src_enum, WM8995_RIGHT_PDM_SPEAKER_1, + 0, spk_src_text); +static const SOC_ENUM_SINGLE_DECL(spk2l_src_enum, WM8995_LEFT_PDM_SPEAKER_2, + 0, spk_src_text); +static const SOC_ENUM_SINGLE_DECL(spk2r_src_enum, WM8995_RIGHT_PDM_SPEAKER_2, + 0, spk_src_text); + +static const struct snd_kcontrol_new spk1l_mux = + SOC_DAPM_ENUM("SPK1L SRC", spk1l_src_enum); +static const struct snd_kcontrol_new spk1r_mux = + SOC_DAPM_ENUM("SPK1R SRC", spk1r_src_enum); +static const struct snd_kcontrol_new spk2l_mux = + SOC_DAPM_ENUM("SPK2L SRC", spk2l_src_enum); +static const struct snd_kcontrol_new spk2r_mux = + SOC_DAPM_ENUM("SPK2R SRC", spk2r_src_enum); + +static const struct snd_soc_dapm_widget wm8995_dapm_widgets[] = { + SND_SOC_DAPM_INPUT("DMIC1DAT"), + SND_SOC_DAPM_INPUT("DMIC2DAT"), + + SND_SOC_DAPM_INPUT("IN1L"), + SND_SOC_DAPM_INPUT("IN1R"), + + SND_SOC_DAPM_MIXER("IN1L PGA", SND_SOC_NOPM, 0, 0, + &in1l_pga, 1), + SND_SOC_DAPM_MIXER("IN1R PGA", SND_SOC_NOPM, 0, 0, + &in1r_pga, 1), + + SND_SOC_DAPM_MICBIAS("MICBIAS1", WM8995_POWER_MANAGEMENT_1, 8, 0), + SND_SOC_DAPM_MICBIAS("MICBIAS2", WM8995_POWER_MANAGEMENT_1, 9, 0), + + SND_SOC_DAPM_SUPPLY("AIF1CLK", WM8995_AIF1_CLOCKING_1, 0, 0, NULL, 0), + SND_SOC_DAPM_SUPPLY("AIF2CLK", WM8995_AIF2_CLOCKING_1, 0, 0, NULL, 0), + SND_SOC_DAPM_SUPPLY("DSP1CLK", WM8995_CLOCKING_1, 3, 0, NULL, 0), + SND_SOC_DAPM_SUPPLY("DSP2CLK", WM8995_CLOCKING_1, 2, 0, NULL, 0), + SND_SOC_DAPM_SUPPLY("SYSDSPCLK", WM8995_CLOCKING_1, 1, 0, NULL, 0), + SND_SOC_DAPM_SUPPLY("CLK_SYS", SND_SOC_NOPM, 0, 0, clk_sys_event, + SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), + + SND_SOC_DAPM_AIF_OUT("AIF1ADC1L", "AIF1 Capture", 0, + WM8995_POWER_MANAGEMENT_3, 9, 0), + SND_SOC_DAPM_AIF_OUT("AIF1ADC1R", "AIF1 Capture", 0, + WM8995_POWER_MANAGEMENT_3, 8, 0), + SND_SOC_DAPM_AIF_OUT("AIF1ADCDAT", "AIF1 Capture", 0, + SND_SOC_NOPM, 0, 0), + SND_SOC_DAPM_AIF_OUT("AIF1ADC2L", "AIF1 Capture", + 0, WM8995_POWER_MANAGEMENT_3, 11, 0), + SND_SOC_DAPM_AIF_OUT("AIF1ADC2R", "AIF1 Capture", + 0, WM8995_POWER_MANAGEMENT_3, 10, 0), + + SND_SOC_DAPM_VIRT_MUX("ADCL Mux", SND_SOC_NOPM, 1, 0, + &adcl_mux), + SND_SOC_DAPM_VIRT_MUX("ADCR Mux", SND_SOC_NOPM, 0, 0, + &adcr_mux), + + SND_SOC_DAPM_ADC("DMIC2L", NULL, WM8995_POWER_MANAGEMENT_3, 5, 0), + SND_SOC_DAPM_ADC("DMIC2R", NULL, WM8995_POWER_MANAGEMENT_3, 4, 0), + SND_SOC_DAPM_ADC("DMIC1L", NULL, WM8995_POWER_MANAGEMENT_3, 3, 0), + SND_SOC_DAPM_ADC("DMIC1R", NULL, WM8995_POWER_MANAGEMENT_3, 2, 0), + + SND_SOC_DAPM_ADC("ADCL", NULL, WM8995_POWER_MANAGEMENT_3, 1, 0), + SND_SOC_DAPM_ADC("ADCR", NULL, WM8995_POWER_MANAGEMENT_3, 0, 0), + + SND_SOC_DAPM_MIXER("AIF1ADC1L Mixer", SND_SOC_NOPM, 0, 0, + aif1adc1l_mix, ARRAY_SIZE(aif1adc1l_mix)), + SND_SOC_DAPM_MIXER("AIF1ADC1R Mixer", SND_SOC_NOPM, 0, 0, + aif1adc1r_mix, ARRAY_SIZE(aif1adc1r_mix)), + SND_SOC_DAPM_MIXER("AIF1ADC2L Mixer", SND_SOC_NOPM, 0, 0, + aif1adc2l_mix, ARRAY_SIZE(aif1adc2l_mix)), + SND_SOC_DAPM_MIXER("AIF1ADC2R Mixer", SND_SOC_NOPM, 0, 0, + aif1adc2r_mix, ARRAY_SIZE(aif1adc2r_mix)), + + SND_SOC_DAPM_AIF_IN("AIF1DAC1L", NULL, 0, WM8995_POWER_MANAGEMENT_4, + 9, 0), + SND_SOC_DAPM_AIF_IN("AIF1DAC1R", NULL, 0, WM8995_POWER_MANAGEMENT_4, + 8, 0), + SND_SOC_DAPM_AIF_IN("AIF1DACDAT", "AIF1 Playback", 0, SND_SOC_NOPM, + 0, 0), + + SND_SOC_DAPM_AIF_IN("AIF1DAC2L", NULL, 0, WM8995_POWER_MANAGEMENT_4, + 11, 0), + SND_SOC_DAPM_AIF_IN("AIF1DAC2R", NULL, 0, WM8995_POWER_MANAGEMENT_4, + 10, 0), + + SND_SOC_DAPM_MIXER("AIF2DAC2L Mixer", SND_SOC_NOPM, 0, 0, + aif2dac2l_mix, ARRAY_SIZE(aif2dac2l_mix)), + SND_SOC_DAPM_MIXER("AIF2DAC2R Mixer", SND_SOC_NOPM, 0, 0, + aif2dac2r_mix, ARRAY_SIZE(aif2dac2r_mix)), + + SND_SOC_DAPM_DAC("DAC2L", NULL, WM8995_POWER_MANAGEMENT_4, 3, 0), + SND_SOC_DAPM_DAC("DAC2R", NULL, WM8995_POWER_MANAGEMENT_4, 2, 0), + SND_SOC_DAPM_DAC("DAC1L", NULL, WM8995_POWER_MANAGEMENT_4, 1, 0), + SND_SOC_DAPM_DAC("DAC1R", NULL, WM8995_POWER_MANAGEMENT_4, 0, 0), + + SND_SOC_DAPM_MIXER("DAC1L Mixer", SND_SOC_NOPM, 0, 0, dac1l_mix, + ARRAY_SIZE(dac1l_mix)), + SND_SOC_DAPM_MIXER("DAC1R Mixer", SND_SOC_NOPM, 0, 0, dac1r_mix, + ARRAY_SIZE(dac1r_mix)), + + SND_SOC_DAPM_MUX("Left Sidetone", SND_SOC_NOPM, 0, 0, &sidetone1_mux), + SND_SOC_DAPM_MUX("Right Sidetone", SND_SOC_NOPM, 0, 0, &sidetone2_mux), + + SND_SOC_DAPM_PGA_E("Headphone PGA", SND_SOC_NOPM, 0, 0, NULL, 0, + hp_event, SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), + + SND_SOC_DAPM_SUPPLY("Headphone Supply", SND_SOC_NOPM, 0, 0, + hp_supply_event, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD), + + SND_SOC_DAPM_MUX("SPK1L Driver", WM8995_LEFT_PDM_SPEAKER_1, + 4, 0, &spk1l_mux), + SND_SOC_DAPM_MUX("SPK1R Driver", WM8995_RIGHT_PDM_SPEAKER_1, + 4, 0, &spk1r_mux), + SND_SOC_DAPM_MUX("SPK2L Driver", WM8995_LEFT_PDM_SPEAKER_2, + 4, 0, &spk2l_mux), + SND_SOC_DAPM_MUX("SPK2R Driver", WM8995_RIGHT_PDM_SPEAKER_2, + 4, 0, &spk2r_mux), + + SND_SOC_DAPM_SUPPLY("LDO2", WM8995_POWER_MANAGEMENT_2, 1, 0, NULL, 0), + + SND_SOC_DAPM_OUTPUT("HP1L"), + SND_SOC_DAPM_OUTPUT("HP1R"), + SND_SOC_DAPM_OUTPUT("SPK1L"), + SND_SOC_DAPM_OUTPUT("SPK1R"), + SND_SOC_DAPM_OUTPUT("SPK2L"), + SND_SOC_DAPM_OUTPUT("SPK2R") +}; + +static const struct snd_soc_dapm_route wm8995_intercon[] = { + { "CLK_SYS", NULL, "AIF1CLK", check_clk_sys }, + { "CLK_SYS", NULL, "AIF2CLK", check_clk_sys }, + + { "DSP1CLK", NULL, "CLK_SYS" }, + { "DSP2CLK", NULL, "CLK_SYS" }, + { "SYSDSPCLK", NULL, "CLK_SYS" }, + + { "AIF1ADC1L", NULL, "AIF1CLK" }, + { "AIF1ADC1L", NULL, "DSP1CLK" }, + { "AIF1ADC1R", NULL, "AIF1CLK" }, + { "AIF1ADC1R", NULL, "DSP1CLK" }, + { "AIF1ADC1R", NULL, "SYSDSPCLK" }, + + { "AIF1ADC2L", NULL, "AIF1CLK" }, + { "AIF1ADC2L", NULL, "DSP1CLK" }, + { "AIF1ADC2R", NULL, "AIF1CLK" }, + { "AIF1ADC2R", NULL, "DSP1CLK" }, + { "AIF1ADC2R", NULL, "SYSDSPCLK" }, + + { "DMIC1L", NULL, "DMIC1DAT" }, + { "DMIC1L", NULL, "CLK_SYS" }, + { "DMIC1R", NULL, "DMIC1DAT" }, + { "DMIC1R", NULL, "CLK_SYS" }, + { "DMIC2L", NULL, "DMIC2DAT" }, + { "DMIC2L", NULL, "CLK_SYS" }, + { "DMIC2R", NULL, "DMIC2DAT" }, + { "DMIC2R", NULL, "CLK_SYS" }, + + { "ADCL", NULL, "AIF1CLK" }, + { "ADCL", NULL, "DSP1CLK" }, + { "ADCL", NULL, "SYSDSPCLK" }, + + { "ADCR", NULL, "AIF1CLK" }, + { "ADCR", NULL, "DSP1CLK" }, + { "ADCR", NULL, "SYSDSPCLK" }, + + { "IN1L PGA", "IN1L Switch", "IN1L" }, + { "IN1R PGA", "IN1R Switch", "IN1R" }, + { "IN1L PGA", NULL, "LDO2" }, + { "IN1R PGA", NULL, "LDO2" }, + + { "ADCL", NULL, "IN1L PGA" }, + { "ADCR", NULL, "IN1R PGA" }, + + { "ADCL Mux", "ADC", "ADCL" }, + { "ADCL Mux", "DMIC", "DMIC1L" }, + { "ADCR Mux", "ADC", "ADCR" }, + { "ADCR Mux", "DMIC", "DMIC1R" }, + + /* AIF1 outputs */ + { "AIF1ADC1L", NULL, "AIF1ADC1L Mixer" }, + { "AIF1ADC1L Mixer", "ADC/DMIC Switch", "ADCL Mux" }, + + { "AIF1ADC1R", NULL, "AIF1ADC1R Mixer" }, + { "AIF1ADC1R Mixer", "ADC/DMIC Switch", "ADCR Mux" }, + + { "AIF1ADC2L", NULL, "AIF1ADC2L Mixer" }, + { "AIF1ADC2L Mixer", "DMIC Switch", "DMIC2L" }, + + { "AIF1ADC2R", NULL, "AIF1ADC2R Mixer" }, + { "AIF1ADC2R Mixer", "DMIC Switch", "DMIC2R" }, + + /* Sidetone */ + { "Left Sidetone", "ADC/DMIC1", "AIF1ADC1L" }, + { "Left Sidetone", "DMIC2", "AIF1ADC2L" }, + { "Right Sidetone", "ADC/DMIC1", "AIF1ADC1R" }, + { "Right Sidetone", "DMIC2", "AIF1ADC2R" }, + + { "AIF1DAC1L", NULL, "AIF1CLK" }, + { "AIF1DAC1L", NULL, "DSP1CLK" }, + { "AIF1DAC1R", NULL, "AIF1CLK" }, + { "AIF1DAC1R", NULL, "DSP1CLK" }, + { "AIF1DAC1R", NULL, "SYSDSPCLK" }, + + { "AIF1DAC2L", NULL, "AIF1CLK" }, + { "AIF1DAC2L", NULL, "DSP1CLK" }, + { "AIF1DAC2R", NULL, "AIF1CLK" }, + { "AIF1DAC2R", NULL, "DSP1CLK" }, + { "AIF1DAC2R", NULL, "SYSDSPCLK" }, + + { "DAC1L", NULL, "AIF1CLK" }, + { "DAC1L", NULL, "DSP1CLK" }, + { "DAC1L", NULL, "SYSDSPCLK" }, + + { "DAC1R", NULL, "AIF1CLK" }, + { "DAC1R", NULL, "DSP1CLK" }, + { "DAC1R", NULL, "SYSDSPCLK" }, + + { "AIF1DAC1L", NULL, "AIF1DACDAT" }, + { "AIF1DAC1R", NULL, "AIF1DACDAT" }, + { "AIF1DAC2L", NULL, "AIF1DACDAT" }, + { "AIF1DAC2R", NULL, "AIF1DACDAT" }, + + /* DAC1 inputs */ + { "DAC1L", NULL, "DAC1L Mixer" }, + { "DAC1L Mixer", "AIF1.1 Switch", "AIF1DAC1L" }, + { "DAC1L Mixer", "AIF1.2 Switch", "AIF1DAC2L" }, + { "DAC1L Mixer", "Left Sidetone Switch", "Left Sidetone" }, + { "DAC1L Mixer", "Right Sidetone Switch", "Right Sidetone" }, + + { "DAC1R", NULL, "DAC1R Mixer" }, + { "DAC1R Mixer", "AIF1.1 Switch", "AIF1DAC1R" }, + { "DAC1R Mixer", "AIF1.2 Switch", "AIF1DAC2R" }, + { "DAC1R Mixer", "Left Sidetone Switch", "Left Sidetone" }, + { "DAC1R Mixer", "Right Sidetone Switch", "Right Sidetone" }, + + /* DAC2/AIF2 outputs */ + { "DAC2L", NULL, "AIF2DAC2L Mixer" }, + { "AIF2DAC2L Mixer", "AIF1.2 Switch", "AIF1DAC2L" }, + { "AIF2DAC2L Mixer", "AIF1.1 Switch", "AIF1DAC1L" }, + + { "DAC2R", NULL, "AIF2DAC2R Mixer" }, + { "AIF2DAC2R Mixer", "AIF1.2 Switch", "AIF1DAC2R" }, + { "AIF2DAC2R Mixer", "AIF1.1 Switch", "AIF1DAC1R" }, + + /* Output stages */ + { "Headphone PGA", NULL, "DAC1L" }, + { "Headphone PGA", NULL, "DAC1R" }, + + { "Headphone PGA", NULL, "DAC2L" }, + { "Headphone PGA", NULL, "DAC2R" }, + + { "Headphone PGA", NULL, "Headphone Supply" }, + { "Headphone PGA", NULL, "CLK_SYS" }, + { "Headphone PGA", NULL, "LDO2" }, + + { "HP1L", NULL, "Headphone PGA" }, + { "HP1R", NULL, "Headphone PGA" }, + + { "SPK1L Driver", "DAC1L", "DAC1L" }, + { "SPK1L Driver", "DAC1R", "DAC1R" }, + { "SPK1L Driver", "DAC2L", "DAC2L" }, + { "SPK1L Driver", "DAC2R", "DAC2R" }, + { "SPK1L Driver", NULL, "CLK_SYS" }, + + { "SPK1R Driver", "DAC1L", "DAC1L" }, + { "SPK1R Driver", "DAC1R", "DAC1R" }, + { "SPK1R Driver", "DAC2L", "DAC2L" }, + { "SPK1R Driver", "DAC2R", "DAC2R" }, + { "SPK1R Driver", NULL, "CLK_SYS" }, + + { "SPK2L Driver", "DAC1L", "DAC1L" }, + { "SPK2L Driver", "DAC1R", "DAC1R" }, + { "SPK2L Driver", "DAC2L", "DAC2L" }, + { "SPK2L Driver", "DAC2R", "DAC2R" }, + { "SPK2L Driver", NULL, "CLK_SYS" }, + + { "SPK2R Driver", "DAC1L", "DAC1L" }, + { "SPK2R Driver", "DAC1R", "DAC1R" }, + { "SPK2R Driver", "DAC2L", "DAC2L" }, + { "SPK2R Driver", "DAC2R", "DAC2R" }, + { "SPK2R Driver", NULL, "CLK_SYS" }, + + { "SPK1L", NULL, "SPK1L Driver" }, + { "SPK1R", NULL, "SPK1R Driver" }, + { "SPK2L", NULL, "SPK2L Driver" }, + { "SPK2R", NULL, "SPK2R Driver" } +}; + +static int wm8995_volatile(unsigned int reg) +{ + /* out of bounds registers are generally considered + * volatile to support register banks that are partially + * owned by something else for e.g. a DSP + */ + if (reg > WM8995_MAX_CACHED_REGISTER) + return 1; + + switch (reg) { + case WM8995_SOFTWARE_RESET: + case WM8995_DC_SERVO_READBACK_0: + case WM8995_INTERRUPT_STATUS_1: + case WM8995_INTERRUPT_STATUS_2: + case WM8995_INTERRUPT_STATUS_1_MASK: + case WM8995_INTERRUPT_STATUS_2_MASK: + case WM8995_INTERRUPT_CONTROL: + case WM8995_ACCESSORY_DETECT_MODE1: + case WM8995_ACCESSORY_DETECT_MODE2: + case WM8995_HEADPHONE_DETECT1: + case WM8995_HEADPHONE_DETECT2: + return 1; + } + + return 0; +} + +static int wm8995_aif_mute(struct snd_soc_dai *dai, int mute) +{ + struct snd_soc_codec *codec = dai->codec; + int mute_reg; + + switch (dai->id) { + case 0: + mute_reg = WM8995_AIF1_DAC1_FILTERS_1; + break; + case 1: + mute_reg = WM8995_AIF2_DAC_FILTERS_1; + break; + default: + return -EINVAL; + } + + snd_soc_update_bits(codec, mute_reg, WM8995_AIF1DAC1_MUTE_MASK, + !!mute << WM8995_AIF1DAC1_MUTE_SHIFT); + return 0; +} + +static int wm8995_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt) +{ + struct snd_soc_codec *codec; + int master; + int aif; + + codec = dai->codec; + + master = 0; + switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { + case SND_SOC_DAIFMT_CBS_CFS: + break; + case SND_SOC_DAIFMT_CBM_CFM: + master = WM8995_AIF1_MSTR; + break; + default: + dev_err(dai->dev, "Unknown master/slave configuration\n"); + return -EINVAL; + } + + aif = 0; + switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { + case SND_SOC_DAIFMT_DSP_B: + aif |= WM8995_AIF1_LRCLK_INV; + case SND_SOC_DAIFMT_DSP_A: + aif |= (0x3 << WM8995_AIF1_FMT_SHIFT); + break; + case SND_SOC_DAIFMT_I2S: + aif |= (0x2 << WM8995_AIF1_FMT_SHIFT); + break; + case SND_SOC_DAIFMT_RIGHT_J: + break; + case SND_SOC_DAIFMT_LEFT_J: + aif |= (0x1 << WM8995_AIF1_FMT_SHIFT); + break; + default: + dev_err(dai->dev, "Unknown dai format\n"); + return -EINVAL; + } + + switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { + case SND_SOC_DAIFMT_DSP_A: + case SND_SOC_DAIFMT_DSP_B: + /* frame inversion not valid for DSP modes */ + switch (fmt & SND_SOC_DAIFMT_INV_MASK) { + case SND_SOC_DAIFMT_NB_NF: + break; + case SND_SOC_DAIFMT_IB_NF: + aif |= WM8995_AIF1_BCLK_INV; + break; + default: + return -EINVAL; + } + break; + + case SND_SOC_DAIFMT_I2S: + case SND_SOC_DAIFMT_RIGHT_J: + case SND_SOC_DAIFMT_LEFT_J: + switch (fmt & SND_SOC_DAIFMT_INV_MASK) { + case SND_SOC_DAIFMT_NB_NF: + break; + case SND_SOC_DAIFMT_IB_IF: + aif |= WM8995_AIF1_BCLK_INV | WM8995_AIF1_LRCLK_INV; + break; + case SND_SOC_DAIFMT_IB_NF: + aif |= WM8995_AIF1_BCLK_INV; + break; + case SND_SOC_DAIFMT_NB_IF: + aif |= WM8995_AIF1_LRCLK_INV; + break; + default: + return -EINVAL; + } + break; + default: + return -EINVAL; + } + + snd_soc_update_bits(codec, WM8995_AIF1_CONTROL_1, + WM8995_AIF1_BCLK_INV_MASK | + WM8995_AIF1_LRCLK_INV_MASK | + WM8995_AIF1_FMT_MASK, aif); + snd_soc_update_bits(codec, WM8995_AIF1_MASTER_SLAVE, + WM8995_AIF1_MSTR_MASK, master); + return 0; +} + +static const int srs[] = { + 8000, 11025, 12000, 16000, 22050, 24000, 32000, 44100, + 48000, 88200, 96000 +}; + +static const int fs_ratios[] = { + -1 /* reserved */, + 128, 192, 256, 384, 512, 768, 1024, 1408, 1536 +}; + +static const int bclk_divs[] = { + 10, 15, 20, 30, 40, 55, 60, 80, 110, 120, 160, 220, 240, 320, 440, 480 +}; + +static int wm8995_hw_params(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params, + struct snd_soc_dai *dai) +{ + struct snd_soc_codec *codec; + struct wm8995_priv *wm8995; + int aif1_reg; + int bclk_reg; + int lrclk_reg; + int rate_reg; + int bclk_rate; + int aif1; + int lrclk, bclk; + int i, rate_val, best, best_val, cur_val; + + codec = dai->codec; + wm8995 = snd_soc_codec_get_drvdata(codec); + + switch (dai->id) { + case 0: + aif1_reg = WM8995_AIF1_CONTROL_1; + bclk_reg = WM8995_AIF1_BCLK; + rate_reg = WM8995_AIF1_RATE; + if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK /* || + wm8995->lrclk_shared[0] */) { + lrclk_reg = WM8995_AIF1DAC_LRCLK; + } else { + lrclk_reg = WM8995_AIF1ADC_LRCLK; + dev_dbg(codec->dev, "AIF1 using split LRCLK\n"); + } + break; + case 1: + aif1_reg = WM8995_AIF2_CONTROL_1; + bclk_reg = WM8995_AIF2_BCLK; + rate_reg = WM8995_AIF2_RATE; + if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK /* || + wm8995->lrclk_shared[1] */) { + lrclk_reg = WM8995_AIF2DAC_LRCLK; + } else { + lrclk_reg = WM8995_AIF2ADC_LRCLK; + dev_dbg(codec->dev, "AIF2 using split LRCLK\n"); + } + break; + default: + return -EINVAL; + } + + bclk_rate = snd_soc_params_to_bclk(params); + if (bclk_rate < 0) + return bclk_rate; + + aif1 = 0; + switch (params_format(params)) { + case SNDRV_PCM_FORMAT_S16_LE: + break; + case SNDRV_PCM_FORMAT_S20_3LE: + aif1 |= (0x1 << WM8995_AIF1_WL_SHIFT); + break; + case SNDRV_PCM_FORMAT_S24_LE: + aif1 |= (0x2 << WM8995_AIF1_WL_SHIFT); + break; + case SNDRV_PCM_FORMAT_S32_LE: + aif1 |= (0x3 << WM8995_AIF1_WL_SHIFT); + break; + default: + dev_err(dai->dev, "Unsupported word length %u\n", + params_format(params)); + return -EINVAL; + } + + /* try to find a suitable sample rate */ + for (i = 0; i < ARRAY_SIZE(srs); ++i) + if (srs[i] == params_rate(params)) + break; + if (i == ARRAY_SIZE(srs)) { + dev_err(dai->dev, "Sample rate %d is not supported\n", + params_rate(params)); + return -EINVAL; + } + rate_val = i << WM8995_AIF1_SR_SHIFT; + + dev_dbg(dai->dev, "Sample rate is %dHz\n", srs[i]); + dev_dbg(dai->dev, "AIF%dCLK is %dHz, target BCLK %dHz\n", + dai->id + 1, wm8995->aifclk[dai->id], bclk_rate); + + /* AIFCLK/fs ratio; look for a close match in either direction */ + best = 1; + best_val = abs((fs_ratios[1] * params_rate(params)) + - wm8995->aifclk[dai->id]); + for (i = 2; i < ARRAY_SIZE(fs_ratios); i++) { + cur_val = abs((fs_ratios[i] * params_rate(params)) + - wm8995->aifclk[dai->id]); + if (cur_val >= best_val) + continue; + best = i; + best_val = cur_val; + } + rate_val |= best; + + dev_dbg(dai->dev, "Selected AIF%dCLK/fs = %d\n", + dai->id + 1, fs_ratios[best]); + + /* + * We may not get quite the right frequency if using + * approximate clocks so look for the closest match that is + * higher than the target (we need to ensure that there enough + * BCLKs to clock out the samples). + */ + best = 0; + bclk = 0; + for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) { + cur_val = (wm8995->aifclk[dai->id] * 10 / bclk_divs[i]) - bclk_rate; + if (cur_val < 0) /* BCLK table is sorted */ + break; + best = i; + } + bclk |= best << WM8995_AIF1_BCLK_DIV_SHIFT; + + bclk_rate = wm8995->aifclk[dai->id] * 10 / bclk_divs[best]; + dev_dbg(dai->dev, "Using BCLK_DIV %d for actual BCLK %dHz\n", + bclk_divs[best], bclk_rate); + + lrclk = bclk_rate / params_rate(params); + dev_dbg(dai->dev, "Using LRCLK rate %d for actual LRCLK %dHz\n", + lrclk, bclk_rate / lrclk); + + snd_soc_update_bits(codec, aif1_reg, + WM8995_AIF1_WL_MASK, aif1); + snd_soc_update_bits(codec, bclk_reg, + WM8995_AIF1_BCLK_DIV_MASK, bclk); + snd_soc_update_bits(codec, lrclk_reg, + WM8995_AIF1DAC_RATE_MASK, lrclk); + snd_soc_update_bits(codec, rate_reg, + WM8995_AIF1_SR_MASK | + WM8995_AIF1CLK_RATE_MASK, rate_val); + return 0; +} + +static int wm8995_set_tristate(struct snd_soc_dai *codec_dai, int tristate) +{ + struct snd_soc_codec *codec = codec_dai->codec; + int reg, val, mask; + + switch (codec_dai->id) { + case 0: + reg = WM8995_AIF1_MASTER_SLAVE; + mask = WM8995_AIF1_TRI; + break; + case 1: + reg = WM8995_AIF2_MASTER_SLAVE; + mask = WM8995_AIF2_TRI; + break; + case 2: + reg = WM8995_POWER_MANAGEMENT_5; + mask = WM8995_AIF3_TRI; + break; + default: + return -EINVAL; + } + + if (tristate) + val = mask; + else + val = 0; + + return snd_soc_update_bits(codec, reg, mask, reg); +} + +/* The size in bits of the FLL divide multiplied by 10 + * to allow rounding later */ +#define FIXED_FLL_SIZE ((1 << 16) * 10) + +struct fll_div { + u16 outdiv; + u16 n; + u16 k; + u16 clk_ref_div; + u16 fll_fratio; +}; + +static int wm8995_get_fll_config(struct fll_div *fll, + int freq_in, int freq_out) +{ + u64 Kpart; + unsigned int K, Ndiv, Nmod; + + pr_debug("FLL input=%dHz, output=%dHz\n", freq_in, freq_out); + + /* Scale the input frequency down to <= 13.5MHz */ + fll->clk_ref_div = 0; + while (freq_in > 13500000) { + fll->clk_ref_div++; + freq_in /= 2; + + if (fll->clk_ref_div > 3) + return -EINVAL; + } + pr_debug("CLK_REF_DIV=%d, Fref=%dHz\n", fll->clk_ref_div, freq_in); + + /* Scale the output to give 90MHz<=Fvco<=100MHz */ + fll->outdiv = 3; + while (freq_out * (fll->outdiv + 1) < 90000000) { + fll->outdiv++; + if (fll->outdiv > 63) + return -EINVAL; + } + freq_out *= fll->outdiv + 1; + pr_debug("OUTDIV=%d, Fvco=%dHz\n", fll->outdiv, freq_out); + + if (freq_in > 1000000) { + fll->fll_fratio = 0; + } else if (freq_in > 256000) { + fll->fll_fratio = 1; + freq_in *= 2; + } else if (freq_in > 128000) { + fll->fll_fratio = 2; + freq_in *= 4; + } else if (freq_in > 64000) { + fll->fll_fratio = 3; + freq_in *= 8; + } else { + fll->fll_fratio = 4; + freq_in *= 16; + } + pr_debug("FLL_FRATIO=%d, Fref=%dHz\n", fll->fll_fratio, freq_in); + + /* Now, calculate N.K */ + Ndiv = freq_out / freq_in; + + fll->n = Ndiv; + Nmod = freq_out % freq_in; + pr_debug("Nmod=%d\n", Nmod); + + /* Calculate fractional part - scale up so we can round. */ + Kpart = FIXED_FLL_SIZE * (long long)Nmod; + + do_div(Kpart, freq_in); + + K = Kpart & 0xFFFFFFFF; + + if ((K % 10) >= 5) + K += 5; + + /* Move down to proper range now rounding is done */ + fll->k = K / 10; + + pr_debug("N=%x K=%x\n", fll->n, fll->k); + + return 0; +} + +static int wm8995_set_fll(struct snd_soc_dai *dai, int id, + int src, unsigned int freq_in, + unsigned int freq_out) +{ + struct snd_soc_codec *codec; + struct wm8995_priv *wm8995; + int reg_offset, ret; + struct fll_div fll; + u16 reg, aif1, aif2; + + codec = dai->codec; + wm8995 = snd_soc_codec_get_drvdata(codec); + + aif1 = snd_soc_read(codec, WM8995_AIF1_CLOCKING_1) + & WM8995_AIF1CLK_ENA; + + aif2 = snd_soc_read(codec, WM8995_AIF2_CLOCKING_1) + & WM8995_AIF2CLK_ENA; + + switch (id) { + case WM8995_FLL1: + reg_offset = 0; + id = 0; + break; + case WM8995_FLL2: + reg_offset = 0x20; + id = 1; + break; + default: + return -EINVAL; + } + + switch (src) { + case 0: + /* Allow no source specification when stopping */ + if (freq_out) + return -EINVAL; + break; + case WM8995_FLL_SRC_MCLK1: + case WM8995_FLL_SRC_MCLK2: + case WM8995_FLL_SRC_LRCLK: + case WM8995_FLL_SRC_BCLK: + break; + default: + return -EINVAL; + } + + /* Are we changing anything? */ + if (wm8995->fll[id].src == src && + wm8995->fll[id].in == freq_in && wm8995->fll[id].out == freq_out) + return 0; + + /* If we're stopping the FLL redo the old config - no + * registers will actually be written but we avoid GCC flow + * analysis bugs spewing warnings. + */ + if (freq_out) + ret = wm8995_get_fll_config(&fll, freq_in, freq_out); + else + ret = wm8995_get_fll_config(&fll, wm8995->fll[id].in, + wm8995->fll[id].out); + if (ret < 0) + return ret; + + /* Gate the AIF clocks while we reclock */ + snd_soc_update_bits(codec, WM8995_AIF1_CLOCKING_1, + WM8995_AIF1CLK_ENA_MASK, 0); + snd_soc_update_bits(codec, WM8995_AIF2_CLOCKING_1, + WM8995_AIF2CLK_ENA_MASK, 0); + + /* We always need to disable the FLL while reconfiguring */ + snd_soc_update_bits(codec, WM8995_FLL1_CONTROL_1 + reg_offset, + WM8995_FLL1_ENA_MASK, 0); + + reg = (fll.outdiv << WM8995_FLL1_OUTDIV_SHIFT) | + (fll.fll_fratio << WM8995_FLL1_FRATIO_SHIFT); + snd_soc_update_bits(codec, WM8995_FLL1_CONTROL_2 + reg_offset, + WM8995_FLL1_OUTDIV_MASK | + WM8995_FLL1_FRATIO_MASK, reg); + + snd_soc_write(codec, WM8995_FLL1_CONTROL_3 + reg_offset, fll.k); + + snd_soc_update_bits(codec, WM8995_FLL1_CONTROL_4 + reg_offset, + WM8995_FLL1_N_MASK, + fll.n << WM8995_FLL1_N_SHIFT); + + snd_soc_update_bits(codec, WM8995_FLL1_CONTROL_5 + reg_offset, + WM8995_FLL1_REFCLK_DIV_MASK | + WM8995_FLL1_REFCLK_SRC_MASK, + (fll.clk_ref_div << WM8995_FLL1_REFCLK_DIV_SHIFT) | + (src - 1)); + + if (freq_out) + snd_soc_update_bits(codec, WM8995_FLL1_CONTROL_1 + reg_offset, + WM8995_FLL1_ENA_MASK, WM8995_FLL1_ENA); + + wm8995->fll[id].in = freq_in; + wm8995->fll[id].out = freq_out; + wm8995->fll[id].src = src; + + /* Enable any gated AIF clocks */ + snd_soc_update_bits(codec, WM8995_AIF1_CLOCKING_1, + WM8995_AIF1CLK_ENA_MASK, aif1); + snd_soc_update_bits(codec, WM8995_AIF2_CLOCKING_1, + WM8995_AIF2CLK_ENA_MASK, aif2); + + configure_clock(codec); + + return 0; +} + +static int wm8995_set_dai_sysclk(struct snd_soc_dai *dai, + int clk_id, unsigned int freq, int dir) +{ + struct snd_soc_codec *codec; + struct wm8995_priv *wm8995; + + codec = dai->codec; + wm8995 = snd_soc_codec_get_drvdata(codec); + + switch (dai->id) { + case 0: + case 1: + break; + default: + /* AIF3 shares clocking with AIF1/2 */ + return -EINVAL; + } + + switch (clk_id) { + case WM8995_SYSCLK_MCLK1: + wm8995->sysclk[dai->id] = WM8995_SYSCLK_MCLK1; + wm8995->mclk[0] = freq; + dev_dbg(dai->dev, "AIF%d using MCLK1 at %uHz\n", + dai->id + 1, freq); + break; + case WM8995_SYSCLK_MCLK2: + wm8995->sysclk[dai->id] = WM8995_SYSCLK_MCLK1; + wm8995->mclk[1] = freq; + dev_dbg(dai->dev, "AIF%d using MCLK2 at %uHz\n", + dai->id + 1, freq); + break; + case WM8995_SYSCLK_FLL1: + wm8995->sysclk[dai->id] = WM8995_SYSCLK_FLL1; + dev_dbg(dai->dev, "AIF%d using FLL1\n", dai->id + 1); + break; + case WM8995_SYSCLK_FLL2: + wm8995->sysclk[dai->id] = WM8995_SYSCLK_FLL2; + dev_dbg(dai->dev, "AIF%d using FLL2\n", dai->id + 1); + break; + case WM8995_SYSCLK_OPCLK: + default: + dev_err(dai->dev, "Unknown clock source %d\n", clk_id); + return -EINVAL; + } + + configure_clock(codec); + + return 0; +} + +static int wm8995_set_bias_level(struct snd_soc_codec *codec, + enum snd_soc_bias_level level) +{ + struct wm8995_priv *wm8995; + int ret; + + wm8995 = snd_soc_codec_get_drvdata(codec); + switch (level) { + case SND_SOC_BIAS_ON: + case SND_SOC_BIAS_PREPARE: + break; + case SND_SOC_BIAS_STANDBY: + if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) { + ret = snd_soc_cache_sync(codec); + if (ret) { + dev_err(codec->dev, + "Failed to sync cache: %d\n", ret); + return ret; + } + + snd_soc_update_bits(codec, WM8995_POWER_MANAGEMENT_1, + WM8995_BG_ENA_MASK, WM8995_BG_ENA); + + } + break; + case SND_SOC_BIAS_OFF: + snd_soc_update_bits(codec, WM8995_POWER_MANAGEMENT_1, + WM8995_BG_ENA_MASK, 0); + break; + } + + codec->dapm.bias_level = level; + return 0; +} + +#ifdef CONFIG_PM +static int wm8995_suspend(struct snd_soc_codec *codec, pm_message_t state) +{ + wm8995_set_bias_level(codec, SND_SOC_BIAS_OFF); + return 0; +} + +static int wm8995_resume(struct snd_soc_codec *codec) +{ + wm8995_set_bias_level(codec, SND_SOC_BIAS_STANDBY); + return 0; +} +#else +#define wm8995_suspend NULL +#define wm8995_resume NULL +#endif + +static int wm8995_remove(struct snd_soc_codec *codec) +{ + struct wm8995_priv *wm8995; + struct i2c_client *i2c; + + i2c = container_of(codec->dev, struct i2c_client, dev); + wm8995 = snd_soc_codec_get_drvdata(codec); + wm8995_set_bias_level(codec, SND_SOC_BIAS_OFF); + return 0; +} + +static int wm8995_probe(struct snd_soc_codec *codec) +{ + struct wm8995_priv *wm8995; + int ret; + + codec->dapm.idle_bias_off = 1; + wm8995 = snd_soc_codec_get_drvdata(codec); + + ret = snd_soc_codec_set_cache_io(codec, 16, 16, wm8995->control_type); + if (ret < 0) { + dev_err(codec->dev, "Failed to set cache i/o: %d\n", ret); + return ret; + } + + ret = snd_soc_read(codec, WM8995_SOFTWARE_RESET); + if (ret < 0) { + dev_err(codec->dev, "Failed to read device ID: %d\n", ret); + return ret; + } + + if (ret != 0x8995) { + dev_err(codec->dev, "Invalid device ID: %#x\n", ret); + return -EINVAL; + } + + ret = snd_soc_write(codec, WM8995_SOFTWARE_RESET, 0); + if (ret < 0) { + dev_err(codec->dev, "Failed to issue reset: %d\n", ret); + return ret; + } + + wm8995_set_bias_level(codec, SND_SOC_BIAS_STANDBY); + + /* Latch volume updates (right only; we always do left then right). */ + snd_soc_update_bits(codec, WM8995_AIF1_DAC1_RIGHT_VOLUME, + WM8995_AIF1DAC1_VU_MASK, WM8995_AIF1DAC1_VU); + snd_soc_update_bits(codec, WM8995_AIF1_DAC2_RIGHT_VOLUME, + WM8995_AIF1DAC2_VU_MASK, WM8995_AIF1DAC2_VU); + snd_soc_update_bits(codec, WM8995_AIF2_DAC_RIGHT_VOLUME, + WM8995_AIF2DAC_VU_MASK, WM8995_AIF2DAC_VU); + snd_soc_update_bits(codec, WM8995_AIF1_ADC1_RIGHT_VOLUME, + WM8995_AIF1ADC1_VU_MASK, WM8995_AIF1ADC1_VU); + snd_soc_update_bits(codec, WM8995_AIF1_ADC2_RIGHT_VOLUME, + WM8995_AIF1ADC2_VU_MASK, WM8995_AIF1ADC2_VU); + snd_soc_update_bits(codec, WM8995_AIF2_ADC_RIGHT_VOLUME, + WM8995_AIF2ADC_VU_MASK, WM8995_AIF1ADC2_VU); + snd_soc_update_bits(codec, WM8995_DAC1_RIGHT_VOLUME, + WM8995_DAC1_VU_MASK, WM8995_DAC1_VU); + snd_soc_update_bits(codec, WM8995_DAC2_RIGHT_VOLUME, + WM8995_DAC2_VU_MASK, WM8995_DAC2_VU); + snd_soc_update_bits(codec, WM8995_RIGHT_LINE_INPUT_1_VOLUME, + WM8995_IN1_VU_MASK, WM8995_IN1_VU); + + wm8995_update_class_w(codec); + + snd_soc_add_controls(codec, wm8995_snd_controls, + ARRAY_SIZE(wm8995_snd_controls)); + snd_soc_dapm_new_controls(&codec->dapm, wm8995_dapm_widgets, + ARRAY_SIZE(wm8995_dapm_widgets)); + snd_soc_dapm_add_routes(&codec->dapm, wm8995_intercon, + ARRAY_SIZE(wm8995_intercon)); + + return 0; +} + +#define WM8995_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\ + SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE) + +static struct snd_soc_dai_ops wm8995_aif1_dai_ops = { + .set_sysclk = wm8995_set_dai_sysclk, + .set_fmt = wm8995_set_dai_fmt, + .hw_params = wm8995_hw_params, + .digital_mute = wm8995_aif_mute, + .set_pll = wm8995_set_fll, + .set_tristate = wm8995_set_tristate, +}; + +static struct snd_soc_dai_ops wm8995_aif2_dai_ops = { + .set_sysclk = wm8995_set_dai_sysclk, + .set_fmt = wm8995_set_dai_fmt, + .hw_params = wm8995_hw_params, + .digital_mute = wm8995_aif_mute, + .set_pll = wm8995_set_fll, + .set_tristate = wm8995_set_tristate, +}; + +static struct snd_soc_dai_ops wm8995_aif3_dai_ops = { + .set_tristate = wm8995_set_tristate, +}; + +static struct snd_soc_dai_driver wm8995_dai[] = { + { + .name = "wm8995-aif1", + .playback = { + .stream_name = "AIF1 Playback", + .channels_min = 2, + .channels_max = 2, + .rates = SNDRV_PCM_RATE_8000_96000, + .formats = WM8995_FORMATS + }, + .capture = { + .stream_name = "AIF1 Capture", + .channels_min = 2, + .channels_max = 2, + .rates = SNDRV_PCM_RATE_8000_48000, + .formats = WM8995_FORMATS + }, + .ops = &wm8995_aif1_dai_ops + }, + { + .name = "wm8995-aif2", + .playback = { + .stream_name = "AIF2 Playback", + .channels_min = 2, + .channels_max = 2, + .rates = SNDRV_PCM_RATE_8000_96000, + .formats = WM8995_FORMATS + }, + .capture = { + .stream_name = "AIF2 Capture", + .channels_min = 2, + .channels_max = 2, + .rates = SNDRV_PCM_RATE_8000_48000, + .formats = WM8995_FORMATS + }, + .ops = &wm8995_aif2_dai_ops + }, + { + .name = "wm8995-aif3", + .playback = { + .stream_name = "AIF3 Playback", + .channels_min = 2, + .channels_max = 2, + .rates = SNDRV_PCM_RATE_8000_96000, + .formats = WM8995_FORMATS + }, + .capture = { + .stream_name = "AIF3 Capture", + .channels_min = 2, + .channels_max = 2, + .rates = SNDRV_PCM_RATE_8000_48000, + .formats = WM8995_FORMATS + }, + .ops = &wm8995_aif3_dai_ops + } +}; + +static struct snd_soc_codec_driver soc_codec_dev_wm8995 = { + .probe = wm8995_probe, + .remove = wm8995_remove, + .suspend = wm8995_suspend, + .resume = wm8995_resume, + .set_bias_level = wm8995_set_bias_level, + .reg_cache_size = ARRAY_SIZE(wm8995_reg_defs), + .reg_word_size = sizeof(u16), + .reg_cache_default = wm8995_reg_defs, + .volatile_register = wm8995_volatile, + .compress_type = SND_SOC_RBTREE_COMPRESSION +}; + +#if defined(CONFIG_SPI_MASTER) +static int __devinit wm8995_spi_probe(struct spi_device *spi) +{ + struct wm8995_priv *wm8995; + int ret; + + wm8995 = kzalloc(sizeof *wm8995, GFP_KERNEL); + if (!wm8995) + return -ENOMEM; + + wm8995->control_type = SND_SOC_SPI; + spi_set_drvdata(spi, wm8995); + + ret = snd_soc_register_codec(&spi->dev, + &soc_codec_dev_wm8995, wm8995_dai, + ARRAY_SIZE(wm8995_dai)); + if (ret < 0) + kfree(wm8995); + return ret; +} + +static int __devexit wm8995_spi_remove(struct spi_device *spi) +{ + snd_soc_unregister_codec(&spi->dev); + kfree(spi_get_drvdata(spi)); + return 0; +} + +static struct spi_driver wm8995_spi_driver = { + .driver = { + .name = "wm8995", + .owner = THIS_MODULE, + }, + .probe = wm8995_spi_probe, + .remove = __devexit_p(wm8995_spi_remove) +}; +#endif + +#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) +static __devinit int wm8995_i2c_probe(struct i2c_client *i2c, + const struct i2c_device_id *id) +{ + struct wm8995_priv *wm8995; + int ret; + + wm8995 = kzalloc(sizeof *wm8995, GFP_KERNEL); + if (!wm8995) + return -ENOMEM; + + wm8995->control_type = SND_SOC_I2C; + i2c_set_clientdata(i2c, wm8995); + + ret = snd_soc_register_codec(&i2c->dev, + &soc_codec_dev_wm8995, wm8995_dai, + ARRAY_SIZE(wm8995_dai)); + if (ret < 0) + kfree(wm8995); + return ret; +} + +static __devexit int wm8995_i2c_remove(struct i2c_client *client) +{ + snd_soc_unregister_codec(&client->dev); + kfree(i2c_get_clientdata(client)); + return 0; +} + +static const struct i2c_device_id wm8995_i2c_id[] = { + {"wm8995", 0}, + {} +}; + +MODULE_DEVICE_TABLE(i2c, wm8995_i2c_id); + +static struct i2c_driver wm8995_i2c_driver = { + .driver = { + .name = "wm8995", + .owner = THIS_MODULE, + }, + .probe = wm8995_i2c_probe, + .remove = __devexit_p(wm8995_i2c_remove), + .id_table = wm8995_i2c_id +}; +#endif + +static int __init wm8995_modinit(void) +{ + int ret = 0; + +#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) + ret = i2c_add_driver(&wm8995_i2c_driver); + if (ret) { + printk(KERN_ERR "Failed to register wm8995 I2C driver: %d\n", + ret); + } +#endif +#if defined(CONFIG_SPI_MASTER) + ret = spi_register_driver(&wm8995_spi_driver); + if (ret) { + printk(KERN_ERR "Failed to register wm8995 SPI driver: %d\n", + ret); + } +#endif + return ret; +} + +module_init(wm8995_modinit); + +static void __exit wm8995_exit(void) +{ +#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) + i2c_del_driver(&wm8995_i2c_driver); +#endif +#if defined(CONFIG_SPI_MASTER) + spi_unregister_driver(&wm8995_spi_driver); +#endif +} + +module_exit(wm8995_exit); + +MODULE_DESCRIPTION("ASoC WM8995 driver"); +MODULE_AUTHOR("Dimitris Papastamos "); +MODULE_LICENSE("GPL"); diff --git a/sound/soc/codecs/wm8995.h b/sound/soc/codecs/wm8995.h new file mode 100644 index 000000000000..6409e5a6b574 --- /dev/null +++ b/sound/soc/codecs/wm8995.h @@ -0,0 +1,8749 @@ +/* + * wm8995.h -- WM8995 ALSA SoC Audio driver + * + * Copyright 2010 Wolfson Microelectronics plc + * + * Author: Dimitris Papastamos + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef _WM8995_H +#define _WM8995_H + +#include + +/* + * Register values. + */ +#define WM8995_SOFTWARE_RESET 0x00 +#define WM8995_POWER_MANAGEMENT_1 0x01 +#define WM8995_POWER_MANAGEMENT_2 0x02 +#define WM8995_POWER_MANAGEMENT_3 0x03 +#define WM8995_POWER_MANAGEMENT_4 0x04 +#define WM8995_POWER_MANAGEMENT_5 0x05 +#define WM8995_LEFT_LINE_INPUT_1_VOLUME 0x10 +#define WM8995_RIGHT_LINE_INPUT_1_VOLUME 0x11 +#define WM8995_LEFT_LINE_INPUT_CONTROL 0x12 +#define WM8995_DAC1_LEFT_VOLUME 0x18 +#define WM8995_DAC1_RIGHT_VOLUME 0x19 +#define WM8995_DAC2_LEFT_VOLUME 0x1A +#define WM8995_DAC2_RIGHT_VOLUME 0x1B +#define WM8995_OUTPUT_VOLUME_ZC_1 0x1C +#define WM8995_MICBIAS_1 0x20 +#define WM8995_MICBIAS_2 0x21 +#define WM8995_LDO_1 0x28 +#define WM8995_LDO_2 0x29 +#define WM8995_ACCESSORY_DETECT_MODE1 0x30 +#define WM8995_ACCESSORY_DETECT_MODE2 0x31 +#define WM8995_HEADPHONE_DETECT1 0x34 +#define WM8995_HEADPHONE_DETECT2 0x35 +#define WM8995_MIC_DETECT_1 0x38 +#define WM8995_MIC_DETECT_2 0x39 +#define WM8995_CHARGE_PUMP_1 0x40 +#define WM8995_CLASS_W_1 0x45 +#define WM8995_DC_SERVO_1 0x50 +#define WM8995_DC_SERVO_2 0x51 +#define WM8995_DC_SERVO_3 0x52 +#define WM8995_DC_SERVO_5 0x54 +#define WM8995_DC_SERVO_6 0x55 +#define WM8995_DC_SERVO_7 0x56 +#define WM8995_DC_SERVO_READBACK_0 0x57 +#define WM8995_ANALOGUE_HP_1 0x60 +#define WM8995_ANALOGUE_HP_2 0x61 +#define WM8995_CHIP_REVISION 0x100 +#define WM8995_CONTROL_INTERFACE_1 0x101 +#define WM8995_CONTROL_INTERFACE_2 0x102 +#define WM8995_WRITE_SEQUENCER_CTRL_1 0x110 +#define WM8995_WRITE_SEQUENCER_CTRL_2 0x111 +#define WM8995_AIF1_CLOCKING_1 0x200 +#define WM8995_AIF1_CLOCKING_2 0x201 +#define WM8995_AIF2_CLOCKING_1 0x204 +#define WM8995_AIF2_CLOCKING_2 0x205 +#define WM8995_CLOCKING_1 0x208 +#define WM8995_CLOCKING_2 0x209 +#define WM8995_AIF1_RATE 0x210 +#define WM8995_AIF2_RATE 0x211 +#define WM8995_RATE_STATUS 0x212 +#define WM8995_FLL1_CONTROL_1 0x220 +#define WM8995_FLL1_CONTROL_2 0x221 +#define WM8995_FLL1_CONTROL_3 0x222 +#define WM8995_FLL1_CONTROL_4 0x223 +#define WM8995_FLL1_CONTROL_5 0x224 +#define WM8995_FLL2_CONTROL_1 0x240 +#define WM8995_FLL2_CONTROL_2 0x241 +#define WM8995_FLL2_CONTROL_3 0x242 +#define WM8995_FLL2_CONTROL_4 0x243 +#define WM8995_FLL2_CONTROL_5 0x244 +#define WM8995_AIF1_CONTROL_1 0x300 +#define WM8995_AIF1_CONTROL_2 0x301 +#define WM8995_AIF1_MASTER_SLAVE 0x302 +#define WM8995_AIF1_BCLK 0x303 +#define WM8995_AIF1ADC_LRCLK 0x304 +#define WM8995_AIF1DAC_LRCLK 0x305 +#define WM8995_AIF1DAC_DATA 0x306 +#define WM8995_AIF1ADC_DATA 0x307 +#define WM8995_AIF2_CONTROL_1 0x310 +#define WM8995_AIF2_CONTROL_2 0x311 +#define WM8995_AIF2_MASTER_SLAVE 0x312 +#define WM8995_AIF2_BCLK 0x313 +#define WM8995_AIF2ADC_LRCLK 0x314 +#define WM8995_AIF2DAC_LRCLK 0x315 +#define WM8995_AIF2DAC_DATA 0x316 +#define WM8995_AIF2ADC_DATA 0x317 +#define WM8995_AIF1_ADC1_LEFT_VOLUME 0x400 +#define WM8995_AIF1_ADC1_RIGHT_VOLUME 0x401 +#define WM8995_AIF1_DAC1_LEFT_VOLUME 0x402 +#define WM8995_AIF1_DAC1_RIGHT_VOLUME 0x403 +#define WM8995_AIF1_ADC2_LEFT_VOLUME 0x404 +#define WM8995_AIF1_ADC2_RIGHT_VOLUME 0x405 +#define WM8995_AIF1_DAC2_LEFT_VOLUME 0x406 +#define WM8995_AIF1_DAC2_RIGHT_VOLUME 0x407 +#define WM8995_AIF1_ADC1_FILTERS 0x410 +#define WM8995_AIF1_ADC2_FILTERS 0x411 +#define WM8995_AIF1_DAC1_FILTERS_1 0x420 +#define WM8995_AIF1_DAC1_FILTERS_2 0x421 +#define WM8995_AIF1_DAC2_FILTERS_1 0x422 +#define WM8995_AIF1_DAC2_FILTERS_2 0x423 +#define WM8995_AIF1_DRC1_1 0x440 +#define WM8995_AIF1_DRC1_2 0x441 +#define WM8995_AIF1_DRC1_3 0x442 +#define WM8995_AIF1_DRC1_4 0x443 +#define WM8995_AIF1_DRC1_5 0x444 +#define WM8995_AIF1_DRC2_1 0x450 +#define WM8995_AIF1_DRC2_2 0x451 +#define WM8995_AIF1_DRC2_3 0x452 +#define WM8995_AIF1_DRC2_4 0x453 +#define WM8995_AIF1_DRC2_5 0x454 +#define WM8995_AIF1_DAC1_EQ_GAINS_1 0x480 +#define WM8995_AIF1_DAC1_EQ_GAINS_2 0x481 +#define WM8995_AIF1_DAC1_EQ_BAND_1_A 0x482 +#define WM8995_AIF1_DAC1_EQ_BAND_1_B 0x483 +#define WM8995_AIF1_DAC1_EQ_BAND_1_PG 0x484 +#define WM8995_AIF1_DAC1_EQ_BAND_2_A 0x485 +#define WM8995_AIF1_DAC1_EQ_BAND_2_B 0x486 +#define WM8995_AIF1_DAC1_EQ_BAND_2_C 0x487 +#define WM8995_AIF1_DAC1_EQ_BAND_2_PG 0x488 +#define WM8995_AIF1_DAC1_EQ_BAND_3_A 0x489 +#define WM8995_AIF1_DAC1_EQ_BAND_3_B 0x48A +#define WM8995_AIF1_DAC1_EQ_BAND_3_C 0x48B +#define WM8995_AIF1_DAC1_EQ_BAND_3_PG 0x48C +#define WM8995_AIF1_DAC1_EQ_BAND_4_A 0x48D +#define WM8995_AIF1_DAC1_EQ_BAND_4_B 0x48E +#define WM8995_AIF1_DAC1_EQ_BAND_4_C 0x48F +#define WM8995_AIF1_DAC1_EQ_BAND_4_PG 0x490 +#define WM8995_AIF1_DAC1_EQ_BAND_5_A 0x491 +#define WM8995_AIF1_DAC1_EQ_BAND_5_B 0x492 +#define WM8995_AIF1_DAC1_EQ_BAND_5_PG 0x493 +#define WM8995_AIF1_DAC2_EQ_GAINS_1 0x4A0 +#define WM8995_AIF1_DAC2_EQ_GAINS_2 0x4A1 +#define WM8995_AIF1_DAC2_EQ_BAND_1_A 0x4A2 +#define WM8995_AIF1_DAC2_EQ_BAND_1_B 0x4A3 +#define WM8995_AIF1_DAC2_EQ_BAND_1_PG 0x4A4 +#define WM8995_AIF1_DAC2_EQ_BAND_2_A 0x4A5 +#define WM8995_AIF1_DAC2_EQ_BAND_2_B 0x4A6 +#define WM8995_AIF1_DAC2_EQ_BAND_2_C 0x4A7 +#define WM8995_AIF1_DAC2_EQ_BAND_2_PG 0x4A8 +#define WM8995_AIF1_DAC2_EQ_BAND_3_A 0x4A9 +#define WM8995_AIF1_DAC2_EQ_BAND_3_B 0x4AA +#define WM8995_AIF1_DAC2_EQ_BAND_3_C 0x4AB +#define WM8995_AIF1_DAC2_EQ_BAND_3_PG 0x4AC +#define WM8995_AIF1_DAC2_EQ_BAND_4_A 0x4AD +#define WM8995_AIF1_DAC2_EQ_BAND_4_B 0x4AE +#define WM8995_AIF1_DAC2_EQ_BAND_4_C 0x4AF +#define WM8995_AIF1_DAC2_EQ_BAND_4_PG 0x4B0 +#define WM8995_AIF1_DAC2_EQ_BAND_5_A 0x4B1 +#define WM8995_AIF1_DAC2_EQ_BAND_5_B 0x4B2 +#define WM8995_AIF1_DAC2_EQ_BAND_5_PG 0x4B3 +#define WM8995_AIF2_ADC_LEFT_VOLUME 0x500 +#define WM8995_AIF2_ADC_RIGHT_VOLUME 0x501 +#define WM8995_AIF2_DAC_LEFT_VOLUME 0x502 +#define WM8995_AIF2_DAC_RIGHT_VOLUME 0x503 +#define WM8995_AIF2_ADC_FILTERS 0x510 +#define WM8995_AIF2_DAC_FILTERS_1 0x520 +#define WM8995_AIF2_DAC_FILTERS_2 0x521 +#define WM8995_AIF2_DRC_1 0x540 +#define WM8995_AIF2_DRC_2 0x541 +#define WM8995_AIF2_DRC_3 0x542 +#define WM8995_AIF2_DRC_4 0x543 +#define WM8995_AIF2_DRC_5 0x544 +#define WM8995_AIF2_EQ_GAINS_1 0x580 +#define WM8995_AIF2_EQ_GAINS_2 0x581 +#define WM8995_AIF2_EQ_BAND_1_A 0x582 +#define WM8995_AIF2_EQ_BAND_1_B 0x583 +#define WM8995_AIF2_EQ_BAND_1_PG 0x584 +#define WM8995_AIF2_EQ_BAND_2_A 0x585 +#define WM8995_AIF2_EQ_BAND_2_B 0x586 +#define WM8995_AIF2_EQ_BAND_2_C 0x587 +#define WM8995_AIF2_EQ_BAND_2_PG 0x588 +#define WM8995_AIF2_EQ_BAND_3_A 0x589 +#define WM8995_AIF2_EQ_BAND_3_B 0x58A +#define WM8995_AIF2_EQ_BAND_3_C 0x58B +#define WM8995_AIF2_EQ_BAND_3_PG 0x58C +#define WM8995_AIF2_EQ_BAND_4_A 0x58D +#define WM8995_AIF2_EQ_BAND_4_B 0x58E +#define WM8995_AIF2_EQ_BAND_4_C 0x58F +#define WM8995_AIF2_EQ_BAND_4_PG 0x590 +#define WM8995_AIF2_EQ_BAND_5_A 0x591 +#define WM8995_AIF2_EQ_BAND_5_B 0x592 +#define WM8995_AIF2_EQ_BAND_5_PG 0x593 +#define WM8995_DAC1_MIXER_VOLUMES 0x600 +#define WM8995_DAC1_LEFT_MIXER_ROUTING 0x601 +#define WM8995_DAC1_RIGHT_MIXER_ROUTING 0x602 +#define WM8995_DAC2_MIXER_VOLUMES 0x603 +#define WM8995_DAC2_LEFT_MIXER_ROUTING 0x604 +#define WM8995_DAC2_RIGHT_MIXER_ROUTING 0x605 +#define WM8995_AIF1_ADC1_LEFT_MIXER_ROUTING 0x606 +#define WM8995_AIF1_ADC1_RIGHT_MIXER_ROUTING 0x607 +#define WM8995_AIF1_ADC2_LEFT_MIXER_ROUTING 0x608 +#define WM8995_AIF1_ADC2_RIGHT_MIXER_ROUTING 0x609 +#define WM8995_DAC_SOFTMUTE 0x610 +#define WM8995_OVERSAMPLING 0x620 +#define WM8995_SIDETONE 0x621 +#define WM8995_GPIO_1 0x700 +#define WM8995_GPIO_2 0x701 +#define WM8995_GPIO_3 0x702 +#define WM8995_GPIO_4 0x703 +#define WM8995_GPIO_5 0x704 +#define WM8995_GPIO_6 0x705 +#define WM8995_GPIO_7 0x706 +#define WM8995_GPIO_8 0x707 +#define WM8995_GPIO_9 0x708 +#define WM8995_GPIO_10 0x709 +#define WM8995_GPIO_11 0x70A +#define WM8995_GPIO_12 0x70B +#define WM8995_GPIO_13 0x70C +#define WM8995_GPIO_14 0x70D +#define WM8995_PULL_CONTROL_1 0x720 +#define WM8995_PULL_CONTROL_2 0x721 +#define WM8995_INTERRUPT_STATUS_1 0x730 +#define WM8995_INTERRUPT_STATUS_2 0x731 +#define WM8995_INTERRUPT_RAW_STATUS_2 0x732 +#define WM8995_INTERRUPT_STATUS_1_MASK 0x738 +#define WM8995_INTERRUPT_STATUS_2_MASK 0x739 +#define WM8995_INTERRUPT_CONTROL 0x740 +#define WM8995_LEFT_PDM_SPEAKER_1 0x800 +#define WM8995_RIGHT_PDM_SPEAKER_1 0x801 +#define WM8995_PDM_SPEAKER_1_MUTE_SEQUENCE 0x802 +#define WM8995_LEFT_PDM_SPEAKER_2 0x808 +#define WM8995_RIGHT_PDM_SPEAKER_2 0x809 +#define WM8995_PDM_SPEAKER_2_MUTE_SEQUENCE 0x80A +#define WM8995_WRITE_SEQUENCER_0 0x3000 +#define WM8995_WRITE_SEQUENCER_1 0x3001 +#define WM8995_WRITE_SEQUENCER_2 0x3002 +#define WM8995_WRITE_SEQUENCER_3 0x3003 +#define WM8995_WRITE_SEQUENCER_4 0x3004 +#define WM8995_WRITE_SEQUENCER_5 0x3005 +#define WM8995_WRITE_SEQUENCER_6 0x3006 +#define WM8995_WRITE_SEQUENCER_7 0x3007 +#define WM8995_WRITE_SEQUENCER_8 0x3008 +#define WM8995_WRITE_SEQUENCER_9 0x3009 +#define WM8995_WRITE_SEQUENCER_10 0x300A +#define WM8995_WRITE_SEQUENCER_11 0x300B +#define WM8995_WRITE_SEQUENCER_12 0x300C +#define WM8995_WRITE_SEQUENCER_13 0x300D +#define WM8995_WRITE_SEQUENCER_14 0x300E +#define WM8995_WRITE_SEQUENCER_15 0x300F +#define WM8995_WRITE_SEQUENCER_16 0x3010 +#define WM8995_WRITE_SEQUENCER_17 0x3011 +#define WM8995_WRITE_SEQUENCER_18 0x3012 +#define WM8995_WRITE_SEQUENCER_19 0x3013 +#define WM8995_WRITE_SEQUENCER_20 0x3014 +#define WM8995_WRITE_SEQUENCER_21 0x3015 +#define WM8995_WRITE_SEQUENCER_22 0x3016 +#define WM8995_WRITE_SEQUENCER_23 0x3017 +#define WM8995_WRITE_SEQUENCER_24 0x3018 +#define WM8995_WRITE_SEQUENCER_25 0x3019 +#define WM8995_WRITE_SEQUENCER_26 0x301A +#define WM8995_WRITE_SEQUENCER_27 0x301B +#define WM8995_WRITE_SEQUENCER_28 0x301C +#define WM8995_WRITE_SEQUENCER_29 0x301D +#define WM8995_WRITE_SEQUENCER_30 0x301E +#define WM8995_WRITE_SEQUENCER_31 0x301F +#define WM8995_WRITE_SEQUENCER_32 0x3020 +#define WM8995_WRITE_SEQUENCER_33 0x3021 +#define WM8995_WRITE_SEQUENCER_34 0x3022 +#define WM8995_WRITE_SEQUENCER_35 0x3023 +#define WM8995_WRITE_SEQUENCER_36 0x3024 +#define WM8995_WRITE_SEQUENCER_37 0x3025 +#define WM8995_WRITE_SEQUENCER_38 0x3026 +#define WM8995_WRITE_SEQUENCER_39 0x3027 +#define WM8995_WRITE_SEQUENCER_40 0x3028 +#define WM8995_WRITE_SEQUENCER_41 0x3029 +#define WM8995_WRITE_SEQUENCER_42 0x302A +#define WM8995_WRITE_SEQUENCER_43 0x302B +#define WM8995_WRITE_SEQUENCER_44 0x302C +#define WM8995_WRITE_SEQUENCER_45 0x302D +#define WM8995_WRITE_SEQUENCER_46 0x302E +#define WM8995_WRITE_SEQUENCER_47 0x302F +#define WM8995_WRITE_SEQUENCER_48 0x3030 +#define WM8995_WRITE_SEQUENCER_49 0x3031 +#define WM8995_WRITE_SEQUENCER_50 0x3032 +#define WM8995_WRITE_SEQUENCER_51 0x3033 +#define WM8995_WRITE_SEQUENCER_52 0x3034 +#define WM8995_WRITE_SEQUENCER_53 0x3035 +#define WM8995_WRITE_SEQUENCER_54 0x3036 +#define WM8995_WRITE_SEQUENCER_55 0x3037 +#define WM8995_WRITE_SEQUENCER_56 0x3038 +#define WM8995_WRITE_SEQUENCER_57 0x3039 +#define WM8995_WRITE_SEQUENCER_58 0x303A +#define WM8995_WRITE_SEQUENCER_59 0x303B +#define WM8995_WRITE_SEQUENCER_60 0x303C +#define WM8995_WRITE_SEQUENCER_61 0x303D +#define WM8995_WRITE_SEQUENCER_62 0x303E +#define WM8995_WRITE_SEQUENCER_63 0x303F +#define WM8995_WRITE_SEQUENCER_64 0x3040 +#define WM8995_WRITE_SEQUENCER_65 0x3041 +#define WM8995_WRITE_SEQUENCER_66 0x3042 +#define WM8995_WRITE_SEQUENCER_67 0x3043 +#define WM8995_WRITE_SEQUENCER_68 0x3044 +#define WM8995_WRITE_SEQUENCER_69 0x3045 +#define WM8995_WRITE_SEQUENCER_70 0x3046 +#define WM8995_WRITE_SEQUENCER_71 0x3047 +#define WM8995_WRITE_SEQUENCER_72 0x3048 +#define WM8995_WRITE_SEQUENCER_73 0x3049 +#define WM8995_WRITE_SEQUENCER_74 0x304A +#define WM8995_WRITE_SEQUENCER_75 0x304B +#define WM8995_WRITE_SEQUENCER_76 0x304C +#define WM8995_WRITE_SEQUENCER_77 0x304D +#define WM8995_WRITE_SEQUENCER_78 0x304E +#define WM8995_WRITE_SEQUENCER_79 0x304F +#define WM8995_WRITE_SEQUENCER_80 0x3050 +#define WM8995_WRITE_SEQUENCER_81 0x3051 +#define WM8995_WRITE_SEQUENCER_82 0x3052 +#define WM8995_WRITE_SEQUENCER_83 0x3053 +#define WM8995_WRITE_SEQUENCER_84 0x3054 +#define WM8995_WRITE_SEQUENCER_85 0x3055 +#define WM8995_WRITE_SEQUENCER_86 0x3056 +#define WM8995_WRITE_SEQUENCER_87 0x3057 +#define WM8995_WRITE_SEQUENCER_88 0x3058 +#define WM8995_WRITE_SEQUENCER_89 0x3059 +#define WM8995_WRITE_SEQUENCER_90 0x305A +#define WM8995_WRITE_SEQUENCER_91 0x305B +#define WM8995_WRITE_SEQUENCER_92 0x305C +#define WM8995_WRITE_SEQUENCER_93 0x305D +#define WM8995_WRITE_SEQUENCER_94 0x305E +#define WM8995_WRITE_SEQUENCER_95 0x305F +#define WM8995_WRITE_SEQUENCER_96 0x3060 +#define WM8995_WRITE_SEQUENCER_97 0x3061 +#define WM8995_WRITE_SEQUENCER_98 0x3062 +#define WM8995_WRITE_SEQUENCER_99 0x3063 +#define WM8995_WRITE_SEQUENCER_100 0x3064 +#define WM8995_WRITE_SEQUENCER_101 0x3065 +#define WM8995_WRITE_SEQUENCER_102 0x3066 +#define WM8995_WRITE_SEQUENCER_103 0x3067 +#define WM8995_WRITE_SEQUENCER_104 0x3068 +#define WM8995_WRITE_SEQUENCER_105 0x3069 +#define WM8995_WRITE_SEQUENCER_106 0x306A +#define WM8995_WRITE_SEQUENCER_107 0x306B +#define WM8995_WRITE_SEQUENCER_108 0x306C +#define WM8995_WRITE_SEQUENCER_109 0x306D +#define WM8995_WRITE_SEQUENCER_110 0x306E +#define WM8995_WRITE_SEQUENCER_111 0x306F +#define WM8995_WRITE_SEQUENCER_112 0x3070 +#define WM8995_WRITE_SEQUENCER_113 0x3071 +#define WM8995_WRITE_SEQUENCER_114 0x3072 +#define WM8995_WRITE_SEQUENCER_115 0x3073 +#define WM8995_WRITE_SEQUENCER_116 0x3074 +#define WM8995_WRITE_SEQUENCER_117 0x3075 +#define WM8995_WRITE_SEQUENCER_118 0x3076 +#define WM8995_WRITE_SEQUENCER_119 0x3077 +#define WM8995_WRITE_SEQUENCER_120 0x3078 +#define WM8995_WRITE_SEQUENCER_121 0x3079 +#define WM8995_WRITE_SEQUENCER_122 0x307A +#define WM8995_WRITE_SEQUENCER_123 0x307B +#define WM8995_WRITE_SEQUENCER_124 0x307C +#define WM8995_WRITE_SEQUENCER_125 0x307D +#define WM8995_WRITE_SEQUENCER_126 0x307E +#define WM8995_WRITE_SEQUENCER_127 0x307F +#define WM8995_WRITE_SEQUENCER_128 0x3080 +#define WM8995_WRITE_SEQUENCER_129 0x3081 +#define WM8995_WRITE_SEQUENCER_130 0x3082 +#define WM8995_WRITE_SEQUENCER_131 0x3083 +#define WM8995_WRITE_SEQUENCER_132 0x3084 +#define WM8995_WRITE_SEQUENCER_133 0x3085 +#define WM8995_WRITE_SEQUENCER_134 0x3086 +#define WM8995_WRITE_SEQUENCER_135 0x3087 +#define WM8995_WRITE_SEQUENCER_136 0x3088 +#define WM8995_WRITE_SEQUENCER_137 0x3089 +#define WM8995_WRITE_SEQUENCER_138 0x308A +#define WM8995_WRITE_SEQUENCER_139 0x308B +#define WM8995_WRITE_SEQUENCER_140 0x308C +#define WM8995_WRITE_SEQUENCER_141 0x308D +#define WM8995_WRITE_SEQUENCER_142 0x308E +#define WM8995_WRITE_SEQUENCER_143 0x308F +#define WM8995_WRITE_SEQUENCER_144 0x3090 +#define WM8995_WRITE_SEQUENCER_145 0x3091 +#define WM8995_WRITE_SEQUENCER_146 0x3092 +#define WM8995_WRITE_SEQUENCER_147 0x3093 +#define WM8995_WRITE_SEQUENCER_148 0x3094 +#define WM8995_WRITE_SEQUENCER_149 0x3095 +#define WM8995_WRITE_SEQUENCER_150 0x3096 +#define WM8995_WRITE_SEQUENCER_151 0x3097 +#define WM8995_WRITE_SEQUENCER_152 0x3098 +#define WM8995_WRITE_SEQUENCER_153 0x3099 +#define WM8995_WRITE_SEQUENCER_154 0x309A +#define WM8995_WRITE_SEQUENCER_155 0x309B +#define WM8995_WRITE_SEQUENCER_156 0x309C +#define WM8995_WRITE_SEQUENCER_157 0x309D +#define WM8995_WRITE_SEQUENCER_158 0x309E +#define WM8995_WRITE_SEQUENCER_159 0x309F +#define WM8995_WRITE_SEQUENCER_160 0x30A0 +#define WM8995_WRITE_SEQUENCER_161 0x30A1 +#define WM8995_WRITE_SEQUENCER_162 0x30A2 +#define WM8995_WRITE_SEQUENCER_163 0x30A3 +#define WM8995_WRITE_SEQUENCER_164 0x30A4 +#define WM8995_WRITE_SEQUENCER_165 0x30A5 +#define WM8995_WRITE_SEQUENCER_166 0x30A6 +#define WM8995_WRITE_SEQUENCER_167 0x30A7 +#define WM8995_WRITE_SEQUENCER_168 0x30A8 +#define WM8995_WRITE_SEQUENCER_169 0x30A9 +#define WM8995_WRITE_SEQUENCER_170 0x30AA +#define WM8995_WRITE_SEQUENCER_171 0x30AB +#define WM8995_WRITE_SEQUENCER_172 0x30AC +#define WM8995_WRITE_SEQUENCER_173 0x30AD +#define WM8995_WRITE_SEQUENCER_174 0x30AE +#define WM8995_WRITE_SEQUENCER_175 0x30AF +#define WM8995_WRITE_SEQUENCER_176 0x30B0 +#define WM8995_WRITE_SEQUENCER_177 0x30B1 +#define WM8995_WRITE_SEQUENCER_178 0x30B2 +#define WM8995_WRITE_SEQUENCER_179 0x30B3 +#define WM8995_WRITE_SEQUENCER_180 0x30B4 +#define WM8995_WRITE_SEQUENCER_181 0x30B5 +#define WM8995_WRITE_SEQUENCER_182 0x30B6 +#define WM8995_WRITE_SEQUENCER_183 0x30B7 +#define WM8995_WRITE_SEQUENCER_184 0x30B8 +#define WM8995_WRITE_SEQUENCER_185 0x30B9 +#define WM8995_WRITE_SEQUENCER_186 0x30BA +#define WM8995_WRITE_SEQUENCER_187 0x30BB +#define WM8995_WRITE_SEQUENCER_188 0x30BC +#define WM8995_WRITE_SEQUENCER_189 0x30BD +#define WM8995_WRITE_SEQUENCER_190 0x30BE +#define WM8995_WRITE_SEQUENCER_191 0x30BF +#define WM8995_WRITE_SEQUENCER_192 0x30C0 +#define WM8995_WRITE_SEQUENCER_193 0x30C1 +#define WM8995_WRITE_SEQUENCER_194 0x30C2 +#define WM8995_WRITE_SEQUENCER_195 0x30C3 +#define WM8995_WRITE_SEQUENCER_196 0x30C4 +#define WM8995_WRITE_SEQUENCER_197 0x30C5 +#define WM8995_WRITE_SEQUENCER_198 0x30C6 +#define WM8995_WRITE_SEQUENCER_199 0x30C7 +#define WM8995_WRITE_SEQUENCER_200 0x30C8 +#define WM8995_WRITE_SEQUENCER_201 0x30C9 +#define WM8995_WRITE_SEQUENCER_202 0x30CA +#define WM8995_WRITE_SEQUENCER_203 0x30CB +#define WM8995_WRITE_SEQUENCER_204 0x30CC +#define WM8995_WRITE_SEQUENCER_205 0x30CD +#define WM8995_WRITE_SEQUENCER_206 0x30CE +#define WM8995_WRITE_SEQUENCER_207 0x30CF +#define WM8995_WRITE_SEQUENCER_208 0x30D0 +#define WM8995_WRITE_SEQUENCER_209 0x30D1 +#define WM8995_WRITE_SEQUENCER_210 0x30D2 +#define WM8995_WRITE_SEQUENCER_211 0x30D3 +#define WM8995_WRITE_SEQUENCER_212 0x30D4 +#define WM8995_WRITE_SEQUENCER_213 0x30D5 +#define WM8995_WRITE_SEQUENCER_214 0x30D6 +#define WM8995_WRITE_SEQUENCER_215 0x30D7 +#define WM8995_WRITE_SEQUENCER_216 0x30D8 +#define WM8995_WRITE_SEQUENCER_217 0x30D9 +#define WM8995_WRITE_SEQUENCER_218 0x30DA +#define WM8995_WRITE_SEQUENCER_219 0x30DB +#define WM8995_WRITE_SEQUENCER_220 0x30DC +#define WM8995_WRITE_SEQUENCER_221 0x30DD +#define WM8995_WRITE_SEQUENCER_222 0x30DE +#define WM8995_WRITE_SEQUENCER_223 0x30DF +#define WM8995_WRITE_SEQUENCER_224 0x30E0 +#define WM8995_WRITE_SEQUENCER_225 0x30E1 +#define WM8995_WRITE_SEQUENCER_226 0x30E2 +#define WM8995_WRITE_SEQUENCER_227 0x30E3 +#define WM8995_WRITE_SEQUENCER_228 0x30E4 +#define WM8995_WRITE_SEQUENCER_229 0x30E5 +#define WM8995_WRITE_SEQUENCER_230 0x30E6 +#define WM8995_WRITE_SEQUENCER_231 0x30E7 +#define WM8995_WRITE_SEQUENCER_232 0x30E8 +#define WM8995_WRITE_SEQUENCER_233 0x30E9 +#define WM8995_WRITE_SEQUENCER_234 0x30EA +#define WM8995_WRITE_SEQUENCER_235 0x30EB +#define WM8995_WRITE_SEQUENCER_236 0x30EC +#define WM8995_WRITE_SEQUENCER_237 0x30ED +#define WM8995_WRITE_SEQUENCER_238 0x30EE +#define WM8995_WRITE_SEQUENCER_239 0x30EF +#define WM8995_WRITE_SEQUENCER_240 0x30F0 +#define WM8995_WRITE_SEQUENCER_241 0x30F1 +#define WM8995_WRITE_SEQUENCER_242 0x30F2 +#define WM8995_WRITE_SEQUENCER_243 0x30F3 +#define WM8995_WRITE_SEQUENCER_244 0x30F4 +#define WM8995_WRITE_SEQUENCER_245 0x30F5 +#define WM8995_WRITE_SEQUENCER_246 0x30F6 +#define WM8995_WRITE_SEQUENCER_247 0x30F7 +#define WM8995_WRITE_SEQUENCER_248 0x30F8 +#define WM8995_WRITE_SEQUENCER_249 0x30F9 +#define WM8995_WRITE_SEQUENCER_250 0x30FA +#define WM8995_WRITE_SEQUENCER_251 0x30FB +#define WM8995_WRITE_SEQUENCER_252 0x30FC +#define WM8995_WRITE_SEQUENCER_253 0x30FD +#define WM8995_WRITE_SEQUENCER_254 0x30FE +#define WM8995_WRITE_SEQUENCER_255 0x30FF +#define WM8995_WRITE_SEQUENCER_256 0x3100 +#define WM8995_WRITE_SEQUENCER_257 0x3101 +#define WM8995_WRITE_SEQUENCER_258 0x3102 +#define WM8995_WRITE_SEQUENCER_259 0x3103 +#define WM8995_WRITE_SEQUENCER_260 0x3104 +#define WM8995_WRITE_SEQUENCER_261 0x3105 +#define WM8995_WRITE_SEQUENCER_262 0x3106 +#define WM8995_WRITE_SEQUENCER_263 0x3107 +#define WM8995_WRITE_SEQUENCER_264 0x3108 +#define WM8995_WRITE_SEQUENCER_265 0x3109 +#define WM8995_WRITE_SEQUENCER_266 0x310A +#define WM8995_WRITE_SEQUENCER_267 0x310B +#define WM8995_WRITE_SEQUENCER_268 0x310C +#define WM8995_WRITE_SEQUENCER_269 0x310D +#define WM8995_WRITE_SEQUENCER_270 0x310E +#define WM8995_WRITE_SEQUENCER_271 0x310F +#define WM8995_WRITE_SEQUENCER_272 0x3110 +#define WM8995_WRITE_SEQUENCER_273 0x3111 +#define WM8995_WRITE_SEQUENCER_274 0x3112 +#define WM8995_WRITE_SEQUENCER_275 0x3113 +#define WM8995_WRITE_SEQUENCER_276 0x3114 +#define WM8995_WRITE_SEQUENCER_277 0x3115 +#define WM8995_WRITE_SEQUENCER_278 0x3116 +#define WM8995_WRITE_SEQUENCER_279 0x3117 +#define WM8995_WRITE_SEQUENCER_280 0x3118 +#define WM8995_WRITE_SEQUENCER_281 0x3119 +#define WM8995_WRITE_SEQUENCER_282 0x311A +#define WM8995_WRITE_SEQUENCER_283 0x311B +#define WM8995_WRITE_SEQUENCER_284 0x311C +#define WM8995_WRITE_SEQUENCER_285 0x311D +#define WM8995_WRITE_SEQUENCER_286 0x311E +#define WM8995_WRITE_SEQUENCER_287 0x311F +#define WM8995_WRITE_SEQUENCER_288 0x3120 +#define WM8995_WRITE_SEQUENCER_289 0x3121 +#define WM8995_WRITE_SEQUENCER_290 0x3122 +#define WM8995_WRITE_SEQUENCER_291 0x3123 +#define WM8995_WRITE_SEQUENCER_292 0x3124 +#define WM8995_WRITE_SEQUENCER_293 0x3125 +#define WM8995_WRITE_SEQUENCER_294 0x3126 +#define WM8995_WRITE_SEQUENCER_295 0x3127 +#define WM8995_WRITE_SEQUENCER_296 0x3128 +#define WM8995_WRITE_SEQUENCER_297 0x3129 +#define WM8995_WRITE_SEQUENCER_298 0x312A +#define WM8995_WRITE_SEQUENCER_299 0x312B +#define WM8995_WRITE_SEQUENCER_300 0x312C +#define WM8995_WRITE_SEQUENCER_301 0x312D +#define WM8995_WRITE_SEQUENCER_302 0x312E +#define WM8995_WRITE_SEQUENCER_303 0x312F +#define WM8995_WRITE_SEQUENCER_304 0x3130 +#define WM8995_WRITE_SEQUENCER_305 0x3131 +#define WM8995_WRITE_SEQUENCER_306 0x3132 +#define WM8995_WRITE_SEQUENCER_307 0x3133 +#define WM8995_WRITE_SEQUENCER_308 0x3134 +#define WM8995_WRITE_SEQUENCER_309 0x3135 +#define WM8995_WRITE_SEQUENCER_310 0x3136 +#define WM8995_WRITE_SEQUENCER_311 0x3137 +#define WM8995_WRITE_SEQUENCER_312 0x3138 +#define WM8995_WRITE_SEQUENCER_313 0x3139 +#define WM8995_WRITE_SEQUENCER_314 0x313A +#define WM8995_WRITE_SEQUENCER_315 0x313B +#define WM8995_WRITE_SEQUENCER_316 0x313C +#define WM8995_WRITE_SEQUENCER_317 0x313D +#define WM8995_WRITE_SEQUENCER_318 0x313E +#define WM8995_WRITE_SEQUENCER_319 0x313F +#define WM8995_WRITE_SEQUENCER_320 0x3140 +#define WM8995_WRITE_SEQUENCER_321 0x3141 +#define WM8995_WRITE_SEQUENCER_322 0x3142 +#define WM8995_WRITE_SEQUENCER_323 0x3143 +#define WM8995_WRITE_SEQUENCER_324 0x3144 +#define WM8995_WRITE_SEQUENCER_325 0x3145 +#define WM8995_WRITE_SEQUENCER_326 0x3146 +#define WM8995_WRITE_SEQUENCER_327 0x3147 +#define WM8995_WRITE_SEQUENCER_328 0x3148 +#define WM8995_WRITE_SEQUENCER_329 0x3149 +#define WM8995_WRITE_SEQUENCER_330 0x314A +#define WM8995_WRITE_SEQUENCER_331 0x314B +#define WM8995_WRITE_SEQUENCER_332 0x314C +#define WM8995_WRITE_SEQUENCER_333 0x314D +#define WM8995_WRITE_SEQUENCER_334 0x314E +#define WM8995_WRITE_SEQUENCER_335 0x314F +#define WM8995_WRITE_SEQUENCER_336 0x3150 +#define WM8995_WRITE_SEQUENCER_337 0x3151 +#define WM8995_WRITE_SEQUENCER_338 0x3152 +#define WM8995_WRITE_SEQUENCER_339 0x3153 +#define WM8995_WRITE_SEQUENCER_340 0x3154 +#define WM8995_WRITE_SEQUENCER_341 0x3155 +#define WM8995_WRITE_SEQUENCER_342 0x3156 +#define WM8995_WRITE_SEQUENCER_343 0x3157 +#define WM8995_WRITE_SEQUENCER_344 0x3158 +#define WM8995_WRITE_SEQUENCER_345 0x3159 +#define WM8995_WRITE_SEQUENCER_346 0x315A +#define WM8995_WRITE_SEQUENCER_347 0x315B +#define WM8995_WRITE_SEQUENCER_348 0x315C +#define WM8995_WRITE_SEQUENCER_349 0x315D +#define WM8995_WRITE_SEQUENCER_350 0x315E +#define WM8995_WRITE_SEQUENCER_351 0x315F +#define WM8995_WRITE_SEQUENCER_352 0x3160 +#define WM8995_WRITE_SEQUENCER_353 0x3161 +#define WM8995_WRITE_SEQUENCER_354 0x3162 +#define WM8995_WRITE_SEQUENCER_355 0x3163 +#define WM8995_WRITE_SEQUENCER_356 0x3164 +#define WM8995_WRITE_SEQUENCER_357 0x3165 +#define WM8995_WRITE_SEQUENCER_358 0x3166 +#define WM8995_WRITE_SEQUENCER_359 0x3167 +#define WM8995_WRITE_SEQUENCER_360 0x3168 +#define WM8995_WRITE_SEQUENCER_361 0x3169 +#define WM8995_WRITE_SEQUENCER_362 0x316A +#define WM8995_WRITE_SEQUENCER_363 0x316B +#define WM8995_WRITE_SEQUENCER_364 0x316C +#define WM8995_WRITE_SEQUENCER_365 0x316D +#define WM8995_WRITE_SEQUENCER_366 0x316E +#define WM8995_WRITE_SEQUENCER_367 0x316F +#define WM8995_WRITE_SEQUENCER_368 0x3170 +#define WM8995_WRITE_SEQUENCER_369 0x3171 +#define WM8995_WRITE_SEQUENCER_370 0x3172 +#define WM8995_WRITE_SEQUENCER_371 0x3173 +#define WM8995_WRITE_SEQUENCER_372 0x3174 +#define WM8995_WRITE_SEQUENCER_373 0x3175 +#define WM8995_WRITE_SEQUENCER_374 0x3176 +#define WM8995_WRITE_SEQUENCER_375 0x3177 +#define WM8995_WRITE_SEQUENCER_376 0x3178 +#define WM8995_WRITE_SEQUENCER_377 0x3179 +#define WM8995_WRITE_SEQUENCER_378 0x317A +#define WM8995_WRITE_SEQUENCER_379 0x317B +#define WM8995_WRITE_SEQUENCER_380 0x317C +#define WM8995_WRITE_SEQUENCER_381 0x317D +#define WM8995_WRITE_SEQUENCER_382 0x317E +#define WM8995_WRITE_SEQUENCER_383 0x317F +#define WM8995_WRITE_SEQUENCER_384 0x3180 +#define WM8995_WRITE_SEQUENCER_385 0x3181 +#define WM8995_WRITE_SEQUENCER_386 0x3182 +#define WM8995_WRITE_SEQUENCER_387 0x3183 +#define WM8995_WRITE_SEQUENCER_388 0x3184 +#define WM8995_WRITE_SEQUENCER_389 0x3185 +#define WM8995_WRITE_SEQUENCER_390 0x3186 +#define WM8995_WRITE_SEQUENCER_391 0x3187 +#define WM8995_WRITE_SEQUENCER_392 0x3188 +#define WM8995_WRITE_SEQUENCER_393 0x3189 +#define WM8995_WRITE_SEQUENCER_394 0x318A +#define WM8995_WRITE_SEQUENCER_395 0x318B +#define WM8995_WRITE_SEQUENCER_396 0x318C +#define WM8995_WRITE_SEQUENCER_397 0x318D +#define WM8995_WRITE_SEQUENCER_398 0x318E +#define WM8995_WRITE_SEQUENCER_399 0x318F +#define WM8995_WRITE_SEQUENCER_400 0x3190 +#define WM8995_WRITE_SEQUENCER_401 0x3191 +#define WM8995_WRITE_SEQUENCER_402 0x3192 +#define WM8995_WRITE_SEQUENCER_403 0x3193 +#define WM8995_WRITE_SEQUENCER_404 0x3194 +#define WM8995_WRITE_SEQUENCER_405 0x3195 +#define WM8995_WRITE_SEQUENCER_406 0x3196 +#define WM8995_WRITE_SEQUENCER_407 0x3197 +#define WM8995_WRITE_SEQUENCER_408 0x3198 +#define WM8995_WRITE_SEQUENCER_409 0x3199 +#define WM8995_WRITE_SEQUENCER_410 0x319A +#define WM8995_WRITE_SEQUENCER_411 0x319B +#define WM8995_WRITE_SEQUENCER_412 0x319C +#define WM8995_WRITE_SEQUENCER_413 0x319D +#define WM8995_WRITE_SEQUENCER_414 0x319E +#define WM8995_WRITE_SEQUENCER_415 0x319F +#define WM8995_WRITE_SEQUENCER_416 0x31A0 +#define WM8995_WRITE_SEQUENCER_417 0x31A1 +#define WM8995_WRITE_SEQUENCER_418 0x31A2 +#define WM8995_WRITE_SEQUENCER_419 0x31A3 +#define WM8995_WRITE_SEQUENCER_420 0x31A4 +#define WM8995_WRITE_SEQUENCER_421 0x31A5 +#define WM8995_WRITE_SEQUENCER_422 0x31A6 +#define WM8995_WRITE_SEQUENCER_423 0x31A7 +#define WM8995_WRITE_SEQUENCER_424 0x31A8 +#define WM8995_WRITE_SEQUENCER_425 0x31A9 +#define WM8995_WRITE_SEQUENCER_426 0x31AA +#define WM8995_WRITE_SEQUENCER_427 0x31AB +#define WM8995_WRITE_SEQUENCER_428 0x31AC +#define WM8995_WRITE_SEQUENCER_429 0x31AD +#define WM8995_WRITE_SEQUENCER_430 0x31AE +#define WM8995_WRITE_SEQUENCER_431 0x31AF +#define WM8995_WRITE_SEQUENCER_432 0x31B0 +#define WM8995_WRITE_SEQUENCER_433 0x31B1 +#define WM8995_WRITE_SEQUENCER_434 0x31B2 +#define WM8995_WRITE_SEQUENCER_435 0x31B3 +#define WM8995_WRITE_SEQUENCER_436 0x31B4 +#define WM8995_WRITE_SEQUENCER_437 0x31B5 +#define WM8995_WRITE_SEQUENCER_438 0x31B6 +#define WM8995_WRITE_SEQUENCER_439 0x31B7 +#define WM8995_WRITE_SEQUENCER_440 0x31B8 +#define WM8995_WRITE_SEQUENCER_441 0x31B9 +#define WM8995_WRITE_SEQUENCER_442 0x31BA +#define WM8995_WRITE_SEQUENCER_443 0x31BB +#define WM8995_WRITE_SEQUENCER_444 0x31BC +#define WM8995_WRITE_SEQUENCER_445 0x31BD +#define WM8995_WRITE_SEQUENCER_446 0x31BE +#define WM8995_WRITE_SEQUENCER_447 0x31BF +#define WM8995_WRITE_SEQUENCER_448 0x31C0 +#define WM8995_WRITE_SEQUENCER_449 0x31C1 +#define WM8995_WRITE_SEQUENCER_450 0x31C2 +#define WM8995_WRITE_SEQUENCER_451 0x31C3 +#define WM8995_WRITE_SEQUENCER_452 0x31C4 +#define WM8995_WRITE_SEQUENCER_453 0x31C5 +#define WM8995_WRITE_SEQUENCER_454 0x31C6 +#define WM8995_WRITE_SEQUENCER_455 0x31C7 +#define WM8995_WRITE_SEQUENCER_456 0x31C8 +#define WM8995_WRITE_SEQUENCER_457 0x31C9 +#define WM8995_WRITE_SEQUENCER_458 0x31CA +#define WM8995_WRITE_SEQUENCER_459 0x31CB +#define WM8995_WRITE_SEQUENCER_460 0x31CC +#define WM8995_WRITE_SEQUENCER_461 0x31CD +#define WM8995_WRITE_SEQUENCER_462 0x31CE +#define WM8995_WRITE_SEQUENCER_463 0x31CF +#define WM8995_WRITE_SEQUENCER_464 0x31D0 +#define WM8995_WRITE_SEQUENCER_465 0x31D1 +#define WM8995_WRITE_SEQUENCER_466 0x31D2 +#define WM8995_WRITE_SEQUENCER_467 0x31D3 +#define WM8995_WRITE_SEQUENCER_468 0x31D4 +#define WM8995_WRITE_SEQUENCER_469 0x31D5 +#define WM8995_WRITE_SEQUENCER_470 0x31D6 +#define WM8995_WRITE_SEQUENCER_471 0x31D7 +#define WM8995_WRITE_SEQUENCER_472 0x31D8 +#define WM8995_WRITE_SEQUENCER_473 0x31D9 +#define WM8995_WRITE_SEQUENCER_474 0x31DA +#define WM8995_WRITE_SEQUENCER_475 0x31DB +#define WM8995_WRITE_SEQUENCER_476 0x31DC +#define WM8995_WRITE_SEQUENCER_477 0x31DD +#define WM8995_WRITE_SEQUENCER_478 0x31DE +#define WM8995_WRITE_SEQUENCER_479 0x31DF +#define WM8995_WRITE_SEQUENCER_480 0x31E0 +#define WM8995_WRITE_SEQUENCER_481 0x31E1 +#define WM8995_WRITE_SEQUENCER_482 0x31E2 +#define WM8995_WRITE_SEQUENCER_483 0x31E3 +#define WM8995_WRITE_SEQUENCER_484 0x31E4 +#define WM8995_WRITE_SEQUENCER_485 0x31E5 +#define WM8995_WRITE_SEQUENCER_486 0x31E6 +#define WM8995_WRITE_SEQUENCER_487 0x31E7 +#define WM8995_WRITE_SEQUENCER_488 0x31E8 +#define WM8995_WRITE_SEQUENCER_489 0x31E9 +#define WM8995_WRITE_SEQUENCER_490 0x31EA +#define WM8995_WRITE_SEQUENCER_491 0x31EB +#define WM8995_WRITE_SEQUENCER_492 0x31EC +#define WM8995_WRITE_SEQUENCER_493 0x31ED +#define WM8995_WRITE_SEQUENCER_494 0x31EE +#define WM8995_WRITE_SEQUENCER_495 0x31EF +#define WM8995_WRITE_SEQUENCER_496 0x31F0 +#define WM8995_WRITE_SEQUENCER_497 0x31F1 +#define WM8995_WRITE_SEQUENCER_498 0x31F2 +#define WM8995_WRITE_SEQUENCER_499 0x31F3 +#define WM8995_WRITE_SEQUENCER_500 0x31F4 +#define WM8995_WRITE_SEQUENCER_501 0x31F5 +#define WM8995_WRITE_SEQUENCER_502 0x31F6 +#define WM8995_WRITE_SEQUENCER_503 0x31F7 +#define WM8995_WRITE_SEQUENCER_504 0x31F8 +#define WM8995_WRITE_SEQUENCER_505 0x31F9 +#define WM8995_WRITE_SEQUENCER_506 0x31FA +#define WM8995_WRITE_SEQUENCER_507 0x31FB +#define WM8995_WRITE_SEQUENCER_508 0x31FC +#define WM8995_WRITE_SEQUENCER_509 0x31FD +#define WM8995_WRITE_SEQUENCER_510 0x31FE +#define WM8995_WRITE_SEQUENCER_511 0x31FF + +#define WM8995_REGISTER_COUNT 725 +#define WM8995_MAX_REGISTER 0x31FF + +#define WM8995_MAX_CACHED_REGISTER WM8995_MAX_REGISTER + +/* + * Field Definitions. + */ + +/* + * R0 (0x00) - Software Reset + */ +#define WM8995_SW_RESET_MASK 0xFFFF /* SW_RESET - [15:0] */ +#define WM8995_SW_RESET_SHIFT 0 /* SW_RESET - [15:0] */ +#define WM8995_SW_RESET_WIDTH 16 /* SW_RESET - [15:0] */ + +/* + * R1 (0x01) - Power Management (1) + */ +#define WM8995_MICB2_ENA 0x0200 /* MICB2_ENA */ +#define WM8995_MICB2_ENA_MASK 0x0200 /* MICB2_ENA */ +#define WM8995_MICB2_ENA_SHIFT 9 /* MICB2_ENA */ +#define WM8995_MICB2_ENA_WIDTH 1 /* MICB2_ENA */ +#define WM8995_MICB1_ENA 0x0100 /* MICB1_ENA */ +#define WM8995_MICB1_ENA_MASK 0x0100 /* MICB1_ENA */ +#define WM8995_MICB1_ENA_SHIFT 8 /* MICB1_ENA */ +#define WM8995_MICB1_ENA_WIDTH 1 /* MICB1_ENA */ +#define WM8995_HPOUT2L_ENA 0x0080 /* HPOUT2L_ENA */ +#define WM8995_HPOUT2L_ENA_MASK 0x0080 /* HPOUT2L_ENA */ +#define WM8995_HPOUT2L_ENA_SHIFT 7 /* HPOUT2L_ENA */ +#define WM8995_HPOUT2L_ENA_WIDTH 1 /* HPOUT2L_ENA */ +#define WM8995_HPOUT2R_ENA 0x0040 /* HPOUT2R_ENA */ +#define WM8995_HPOUT2R_ENA_MASK 0x0040 /* HPOUT2R_ENA */ +#define WM8995_HPOUT2R_ENA_SHIFT 6 /* HPOUT2R_ENA */ +#define WM8995_HPOUT2R_ENA_WIDTH 1 /* HPOUT2R_ENA */ +#define WM8995_HPOUT1L_ENA 0x0020 /* HPOUT1L_ENA */ +#define WM8995_HPOUT1L_ENA_MASK 0x0020 /* HPOUT1L_ENA */ +#define WM8995_HPOUT1L_ENA_SHIFT 5 /* HPOUT1L_ENA */ +#define WM8995_HPOUT1L_ENA_WIDTH 1 /* HPOUT1L_ENA */ +#define WM8995_HPOUT1R_ENA 0x0010 /* HPOUT1R_ENA */ +#define WM8995_HPOUT1R_ENA_MASK 0x0010 /* HPOUT1R_ENA */ +#define WM8995_HPOUT1R_ENA_SHIFT 4 /* HPOUT1R_ENA */ +#define WM8995_HPOUT1R_ENA_WIDTH 1 /* HPOUT1R_ENA */ +#define WM8995_BG_ENA 0x0001 /* BG_ENA */ +#define WM8995_BG_ENA_MASK 0x0001 /* BG_ENA */ +#define WM8995_BG_ENA_SHIFT 0 /* BG_ENA */ +#define WM8995_BG_ENA_WIDTH 1 /* BG_ENA */ + +/* + * R2 (0x02) - Power Management (2) + */ +#define WM8995_OPCLK_ENA 0x0800 /* OPCLK_ENA */ +#define WM8995_OPCLK_ENA_MASK 0x0800 /* OPCLK_ENA */ +#define WM8995_OPCLK_ENA_SHIFT 11 /* OPCLK_ENA */ +#define WM8995_OPCLK_ENA_WIDTH 1 /* OPCLK_ENA */ +#define WM8995_IN1L_ENA 0x0020 /* IN1L_ENA */ +#define WM8995_IN1L_ENA_MASK 0x0020 /* IN1L_ENA */ +#define WM8995_IN1L_ENA_SHIFT 5 /* IN1L_ENA */ +#define WM8995_IN1L_ENA_WIDTH 1 /* IN1L_ENA */ +#define WM8995_IN1R_ENA 0x0010 /* IN1R_ENA */ +#define WM8995_IN1R_ENA_MASK 0x0010 /* IN1R_ENA */ +#define WM8995_IN1R_ENA_SHIFT 4 /* IN1R_ENA */ +#define WM8995_IN1R_ENA_WIDTH 1 /* IN1R_ENA */ +#define WM8995_LDO2_ENA 0x0002 /* LDO2_ENA */ +#define WM8995_LDO2_ENA_MASK 0x0002 /* LDO2_ENA */ +#define WM8995_LDO2_ENA_SHIFT 1 /* LDO2_ENA */ +#define WM8995_LDO2_ENA_WIDTH 1 /* LDO2_ENA */ + +/* + * R3 (0x03) - Power Management (3) + */ +#define WM8995_AIF2ADCL_ENA 0x2000 /* AIF2ADCL_ENA */ +#define WM8995_AIF2ADCL_ENA_MASK 0x2000 /* AIF2ADCL_ENA */ +#define WM8995_AIF2ADCL_ENA_SHIFT 13 /* AIF2ADCL_ENA */ +#define WM8995_AIF2ADCL_ENA_WIDTH 1 /* AIF2ADCL_ENA */ +#define WM8995_AIF2ADCR_ENA 0x1000 /* AIF2ADCR_ENA */ +#define WM8995_AIF2ADCR_ENA_MASK 0x1000 /* AIF2ADCR_ENA */ +#define WM8995_AIF2ADCR_ENA_SHIFT 12 /* AIF2ADCR_ENA */ +#define WM8995_AIF2ADCR_ENA_WIDTH 1 /* AIF2ADCR_ENA */ +#define WM8995_AIF1ADC2L_ENA 0x0800 /* AIF1ADC2L_ENA */ +#define WM8995_AIF1ADC2L_ENA_MASK 0x0800 /* AIF1ADC2L_ENA */ +#define WM8995_AIF1ADC2L_ENA_SHIFT 11 /* AIF1ADC2L_ENA */ +#define WM8995_AIF1ADC2L_ENA_WIDTH 1 /* AIF1ADC2L_ENA */ +#define WM8995_AIF1ADC2R_ENA 0x0400 /* AIF1ADC2R_ENA */ +#define WM8995_AIF1ADC2R_ENA_MASK 0x0400 /* AIF1ADC2R_ENA */ +#define WM8995_AIF1ADC2R_ENA_SHIFT 10 /* AIF1ADC2R_ENA */ +#define WM8995_AIF1ADC2R_ENA_WIDTH 1 /* AIF1ADC2R_ENA */ +#define WM8995_AIF1ADC1L_ENA 0x0200 /* AIF1ADC1L_ENA */ +#define WM8995_AIF1ADC1L_ENA_MASK 0x0200 /* AIF1ADC1L_ENA */ +#define WM8995_AIF1ADC1L_ENA_SHIFT 9 /* AIF1ADC1L_ENA */ +#define WM8995_AIF1ADC1L_ENA_WIDTH 1 /* AIF1ADC1L_ENA */ +#define WM8995_AIF1ADC1R_ENA 0x0100 /* AIF1ADC1R_ENA */ +#define WM8995_AIF1ADC1R_ENA_MASK 0x0100 /* AIF1ADC1R_ENA */ +#define WM8995_AIF1ADC1R_ENA_SHIFT 8 /* AIF1ADC1R_ENA */ +#define WM8995_AIF1ADC1R_ENA_WIDTH 1 /* AIF1ADC1R_ENA */ +#define WM8995_DMIC3L_ENA 0x0080 /* DMIC3L_ENA */ +#define WM8995_DMIC3L_ENA_MASK 0x0080 /* DMIC3L_ENA */ +#define WM8995_DMIC3L_ENA_SHIFT 7 /* DMIC3L_ENA */ +#define WM8995_DMIC3L_ENA_WIDTH 1 /* DMIC3L_ENA */ +#define WM8995_DMIC3R_ENA 0x0040 /* DMIC3R_ENA */ +#define WM8995_DMIC3R_ENA_MASK 0x0040 /* DMIC3R_ENA */ +#define WM8995_DMIC3R_ENA_SHIFT 6 /* DMIC3R_ENA */ +#define WM8995_DMIC3R_ENA_WIDTH 1 /* DMIC3R_ENA */ +#define WM8995_DMIC2L_ENA 0x0020 /* DMIC2L_ENA */ +#define WM8995_DMIC2L_ENA_MASK 0x0020 /* DMIC2L_ENA */ +#define WM8995_DMIC2L_ENA_SHIFT 5 /* DMIC2L_ENA */ +#define WM8995_DMIC2L_ENA_WIDTH 1 /* DMIC2L_ENA */ +#define WM8995_DMIC2R_ENA 0x0010 /* DMIC2R_ENA */ +#define WM8995_DMIC2R_ENA_MASK 0x0010 /* DMIC2R_ENA */ +#define WM8995_DMIC2R_ENA_SHIFT 4 /* DMIC2R_ENA */ +#define WM8995_DMIC2R_ENA_WIDTH 1 /* DMIC2R_ENA */ +#define WM8995_DMIC1L_ENA 0x0008 /* DMIC1L_ENA */ +#define WM8995_DMIC1L_ENA_MASK 0x0008 /* DMIC1L_ENA */ +#define WM8995_DMIC1L_ENA_SHIFT 3 /* DMIC1L_ENA */ +#define WM8995_DMIC1L_ENA_WIDTH 1 /* DMIC1L_ENA */ +#define WM8995_DMIC1R_ENA 0x0004 /* DMIC1R_ENA */ +#define WM8995_DMIC1R_ENA_MASK 0x0004 /* DMIC1R_ENA */ +#define WM8995_DMIC1R_ENA_SHIFT 2 /* DMIC1R_ENA */ +#define WM8995_DMIC1R_ENA_WIDTH 1 /* DMIC1R_ENA */ +#define WM8995_ADCL_ENA 0x0002 /* ADCL_ENA */ +#define WM8995_ADCL_ENA_MASK 0x0002 /* ADCL_ENA */ +#define WM8995_ADCL_ENA_SHIFT 1 /* ADCL_ENA */ +#define WM8995_ADCL_ENA_WIDTH 1 /* ADCL_ENA */ +#define WM8995_ADCR_ENA 0x0001 /* ADCR_ENA */ +#define WM8995_ADCR_ENA_MASK 0x0001 /* ADCR_ENA */ +#define WM8995_ADCR_ENA_SHIFT 0 /* ADCR_ENA */ +#define WM8995_ADCR_ENA_WIDTH 1 /* ADCR_ENA */ + +/* + * R4 (0x04) - Power Management (4) + */ +#define WM8995_AIF2DACL_ENA 0x2000 /* AIF2DACL_ENA */ +#define WM8995_AIF2DACL_ENA_MASK 0x2000 /* AIF2DACL_ENA */ +#define WM8995_AIF2DACL_ENA_SHIFT 13 /* AIF2DACL_ENA */ +#define WM8995_AIF2DACL_ENA_WIDTH 1 /* AIF2DACL_ENA */ +#define WM8995_AIF2DACR_ENA 0x1000 /* AIF2DACR_ENA */ +#define WM8995_AIF2DACR_ENA_MASK 0x1000 /* AIF2DACR_ENA */ +#define WM8995_AIF2DACR_ENA_SHIFT 12 /* AIF2DACR_ENA */ +#define WM8995_AIF2DACR_ENA_WIDTH 1 /* AIF2DACR_ENA */ +#define WM8995_AIF1DAC2L_ENA 0x0800 /* AIF1DAC2L_ENA */ +#define WM8995_AIF1DAC2L_ENA_MASK 0x0800 /* AIF1DAC2L_ENA */ +#define WM8995_AIF1DAC2L_ENA_SHIFT 11 /* AIF1DAC2L_ENA */ +#define WM8995_AIF1DAC2L_ENA_WIDTH 1 /* AIF1DAC2L_ENA */ +#define WM8995_AIF1DAC2R_ENA 0x0400 /* AIF1DAC2R_ENA */ +#define WM8995_AIF1DAC2R_ENA_MASK 0x0400 /* AIF1DAC2R_ENA */ +#define WM8995_AIF1DAC2R_ENA_SHIFT 10 /* AIF1DAC2R_ENA */ +#define WM8995_AIF1DAC2R_ENA_WIDTH 1 /* AIF1DAC2R_ENA */ +#define WM8995_AIF1DAC1L_ENA 0x0200 /* AIF1DAC1L_ENA */ +#define WM8995_AIF1DAC1L_ENA_MASK 0x0200 /* AIF1DAC1L_ENA */ +#define WM8995_AIF1DAC1L_ENA_SHIFT 9 /* AIF1DAC1L_ENA */ +#define WM8995_AIF1DAC1L_ENA_WIDTH 1 /* AIF1DAC1L_ENA */ +#define WM8995_AIF1DAC1R_ENA 0x0100 /* AIF1DAC1R_ENA */ +#define WM8995_AIF1DAC1R_ENA_MASK 0x0100 /* AIF1DAC1R_ENA */ +#define WM8995_AIF1DAC1R_ENA_SHIFT 8 /* AIF1DAC1R_ENA */ +#define WM8995_AIF1DAC1R_ENA_WIDTH 1 /* AIF1DAC1R_ENA */ +#define WM8995_DAC2L_ENA 0x0008 /* DAC2L_ENA */ +#define WM8995_DAC2L_ENA_MASK 0x0008 /* DAC2L_ENA */ +#define WM8995_DAC2L_ENA_SHIFT 3 /* DAC2L_ENA */ +#define WM8995_DAC2L_ENA_WIDTH 1 /* DAC2L_ENA */ +#define WM8995_DAC2R_ENA 0x0004 /* DAC2R_ENA */ +#define WM8995_DAC2R_ENA_MASK 0x0004 /* DAC2R_ENA */ +#define WM8995_DAC2R_ENA_SHIFT 2 /* DAC2R_ENA */ +#define WM8995_DAC2R_ENA_WIDTH 1 /* DAC2R_ENA */ +#define WM8995_DAC1L_ENA 0x0002 /* DAC1L_ENA */ +#define WM8995_DAC1L_ENA_MASK 0x0002 /* DAC1L_ENA */ +#define WM8995_DAC1L_ENA_SHIFT 1 /* DAC1L_ENA */ +#define WM8995_DAC1L_ENA_WIDTH 1 /* DAC1L_ENA */ +#define WM8995_DAC1R_ENA 0x0001 /* DAC1R_ENA */ +#define WM8995_DAC1R_ENA_MASK 0x0001 /* DAC1R_ENA */ +#define WM8995_DAC1R_ENA_SHIFT 0 /* DAC1R_ENA */ +#define WM8995_DAC1R_ENA_WIDTH 1 /* DAC1R_ENA */ + +/* + * R5 (0x05) - Power Management (5) + */ +#define WM8995_DMIC_SRC2_MASK 0x0300 /* DMIC_SRC2 - [9:8] */ +#define WM8995_DMIC_SRC2_SHIFT 8 /* DMIC_SRC2 - [9:8] */ +#define WM8995_DMIC_SRC2_WIDTH 2 /* DMIC_SRC2 - [9:8] */ +#define WM8995_DMIC_SRC1_MASK 0x00C0 /* DMIC_SRC1 - [7:6] */ +#define WM8995_DMIC_SRC1_SHIFT 6 /* DMIC_SRC1 - [7:6] */ +#define WM8995_DMIC_SRC1_WIDTH 2 /* DMIC_SRC1 - [7:6] */ +#define WM8995_AIF3_TRI 0x0020 /* AIF3_TRI */ +#define WM8995_AIF3_TRI_MASK 0x0020 /* AIF3_TRI */ +#define WM8995_AIF3_TRI_SHIFT 5 /* AIF3_TRI */ +#define WM8995_AIF3_TRI_WIDTH 1 /* AIF3_TRI */ +#define WM8995_AIF3_ADCDAT_SRC_MASK 0x0018 /* AIF3_ADCDAT_SRC - [4:3] */ +#define WM8995_AIF3_ADCDAT_SRC_SHIFT 3 /* AIF3_ADCDAT_SRC - [4:3] */ +#define WM8995_AIF3_ADCDAT_SRC_WIDTH 2 /* AIF3_ADCDAT_SRC - [4:3] */ +#define WM8995_AIF2_ADCDAT_SRC 0x0004 /* AIF2_ADCDAT_SRC */ +#define WM8995_AIF2_ADCDAT_SRC_MASK 0x0004 /* AIF2_ADCDAT_SRC */ +#define WM8995_AIF2_ADCDAT_SRC_SHIFT 2 /* AIF2_ADCDAT_SRC */ +#define WM8995_AIF2_ADCDAT_SRC_WIDTH 1 /* AIF2_ADCDAT_SRC */ +#define WM8995_AIF2_DACDAT_SRC 0x0002 /* AIF2_DACDAT_SRC */ +#define WM8995_AIF2_DACDAT_SRC_MASK 0x0002 /* AIF2_DACDAT_SRC */ +#define WM8995_AIF2_DACDAT_SRC_SHIFT 1 /* AIF2_DACDAT_SRC */ +#define WM8995_AIF2_DACDAT_SRC_WIDTH 1 /* AIF2_DACDAT_SRC */ +#define WM8995_AIF1_DACDAT_SRC 0x0001 /* AIF1_DACDAT_SRC */ +#define WM8995_AIF1_DACDAT_SRC_MASK 0x0001 /* AIF1_DACDAT_SRC */ +#define WM8995_AIF1_DACDAT_SRC_SHIFT 0 /* AIF1_DACDAT_SRC */ +#define WM8995_AIF1_DACDAT_SRC_WIDTH 1 /* AIF1_DACDAT_SRC */ + +/* + * R16 (0x10) - Left Line Input 1 Volume + */ +#define WM8995_IN1_VU 0x0080 /* IN1_VU */ +#define WM8995_IN1_VU_MASK 0x0080 /* IN1_VU */ +#define WM8995_IN1_VU_SHIFT 7 /* IN1_VU */ +#define WM8995_IN1_VU_WIDTH 1 /* IN1_VU */ +#define WM8995_IN1L_ZC 0x0020 /* IN1L_ZC */ +#define WM8995_IN1L_ZC_MASK 0x0020 /* IN1L_ZC */ +#define WM8995_IN1L_ZC_SHIFT 5 /* IN1L_ZC */ +#define WM8995_IN1L_ZC_WIDTH 1 /* IN1L_ZC */ +#define WM8995_IN1L_VOL_MASK 0x001F /* IN1L_VOL - [4:0] */ +#define WM8995_IN1L_VOL_SHIFT 0 /* IN1L_VOL - [4:0] */ +#define WM8995_IN1L_VOL_WIDTH 5 /* IN1L_VOL - [4:0] */ + +/* + * R17 (0x11) - Right Line Input 1 Volume + */ +#define WM8995_IN1_VU 0x0080 /* IN1_VU */ +#define WM8995_IN1_VU_MASK 0x0080 /* IN1_VU */ +#define WM8995_IN1_VU_SHIFT 7 /* IN1_VU */ +#define WM8995_IN1_VU_WIDTH 1 /* IN1_VU */ +#define WM8995_IN1R_ZC 0x0020 /* IN1R_ZC */ +#define WM8995_IN1R_ZC_MASK 0x0020 /* IN1R_ZC */ +#define WM8995_IN1R_ZC_SHIFT 5 /* IN1R_ZC */ +#define WM8995_IN1R_ZC_WIDTH 1 /* IN1R_ZC */ +#define WM8995_IN1R_VOL_MASK 0x001F /* IN1R_VOL - [4:0] */ +#define WM8995_IN1R_VOL_SHIFT 0 /* IN1R_VOL - [4:0] */ +#define WM8995_IN1R_VOL_WIDTH 5 /* IN1R_VOL - [4:0] */ + +/* + * R18 (0x12) - Left Line Input Control + */ +#define WM8995_IN1L_BOOST_MASK 0x0030 /* IN1L_BOOST - [5:4] */ +#define WM8995_IN1L_BOOST_SHIFT 4 /* IN1L_BOOST - [5:4] */ +#define WM8995_IN1L_BOOST_WIDTH 2 /* IN1L_BOOST - [5:4] */ +#define WM8995_IN1L_MODE_MASK 0x000C /* IN1L_MODE - [3:2] */ +#define WM8995_IN1L_MODE_SHIFT 2 /* IN1L_MODE - [3:2] */ +#define WM8995_IN1L_MODE_WIDTH 2 /* IN1L_MODE - [3:2] */ +#define WM8995_IN1R_MODE_MASK 0x0003 /* IN1R_MODE - [1:0] */ +#define WM8995_IN1R_MODE_SHIFT 0 /* IN1R_MODE - [1:0] */ +#define WM8995_IN1R_MODE_WIDTH 2 /* IN1R_MODE - [1:0] */ + +/* + * R24 (0x18) - DAC1 Left Volume + */ +#define WM8995_DAC1L_MUTE 0x0200 /* DAC1L_MUTE */ +#define WM8995_DAC1L_MUTE_MASK 0x0200 /* DAC1L_MUTE */ +#define WM8995_DAC1L_MUTE_SHIFT 9 /* DAC1L_MUTE */ +#define WM8995_DAC1L_MUTE_WIDTH 1 /* DAC1L_MUTE */ +#define WM8995_DAC1_VU 0x0100 /* DAC1_VU */ +#define WM8995_DAC1_VU_MASK 0x0100 /* DAC1_VU */ +#define WM8995_DAC1_VU_SHIFT 8 /* DAC1_VU */ +#define WM8995_DAC1_VU_WIDTH 1 /* DAC1_VU */ +#define WM8995_DAC1L_VOL_MASK 0x00FF /* DAC1L_VOL - [7:0] */ +#define WM8995_DAC1L_VOL_SHIFT 0 /* DAC1L_VOL - [7:0] */ +#define WM8995_DAC1L_VOL_WIDTH 8 /* DAC1L_VOL - [7:0] */ + +/* + * R25 (0x19) - DAC1 Right Volume + */ +#define WM8995_DAC1R_MUTE 0x0200 /* DAC1R_MUTE */ +#define WM8995_DAC1R_MUTE_MASK 0x0200 /* DAC1R_MUTE */ +#define WM8995_DAC1R_MUTE_SHIFT 9 /* DAC1R_MUTE */ +#define WM8995_DAC1R_MUTE_WIDTH 1 /* DAC1R_MUTE */ +#define WM8995_DAC1_VU 0x0100 /* DAC1_VU */ +#define WM8995_DAC1_VU_MASK 0x0100 /* DAC1_VU */ +#define WM8995_DAC1_VU_SHIFT 8 /* DAC1_VU */ +#define WM8995_DAC1_VU_WIDTH 1 /* DAC1_VU */ +#define WM8995_DAC1R_VOL_MASK 0x00FF /* DAC1R_VOL - [7:0] */ +#define WM8995_DAC1R_VOL_SHIFT 0 /* DAC1R_VOL - [7:0] */ +#define WM8995_DAC1R_VOL_WIDTH 8 /* DAC1R_VOL - [7:0] */ + +/* + * R26 (0x1A) - DAC2 Left Volume + */ +#define WM8995_DAC2L_MUTE 0x0200 /* DAC2L_MUTE */ +#define WM8995_DAC2L_MUTE_MASK 0x0200 /* DAC2L_MUTE */ +#define WM8995_DAC2L_MUTE_SHIFT 9 /* DAC2L_MUTE */ +#define WM8995_DAC2L_MUTE_WIDTH 1 /* DAC2L_MUTE */ +#define WM8995_DAC2_VU 0x0100 /* DAC2_VU */ +#define WM8995_DAC2_VU_MASK 0x0100 /* DAC2_VU */ +#define WM8995_DAC2_VU_SHIFT 8 /* DAC2_VU */ +#define WM8995_DAC2_VU_WIDTH 1 /* DAC2_VU */ +#define WM8995_DAC2L_VOL_MASK 0x00FF /* DAC2L_VOL - [7:0] */ +#define WM8995_DAC2L_VOL_SHIFT 0 /* DAC2L_VOL - [7:0] */ +#define WM8995_DAC2L_VOL_WIDTH 8 /* DAC2L_VOL - [7:0] */ + +/* + * R27 (0x1B) - DAC2 Right Volume + */ +#define WM8995_DAC2R_MUTE 0x0200 /* DAC2R_MUTE */ +#define WM8995_DAC2R_MUTE_MASK 0x0200 /* DAC2R_MUTE */ +#define WM8995_DAC2R_MUTE_SHIFT 9 /* DAC2R_MUTE */ +#define WM8995_DAC2R_MUTE_WIDTH 1 /* DAC2R_MUTE */ +#define WM8995_DAC2_VU 0x0100 /* DAC2_VU */ +#define WM8995_DAC2_VU_MASK 0x0100 /* DAC2_VU */ +#define WM8995_DAC2_VU_SHIFT 8 /* DAC2_VU */ +#define WM8995_DAC2_VU_WIDTH 1 /* DAC2_VU */ +#define WM8995_DAC2R_VOL_MASK 0x00FF /* DAC2R_VOL - [7:0] */ +#define WM8995_DAC2R_VOL_SHIFT 0 /* DAC2R_VOL - [7:0] */ +#define WM8995_DAC2R_VOL_WIDTH 8 /* DAC2R_VOL - [7:0] */ + +/* + * R28 (0x1C) - Output Volume ZC (1) + */ +#define WM8995_HPOUT2L_ZC 0x0008 /* HPOUT2L_ZC */ +#define WM8995_HPOUT2L_ZC_MASK 0x0008 /* HPOUT2L_ZC */ +#define WM8995_HPOUT2L_ZC_SHIFT 3 /* HPOUT2L_ZC */ +#define WM8995_HPOUT2L_ZC_WIDTH 1 /* HPOUT2L_ZC */ +#define WM8995_HPOUT2R_ZC 0x0004 /* HPOUT2R_ZC */ +#define WM8995_HPOUT2R_ZC_MASK 0x0004 /* HPOUT2R_ZC */ +#define WM8995_HPOUT2R_ZC_SHIFT 2 /* HPOUT2R_ZC */ +#define WM8995_HPOUT2R_ZC_WIDTH 1 /* HPOUT2R_ZC */ +#define WM8995_HPOUT1L_ZC 0x0002 /* HPOUT1L_ZC */ +#define WM8995_HPOUT1L_ZC_MASK 0x0002 /* HPOUT1L_ZC */ +#define WM8995_HPOUT1L_ZC_SHIFT 1 /* HPOUT1L_ZC */ +#define WM8995_HPOUT1L_ZC_WIDTH 1 /* HPOUT1L_ZC */ +#define WM8995_HPOUT1R_ZC 0x0001 /* HPOUT1R_ZC */ +#define WM8995_HPOUT1R_ZC_MASK 0x0001 /* HPOUT1R_ZC */ +#define WM8995_HPOUT1R_ZC_SHIFT 0 /* HPOUT1R_ZC */ +#define WM8995_HPOUT1R_ZC_WIDTH 1 /* HPOUT1R_ZC */ + +/* + * R32 (0x20) - MICBIAS (1) + */ +#define WM8995_MICB1_MODE 0x0008 /* MICB1_MODE */ +#define WM8995_MICB1_MODE_MASK 0x0008 /* MICB1_MODE */ +#define WM8995_MICB1_MODE_SHIFT 3 /* MICB1_MODE */ +#define WM8995_MICB1_MODE_WIDTH 1 /* MICB1_MODE */ +#define WM8995_MICB1_LVL_MASK 0x0006 /* MICB1_LVL - [2:1] */ +#define WM8995_MICB1_LVL_SHIFT 1 /* MICB1_LVL - [2:1] */ +#define WM8995_MICB1_LVL_WIDTH 2 /* MICB1_LVL - [2:1] */ +#define WM8995_MICB1_DISCH 0x0001 /* MICB1_DISCH */ +#define WM8995_MICB1_DISCH_MASK 0x0001 /* MICB1_DISCH */ +#define WM8995_MICB1_DISCH_SHIFT 0 /* MICB1_DISCH */ +#define WM8995_MICB1_DISCH_WIDTH 1 /* MICB1_DISCH */ + +/* + * R33 (0x21) - MICBIAS (2) + */ +#define WM8995_MICB2_MODE 0x0008 /* MICB2_MODE */ +#define WM8995_MICB2_MODE_MASK 0x0008 /* MICB2_MODE */ +#define WM8995_MICB2_MODE_SHIFT 3 /* MICB2_MODE */ +#define WM8995_MICB2_MODE_WIDTH 1 /* MICB2_MODE */ +#define WM8995_MICB2_LVL_MASK 0x0006 /* MICB2_LVL - [2:1] */ +#define WM8995_MICB2_LVL_SHIFT 1 /* MICB2_LVL - [2:1] */ +#define WM8995_MICB2_LVL_WIDTH 2 /* MICB2_LVL - [2:1] */ +#define WM8995_MICB2_DISCH 0x0001 /* MICB2_DISCH */ +#define WM8995_MICB2_DISCH_MASK 0x0001 /* MICB2_DISCH */ +#define WM8995_MICB2_DISCH_SHIFT 0 /* MICB2_DISCH */ +#define WM8995_MICB2_DISCH_WIDTH 1 /* MICB2_DISCH */ + +/* + * R40 (0x28) - LDO 1 + */ +#define WM8995_LDO1_MODE 0x0020 /* LDO1_MODE */ +#define WM8995_LDO1_MODE_MASK 0x0020 /* LDO1_MODE */ +#define WM8995_LDO1_MODE_SHIFT 5 /* LDO1_MODE */ +#define WM8995_LDO1_MODE_WIDTH 1 /* LDO1_MODE */ +#define WM8995_LDO1_VSEL_MASK 0x0006 /* LDO1_VSEL - [2:1] */ +#define WM8995_LDO1_VSEL_SHIFT 1 /* LDO1_VSEL - [2:1] */ +#define WM8995_LDO1_VSEL_WIDTH 2 /* LDO1_VSEL - [2:1] */ +#define WM8995_LDO1_DISCH 0x0001 /* LDO1_DISCH */ +#define WM8995_LDO1_DISCH_MASK 0x0001 /* LDO1_DISCH */ +#define WM8995_LDO1_DISCH_SHIFT 0 /* LDO1_DISCH */ +#define WM8995_LDO1_DISCH_WIDTH 1 /* LDO1_DISCH */ + +/* + * R41 (0x29) - LDO 2 + */ +#define WM8995_LDO2_MODE 0x0020 /* LDO2_MODE */ +#define WM8995_LDO2_MODE_MASK 0x0020 /* LDO2_MODE */ +#define WM8995_LDO2_MODE_SHIFT 5 /* LDO2_MODE */ +#define WM8995_LDO2_MODE_WIDTH 1 /* LDO2_MODE */ +#define WM8995_LDO2_VSEL_MASK 0x001E /* LDO2_VSEL - [4:1] */ +#define WM8995_LDO2_VSEL_SHIFT 1 /* LDO2_VSEL - [4:1] */ +#define WM8995_LDO2_VSEL_WIDTH 4 /* LDO2_VSEL - [4:1] */ +#define WM8995_LDO2_DISCH 0x0001 /* LDO2_DISCH */ +#define WM8995_LDO2_DISCH_MASK 0x0001 /* LDO2_DISCH */ +#define WM8995_LDO2_DISCH_SHIFT 0 /* LDO2_DISCH */ +#define WM8995_LDO2_DISCH_WIDTH 1 /* LDO2_DISCH */ + +/* + * R48 (0x30) - Accessory Detect Mode1 + */ +#define WM8995_JD_MODE_MASK 0x0003 /* JD_MODE - [1:0] */ +#define WM8995_JD_MODE_SHIFT 0 /* JD_MODE - [1:0] */ +#define WM8995_JD_MODE_WIDTH 2 /* JD_MODE - [1:0] */ + +/* + * R49 (0x31) - Accessory Detect Mode2 + */ +#define WM8995_VID_ENA 0x0001 /* VID_ENA */ +#define WM8995_VID_ENA_MASK 0x0001 /* VID_ENA */ +#define WM8995_VID_ENA_SHIFT 0 /* VID_ENA */ +#define WM8995_VID_ENA_WIDTH 1 /* VID_ENA */ + +/* + * R52 (0x34) - Headphone Detect1 + */ +#define WM8995_HP_RAMPRATE 0x0002 /* HP_RAMPRATE */ +#define WM8995_HP_RAMPRATE_MASK 0x0002 /* HP_RAMPRATE */ +#define WM8995_HP_RAMPRATE_SHIFT 1 /* HP_RAMPRATE */ +#define WM8995_HP_RAMPRATE_WIDTH 1 /* HP_RAMPRATE */ +#define WM8995_HP_POLL 0x0001 /* HP_POLL */ +#define WM8995_HP_POLL_MASK 0x0001 /* HP_POLL */ +#define WM8995_HP_POLL_SHIFT 0 /* HP_POLL */ +#define WM8995_HP_POLL_WIDTH 1 /* HP_POLL */ + +/* + * R53 (0x35) - Headphone Detect2 + */ +#define WM8995_HP_DONE 0x0080 /* HP_DONE */ +#define WM8995_HP_DONE_MASK 0x0080 /* HP_DONE */ +#define WM8995_HP_DONE_SHIFT 7 /* HP_DONE */ +#define WM8995_HP_DONE_WIDTH 1 /* HP_DONE */ +#define WM8995_HP_LVL_MASK 0x007F /* HP_LVL - [6:0] */ +#define WM8995_HP_LVL_SHIFT 0 /* HP_LVL - [6:0] */ +#define WM8995_HP_LVL_WIDTH 7 /* HP_LVL - [6:0] */ + +/* + * R56 (0x38) - Mic Detect (1) + */ +#define WM8995_MICD_RATE_MASK 0x7800 /* MICD_RATE - [14:11] */ +#define WM8995_MICD_RATE_SHIFT 11 /* MICD_RATE - [14:11] */ +#define WM8995_MICD_RATE_WIDTH 4 /* MICD_RATE - [14:11] */ +#define WM8995_MICD_LVL_SEL_MASK 0x01F8 /* MICD_LVL_SEL - [8:3] */ +#define WM8995_MICD_LVL_SEL_SHIFT 3 /* MICD_LVL_SEL - [8:3] */ +#define WM8995_MICD_LVL_SEL_WIDTH 6 /* MICD_LVL_SEL - [8:3] */ +#define WM8995_MICD_DBTIME 0x0002 /* MICD_DBTIME */ +#define WM8995_MICD_DBTIME_MASK 0x0002 /* MICD_DBTIME */ +#define WM8995_MICD_DBTIME_SHIFT 1 /* MICD_DBTIME */ +#define WM8995_MICD_DBTIME_WIDTH 1 /* MICD_DBTIME */ +#define WM8995_MICD_ENA 0x0001 /* MICD_ENA */ +#define WM8995_MICD_ENA_MASK 0x0001 /* MICD_ENA */ +#define WM8995_MICD_ENA_SHIFT 0 /* MICD_ENA */ +#define WM8995_MICD_ENA_WIDTH 1 /* MICD_ENA */ + +/* + * R57 (0x39) - Mic Detect (2) + */ +#define WM8995_MICD_LVL_MASK 0x01FC /* MICD_LVL - [8:2] */ +#define WM8995_MICD_LVL_SHIFT 2 /* MICD_LVL - [8:2] */ +#define WM8995_MICD_LVL_WIDTH 7 /* MICD_LVL - [8:2] */ +#define WM8995_MICD_VALID 0x0002 /* MICD_VALID */ +#define WM8995_MICD_VALID_MASK 0x0002 /* MICD_VALID */ +#define WM8995_MICD_VALID_SHIFT 1 /* MICD_VALID */ +#define WM8995_MICD_VALID_WIDTH 1 /* MICD_VALID */ +#define WM8995_MICD_STS 0x0001 /* MICD_STS */ +#define WM8995_MICD_STS_MASK 0x0001 /* MICD_STS */ +#define WM8995_MICD_STS_SHIFT 0 /* MICD_STS */ +#define WM8995_MICD_STS_WIDTH 1 /* MICD_STS */ + +/* + * R64 (0x40) - Charge Pump (1) + */ +#define WM8995_CP_ENA 0x8000 /* CP_ENA */ +#define WM8995_CP_ENA_MASK 0x8000 /* CP_ENA */ +#define WM8995_CP_ENA_SHIFT 15 /* CP_ENA */ +#define WM8995_CP_ENA_WIDTH 1 /* CP_ENA */ + +/* + * R69 (0x45) - Class W (1) + */ +#define WM8995_CP_DYN_SRC_SEL_MASK 0x0300 /* CP_DYN_SRC_SEL - [9:8] */ +#define WM8995_CP_DYN_SRC_SEL_SHIFT 8 /* CP_DYN_SRC_SEL - [9:8] */ +#define WM8995_CP_DYN_SRC_SEL_WIDTH 2 /* CP_DYN_SRC_SEL - [9:8] */ +#define WM8995_CP_DYN_PWR 0x0001 /* CP_DYN_PWR */ +#define WM8995_CP_DYN_PWR_MASK 0x0001 /* CP_DYN_PWR */ +#define WM8995_CP_DYN_PWR_SHIFT 0 /* CP_DYN_PWR */ +#define WM8995_CP_DYN_PWR_WIDTH 1 /* CP_DYN_PWR */ + +/* + * R80 (0x50) - DC Servo (1) + */ +#define WM8995_DCS_ENA_CHAN_3 0x0008 /* DCS_ENA_CHAN_3 */ +#define WM8995_DCS_ENA_CHAN_3_MASK 0x0008 /* DCS_ENA_CHAN_3 */ +#define WM8995_DCS_ENA_CHAN_3_SHIFT 3 /* DCS_ENA_CHAN_3 */ +#define WM8995_DCS_ENA_CHAN_3_WIDTH 1 /* DCS_ENA_CHAN_3 */ +#define WM8995_DCS_ENA_CHAN_2 0x0004 /* DCS_ENA_CHAN_2 */ +#define WM8995_DCS_ENA_CHAN_2_MASK 0x0004 /* DCS_ENA_CHAN_2 */ +#define WM8995_DCS_ENA_CHAN_2_SHIFT 2 /* DCS_ENA_CHAN_2 */ +#define WM8995_DCS_ENA_CHAN_2_WIDTH 1 /* DCS_ENA_CHAN_2 */ +#define WM8995_DCS_ENA_CHAN_1 0x0002 /* DCS_ENA_CHAN_1 */ +#define WM8995_DCS_ENA_CHAN_1_MASK 0x0002 /* DCS_ENA_CHAN_1 */ +#define WM8995_DCS_ENA_CHAN_1_SHIFT 1 /* DCS_ENA_CHAN_1 */ +#define WM8995_DCS_ENA_CHAN_1_WIDTH 1 /* DCS_ENA_CHAN_1 */ +#define WM8995_DCS_ENA_CHAN_0 0x0001 /* DCS_ENA_CHAN_0 */ +#define WM8995_DCS_ENA_CHAN_0_MASK 0x0001 /* DCS_ENA_CHAN_0 */ +#define WM8995_DCS_ENA_CHAN_0_SHIFT 0 /* DCS_ENA_CHAN_0 */ +#define WM8995_DCS_ENA_CHAN_0_WIDTH 1 /* DCS_ENA_CHAN_0 */ + +/* + * R81 (0x51) - DC Servo (2) + */ +#define WM8995_DCS_TRIG_SINGLE_3 0x8000 /* DCS_TRIG_SINGLE_3 */ +#define WM8995_DCS_TRIG_SINGLE_3_MASK 0x8000 /* DCS_TRIG_SINGLE_3 */ +#define WM8995_DCS_TRIG_SINGLE_3_SHIFT 15 /* DCS_TRIG_SINGLE_3 */ +#define WM8995_DCS_TRIG_SINGLE_3_WIDTH 1 /* DCS_TRIG_SINGLE_3 */ +#define WM8995_DCS_TRIG_SINGLE_2 0x4000 /* DCS_TRIG_SINGLE_2 */ +#define WM8995_DCS_TRIG_SINGLE_2_MASK 0x4000 /* DCS_TRIG_SINGLE_2 */ +#define WM8995_DCS_TRIG_SINGLE_2_SHIFT 14 /* DCS_TRIG_SINGLE_2 */ +#define WM8995_DCS_TRIG_SINGLE_2_WIDTH 1 /* DCS_TRIG_SINGLE_2 */ +#define WM8995_DCS_TRIG_SINGLE_1 0x2000 /* DCS_TRIG_SINGLE_1 */ +#define WM8995_DCS_TRIG_SINGLE_1_MASK 0x2000 /* DCS_TRIG_SINGLE_1 */ +#define WM8995_DCS_TRIG_SINGLE_1_SHIFT 13 /* DCS_TRIG_SINGLE_1 */ +#define WM8995_DCS_TRIG_SINGLE_1_WIDTH 1 /* DCS_TRIG_SINGLE_1 */ +#define WM8995_DCS_TRIG_SINGLE_0 0x1000 /* DCS_TRIG_SINGLE_0 */ +#define WM8995_DCS_TRIG_SINGLE_0_MASK 0x1000 /* DCS_TRIG_SINGLE_0 */ +#define WM8995_DCS_TRIG_SINGLE_0_SHIFT 12 /* DCS_TRIG_SINGLE_0 */ +#define WM8995_DCS_TRIG_SINGLE_0_WIDTH 1 /* DCS_TRIG_SINGLE_0 */ +#define WM8995_DCS_TRIG_SERIES_3 0x0800 /* DCS_TRIG_SERIES_3 */ +#define WM8995_DCS_TRIG_SERIES_3_MASK 0x0800 /* DCS_TRIG_SERIES_3 */ +#define WM8995_DCS_TRIG_SERIES_3_SHIFT 11 /* DCS_TRIG_SERIES_3 */ +#define WM8995_DCS_TRIG_SERIES_3_WIDTH 1 /* DCS_TRIG_SERIES_3 */ +#define WM8995_DCS_TRIG_SERIES_2 0x0400 /* DCS_TRIG_SERIES_2 */ +#define WM8995_DCS_TRIG_SERIES_2_MASK 0x0400 /* DCS_TRIG_SERIES_2 */ +#define WM8995_DCS_TRIG_SERIES_2_SHIFT 10 /* DCS_TRIG_SERIES_2 */ +#define WM8995_DCS_TRIG_SERIES_2_WIDTH 1 /* DCS_TRIG_SERIES_2 */ +#define WM8995_DCS_TRIG_SERIES_1 0x0200 /* DCS_TRIG_SERIES_1 */ +#define WM8995_DCS_TRIG_SERIES_1_MASK 0x0200 /* DCS_TRIG_SERIES_1 */ +#define WM8995_DCS_TRIG_SERIES_1_SHIFT 9 /* DCS_TRIG_SERIES_1 */ +#define WM8995_DCS_TRIG_SERIES_1_WIDTH 1 /* DCS_TRIG_SERIES_1 */ +#define WM8995_DCS_TRIG_SERIES_0 0x0100 /* DCS_TRIG_SERIES_0 */ +#define WM8995_DCS_TRIG_SERIES_0_MASK 0x0100 /* DCS_TRIG_SERIES_0 */ +#define WM8995_DCS_TRIG_SERIES_0_SHIFT 8 /* DCS_TRIG_SERIES_0 */ +#define WM8995_DCS_TRIG_SERIES_0_WIDTH 1 /* DCS_TRIG_SERIES_0 */ +#define WM8995_DCS_TRIG_STARTUP_3 0x0080 /* DCS_TRIG_STARTUP_3 */ +#define WM8995_DCS_TRIG_STARTUP_3_MASK 0x0080 /* DCS_TRIG_STARTUP_3 */ +#define WM8995_DCS_TRIG_STARTUP_3_SHIFT 7 /* DCS_TRIG_STARTUP_3 */ +#define WM8995_DCS_TRIG_STARTUP_3_WIDTH 1 /* DCS_TRIG_STARTUP_3 */ +#define WM8995_DCS_TRIG_STARTUP_2 0x0040 /* DCS_TRIG_STARTUP_2 */ +#define WM8995_DCS_TRIG_STARTUP_2_MASK 0x0040 /* DCS_TRIG_STARTUP_2 */ +#define WM8995_DCS_TRIG_STARTUP_2_SHIFT 6 /* DCS_TRIG_STARTUP_2 */ +#define WM8995_DCS_TRIG_STARTUP_2_WIDTH 1 /* DCS_TRIG_STARTUP_2 */ +#define WM8995_DCS_TRIG_STARTUP_1 0x0020 /* DCS_TRIG_STARTUP_1 */ +#define WM8995_DCS_TRIG_STARTUP_1_MASK 0x0020 /* DCS_TRIG_STARTUP_1 */ +#define WM8995_DCS_TRIG_STARTUP_1_SHIFT 5 /* DCS_TRIG_STARTUP_1 */ +#define WM8995_DCS_TRIG_STARTUP_1_WIDTH 1 /* DCS_TRIG_STARTUP_1 */ +#define WM8995_DCS_TRIG_STARTUP_0 0x0010 /* DCS_TRIG_STARTUP_0 */ +#define WM8995_DCS_TRIG_STARTUP_0_MASK 0x0010 /* DCS_TRIG_STARTUP_0 */ +#define WM8995_DCS_TRIG_STARTUP_0_SHIFT 4 /* DCS_TRIG_STARTUP_0 */ +#define WM8995_DCS_TRIG_STARTUP_0_WIDTH 1 /* DCS_TRIG_STARTUP_0 */ +#define WM8995_DCS_TRIG_DAC_WR_3 0x0008 /* DCS_TRIG_DAC_WR_3 */ +#define WM8995_DCS_TRIG_DAC_WR_3_MASK 0x0008 /* DCS_TRIG_DAC_WR_3 */ +#define WM8995_DCS_TRIG_DAC_WR_3_SHIFT 3 /* DCS_TRIG_DAC_WR_3 */ +#define WM8995_DCS_TRIG_DAC_WR_3_WIDTH 1 /* DCS_TRIG_DAC_WR_3 */ +#define WM8995_DCS_TRIG_DAC_WR_2 0x0004 /* DCS_TRIG_DAC_WR_2 */ +#define WM8995_DCS_TRIG_DAC_WR_2_MASK 0x0004 /* DCS_TRIG_DAC_WR_2 */ +#define WM8995_DCS_TRIG_DAC_WR_2_SHIFT 2 /* DCS_TRIG_DAC_WR_2 */ +#define WM8995_DCS_TRIG_DAC_WR_2_WIDTH 1 /* DCS_TRIG_DAC_WR_2 */ +#define WM8995_DCS_TRIG_DAC_WR_1 0x0002 /* DCS_TRIG_DAC_WR_1 */ +#define WM8995_DCS_TRIG_DAC_WR_1_MASK 0x0002 /* DCS_TRIG_DAC_WR_1 */ +#define WM8995_DCS_TRIG_DAC_WR_1_SHIFT 1 /* DCS_TRIG_DAC_WR_1 */ +#define WM8995_DCS_TRIG_DAC_WR_1_WIDTH 1 /* DCS_TRIG_DAC_WR_1 */ +#define WM8995_DCS_TRIG_DAC_WR_0 0x0001 /* DCS_TRIG_DAC_WR_0 */ +#define WM8995_DCS_TRIG_DAC_WR_0_MASK 0x0001 /* DCS_TRIG_DAC_WR_0 */ +#define WM8995_DCS_TRIG_DAC_WR_0_SHIFT 0 /* DCS_TRIG_DAC_WR_0 */ +#define WM8995_DCS_TRIG_DAC_WR_0_WIDTH 1 /* DCS_TRIG_DAC_WR_0 */ + +/* + * R82 (0x52) - DC Servo (3) + */ +#define WM8995_DCS_TIMER_PERIOD_23_MASK 0x0F00 /* DCS_TIMER_PERIOD_23 - [11:8] */ +#define WM8995_DCS_TIMER_PERIOD_23_SHIFT 8 /* DCS_TIMER_PERIOD_23 - [11:8] */ +#define WM8995_DCS_TIMER_PERIOD_23_WIDTH 4 /* DCS_TIMER_PERIOD_23 - [11:8] */ +#define WM8995_DCS_TIMER_PERIOD_01_MASK 0x000F /* DCS_TIMER_PERIOD_01 - [3:0] */ +#define WM8995_DCS_TIMER_PERIOD_01_SHIFT 0 /* DCS_TIMER_PERIOD_01 - [3:0] */ +#define WM8995_DCS_TIMER_PERIOD_01_WIDTH 4 /* DCS_TIMER_PERIOD_01 - [3:0] */ + +/* + * R84 (0x54) - DC Servo (5) + */ +#define WM8995_DCS_SERIES_NO_23_MASK 0x7F00 /* DCS_SERIES_NO_23 - [14:8] */ +#define WM8995_DCS_SERIES_NO_23_SHIFT 8 /* DCS_SERIES_NO_23 - [14:8] */ +#define WM8995_DCS_SERIES_NO_23_WIDTH 7 /* DCS_SERIES_NO_23 - [14:8] */ +#define WM8995_DCS_SERIES_NO_01_MASK 0x007F /* DCS_SERIES_NO_01 - [6:0] */ +#define WM8995_DCS_SERIES_NO_01_SHIFT 0 /* DCS_SERIES_NO_01 - [6:0] */ +#define WM8995_DCS_SERIES_NO_01_WIDTH 7 /* DCS_SERIES_NO_01 - [6:0] */ + +/* + * R85 (0x55) - DC Servo (6) + */ +#define WM8995_DCS_DAC_WR_VAL_3_MASK 0xFF00 /* DCS_DAC_WR_VAL_3 - [15:8] */ +#define WM8995_DCS_DAC_WR_VAL_3_SHIFT 8 /* DCS_DAC_WR_VAL_3 - [15:8] */ +#define WM8995_DCS_DAC_WR_VAL_3_WIDTH 8 /* DCS_DAC_WR_VAL_3 - [15:8] */ +#define WM8995_DCS_DAC_WR_VAL_2_MASK 0x00FF /* DCS_DAC_WR_VAL_2 - [7:0] */ +#define WM8995_DCS_DAC_WR_VAL_2_SHIFT 0 /* DCS_DAC_WR_VAL_2 - [7:0] */ +#define WM8995_DCS_DAC_WR_VAL_2_WIDTH 8 /* DCS_DAC_WR_VAL_2 - [7:0] */ + +/* + * R86 (0x56) - DC Servo (7) + */ +#define WM8995_DCS_DAC_WR_VAL_1_MASK 0xFF00 /* DCS_DAC_WR_VAL_1 - [15:8] */ +#define WM8995_DCS_DAC_WR_VAL_1_SHIFT 8 /* DCS_DAC_WR_VAL_1 - [15:8] */ +#define WM8995_DCS_DAC_WR_VAL_1_WIDTH 8 /* DCS_DAC_WR_VAL_1 - [15:8] */ +#define WM8995_DCS_DAC_WR_VAL_0_MASK 0x00FF /* DCS_DAC_WR_VAL_0 - [7:0] */ +#define WM8995_DCS_DAC_WR_VAL_0_SHIFT 0 /* DCS_DAC_WR_VAL_0 - [7:0] */ +#define WM8995_DCS_DAC_WR_VAL_0_WIDTH 8 /* DCS_DAC_WR_VAL_0 - [7:0] */ + +/* + * R87 (0x57) - DC Servo Readback 0 + */ +#define WM8995_DCS_CAL_COMPLETE_MASK 0x0F00 /* DCS_CAL_COMPLETE - [11:8] */ +#define WM8995_DCS_CAL_COMPLETE_SHIFT 8 /* DCS_CAL_COMPLETE - [11:8] */ +#define WM8995_DCS_CAL_COMPLETE_WIDTH 4 /* DCS_CAL_COMPLETE - [11:8] */ +#define WM8995_DCS_DAC_WR_COMPLETE_MASK 0x00F0 /* DCS_DAC_WR_COMPLETE - [7:4] */ +#define WM8995_DCS_DAC_WR_COMPLETE_SHIFT 4 /* DCS_DAC_WR_COMPLETE - [7:4] */ +#define WM8995_DCS_DAC_WR_COMPLETE_WIDTH 4 /* DCS_DAC_WR_COMPLETE - [7:4] */ +#define WM8995_DCS_STARTUP_COMPLETE_MASK 0x000F /* DCS_STARTUP_COMPLETE - [3:0] */ +#define WM8995_DCS_STARTUP_COMPLETE_SHIFT 0 /* DCS_STARTUP_COMPLETE - [3:0] */ +#define WM8995_DCS_STARTUP_COMPLETE_WIDTH 4 /* DCS_STARTUP_COMPLETE - [3:0] */ + +/* + * R96 (0x60) - Analogue HP (1) + */ +#define WM8995_HPOUT1L_RMV_SHORT 0x0080 /* HPOUT1L_RMV_SHORT */ +#define WM8995_HPOUT1L_RMV_SHORT_MASK 0x0080 /* HPOUT1L_RMV_SHORT */ +#define WM8995_HPOUT1L_RMV_SHORT_SHIFT 7 /* HPOUT1L_RMV_SHORT */ +#define WM8995_HPOUT1L_RMV_SHORT_WIDTH 1 /* HPOUT1L_RMV_SHORT */ +#define WM8995_HPOUT1L_OUTP 0x0040 /* HPOUT1L_OUTP */ +#define WM8995_HPOUT1L_OUTP_MASK 0x0040 /* HPOUT1L_OUTP */ +#define WM8995_HPOUT1L_OUTP_SHIFT 6 /* HPOUT1L_OUTP */ +#define WM8995_HPOUT1L_OUTP_WIDTH 1 /* HPOUT1L_OUTP */ +#define WM8995_HPOUT1L_DLY 0x0020 /* HPOUT1L_DLY */ +#define WM8995_HPOUT1L_DLY_MASK 0x0020 /* HPOUT1L_DLY */ +#define WM8995_HPOUT1L_DLY_SHIFT 5 /* HPOUT1L_DLY */ +#define WM8995_HPOUT1L_DLY_WIDTH 1 /* HPOUT1L_DLY */ +#define WM8995_HPOUT1R_RMV_SHORT 0x0008 /* HPOUT1R_RMV_SHORT */ +#define WM8995_HPOUT1R_RMV_SHORT_MASK 0x0008 /* HPOUT1R_RMV_SHORT */ +#define WM8995_HPOUT1R_RMV_SHORT_SHIFT 3 /* HPOUT1R_RMV_SHORT */ +#define WM8995_HPOUT1R_RMV_SHORT_WIDTH 1 /* HPOUT1R_RMV_SHORT */ +#define WM8995_HPOUT1R_OUTP 0x0004 /* HPOUT1R_OUTP */ +#define WM8995_HPOUT1R_OUTP_MASK 0x0004 /* HPOUT1R_OUTP */ +#define WM8995_HPOUT1R_OUTP_SHIFT 2 /* HPOUT1R_OUTP */ +#define WM8995_HPOUT1R_OUTP_WIDTH 1 /* HPOUT1R_OUTP */ +#define WM8995_HPOUT1R_DLY 0x0002 /* HPOUT1R_DLY */ +#define WM8995_HPOUT1R_DLY_MASK 0x0002 /* HPOUT1R_DLY */ +#define WM8995_HPOUT1R_DLY_SHIFT 1 /* HPOUT1R_DLY */ +#define WM8995_HPOUT1R_DLY_WIDTH 1 /* HPOUT1R_DLY */ + +/* + * R97 (0x61) - Analogue HP (2) + */ +#define WM8995_HPOUT2L_RMV_SHORT 0x0080 /* HPOUT2L_RMV_SHORT */ +#define WM8995_HPOUT2L_RMV_SHORT_MASK 0x0080 /* HPOUT2L_RMV_SHORT */ +#define WM8995_HPOUT2L_RMV_SHORT_SHIFT 7 /* HPOUT2L_RMV_SHORT */ +#define WM8995_HPOUT2L_RMV_SHORT_WIDTH 1 /* HPOUT2L_RMV_SHORT */ +#define WM8995_HPOUT2L_OUTP 0x0040 /* HPOUT2L_OUTP */ +#define WM8995_HPOUT2L_OUTP_MASK 0x0040 /* HPOUT2L_OUTP */ +#define WM8995_HPOUT2L_OUTP_SHIFT 6 /* HPOUT2L_OUTP */ +#define WM8995_HPOUT2L_OUTP_WIDTH 1 /* HPOUT2L_OUTP */ +#define WM8995_HPOUT2L_DLY 0x0020 /* HPOUT2L_DLY */ +#define WM8995_HPOUT2L_DLY_MASK 0x0020 /* HPOUT2L_DLY */ +#define WM8995_HPOUT2L_DLY_SHIFT 5 /* HPOUT2L_DLY */ +#define WM8995_HPOUT2L_DLY_WIDTH 1 /* HPOUT2L_DLY */ +#define WM8995_HPOUT2R_RMV_SHORT 0x0008 /* HPOUT2R_RMV_SHORT */ +#define WM8995_HPOUT2R_RMV_SHORT_MASK 0x0008 /* HPOUT2R_RMV_SHORT */ +#define WM8995_HPOUT2R_RMV_SHORT_SHIFT 3 /* HPOUT2R_RMV_SHORT */ +#define WM8995_HPOUT2R_RMV_SHORT_WIDTH 1 /* HPOUT2R_RMV_SHORT */ +#define WM8995_HPOUT2R_OUTP 0x0004 /* HPOUT2R_OUTP */ +#define WM8995_HPOUT2R_OUTP_MASK 0x0004 /* HPOUT2R_OUTP */ +#define WM8995_HPOUT2R_OUTP_SHIFT 2 /* HPOUT2R_OUTP */ +#define WM8995_HPOUT2R_OUTP_WIDTH 1 /* HPOUT2R_OUTP */ +#define WM8995_HPOUT2R_DLY 0x0002 /* HPOUT2R_DLY */ +#define WM8995_HPOUT2R_DLY_MASK 0x0002 /* HPOUT2R_DLY */ +#define WM8995_HPOUT2R_DLY_SHIFT 1 /* HPOUT2R_DLY */ +#define WM8995_HPOUT2R_DLY_WIDTH 1 /* HPOUT2R_DLY */ + +/* + * R256 (0x100) - Chip Revision + */ +#define WM8995_CHIP_REV_MASK 0x000F /* CHIP_REV - [3:0] */ +#define WM8995_CHIP_REV_SHIFT 0 /* CHIP_REV - [3:0] */ +#define WM8995_CHIP_REV_WIDTH 4 /* CHIP_REV - [3:0] */ + +/* + * R257 (0x101) - Control Interface (1) + */ +#define WM8995_REG_SYNC 0x8000 /* REG_SYNC */ +#define WM8995_REG_SYNC_MASK 0x8000 /* REG_SYNC */ +#define WM8995_REG_SYNC_SHIFT 15 /* REG_SYNC */ +#define WM8995_REG_SYNC_WIDTH 1 /* REG_SYNC */ +#define WM8995_SPI_CONTRD 0x0040 /* SPI_CONTRD */ +#define WM8995_SPI_CONTRD_MASK 0x0040 /* SPI_CONTRD */ +#define WM8995_SPI_CONTRD_SHIFT 6 /* SPI_CONTRD */ +#define WM8995_SPI_CONTRD_WIDTH 1 /* SPI_CONTRD */ +#define WM8995_SPI_4WIRE 0x0020 /* SPI_4WIRE */ +#define WM8995_SPI_4WIRE_MASK 0x0020 /* SPI_4WIRE */ +#define WM8995_SPI_4WIRE_SHIFT 5 /* SPI_4WIRE */ +#define WM8995_SPI_4WIRE_WIDTH 1 /* SPI_4WIRE */ +#define WM8995_SPI_CFG 0x0010 /* SPI_CFG */ +#define WM8995_SPI_CFG_MASK 0x0010 /* SPI_CFG */ +#define WM8995_SPI_CFG_SHIFT 4 /* SPI_CFG */ +#define WM8995_SPI_CFG_WIDTH 1 /* SPI_CFG */ +#define WM8995_AUTO_INC 0x0004 /* AUTO_INC */ +#define WM8995_AUTO_INC_MASK 0x0004 /* AUTO_INC */ +#define WM8995_AUTO_INC_SHIFT 2 /* AUTO_INC */ +#define WM8995_AUTO_INC_WIDTH 1 /* AUTO_INC */ + +/* + * R258 (0x102) - Control Interface (2) + */ +#define WM8995_CTRL_IF_SRC 0x0001 /* CTRL_IF_SRC */ +#define WM8995_CTRL_IF_SRC_MASK 0x0001 /* CTRL_IF_SRC */ +#define WM8995_CTRL_IF_SRC_SHIFT 0 /* CTRL_IF_SRC */ +#define WM8995_CTRL_IF_SRC_WIDTH 1 /* CTRL_IF_SRC */ + +/* + * R272 (0x110) - Write Sequencer Ctrl (1) + */ +#define WM8995_WSEQ_ENA 0x8000 /* WSEQ_ENA */ +#define WM8995_WSEQ_ENA_MASK 0x8000 /* WSEQ_ENA */ +#define WM8995_WSEQ_ENA_SHIFT 15 /* WSEQ_ENA */ +#define WM8995_WSEQ_ENA_WIDTH 1 /* WSEQ_ENA */ +#define WM8995_WSEQ_ABORT 0x0200 /* WSEQ_ABORT */ +#define WM8995_WSEQ_ABORT_MASK 0x0200 /* WSEQ_ABORT */ +#define WM8995_WSEQ_ABORT_SHIFT 9 /* WSEQ_ABORT */ +#define WM8995_WSEQ_ABORT_WIDTH 1 /* WSEQ_ABORT */ +#define WM8995_WSEQ_START 0x0100 /* WSEQ_START */ +#define WM8995_WSEQ_START_MASK 0x0100 /* WSEQ_START */ +#define WM8995_WSEQ_START_SHIFT 8 /* WSEQ_START */ +#define WM8995_WSEQ_START_WIDTH 1 /* WSEQ_START */ +#define WM8995_WSEQ_START_INDEX_MASK 0x007F /* WSEQ_START_INDEX - [6:0] */ +#define WM8995_WSEQ_START_INDEX_SHIFT 0 /* WSEQ_START_INDEX - [6:0] */ +#define WM8995_WSEQ_START_INDEX_WIDTH 7 /* WSEQ_START_INDEX - [6:0] */ + +/* + * R273 (0x111) - Write Sequencer Ctrl (2) + */ +#define WM8995_WSEQ_BUSY 0x0100 /* WSEQ_BUSY */ +#define WM8995_WSEQ_BUSY_MASK 0x0100 /* WSEQ_BUSY */ +#define WM8995_WSEQ_BUSY_SHIFT 8 /* WSEQ_BUSY */ +#define WM8995_WSEQ_BUSY_WIDTH 1 /* WSEQ_BUSY */ +#define WM8995_WSEQ_CURRENT_INDEX_MASK 0x007F /* WSEQ_CURRENT_INDEX - [6:0] */ +#define WM8995_WSEQ_CURRENT_INDEX_SHIFT 0 /* WSEQ_CURRENT_INDEX - [6:0] */ +#define WM8995_WSEQ_CURRENT_INDEX_WIDTH 7 /* WSEQ_CURRENT_INDEX - [6:0] */ + +/* + * R512 (0x200) - AIF1 Clocking (1) + */ +#define WM8995_AIF1CLK_SRC_MASK 0x0018 /* AIF1CLK_SRC - [4:3] */ +#define WM8995_AIF1CLK_SRC_SHIFT 3 /* AIF1CLK_SRC - [4:3] */ +#define WM8995_AIF1CLK_SRC_WIDTH 2 /* AIF1CLK_SRC - [4:3] */ +#define WM8995_AIF1CLK_INV 0x0004 /* AIF1CLK_INV */ +#define WM8995_AIF1CLK_INV_MASK 0x0004 /* AIF1CLK_INV */ +#define WM8995_AIF1CLK_INV_SHIFT 2 /* AIF1CLK_INV */ +#define WM8995_AIF1CLK_INV_WIDTH 1 /* AIF1CLK_INV */ +#define WM8995_AIF1CLK_DIV 0x0002 /* AIF1CLK_DIV */ +#define WM8995_AIF1CLK_DIV_MASK 0x0002 /* AIF1CLK_DIV */ +#define WM8995_AIF1CLK_DIV_SHIFT 1 /* AIF1CLK_DIV */ +#define WM8995_AIF1CLK_DIV_WIDTH 1 /* AIF1CLK_DIV */ +#define WM8995_AIF1CLK_ENA 0x0001 /* AIF1CLK_ENA */ +#define WM8995_AIF1CLK_ENA_MASK 0x0001 /* AIF1CLK_ENA */ +#define WM8995_AIF1CLK_ENA_SHIFT 0 /* AIF1CLK_ENA */ +#define WM8995_AIF1CLK_ENA_WIDTH 1 /* AIF1CLK_ENA */ + +/* + * R513 (0x201) - AIF1 Clocking (2) + */ +#define WM8995_AIF1DAC_DIV_MASK 0x0038 /* AIF1DAC_DIV - [5:3] */ +#define WM8995_AIF1DAC_DIV_SHIFT 3 /* AIF1DAC_DIV - [5:3] */ +#define WM8995_AIF1DAC_DIV_WIDTH 3 /* AIF1DAC_DIV - [5:3] */ +#define WM8995_AIF1ADC_DIV_MASK 0x0007 /* AIF1ADC_DIV - [2:0] */ +#define WM8995_AIF1ADC_DIV_SHIFT 0 /* AIF1ADC_DIV - [2:0] */ +#define WM8995_AIF1ADC_DIV_WIDTH 3 /* AIF1ADC_DIV - [2:0] */ + +/* + * R516 (0x204) - AIF2 Clocking (1) + */ +#define WM8995_AIF2CLK_SRC_MASK 0x0018 /* AIF2CLK_SRC - [4:3] */ +#define WM8995_AIF2CLK_SRC_SHIFT 3 /* AIF2CLK_SRC - [4:3] */ +#define WM8995_AIF2CLK_SRC_WIDTH 2 /* AIF2CLK_SRC - [4:3] */ +#define WM8995_AIF2CLK_INV 0x0004 /* AIF2CLK_INV */ +#define WM8995_AIF2CLK_INV_MASK 0x0004 /* AIF2CLK_INV */ +#define WM8995_AIF2CLK_INV_SHIFT 2 /* AIF2CLK_INV */ +#define WM8995_AIF2CLK_INV_WIDTH 1 /* AIF2CLK_INV */ +#define WM8995_AIF2CLK_DIV 0x0002 /* AIF2CLK_DIV */ +#define WM8995_AIF2CLK_DIV_MASK 0x0002 /* AIF2CLK_DIV */ +#define WM8995_AIF2CLK_DIV_SHIFT 1 /* AIF2CLK_DIV */ +#define WM8995_AIF2CLK_DIV_WIDTH 1 /* AIF2CLK_DIV */ +#define WM8995_AIF2CLK_ENA 0x0001 /* AIF2CLK_ENA */ +#define WM8995_AIF2CLK_ENA_MASK 0x0001 /* AIF2CLK_ENA */ +#define WM8995_AIF2CLK_ENA_SHIFT 0 /* AIF2CLK_ENA */ +#define WM8995_AIF2CLK_ENA_WIDTH 1 /* AIF2CLK_ENA */ + +/* + * R517 (0x205) - AIF2 Clocking (2) + */ +#define WM8995_AIF2DAC_DIV_MASK 0x0038 /* AIF2DAC_DIV - [5:3] */ +#define WM8995_AIF2DAC_DIV_SHIFT 3 /* AIF2DAC_DIV - [5:3] */ +#define WM8995_AIF2DAC_DIV_WIDTH 3 /* AIF2DAC_DIV - [5:3] */ +#define WM8995_AIF2ADC_DIV_MASK 0x0007 /* AIF2ADC_DIV - [2:0] */ +#define WM8995_AIF2ADC_DIV_SHIFT 0 /* AIF2ADC_DIV - [2:0] */ +#define WM8995_AIF2ADC_DIV_WIDTH 3 /* AIF2ADC_DIV - [2:0] */ + +/* + * R520 (0x208) - Clocking (1) + */ +#define WM8995_LFCLK_ENA 0x0020 /* LFCLK_ENA */ +#define WM8995_LFCLK_ENA_MASK 0x0020 /* LFCLK_ENA */ +#define WM8995_LFCLK_ENA_SHIFT 5 /* LFCLK_ENA */ +#define WM8995_LFCLK_ENA_WIDTH 1 /* LFCLK_ENA */ +#define WM8995_TOCLK_ENA 0x0010 /* TOCLK_ENA */ +#define WM8995_TOCLK_ENA_MASK 0x0010 /* TOCLK_ENA */ +#define WM8995_TOCLK_ENA_SHIFT 4 /* TOCLK_ENA */ +#define WM8995_TOCLK_ENA_WIDTH 1 /* TOCLK_ENA */ +#define WM8995_AIF1DSPCLK_ENA 0x0008 /* AIF1DSPCLK_ENA */ +#define WM8995_AIF1DSPCLK_ENA_MASK 0x0008 /* AIF1DSPCLK_ENA */ +#define WM8995_AIF1DSPCLK_ENA_SHIFT 3 /* AIF1DSPCLK_ENA */ +#define WM8995_AIF1DSPCLK_ENA_WIDTH 1 /* AIF1DSPCLK_ENA */ +#define WM8995_AIF2DSPCLK_ENA 0x0004 /* AIF2DSPCLK_ENA */ +#define WM8995_AIF2DSPCLK_ENA_MASK 0x0004 /* AIF2DSPCLK_ENA */ +#define WM8995_AIF2DSPCLK_ENA_SHIFT 2 /* AIF2DSPCLK_ENA */ +#define WM8995_AIF2DSPCLK_ENA_WIDTH 1 /* AIF2DSPCLK_ENA */ +#define WM8995_SYSDSPCLK_ENA 0x0002 /* SYSDSPCLK_ENA */ +#define WM8995_SYSDSPCLK_ENA_MASK 0x0002 /* SYSDSPCLK_ENA */ +#define WM8995_SYSDSPCLK_ENA_SHIFT 1 /* SYSDSPCLK_ENA */ +#define WM8995_SYSDSPCLK_ENA_WIDTH 1 /* SYSDSPCLK_ENA */ +#define WM8995_SYSCLK_SRC 0x0001 /* SYSCLK_SRC */ +#define WM8995_SYSCLK_SRC_MASK 0x0001 /* SYSCLK_SRC */ +#define WM8995_SYSCLK_SRC_SHIFT 0 /* SYSCLK_SRC */ +#define WM8995_SYSCLK_SRC_WIDTH 1 /* SYSCLK_SRC */ + +/* + * R521 (0x209) - Clocking (2) + */ +#define WM8995_TOCLK_DIV_MASK 0x0700 /* TOCLK_DIV - [10:8] */ +#define WM8995_TOCLK_DIV_SHIFT 8 /* TOCLK_DIV - [10:8] */ +#define WM8995_TOCLK_DIV_WIDTH 3 /* TOCLK_DIV - [10:8] */ +#define WM8995_DBCLK_DIV_MASK 0x00F0 /* DBCLK_DIV - [7:4] */ +#define WM8995_DBCLK_DIV_SHIFT 4 /* DBCLK_DIV - [7:4] */ +#define WM8995_DBCLK_DIV_WIDTH 4 /* DBCLK_DIV - [7:4] */ +#define WM8995_OPCLK_DIV_MASK 0x0007 /* OPCLK_DIV - [2:0] */ +#define WM8995_OPCLK_DIV_SHIFT 0 /* OPCLK_DIV - [2:0] */ +#define WM8995_OPCLK_DIV_WIDTH 3 /* OPCLK_DIV - [2:0] */ + +/* + * R528 (0x210) - AIF1 Rate + */ +#define WM8995_AIF1_SR_MASK 0x00F0 /* AIF1_SR - [7:4] */ +#define WM8995_AIF1_SR_SHIFT 4 /* AIF1_SR - [7:4] */ +#define WM8995_AIF1_SR_WIDTH 4 /* AIF1_SR - [7:4] */ +#define WM8995_AIF1CLK_RATE_MASK 0x000F /* AIF1CLK_RATE - [3:0] */ +#define WM8995_AIF1CLK_RATE_SHIFT 0 /* AIF1CLK_RATE - [3:0] */ +#define WM8995_AIF1CLK_RATE_WIDTH 4 /* AIF1CLK_RATE - [3:0] */ + +/* + * R529 (0x211) - AIF2 Rate + */ +#define WM8995_AIF2_SR_MASK 0x00F0 /* AIF2_SR - [7:4] */ +#define WM8995_AIF2_SR_SHIFT 4 /* AIF2_SR - [7:4] */ +#define WM8995_AIF2_SR_WIDTH 4 /* AIF2_SR - [7:4] */ +#define WM8995_AIF2CLK_RATE_MASK 0x000F /* AIF2CLK_RATE - [3:0] */ +#define WM8995_AIF2CLK_RATE_SHIFT 0 /* AIF2CLK_RATE - [3:0] */ +#define WM8995_AIF2CLK_RATE_WIDTH 4 /* AIF2CLK_RATE - [3:0] */ + +/* + * R530 (0x212) - Rate Status + */ +#define WM8995_SR_ERROR_MASK 0x000F /* SR_ERROR - [3:0] */ +#define WM8995_SR_ERROR_SHIFT 0 /* SR_ERROR - [3:0] */ +#define WM8995_SR_ERROR_WIDTH 4 /* SR_ERROR - [3:0] */ + +/* + * R544 (0x220) - FLL1 Control (1) + */ +#define WM8995_FLL1_OSC_ENA 0x0002 /* FLL1_OSC_ENA */ +#define WM8995_FLL1_OSC_ENA_MASK 0x0002 /* FLL1_OSC_ENA */ +#define WM8995_FLL1_OSC_ENA_SHIFT 1 /* FLL1_OSC_ENA */ +#define WM8995_FLL1_OSC_ENA_WIDTH 1 /* FLL1_OSC_ENA */ +#define WM8995_FLL1_ENA 0x0001 /* FLL1_ENA */ +#define WM8995_FLL1_ENA_MASK 0x0001 /* FLL1_ENA */ +#define WM8995_FLL1_ENA_SHIFT 0 /* FLL1_ENA */ +#define WM8995_FLL1_ENA_WIDTH 1 /* FLL1_ENA */ + +/* + * R545 (0x221) - FLL1 Control (2) + */ +#define WM8995_FLL1_OUTDIV_MASK 0x3F00 /* FLL1_OUTDIV - [13:8] */ +#define WM8995_FLL1_OUTDIV_SHIFT 8 /* FLL1_OUTDIV - [13:8] */ +#define WM8995_FLL1_OUTDIV_WIDTH 6 /* FLL1_OUTDIV - [13:8] */ +#define WM8995_FLL1_CTRL_RATE_MASK 0x0070 /* FLL1_CTRL_RATE - [6:4] */ +#define WM8995_FLL1_CTRL_RATE_SHIFT 4 /* FLL1_CTRL_RATE - [6:4] */ +#define WM8995_FLL1_CTRL_RATE_WIDTH 3 /* FLL1_CTRL_RATE - [6:4] */ +#define WM8995_FLL1_FRATIO_MASK 0x0007 /* FLL1_FRATIO - [2:0] */ +#define WM8995_FLL1_FRATIO_SHIFT 0 /* FLL1_FRATIO - [2:0] */ +#define WM8995_FLL1_FRATIO_WIDTH 3 /* FLL1_FRATIO - [2:0] */ + +/* + * R546 (0x222) - FLL1 Control (3) + */ +#define WM8995_FLL1_K_MASK 0xFFFF /* FLL1_K - [15:0] */ +#define WM8995_FLL1_K_SHIFT 0 /* FLL1_K - [15:0] */ +#define WM8995_FLL1_K_WIDTH 16 /* FLL1_K - [15:0] */ + +/* + * R547 (0x223) - FLL1 Control (4) + */ +#define WM8995_FLL1_N_MASK 0x7FE0 /* FLL1_N - [14:5] */ +#define WM8995_FLL1_N_SHIFT 5 /* FLL1_N - [14:5] */ +#define WM8995_FLL1_N_WIDTH 10 /* FLL1_N - [14:5] */ +#define WM8995_FLL1_LOOP_GAIN_MASK 0x000F /* FLL1_LOOP_GAIN - [3:0] */ +#define WM8995_FLL1_LOOP_GAIN_SHIFT 0 /* FLL1_LOOP_GAIN - [3:0] */ +#define WM8995_FLL1_LOOP_GAIN_WIDTH 4 /* FLL1_LOOP_GAIN - [3:0] */ + +/* + * R548 (0x224) - FLL1 Control (5) + */ +#define WM8995_FLL1_FRC_NCO_VAL_MASK 0x1F80 /* FLL1_FRC_NCO_VAL - [12:7] */ +#define WM8995_FLL1_FRC_NCO_VAL_SHIFT 7 /* FLL1_FRC_NCO_VAL - [12:7] */ +#define WM8995_FLL1_FRC_NCO_VAL_WIDTH 6 /* FLL1_FRC_NCO_VAL - [12:7] */ +#define WM8995_FLL1_FRC_NCO 0x0040 /* FLL1_FRC_NCO */ +#define WM8995_FLL1_FRC_NCO_MASK 0x0040 /* FLL1_FRC_NCO */ +#define WM8995_FLL1_FRC_NCO_SHIFT 6 /* FLL1_FRC_NCO */ +#define WM8995_FLL1_FRC_NCO_WIDTH 1 /* FLL1_FRC_NCO */ +#define WM8995_FLL1_REFCLK_DIV_MASK 0x0018 /* FLL1_REFCLK_DIV - [4:3] */ +#define WM8995_FLL1_REFCLK_DIV_SHIFT 3 /* FLL1_REFCLK_DIV - [4:3] */ +#define WM8995_FLL1_REFCLK_DIV_WIDTH 2 /* FLL1_REFCLK_DIV - [4:3] */ +#define WM8995_FLL1_REFCLK_SRC_MASK 0x0003 /* FLL1_REFCLK_SRC - [1:0] */ +#define WM8995_FLL1_REFCLK_SRC_SHIFT 0 /* FLL1_REFCLK_SRC - [1:0] */ +#define WM8995_FLL1_REFCLK_SRC_WIDTH 2 /* FLL1_REFCLK_SRC - [1:0] */ + +/* + * R576 (0x240) - FLL2 Control (1) + */ +#define WM8995_FLL2_OSC_ENA 0x0002 /* FLL2_OSC_ENA */ +#define WM8995_FLL2_OSC_ENA_MASK 0x0002 /* FLL2_OSC_ENA */ +#define WM8995_FLL2_OSC_ENA_SHIFT 1 /* FLL2_OSC_ENA */ +#define WM8995_FLL2_OSC_ENA_WIDTH 1 /* FLL2_OSC_ENA */ +#define WM8995_FLL2_ENA 0x0001 /* FLL2_ENA */ +#define WM8995_FLL2_ENA_MASK 0x0001 /* FLL2_ENA */ +#define WM8995_FLL2_ENA_SHIFT 0 /* FLL2_ENA */ +#define WM8995_FLL2_ENA_WIDTH 1 /* FLL2_ENA */ + +/* + * R577 (0x241) - FLL2 Control (2) + */ +#define WM8995_FLL2_OUTDIV_MASK 0x3F00 /* FLL2_OUTDIV - [13:8] */ +#define WM8995_FLL2_OUTDIV_SHIFT 8 /* FLL2_OUTDIV - [13:8] */ +#define WM8995_FLL2_OUTDIV_WIDTH 6 /* FLL2_OUTDIV - [13:8] */ +#define WM8995_FLL2_CTRL_RATE_MASK 0x0070 /* FLL2_CTRL_RATE - [6:4] */ +#define WM8995_FLL2_CTRL_RATE_SHIFT 4 /* FLL2_CTRL_RATE - [6:4] */ +#define WM8995_FLL2_CTRL_RATE_WIDTH 3 /* FLL2_CTRL_RATE - [6:4] */ +#define WM8995_FLL2_FRATIO_MASK 0x0007 /* FLL2_FRATIO - [2:0] */ +#define WM8995_FLL2_FRATIO_SHIFT 0 /* FLL2_FRATIO - [2:0] */ +#define WM8995_FLL2_FRATIO_WIDTH 3 /* FLL2_FRATIO - [2:0] */ + +/* + * R578 (0x242) - FLL2 Control (3) + */ +#define WM8995_FLL2_K_MASK 0xFFFF /* FLL2_K - [15:0] */ +#define WM8995_FLL2_K_SHIFT 0 /* FLL2_K - [15:0] */ +#define WM8995_FLL2_K_WIDTH 16 /* FLL2_K - [15:0] */ + +/* + * R579 (0x243) - FLL2 Control (4) + */ +#define WM8995_FLL2_N_MASK 0x7FE0 /* FLL2_N - [14:5] */ +#define WM8995_FLL2_N_SHIFT 5 /* FLL2_N - [14:5] */ +#define WM8995_FLL2_N_WIDTH 10 /* FLL2_N - [14:5] */ +#define WM8995_FLL2_LOOP_GAIN_MASK 0x000F /* FLL2_LOOP_GAIN - [3:0] */ +#define WM8995_FLL2_LOOP_GAIN_SHIFT 0 /* FLL2_LOOP_GAIN - [3:0] */ +#define WM8995_FLL2_LOOP_GAIN_WIDTH 4 /* FLL2_LOOP_GAIN - [3:0] */ + +/* + * R580 (0x244) - FLL2 Control (5) + */ +#define WM8995_FLL2_FRC_NCO_VAL_MASK 0x1F80 /* FLL2_FRC_NCO_VAL - [12:7] */ +#define WM8995_FLL2_FRC_NCO_VAL_SHIFT 7 /* FLL2_FRC_NCO_VAL - [12:7] */ +#define WM8995_FLL2_FRC_NCO_VAL_WIDTH 6 /* FLL2_FRC_NCO_VAL - [12:7] */ +#define WM8995_FLL2_FRC_NCO 0x0040 /* FLL2_FRC_NCO */ +#define WM8995_FLL2_FRC_NCO_MASK 0x0040 /* FLL2_FRC_NCO */ +#define WM8995_FLL2_FRC_NCO_SHIFT 6 /* FLL2_FRC_NCO */ +#define WM8995_FLL2_FRC_NCO_WIDTH 1 /* FLL2_FRC_NCO */ +#define WM8995_FLL2_REFCLK_DIV_MASK 0x0018 /* FLL2_REFCLK_DIV - [4:3] */ +#define WM8995_FLL2_REFCLK_DIV_SHIFT 3 /* FLL2_REFCLK_DIV - [4:3] */ +#define WM8995_FLL2_REFCLK_DIV_WIDTH 2 /* FLL2_REFCLK_DIV - [4:3] */ +#define WM8995_FLL2_REFCLK_SRC_MASK 0x0003 /* FLL2_REFCLK_SRC - [1:0] */ +#define WM8995_FLL2_REFCLK_SRC_SHIFT 0 /* FLL2_REFCLK_SRC - [1:0] */ +#define WM8995_FLL2_REFCLK_SRC_WIDTH 2 /* FLL2_REFCLK_SRC - [1:0] */ + +/* + * R768 (0x300) - AIF1 Control (1) + */ +#define WM8995_AIF1ADCL_SRC 0x8000 /* AIF1ADCL_SRC */ +#define WM8995_AIF1ADCL_SRC_MASK 0x8000 /* AIF1ADCL_SRC */ +#define WM8995_AIF1ADCL_SRC_SHIFT 15 /* AIF1ADCL_SRC */ +#define WM8995_AIF1ADCL_SRC_WIDTH 1 /* AIF1ADCL_SRC */ +#define WM8995_AIF1ADCR_SRC 0x4000 /* AIF1ADCR_SRC */ +#define WM8995_AIF1ADCR_SRC_MASK 0x4000 /* AIF1ADCR_SRC */ +#define WM8995_AIF1ADCR_SRC_SHIFT 14 /* AIF1ADCR_SRC */ +#define WM8995_AIF1ADCR_SRC_WIDTH 1 /* AIF1ADCR_SRC */ +#define WM8995_AIF1ADC_TDM 0x2000 /* AIF1ADC_TDM */ +#define WM8995_AIF1ADC_TDM_MASK 0x2000 /* AIF1ADC_TDM */ +#define WM8995_AIF1ADC_TDM_SHIFT 13 /* AIF1ADC_TDM */ +#define WM8995_AIF1ADC_TDM_WIDTH 1 /* AIF1ADC_TDM */ +#define WM8995_AIF1_BCLK_INV 0x0100 /* AIF1_BCLK_INV */ +#define WM8995_AIF1_BCLK_INV_MASK 0x0100 /* AIF1_BCLK_INV */ +#define WM8995_AIF1_BCLK_INV_SHIFT 8 /* AIF1_BCLK_INV */ +#define WM8995_AIF1_BCLK_INV_WIDTH 1 /* AIF1_BCLK_INV */ +#define WM8995_AIF1_LRCLK_INV 0x0080 /* AIF1_LRCLK_INV */ +#define WM8995_AIF1_LRCLK_INV_MASK 0x0080 /* AIF1_LRCLK_INV */ +#define WM8995_AIF1_LRCLK_INV_SHIFT 7 /* AIF1_LRCLK_INV */ +#define WM8995_AIF1_LRCLK_INV_WIDTH 1 /* AIF1_LRCLK_INV */ +#define WM8995_AIF1_WL_MASK 0x0060 /* AIF1_WL - [6:5] */ +#define WM8995_AIF1_WL_SHIFT 5 /* AIF1_WL - [6:5] */ +#define WM8995_AIF1_WL_WIDTH 2 /* AIF1_WL - [6:5] */ +#define WM8995_AIF1_FMT_MASK 0x0018 /* AIF1_FMT - [4:3] */ +#define WM8995_AIF1_FMT_SHIFT 3 /* AIF1_FMT - [4:3] */ +#define WM8995_AIF1_FMT_WIDTH 2 /* AIF1_FMT - [4:3] */ + +/* + * R769 (0x301) - AIF1 Control (2) + */ +#define WM8995_AIF1DACL_SRC 0x8000 /* AIF1DACL_SRC */ +#define WM8995_AIF1DACL_SRC_MASK 0x8000 /* AIF1DACL_SRC */ +#define WM8995_AIF1DACL_SRC_SHIFT 15 /* AIF1DACL_SRC */ +#define WM8995_AIF1DACL_SRC_WIDTH 1 /* AIF1DACL_SRC */ +#define WM8995_AIF1DACR_SRC 0x4000 /* AIF1DACR_SRC */ +#define WM8995_AIF1DACR_SRC_MASK 0x4000 /* AIF1DACR_SRC */ +#define WM8995_AIF1DACR_SRC_SHIFT 14 /* AIF1DACR_SRC */ +#define WM8995_AIF1DACR_SRC_WIDTH 1 /* AIF1DACR_SRC */ +#define WM8995_AIF1DAC_BOOST_MASK 0x0C00 /* AIF1DAC_BOOST - [11:10] */ +#define WM8995_AIF1DAC_BOOST_SHIFT 10 /* AIF1DAC_BOOST - [11:10] */ +#define WM8995_AIF1DAC_BOOST_WIDTH 2 /* AIF1DAC_BOOST - [11:10] */ +#define WM8995_AIF1DAC_COMP 0x0010 /* AIF1DAC_COMP */ +#define WM8995_AIF1DAC_COMP_MASK 0x0010 /* AIF1DAC_COMP */ +#define WM8995_AIF1DAC_COMP_SHIFT 4 /* AIF1DAC_COMP */ +#define WM8995_AIF1DAC_COMP_WIDTH 1 /* AIF1DAC_COMP */ +#define WM8995_AIF1DAC_COMPMODE 0x0008 /* AIF1DAC_COMPMODE */ +#define WM8995_AIF1DAC_COMPMODE_MASK 0x0008 /* AIF1DAC_COMPMODE */ +#define WM8995_AIF1DAC_COMPMODE_SHIFT 3 /* AIF1DAC_COMPMODE */ +#define WM8995_AIF1DAC_COMPMODE_WIDTH 1 /* AIF1DAC_COMPMODE */ +#define WM8995_AIF1ADC_COMP 0x0004 /* AIF1ADC_COMP */ +#define WM8995_AIF1ADC_COMP_MASK 0x0004 /* AIF1ADC_COMP */ +#define WM8995_AIF1ADC_COMP_SHIFT 2 /* AIF1ADC_COMP */ +#define WM8995_AIF1ADC_COMP_WIDTH 1 /* AIF1ADC_COMP */ +#define WM8995_AIF1ADC_COMPMODE 0x0002 /* AIF1ADC_COMPMODE */ +#define WM8995_AIF1ADC_COMPMODE_MASK 0x0002 /* AIF1ADC_COMPMODE */ +#define WM8995_AIF1ADC_COMPMODE_SHIFT 1 /* AIF1ADC_COMPMODE */ +#define WM8995_AIF1ADC_COMPMODE_WIDTH 1 /* AIF1ADC_COMPMODE */ +#define WM8995_AIF1_LOOPBACK 0x0001 /* AIF1_LOOPBACK */ +#define WM8995_AIF1_LOOPBACK_MASK 0x0001 /* AIF1_LOOPBACK */ +#define WM8995_AIF1_LOOPBACK_SHIFT 0 /* AIF1_LOOPBACK */ +#define WM8995_AIF1_LOOPBACK_WIDTH 1 /* AIF1_LOOPBACK */ + +/* + * R770 (0x302) - AIF1 Master/Slave + */ +#define WM8995_AIF1_TRI 0x8000 /* AIF1_TRI */ +#define WM8995_AIF1_TRI_MASK 0x8000 /* AIF1_TRI */ +#define WM8995_AIF1_TRI_SHIFT 15 /* AIF1_TRI */ +#define WM8995_AIF1_TRI_WIDTH 1 /* AIF1_TRI */ +#define WM8995_AIF1_MSTR 0x4000 /* AIF1_MSTR */ +#define WM8995_AIF1_MSTR_MASK 0x4000 /* AIF1_MSTR */ +#define WM8995_AIF1_MSTR_SHIFT 14 /* AIF1_MSTR */ +#define WM8995_AIF1_MSTR_WIDTH 1 /* AIF1_MSTR */ +#define WM8995_AIF1_CLK_FRC 0x2000 /* AIF1_CLK_FRC */ +#define WM8995_AIF1_CLK_FRC_MASK 0x2000 /* AIF1_CLK_FRC */ +#define WM8995_AIF1_CLK_FRC_SHIFT 13 /* AIF1_CLK_FRC */ +#define WM8995_AIF1_CLK_FRC_WIDTH 1 /* AIF1_CLK_FRC */ +#define WM8995_AIF1_LRCLK_FRC 0x1000 /* AIF1_LRCLK_FRC */ +#define WM8995_AIF1_LRCLK_FRC_MASK 0x1000 /* AIF1_LRCLK_FRC */ +#define WM8995_AIF1_LRCLK_FRC_SHIFT 12 /* AIF1_LRCLK_FRC */ +#define WM8995_AIF1_LRCLK_FRC_WIDTH 1 /* AIF1_LRCLK_FRC */ + +/* + * R771 (0x303) - AIF1 BCLK + */ +#define WM8995_AIF1_BCLK_DIV_MASK 0x00F0 /* AIF1_BCLK_DIV - [7:4] */ +#define WM8995_AIF1_BCLK_DIV_SHIFT 4 /* AIF1_BCLK_DIV - [7:4] */ +#define WM8995_AIF1_BCLK_DIV_WIDTH 4 /* AIF1_BCLK_DIV - [7:4] */ + +/* + * R772 (0x304) - AIF1ADC LRCLK + */ +#define WM8995_AIF1ADC_LRCLK_DIR 0x0800 /* AIF1ADC_LRCLK_DIR */ +#define WM8995_AIF1ADC_LRCLK_DIR_MASK 0x0800 /* AIF1ADC_LRCLK_DIR */ +#define WM8995_AIF1ADC_LRCLK_DIR_SHIFT 11 /* AIF1ADC_LRCLK_DIR */ +#define WM8995_AIF1ADC_LRCLK_DIR_WIDTH 1 /* AIF1ADC_LRCLK_DIR */ +#define WM8995_AIF1ADC_RATE_MASK 0x07FF /* AIF1ADC_RATE - [10:0] */ +#define WM8995_AIF1ADC_RATE_SHIFT 0 /* AIF1ADC_RATE - [10:0] */ +#define WM8995_AIF1ADC_RATE_WIDTH 11 /* AIF1ADC_RATE - [10:0] */ + +/* + * R773 (0x305) - AIF1DAC LRCLK + */ +#define WM8995_AIF1DAC_LRCLK_DIR 0x0800 /* AIF1DAC_LRCLK_DIR */ +#define WM8995_AIF1DAC_LRCLK_DIR_MASK 0x0800 /* AIF1DAC_LRCLK_DIR */ +#define WM8995_AIF1DAC_LRCLK_DIR_SHIFT 11 /* AIF1DAC_LRCLK_DIR */ +#define WM8995_AIF1DAC_LRCLK_DIR_WIDTH 1 /* AIF1DAC_LRCLK_DIR */ +#define WM8995_AIF1DAC_RATE_MASK 0x07FF /* AIF1DAC_RATE - [10:0] */ +#define WM8995_AIF1DAC_RATE_SHIFT 0 /* AIF1DAC_RATE - [10:0] */ +#define WM8995_AIF1DAC_RATE_WIDTH 11 /* AIF1DAC_RATE - [10:0] */ + +/* + * R774 (0x306) - AIF1DAC Data + */ +#define WM8995_AIF1DACL_DAT_INV 0x0002 /* AIF1DACL_DAT_INV */ +#define WM8995_AIF1DACL_DAT_INV_MASK 0x0002 /* AIF1DACL_DAT_INV */ +#define WM8995_AIF1DACL_DAT_INV_SHIFT 1 /* AIF1DACL_DAT_INV */ +#define WM8995_AIF1DACL_DAT_INV_WIDTH 1 /* AIF1DACL_DAT_INV */ +#define WM8995_AIF1DACR_DAT_INV 0x0001 /* AIF1DACR_DAT_INV */ +#define WM8995_AIF1DACR_DAT_INV_MASK 0x0001 /* AIF1DACR_DAT_INV */ +#define WM8995_AIF1DACR_DAT_INV_SHIFT 0 /* AIF1DACR_DAT_INV */ +#define WM8995_AIF1DACR_DAT_INV_WIDTH 1 /* AIF1DACR_DAT_INV */ + +/* + * R775 (0x307) - AIF1ADC Data + */ +#define WM8995_AIF1ADCL_DAT_INV 0x0002 /* AIF1ADCL_DAT_INV */ +#define WM8995_AIF1ADCL_DAT_INV_MASK 0x0002 /* AIF1ADCL_DAT_INV */ +#define WM8995_AIF1ADCL_DAT_INV_SHIFT 1 /* AIF1ADCL_DAT_INV */ +#define WM8995_AIF1ADCL_DAT_INV_WIDTH 1 /* AIF1ADCL_DAT_INV */ +#define WM8995_AIF1ADCR_DAT_INV 0x0001 /* AIF1ADCR_DAT_INV */ +#define WM8995_AIF1ADCR_DAT_INV_MASK 0x0001 /* AIF1ADCR_DAT_INV */ +#define WM8995_AIF1ADCR_DAT_INV_SHIFT 0 /* AIF1ADCR_DAT_INV */ +#define WM8995_AIF1ADCR_DAT_INV_WIDTH 1 /* AIF1ADCR_DAT_INV */ + +/* + * R784 (0x310) - AIF2 Control (1) + */ +#define WM8995_AIF2ADCL_SRC 0x8000 /* AIF2ADCL_SRC */ +#define WM8995_AIF2ADCL_SRC_MASK 0x8000 /* AIF2ADCL_SRC */ +#define WM8995_AIF2ADCL_SRC_SHIFT 15 /* AIF2ADCL_SRC */ +#define WM8995_AIF2ADCL_SRC_WIDTH 1 /* AIF2ADCL_SRC */ +#define WM8995_AIF2ADCR_SRC 0x4000 /* AIF2ADCR_SRC */ +#define WM8995_AIF2ADCR_SRC_MASK 0x4000 /* AIF2ADCR_SRC */ +#define WM8995_AIF2ADCR_SRC_SHIFT 14 /* AIF2ADCR_SRC */ +#define WM8995_AIF2ADCR_SRC_WIDTH 1 /* AIF2ADCR_SRC */ +#define WM8995_AIF2ADC_TDM 0x2000 /* AIF2ADC_TDM */ +#define WM8995_AIF2ADC_TDM_MASK 0x2000 /* AIF2ADC_TDM */ +#define WM8995_AIF2ADC_TDM_SHIFT 13 /* AIF2ADC_TDM */ +#define WM8995_AIF2ADC_TDM_WIDTH 1 /* AIF2ADC_TDM */ +#define WM8995_AIF2ADC_TDM_CHAN 0x1000 /* AIF2ADC_TDM_CHAN */ +#define WM8995_AIF2ADC_TDM_CHAN_MASK 0x1000 /* AIF2ADC_TDM_CHAN */ +#define WM8995_AIF2ADC_TDM_CHAN_SHIFT 12 /* AIF2ADC_TDM_CHAN */ +#define WM8995_AIF2ADC_TDM_CHAN_WIDTH 1 /* AIF2ADC_TDM_CHAN */ +#define WM8995_AIF2_BCLK_INV 0x0100 /* AIF2_BCLK_INV */ +#define WM8995_AIF2_BCLK_INV_MASK 0x0100 /* AIF2_BCLK_INV */ +#define WM8995_AIF2_BCLK_INV_SHIFT 8 /* AIF2_BCLK_INV */ +#define WM8995_AIF2_BCLK_INV_WIDTH 1 /* AIF2_BCLK_INV */ +#define WM8995_AIF2_LRCLK_INV 0x0080 /* AIF2_LRCLK_INV */ +#define WM8995_AIF2_LRCLK_INV_MASK 0x0080 /* AIF2_LRCLK_INV */ +#define WM8995_AIF2_LRCLK_INV_SHIFT 7 /* AIF2_LRCLK_INV */ +#define WM8995_AIF2_LRCLK_INV_WIDTH 1 /* AIF2_LRCLK_INV */ +#define WM8995_AIF2_WL_MASK 0x0060 /* AIF2_WL - [6:5] */ +#define WM8995_AIF2_WL_SHIFT 5 /* AIF2_WL - [6:5] */ +#define WM8995_AIF2_WL_WIDTH 2 /* AIF2_WL - [6:5] */ +#define WM8995_AIF2_FMT_MASK 0x0018 /* AIF2_FMT - [4:3] */ +#define WM8995_AIF2_FMT_SHIFT 3 /* AIF2_FMT - [4:3] */ +#define WM8995_AIF2_FMT_WIDTH 2 /* AIF2_FMT - [4:3] */ + +/* + * R785 (0x311) - AIF2 Control (2) + */ +#define WM8995_AIF2DACL_SRC 0x8000 /* AIF2DACL_SRC */ +#define WM8995_AIF2DACL_SRC_MASK 0x8000 /* AIF2DACL_SRC */ +#define WM8995_AIF2DACL_SRC_SHIFT 15 /* AIF2DACL_SRC */ +#define WM8995_AIF2DACL_SRC_WIDTH 1 /* AIF2DACL_SRC */ +#define WM8995_AIF2DACR_SRC 0x4000 /* AIF2DACR_SRC */ +#define WM8995_AIF2DACR_SRC_MASK 0x4000 /* AIF2DACR_SRC */ +#define WM8995_AIF2DACR_SRC_SHIFT 14 /* AIF2DACR_SRC */ +#define WM8995_AIF2DACR_SRC_WIDTH 1 /* AIF2DACR_SRC */ +#define WM8995_AIF2DAC_TDM 0x2000 /* AIF2DAC_TDM */ +#define WM8995_AIF2DAC_TDM_MASK 0x2000 /* AIF2DAC_TDM */ +#define WM8995_AIF2DAC_TDM_SHIFT 13 /* AIF2DAC_TDM */ +#define WM8995_AIF2DAC_TDM_WIDTH 1 /* AIF2DAC_TDM */ +#define WM8995_AIF2DAC_TDM_CHAN 0x1000 /* AIF2DAC_TDM_CHAN */ +#define WM8995_AIF2DAC_TDM_CHAN_MASK 0x1000 /* AIF2DAC_TDM_CHAN */ +#define WM8995_AIF2DAC_TDM_CHAN_SHIFT 12 /* AIF2DAC_TDM_CHAN */ +#define WM8995_AIF2DAC_TDM_CHAN_WIDTH 1 /* AIF2DAC_TDM_CHAN */ +#define WM8995_AIF2DAC_BOOST_MASK 0x0C00 /* AIF2DAC_BOOST - [11:10] */ +#define WM8995_AIF2DAC_BOOST_SHIFT 10 /* AIF2DAC_BOOST - [11:10] */ +#define WM8995_AIF2DAC_BOOST_WIDTH 2 /* AIF2DAC_BOOST - [11:10] */ +#define WM8995_AIF2DAC_COMP 0x0010 /* AIF2DAC_COMP */ +#define WM8995_AIF2DAC_COMP_MASK 0x0010 /* AIF2DAC_COMP */ +#define WM8995_AIF2DAC_COMP_SHIFT 4 /* AIF2DAC_COMP */ +#define WM8995_AIF2DAC_COMP_WIDTH 1 /* AIF2DAC_COMP */ +#define WM8995_AIF2DAC_COMPMODE 0x0008 /* AIF2DAC_COMPMODE */ +#define WM8995_AIF2DAC_COMPMODE_MASK 0x0008 /* AIF2DAC_COMPMODE */ +#define WM8995_AIF2DAC_COMPMODE_SHIFT 3 /* AIF2DAC_COMPMODE */ +#define WM8995_AIF2DAC_COMPMODE_WIDTH 1 /* AIF2DAC_COMPMODE */ +#define WM8995_AIF2ADC_COMP 0x0004 /* AIF2ADC_COMP */ +#define WM8995_AIF2ADC_COMP_MASK 0x0004 /* AIF2ADC_COMP */ +#define WM8995_AIF2ADC_COMP_SHIFT 2 /* AIF2ADC_COMP */ +#define WM8995_AIF2ADC_COMP_WIDTH 1 /* AIF2ADC_COMP */ +#define WM8995_AIF2ADC_COMPMODE 0x0002 /* AIF2ADC_COMPMODE */ +#define WM8995_AIF2ADC_COMPMODE_MASK 0x0002 /* AIF2ADC_COMPMODE */ +#define WM8995_AIF2ADC_COMPMODE_SHIFT 1 /* AIF2ADC_COMPMODE */ +#define WM8995_AIF2ADC_COMPMODE_WIDTH 1 /* AIF2ADC_COMPMODE */ +#define WM8995_AIF2_LOOPBACK 0x0001 /* AIF2_LOOPBACK */ +#define WM8995_AIF2_LOOPBACK_MASK 0x0001 /* AIF2_LOOPBACK */ +#define WM8995_AIF2_LOOPBACK_SHIFT 0 /* AIF2_LOOPBACK */ +#define WM8995_AIF2_LOOPBACK_WIDTH 1 /* AIF2_LOOPBACK */ + +/* + * R786 (0x312) - AIF2 Master/Slave + */ +#define WM8995_AIF2_TRI 0x8000 /* AIF2_TRI */ +#define WM8995_AIF2_TRI_MASK 0x8000 /* AIF2_TRI */ +#define WM8995_AIF2_TRI_SHIFT 15 /* AIF2_TRI */ +#define WM8995_AIF2_TRI_WIDTH 1 /* AIF2_TRI */ +#define WM8995_AIF2_MSTR 0x4000 /* AIF2_MSTR */ +#define WM8995_AIF2_MSTR_MASK 0x4000 /* AIF2_MSTR */ +#define WM8995_AIF2_MSTR_SHIFT 14 /* AIF2_MSTR */ +#define WM8995_AIF2_MSTR_WIDTH 1 /* AIF2_MSTR */ +#define WM8995_AIF2_CLK_FRC 0x2000 /* AIF2_CLK_FRC */ +#define WM8995_AIF2_CLK_FRC_MASK 0x2000 /* AIF2_CLK_FRC */ +#define WM8995_AIF2_CLK_FRC_SHIFT 13 /* AIF2_CLK_FRC */ +#define WM8995_AIF2_CLK_FRC_WIDTH 1 /* AIF2_CLK_FRC */ +#define WM8995_AIF2_LRCLK_FRC 0x1000 /* AIF2_LRCLK_FRC */ +#define WM8995_AIF2_LRCLK_FRC_MASK 0x1000 /* AIF2_LRCLK_FRC */ +#define WM8995_AIF2_LRCLK_FRC_SHIFT 12 /* AIF2_LRCLK_FRC */ +#define WM8995_AIF2_LRCLK_FRC_WIDTH 1 /* AIF2_LRCLK_FRC */ + +/* + * R787 (0x313) - AIF2 BCLK + */ +#define WM8995_AIF2_BCLK_DIV_MASK 0x00F0 /* AIF2_BCLK_DIV - [7:4] */ +#define WM8995_AIF2_BCLK_DIV_SHIFT 4 /* AIF2_BCLK_DIV - [7:4] */ +#define WM8995_AIF2_BCLK_DIV_WIDTH 4 /* AIF2_BCLK_DIV - [7:4] */ + +/* + * R788 (0x314) - AIF2ADC LRCLK + */ +#define WM8995_AIF2ADC_LRCLK_DIR 0x0800 /* AIF2ADC_LRCLK_DIR */ +#define WM8995_AIF2ADC_LRCLK_DIR_MASK 0x0800 /* AIF2ADC_LRCLK_DIR */ +#define WM8995_AIF2ADC_LRCLK_DIR_SHIFT 11 /* AIF2ADC_LRCLK_DIR */ +#define WM8995_AIF2ADC_LRCLK_DIR_WIDTH 1 /* AIF2ADC_LRCLK_DIR */ +#define WM8995_AIF2ADC_RATE_MASK 0x07FF /* AIF2ADC_RATE - [10:0] */ +#define WM8995_AIF2ADC_RATE_SHIFT 0 /* AIF2ADC_RATE - [10:0] */ +#define WM8995_AIF2ADC_RATE_WIDTH 11 /* AIF2ADC_RATE - [10:0] */ + +/* + * R789 (0x315) - AIF2DAC LRCLK + */ +#define WM8995_AIF2DAC_LRCLK_DIR 0x0800 /* AIF2DAC_LRCLK_DIR */ +#define WM8995_AIF2DAC_LRCLK_DIR_MASK 0x0800 /* AIF2DAC_LRCLK_DIR */ +#define WM8995_AIF2DAC_LRCLK_DIR_SHIFT 11 /* AIF2DAC_LRCLK_DIR */ +#define WM8995_AIF2DAC_LRCLK_DIR_WIDTH 1 /* AIF2DAC_LRCLK_DIR */ +#define WM8995_AIF2DAC_RATE_MASK 0x07FF /* AIF2DAC_RATE - [10:0] */ +#define WM8995_AIF2DAC_RATE_SHIFT 0 /* AIF2DAC_RATE - [10:0] */ +#define WM8995_AIF2DAC_RATE_WIDTH 11 /* AIF2DAC_RATE - [10:0] */ + +/* + * R790 (0x316) - AIF2DAC Data + */ +#define WM8995_AIF2DACL_DAT_INV 0x0002 /* AIF2DACL_DAT_INV */ +#define WM8995_AIF2DACL_DAT_INV_MASK 0x0002 /* AIF2DACL_DAT_INV */ +#define WM8995_AIF2DACL_DAT_INV_SHIFT 1 /* AIF2DACL_DAT_INV */ +#define WM8995_AIF2DACL_DAT_INV_WIDTH 1 /* AIF2DACL_DAT_INV */ +#define WM8995_AIF2DACR_DAT_INV 0x0001 /* AIF2DACR_DAT_INV */ +#define WM8995_AIF2DACR_DAT_INV_MASK 0x0001 /* AIF2DACR_DAT_INV */ +#define WM8995_AIF2DACR_DAT_INV_SHIFT 0 /* AIF2DACR_DAT_INV */ +#define WM8995_AIF2DACR_DAT_INV_WIDTH 1 /* AIF2DACR_DAT_INV */ + +/* + * R791 (0x317) - AIF2ADC Data + */ +#define WM8995_AIF2ADCL_DAT_INV 0x0002 /* AIF2ADCL_DAT_INV */ +#define WM8995_AIF2ADCL_DAT_INV_MASK 0x0002 /* AIF2ADCL_DAT_INV */ +#define WM8995_AIF2ADCL_DAT_INV_SHIFT 1 /* AIF2ADCL_DAT_INV */ +#define WM8995_AIF2ADCL_DAT_INV_WIDTH 1 /* AIF2ADCL_DAT_INV */ +#define WM8995_AIF2ADCR_DAT_INV 0x0001 /* AIF2ADCR_DAT_INV */ +#define WM8995_AIF2ADCR_DAT_INV_MASK 0x0001 /* AIF2ADCR_DAT_INV */ +#define WM8995_AIF2ADCR_DAT_INV_SHIFT 0 /* AIF2ADCR_DAT_INV */ +#define WM8995_AIF2ADCR_DAT_INV_WIDTH 1 /* AIF2ADCR_DAT_INV */ + +/* + * R1024 (0x400) - AIF1 ADC1 Left Volume + */ +#define WM8995_AIF1ADC1_VU 0x0100 /* AIF1ADC1_VU */ +#define WM8995_AIF1ADC1_VU_MASK 0x0100 /* AIF1ADC1_VU */ +#define WM8995_AIF1ADC1_VU_SHIFT 8 /* AIF1ADC1_VU */ +#define WM8995_AIF1ADC1_VU_WIDTH 1 /* AIF1ADC1_VU */ +#define WM8995_AIF1ADC1L_VOL_MASK 0x00FF /* AIF1ADC1L_VOL - [7:0] */ +#define WM8995_AIF1ADC1L_VOL_SHIFT 0 /* AIF1ADC1L_VOL - [7:0] */ +#define WM8995_AIF1ADC1L_VOL_WIDTH 8 /* AIF1ADC1L_VOL - [7:0] */ + +/* + * R1025 (0x401) - AIF1 ADC1 Right Volume + */ +#define WM8995_AIF1ADC1_VU 0x0100 /* AIF1ADC1_VU */ +#define WM8995_AIF1ADC1_VU_MASK 0x0100 /* AIF1ADC1_VU */ +#define WM8995_AIF1ADC1_VU_SHIFT 8 /* AIF1ADC1_VU */ +#define WM8995_AIF1ADC1_VU_WIDTH 1 /* AIF1ADC1_VU */ +#define WM8995_AIF1ADC1R_VOL_MASK 0x00FF /* AIF1ADC1R_VOL - [7:0] */ +#define WM8995_AIF1ADC1R_VOL_SHIFT 0 /* AIF1ADC1R_VOL - [7:0] */ +#define WM8995_AIF1ADC1R_VOL_WIDTH 8 /* AIF1ADC1R_VOL - [7:0] */ + +/* + * R1026 (0x402) - AIF1 DAC1 Left Volume + */ +#define WM8995_AIF1DAC1_VU 0x0100 /* AIF1DAC1_VU */ +#define WM8995_AIF1DAC1_VU_MASK 0x0100 /* AIF1DAC1_VU */ +#define WM8995_AIF1DAC1_VU_SHIFT 8 /* AIF1DAC1_VU */ +#define WM8995_AIF1DAC1_VU_WIDTH 1 /* AIF1DAC1_VU */ +#define WM8995_AIF1DAC1L_VOL_MASK 0x00FF /* AIF1DAC1L_VOL - [7:0] */ +#define WM8995_AIF1DAC1L_VOL_SHIFT 0 /* AIF1DAC1L_VOL - [7:0] */ +#define WM8995_AIF1DAC1L_VOL_WIDTH 8 /* AIF1DAC1L_VOL - [7:0] */ + +/* + * R1027 (0x403) - AIF1 DAC1 Right Volume + */ +#define WM8995_AIF1DAC1_VU 0x0100 /* AIF1DAC1_VU */ +#define WM8995_AIF1DAC1_VU_MASK 0x0100 /* AIF1DAC1_VU */ +#define WM8995_AIF1DAC1_VU_SHIFT 8 /* AIF1DAC1_VU */ +#define WM8995_AIF1DAC1_VU_WIDTH 1 /* AIF1DAC1_VU */ +#define WM8995_AIF1DAC1R_VOL_MASK 0x00FF /* AIF1DAC1R_VOL - [7:0] */ +#define WM8995_AIF1DAC1R_VOL_SHIFT 0 /* AIF1DAC1R_VOL - [7:0] */ +#define WM8995_AIF1DAC1R_VOL_WIDTH 8 /* AIF1DAC1R_VOL - [7:0] */ + +/* + * R1028 (0x404) - AIF1 ADC2 Left Volume + */ +#define WM8995_AIF1ADC2_VU 0x0100 /* AIF1ADC2_VU */ +#define WM8995_AIF1ADC2_VU_MASK 0x0100 /* AIF1ADC2_VU */ +#define WM8995_AIF1ADC2_VU_SHIFT 8 /* AIF1ADC2_VU */ +#define WM8995_AIF1ADC2_VU_WIDTH 1 /* AIF1ADC2_VU */ +#define WM8995_AIF1ADC2L_VOL_MASK 0x00FF /* AIF1ADC2L_VOL - [7:0] */ +#define WM8995_AIF1ADC2L_VOL_SHIFT 0 /* AIF1ADC2L_VOL - [7:0] */ +#define WM8995_AIF1ADC2L_VOL_WIDTH 8 /* AIF1ADC2L_VOL - [7:0] */ + +/* + * R1029 (0x405) - AIF1 ADC2 Right Volume + */ +#define WM8995_AIF1ADC2_VU 0x0100 /* AIF1ADC2_VU */ +#define WM8995_AIF1ADC2_VU_MASK 0x0100 /* AIF1ADC2_VU */ +#define WM8995_AIF1ADC2_VU_SHIFT 8 /* AIF1ADC2_VU */ +#define WM8995_AIF1ADC2_VU_WIDTH 1 /* AIF1ADC2_VU */ +#define WM8995_AIF1ADC2R_VOL_MASK 0x00FF /* AIF1ADC2R_VOL - [7:0] */ +#define WM8995_AIF1ADC2R_VOL_SHIFT 0 /* AIF1ADC2R_VOL - [7:0] */ +#define WM8995_AIF1ADC2R_VOL_WIDTH 8 /* AIF1ADC2R_VOL - [7:0] */ + +/* + * R1030 (0x406) - AIF1 DAC2 Left Volume + */ +#define WM8995_AIF1DAC2_VU 0x0100 /* AIF1DAC2_VU */ +#define WM8995_AIF1DAC2_VU_MASK 0x0100 /* AIF1DAC2_VU */ +#define WM8995_AIF1DAC2_VU_SHIFT 8 /* AIF1DAC2_VU */ +#define WM8995_AIF1DAC2_VU_WIDTH 1 /* AIF1DAC2_VU */ +#define WM8995_AIF1DAC2L_VOL_MASK 0x00FF /* AIF1DAC2L_VOL - [7:0] */ +#define WM8995_AIF1DAC2L_VOL_SHIFT 0 /* AIF1DAC2L_VOL - [7:0] */ +#define WM8995_AIF1DAC2L_VOL_WIDTH 8 /* AIF1DAC2L_VOL - [7:0] */ + +/* + * R1031 (0x407) - AIF1 DAC2 Right Volume + */ +#define WM8995_AIF1DAC2_VU 0x0100 /* AIF1DAC2_VU */ +#define WM8995_AIF1DAC2_VU_MASK 0x0100 /* AIF1DAC2_VU */ +#define WM8995_AIF1DAC2_VU_SHIFT 8 /* AIF1DAC2_VU */ +#define WM8995_AIF1DAC2_VU_WIDTH 1 /* AIF1DAC2_VU */ +#define WM8995_AIF1DAC2R_VOL_MASK 0x00FF /* AIF1DAC2R_VOL - [7:0] */ +#define WM8995_AIF1DAC2R_VOL_SHIFT 0 /* AIF1DAC2R_VOL - [7:0] */ +#define WM8995_AIF1DAC2R_VOL_WIDTH 8 /* AIF1DAC2R_VOL - [7:0] */ + +/* + * R1040 (0x410) - AIF1 ADC1 Filters + */ +#define WM8995_AIF1ADC_4FS 0x8000 /* AIF1ADC_4FS */ +#define WM8995_AIF1ADC_4FS_MASK 0x8000 /* AIF1ADC_4FS */ +#define WM8995_AIF1ADC_4FS_SHIFT 15 /* AIF1ADC_4FS */ +#define WM8995_AIF1ADC_4FS_WIDTH 1 /* AIF1ADC_4FS */ +#define WM8995_AIF1ADC1L_HPF 0x1000 /* AIF1ADC1L_HPF */ +#define WM8995_AIF1ADC1L_HPF_MASK 0x1000 /* AIF1ADC1L_HPF */ +#define WM8995_AIF1ADC1L_HPF_SHIFT 12 /* AIF1ADC1L_HPF */ +#define WM8995_AIF1ADC1L_HPF_WIDTH 1 /* AIF1ADC1L_HPF */ +#define WM8995_AIF1ADC1R_HPF 0x0800 /* AIF1ADC1R_HPF */ +#define WM8995_AIF1ADC1R_HPF_MASK 0x0800 /* AIF1ADC1R_HPF */ +#define WM8995_AIF1ADC1R_HPF_SHIFT 11 /* AIF1ADC1R_HPF */ +#define WM8995_AIF1ADC1R_HPF_WIDTH 1 /* AIF1ADC1R_HPF */ +#define WM8995_AIF1ADC1_HPF_MODE 0x0008 /* AIF1ADC1_HPF_MODE */ +#define WM8995_AIF1ADC1_HPF_MODE_MASK 0x0008 /* AIF1ADC1_HPF_MODE */ +#define WM8995_AIF1ADC1_HPF_MODE_SHIFT 3 /* AIF1ADC1_HPF_MODE */ +#define WM8995_AIF1ADC1_HPF_MODE_WIDTH 1 /* AIF1ADC1_HPF_MODE */ +#define WM8995_AIF1ADC1_HPF_CUT_MASK 0x0007 /* AIF1ADC1_HPF_CUT - [2:0] */ +#define WM8995_AIF1ADC1_HPF_CUT_SHIFT 0 /* AIF1ADC1_HPF_CUT - [2:0] */ +#define WM8995_AIF1ADC1_HPF_CUT_WIDTH 3 /* AIF1ADC1_HPF_CUT - [2:0] */ + +/* + * R1041 (0x411) - AIF1 ADC2 Filters + */ +#define WM8995_AIF1ADC2L_HPF 0x1000 /* AIF1ADC2L_HPF */ +#define WM8995_AIF1ADC2L_HPF_MASK 0x1000 /* AIF1ADC2L_HPF */ +#define WM8995_AIF1ADC2L_HPF_SHIFT 12 /* AIF1ADC2L_HPF */ +#define WM8995_AIF1ADC2L_HPF_WIDTH 1 /* AIF1ADC2L_HPF */ +#define WM8995_AIF1ADC2R_HPF 0x0800 /* AIF1ADC2R_HPF */ +#define WM8995_AIF1ADC2R_HPF_MASK 0x0800 /* AIF1ADC2R_HPF */ +#define WM8995_AIF1ADC2R_HPF_SHIFT 11 /* AIF1ADC2R_HPF */ +#define WM8995_AIF1ADC2R_HPF_WIDTH 1 /* AIF1ADC2R_HPF */ +#define WM8995_AIF1ADC2_HPF_MODE 0x0008 /* AIF1ADC2_HPF_MODE */ +#define WM8995_AIF1ADC2_HPF_MODE_MASK 0x0008 /* AIF1ADC2_HPF_MODE */ +#define WM8995_AIF1ADC2_HPF_MODE_SHIFT 3 /* AIF1ADC2_HPF_MODE */ +#define WM8995_AIF1ADC2_HPF_MODE_WIDTH 1 /* AIF1ADC2_HPF_MODE */ +#define WM8995_AIF1ADC2_HPF_CUT_MASK 0x0007 /* AIF1ADC2_HPF_CUT - [2:0] */ +#define WM8995_AIF1ADC2_HPF_CUT_SHIFT 0 /* AIF1ADC2_HPF_CUT - [2:0] */ +#define WM8995_AIF1ADC2_HPF_CUT_WIDTH 3 /* AIF1ADC2_HPF_CUT - [2:0] */ + +/* + * R1056 (0x420) - AIF1 DAC1 Filters (1) + */ +#define WM8995_AIF1DAC1_MUTE 0x0200 /* AIF1DAC1_MUTE */ +#define WM8995_AIF1DAC1_MUTE_MASK 0x0200 /* AIF1DAC1_MUTE */ +#define WM8995_AIF1DAC1_MUTE_SHIFT 9 /* AIF1DAC1_MUTE */ +#define WM8995_AIF1DAC1_MUTE_WIDTH 1 /* AIF1DAC1_MUTE */ +#define WM8995_AIF1DAC1_MONO 0x0080 /* AIF1DAC1_MONO */ +#define WM8995_AIF1DAC1_MONO_MASK 0x0080 /* AIF1DAC1_MONO */ +#define WM8995_AIF1DAC1_MONO_SHIFT 7 /* AIF1DAC1_MONO */ +#define WM8995_AIF1DAC1_MONO_WIDTH 1 /* AIF1DAC1_MONO */ +#define WM8995_AIF1DAC1_MUTERATE 0x0020 /* AIF1DAC1_MUTERATE */ +#define WM8995_AIF1DAC1_MUTERATE_MASK 0x0020 /* AIF1DAC1_MUTERATE */ +#define WM8995_AIF1DAC1_MUTERATE_SHIFT 5 /* AIF1DAC1_MUTERATE */ +#define WM8995_AIF1DAC1_MUTERATE_WIDTH 1 /* AIF1DAC1_MUTERATE */ +#define WM8995_AIF1DAC1_UNMUTE_RAMP 0x0010 /* AIF1DAC1_UNMUTE_RAMP */ +#define WM8995_AIF1DAC1_UNMUTE_RAMP_MASK 0x0010 /* AIF1DAC1_UNMUTE_RAMP */ +#define WM8995_AIF1DAC1_UNMUTE_RAMP_SHIFT 4 /* AIF1DAC1_UNMUTE_RAMP */ +#define WM8995_AIF1DAC1_UNMUTE_RAMP_WIDTH 1 /* AIF1DAC1_UNMUTE_RAMP */ +#define WM8995_AIF1DAC1_DEEMP_MASK 0x0006 /* AIF1DAC1_DEEMP - [2:1] */ +#define WM8995_AIF1DAC1_DEEMP_SHIFT 1 /* AIF1DAC1_DEEMP - [2:1] */ +#define WM8995_AIF1DAC1_DEEMP_WIDTH 2 /* AIF1DAC1_DEEMP - [2:1] */ + +/* + * R1057 (0x421) - AIF1 DAC1 Filters (2) + */ +#define WM8995_AIF1DAC1_3D_GAIN_MASK 0x3E00 /* AIF1DAC1_3D_GAIN - [13:9] */ +#define WM8995_AIF1DAC1_3D_GAIN_SHIFT 9 /* AIF1DAC1_3D_GAIN - [13:9] */ +#define WM8995_AIF1DAC1_3D_GAIN_WIDTH 5 /* AIF1DAC1_3D_GAIN - [13:9] */ +#define WM8995_AIF1DAC1_3D_ENA 0x0100 /* AIF1DAC1_3D_ENA */ +#define WM8995_AIF1DAC1_3D_ENA_MASK 0x0100 /* AIF1DAC1_3D_ENA */ +#define WM8995_AIF1DAC1_3D_ENA_SHIFT 8 /* AIF1DAC1_3D_ENA */ +#define WM8995_AIF1DAC1_3D_ENA_WIDTH 1 /* AIF1DAC1_3D_ENA */ + +/* + * R1058 (0x422) - AIF1 DAC2 Filters (1) + */ +#define WM8995_AIF1DAC2_MUTE 0x0200 /* AIF1DAC2_MUTE */ +#define WM8995_AIF1DAC2_MUTE_MASK 0x0200 /* AIF1DAC2_MUTE */ +#define WM8995_AIF1DAC2_MUTE_SHIFT 9 /* AIF1DAC2_MUTE */ +#define WM8995_AIF1DAC2_MUTE_WIDTH 1 /* AIF1DAC2_MUTE */ +#define WM8995_AIF1DAC2_MONO 0x0080 /* AIF1DAC2_MONO */ +#define WM8995_AIF1DAC2_MONO_MASK 0x0080 /* AIF1DAC2_MONO */ +#define WM8995_AIF1DAC2_MONO_SHIFT 7 /* AIF1DAC2_MONO */ +#define WM8995_AIF1DAC2_MONO_WIDTH 1 /* AIF1DAC2_MONO */ +#define WM8995_AIF1DAC2_MUTERATE 0x0020 /* AIF1DAC2_MUTERATE */ +#define WM8995_AIF1DAC2_MUTERATE_MASK 0x0020 /* AIF1DAC2_MUTERATE */ +#define WM8995_AIF1DAC2_MUTERATE_SHIFT 5 /* AIF1DAC2_MUTERATE */ +#define WM8995_AIF1DAC2_MUTERATE_WIDTH 1 /* AIF1DAC2_MUTERATE */ +#define WM8995_AIF1DAC2_UNMUTE_RAMP 0x0010 /* AIF1DAC2_UNMUTE_RAMP */ +#define WM8995_AIF1DAC2_UNMUTE_RAMP_MASK 0x0010 /* AIF1DAC2_UNMUTE_RAMP */ +#define WM8995_AIF1DAC2_UNMUTE_RAMP_SHIFT 4 /* AIF1DAC2_UNMUTE_RAMP */ +#define WM8995_AIF1DAC2_UNMUTE_RAMP_WIDTH 1 /* AIF1DAC2_UNMUTE_RAMP */ +#define WM8995_AIF1DAC2_DEEMP_MASK 0x0006 /* AIF1DAC2_DEEMP - [2:1] */ +#define WM8995_AIF1DAC2_DEEMP_SHIFT 1 /* AIF1DAC2_DEEMP - [2:1] */ +#define WM8995_AIF1DAC2_DEEMP_WIDTH 2 /* AIF1DAC2_DEEMP - [2:1] */ + +/* + * R1059 (0x423) - AIF1 DAC2 Filters (2) + */ +#define WM8995_AIF1DAC2_3D_GAIN_MASK 0x3E00 /* AIF1DAC2_3D_GAIN - [13:9] */ +#define WM8995_AIF1DAC2_3D_GAIN_SHIFT 9 /* AIF1DAC2_3D_GAIN - [13:9] */ +#define WM8995_AIF1DAC2_3D_GAIN_WIDTH 5 /* AIF1DAC2_3D_GAIN - [13:9] */ +#define WM8995_AIF1DAC2_3D_ENA 0x0100 /* AIF1DAC2_3D_ENA */ +#define WM8995_AIF1DAC2_3D_ENA_MASK 0x0100 /* AIF1DAC2_3D_ENA */ +#define WM8995_AIF1DAC2_3D_ENA_SHIFT 8 /* AIF1DAC2_3D_ENA */ +#define WM8995_AIF1DAC2_3D_ENA_WIDTH 1 /* AIF1DAC2_3D_ENA */ + +/* + * R1088 (0x440) - AIF1 DRC1 (1) + */ +#define WM8995_AIF1DRC1_SIG_DET_RMS_MASK 0xF800 /* AIF1DRC1_SIG_DET_RMS - [15:11] */ +#define WM8995_AIF1DRC1_SIG_DET_RMS_SHIFT 11 /* AIF1DRC1_SIG_DET_RMS - [15:11] */ +#define WM8995_AIF1DRC1_SIG_DET_RMS_WIDTH 5 /* AIF1DRC1_SIG_DET_RMS - [15:11] */ +#define WM8995_AIF1DRC1_SIG_DET_PK_MASK 0x0600 /* AIF1DRC1_SIG_DET_PK - [10:9] */ +#define WM8995_AIF1DRC1_SIG_DET_PK_SHIFT 9 /* AIF1DRC1_SIG_DET_PK - [10:9] */ +#define WM8995_AIF1DRC1_SIG_DET_PK_WIDTH 2 /* AIF1DRC1_SIG_DET_PK - [10:9] */ +#define WM8995_AIF1DRC1_NG_ENA 0x0100 /* AIF1DRC1_NG_ENA */ +#define WM8995_AIF1DRC1_NG_ENA_MASK 0x0100 /* AIF1DRC1_NG_ENA */ +#define WM8995_AIF1DRC1_NG_ENA_SHIFT 8 /* AIF1DRC1_NG_ENA */ +#define WM8995_AIF1DRC1_NG_ENA_WIDTH 1 /* AIF1DRC1_NG_ENA */ +#define WM8995_AIF1DRC1_SIG_DET_MODE 0x0080 /* AIF1DRC1_SIG_DET_MODE */ +#define WM8995_AIF1DRC1_SIG_DET_MODE_MASK 0x0080 /* AIF1DRC1_SIG_DET_MODE */ +#define WM8995_AIF1DRC1_SIG_DET_MODE_SHIFT 7 /* AIF1DRC1_SIG_DET_MODE */ +#define WM8995_AIF1DRC1_SIG_DET_MODE_WIDTH 1 /* AIF1DRC1_SIG_DET_MODE */ +#define WM8995_AIF1DRC1_SIG_DET 0x0040 /* AIF1DRC1_SIG_DET */ +#define WM8995_AIF1DRC1_SIG_DET_MASK 0x0040 /* AIF1DRC1_SIG_DET */ +#define WM8995_AIF1DRC1_SIG_DET_SHIFT 6 /* AIF1DRC1_SIG_DET */ +#define WM8995_AIF1DRC1_SIG_DET_WIDTH 1 /* AIF1DRC1_SIG_DET */ +#define WM8995_AIF1DRC1_KNEE2_OP_ENA 0x0020 /* AIF1DRC1_KNEE2_OP_ENA */ +#define WM8995_AIF1DRC1_KNEE2_OP_ENA_MASK 0x0020 /* AIF1DRC1_KNEE2_OP_ENA */ +#define WM8995_AIF1DRC1_KNEE2_OP_ENA_SHIFT 5 /* AIF1DRC1_KNEE2_OP_ENA */ +#define WM8995_AIF1DRC1_KNEE2_OP_ENA_WIDTH 1 /* AIF1DRC1_KNEE2_OP_ENA */ +#define WM8995_AIF1DRC1_QR 0x0010 /* AIF1DRC1_QR */ +#define WM8995_AIF1DRC1_QR_MASK 0x0010 /* AIF1DRC1_QR */ +#define WM8995_AIF1DRC1_QR_SHIFT 4 /* AIF1DRC1_QR */ +#define WM8995_AIF1DRC1_QR_WIDTH 1 /* AIF1DRC1_QR */ +#define WM8995_AIF1DRC1_ANTICLIP 0x0008 /* AIF1DRC1_ANTICLIP */ +#define WM8995_AIF1DRC1_ANTICLIP_MASK 0x0008 /* AIF1DRC1_ANTICLIP */ +#define WM8995_AIF1DRC1_ANTICLIP_SHIFT 3 /* AIF1DRC1_ANTICLIP */ +#define WM8995_AIF1DRC1_ANTICLIP_WIDTH 1 /* AIF1DRC1_ANTICLIP */ +#define WM8995_AIF1DAC1_DRC_ENA 0x0004 /* AIF1DAC1_DRC_ENA */ +#define WM8995_AIF1DAC1_DRC_ENA_MASK 0x0004 /* AIF1DAC1_DRC_ENA */ +#define WM8995_AIF1DAC1_DRC_ENA_SHIFT 2 /* AIF1DAC1_DRC_ENA */ +#define WM8995_AIF1DAC1_DRC_ENA_WIDTH 1 /* AIF1DAC1_DRC_ENA */ +#define WM8995_AIF1ADC1L_DRC_ENA 0x0002 /* AIF1ADC1L_DRC_ENA */ +#define WM8995_AIF1ADC1L_DRC_ENA_MASK 0x0002 /* AIF1ADC1L_DRC_ENA */ +#define WM8995_AIF1ADC1L_DRC_ENA_SHIFT 1 /* AIF1ADC1L_DRC_ENA */ +#define WM8995_AIF1ADC1L_DRC_ENA_WIDTH 1 /* AIF1ADC1L_DRC_ENA */ +#define WM8995_AIF1ADC1R_DRC_ENA 0x0001 /* AIF1ADC1R_DRC_ENA */ +#define WM8995_AIF1ADC1R_DRC_ENA_MASK 0x0001 /* AIF1ADC1R_DRC_ENA */ +#define WM8995_AIF1ADC1R_DRC_ENA_SHIFT 0 /* AIF1ADC1R_DRC_ENA */ +#define WM8995_AIF1ADC1R_DRC_ENA_WIDTH 1 /* AIF1ADC1R_DRC_ENA */ + +/* + * R1089 (0x441) - AIF1 DRC1 (2) + */ +#define WM8995_AIF1DRC1_ATK_MASK 0x1E00 /* AIF1DRC1_ATK - [12:9] */ +#define WM8995_AIF1DRC1_ATK_SHIFT 9 /* AIF1DRC1_ATK - [12:9] */ +#define WM8995_AIF1DRC1_ATK_WIDTH 4 /* AIF1DRC1_ATK - [12:9] */ +#define WM8995_AIF1DRC1_DCY_MASK 0x01E0 /* AIF1DRC1_DCY - [8:5] */ +#define WM8995_AIF1DRC1_DCY_SHIFT 5 /* AIF1DRC1_DCY - [8:5] */ +#define WM8995_AIF1DRC1_DCY_WIDTH 4 /* AIF1DRC1_DCY - [8:5] */ +#define WM8995_AIF1DRC1_MINGAIN_MASK 0x001C /* AIF1DRC1_MINGAIN - [4:2] */ +#define WM8995_AIF1DRC1_MINGAIN_SHIFT 2 /* AIF1DRC1_MINGAIN - [4:2] */ +#define WM8995_AIF1DRC1_MINGAIN_WIDTH 3 /* AIF1DRC1_MINGAIN - [4:2] */ +#define WM8995_AIF1DRC1_MAXGAIN_MASK 0x0003 /* AIF1DRC1_MAXGAIN - [1:0] */ +#define WM8995_AIF1DRC1_MAXGAIN_SHIFT 0 /* AIF1DRC1_MAXGAIN - [1:0] */ +#define WM8995_AIF1DRC1_MAXGAIN_WIDTH 2 /* AIF1DRC1_MAXGAIN - [1:0] */ + +/* + * R1090 (0x442) - AIF1 DRC1 (3) + */ +#define WM8995_AIF1DRC1_NG_MINGAIN_MASK 0xF000 /* AIF1DRC1_NG_MINGAIN - [15:12] */ +#define WM8995_AIF1DRC1_NG_MINGAIN_SHIFT 12 /* AIF1DRC1_NG_MINGAIN - [15:12] */ +#define WM8995_AIF1DRC1_NG_MINGAIN_WIDTH 4 /* AIF1DRC1_NG_MINGAIN - [15:12] */ +#define WM8995_AIF1DRC1_NG_EXP_MASK 0x0C00 /* AIF1DRC1_NG_EXP - [11:10] */ +#define WM8995_AIF1DRC1_NG_EXP_SHIFT 10 /* AIF1DRC1_NG_EXP - [11:10] */ +#define WM8995_AIF1DRC1_NG_EXP_WIDTH 2 /* AIF1DRC1_NG_EXP - [11:10] */ +#define WM8995_AIF1DRC1_QR_THR_MASK 0x0300 /* AIF1DRC1_QR_THR - [9:8] */ +#define WM8995_AIF1DRC1_QR_THR_SHIFT 8 /* AIF1DRC1_QR_THR - [9:8] */ +#define WM8995_AIF1DRC1_QR_THR_WIDTH 2 /* AIF1DRC1_QR_THR - [9:8] */ +#define WM8995_AIF1DRC1_QR_DCY_MASK 0x00C0 /* AIF1DRC1_QR_DCY - [7:6] */ +#define WM8995_AIF1DRC1_QR_DCY_SHIFT 6 /* AIF1DRC1_QR_DCY - [7:6] */ +#define WM8995_AIF1DRC1_QR_DCY_WIDTH 2 /* AIF1DRC1_QR_DCY - [7:6] */ +#define WM8995_AIF1DRC1_HI_COMP_MASK 0x0038 /* AIF1DRC1_HI_COMP - [5:3] */ +#define WM8995_AIF1DRC1_HI_COMP_SHIFT 3 /* AIF1DRC1_HI_COMP - [5:3] */ +#define WM8995_AIF1DRC1_HI_COMP_WIDTH 3 /* AIF1DRC1_HI_COMP - [5:3] */ +#define WM8995_AIF1DRC1_LO_COMP_MASK 0x0007 /* AIF1DRC1_LO_COMP - [2:0] */ +#define WM8995_AIF1DRC1_LO_COMP_SHIFT 0 /* AIF1DRC1_LO_COMP - [2:0] */ +#define WM8995_AIF1DRC1_LO_COMP_WIDTH 3 /* AIF1DRC1_LO_COMP - [2:0] */ + +/* + * R1091 (0x443) - AIF1 DRC1 (4) + */ +#define WM8995_AIF1DRC1_KNEE_IP_MASK 0x07E0 /* AIF1DRC1_KNEE_IP - [10:5] */ +#define WM8995_AIF1DRC1_KNEE_IP_SHIFT 5 /* AIF1DRC1_KNEE_IP - [10:5] */ +#define WM8995_AIF1DRC1_KNEE_IP_WIDTH 6 /* AIF1DRC1_KNEE_IP - [10:5] */ +#define WM8995_AIF1DRC1_KNEE_OP_MASK 0x001F /* AIF1DRC1_KNEE_OP - [4:0] */ +#define WM8995_AIF1DRC1_KNEE_OP_SHIFT 0 /* AIF1DRC1_KNEE_OP - [4:0] */ +#define WM8995_AIF1DRC1_KNEE_OP_WIDTH 5 /* AIF1DRC1_KNEE_OP - [4:0] */ + +/* + * R1092 (0x444) - AIF1 DRC1 (5) + */ +#define WM8995_AIF1DRC1_KNEE2_IP_MASK 0x03E0 /* AIF1DRC1_KNEE2_IP - [9:5] */ +#define WM8995_AIF1DRC1_KNEE2_IP_SHIFT 5 /* AIF1DRC1_KNEE2_IP - [9:5] */ +#define WM8995_AIF1DRC1_KNEE2_IP_WIDTH 5 /* AIF1DRC1_KNEE2_IP - [9:5] */ +#define WM8995_AIF1DRC1_KNEE2_OP_MASK 0x001F /* AIF1DRC1_KNEE2_OP - [4:0] */ +#define WM8995_AIF1DRC1_KNEE2_OP_SHIFT 0 /* AIF1DRC1_KNEE2_OP - [4:0] */ +#define WM8995_AIF1DRC1_KNEE2_OP_WIDTH 5 /* AIF1DRC1_KNEE2_OP - [4:0] */ + +/* + * R1104 (0x450) - AIF1 DRC2 (1) + */ +#define WM8995_AIF1DRC2_SIG_DET_RMS_MASK 0xF800 /* AIF1DRC2_SIG_DET_RMS - [15:11] */ +#define WM8995_AIF1DRC2_SIG_DET_RMS_SHIFT 11 /* AIF1DRC2_SIG_DET_RMS - [15:11] */ +#define WM8995_AIF1DRC2_SIG_DET_RMS_WIDTH 5 /* AIF1DRC2_SIG_DET_RMS - [15:11] */ +#define WM8995_AIF1DRC2_SIG_DET_PK_MASK 0x0600 /* AIF1DRC2_SIG_DET_PK - [10:9] */ +#define WM8995_AIF1DRC2_SIG_DET_PK_SHIFT 9 /* AIF1DRC2_SIG_DET_PK - [10:9] */ +#define WM8995_AIF1DRC2_SIG_DET_PK_WIDTH 2 /* AIF1DRC2_SIG_DET_PK - [10:9] */ +#define WM8995_AIF1DRC2_NG_ENA 0x0100 /* AIF1DRC2_NG_ENA */ +#define WM8995_AIF1DRC2_NG_ENA_MASK 0x0100 /* AIF1DRC2_NG_ENA */ +#define WM8995_AIF1DRC2_NG_ENA_SHIFT 8 /* AIF1DRC2_NG_ENA */ +#define WM8995_AIF1DRC2_NG_ENA_WIDTH 1 /* AIF1DRC2_NG_ENA */ +#define WM8995_AIF1DRC2_SIG_DET_MODE 0x0080 /* AIF1DRC2_SIG_DET_MODE */ +#define WM8995_AIF1DRC2_SIG_DET_MODE_MASK 0x0080 /* AIF1DRC2_SIG_DET_MODE */ +#define WM8995_AIF1DRC2_SIG_DET_MODE_SHIFT 7 /* AIF1DRC2_SIG_DET_MODE */ +#define WM8995_AIF1DRC2_SIG_DET_MODE_WIDTH 1 /* AIF1DRC2_SIG_DET_MODE */ +#define WM8995_AIF1DRC2_SIG_DET 0x0040 /* AIF1DRC2_SIG_DET */ +#define WM8995_AIF1DRC2_SIG_DET_MASK 0x0040 /* AIF1DRC2_SIG_DET */ +#define WM8995_AIF1DRC2_SIG_DET_SHIFT 6 /* AIF1DRC2_SIG_DET */ +#define WM8995_AIF1DRC2_SIG_DET_WIDTH 1 /* AIF1DRC2_SIG_DET */ +#define WM8995_AIF1DRC2_KNEE2_OP_ENA 0x0020 /* AIF1DRC2_KNEE2_OP_ENA */ +#define WM8995_AIF1DRC2_KNEE2_OP_ENA_MASK 0x0020 /* AIF1DRC2_KNEE2_OP_ENA */ +#define WM8995_AIF1DRC2_KNEE2_OP_ENA_SHIFT 5 /* AIF1DRC2_KNEE2_OP_ENA */ +#define WM8995_AIF1DRC2_KNEE2_OP_ENA_WIDTH 1 /* AIF1DRC2_KNEE2_OP_ENA */ +#define WM8995_AIF1DRC2_QR 0x0010 /* AIF1DRC2_QR */ +#define WM8995_AIF1DRC2_QR_MASK 0x0010 /* AIF1DRC2_QR */ +#define WM8995_AIF1DRC2_QR_SHIFT 4 /* AIF1DRC2_QR */ +#define WM8995_AIF1DRC2_QR_WIDTH 1 /* AIF1DRC2_QR */ +#define WM8995_AIF1DRC2_ANTICLIP 0x0008 /* AIF1DRC2_ANTICLIP */ +#define WM8995_AIF1DRC2_ANTICLIP_MASK 0x0008 /* AIF1DRC2_ANTICLIP */ +#define WM8995_AIF1DRC2_ANTICLIP_SHIFT 3 /* AIF1DRC2_ANTICLIP */ +#define WM8995_AIF1DRC2_ANTICLIP_WIDTH 1 /* AIF1DRC2_ANTICLIP */ +#define WM8995_AIF1DAC2_DRC_ENA 0x0004 /* AIF1DAC2_DRC_ENA */ +#define WM8995_AIF1DAC2_DRC_ENA_MASK 0x0004 /* AIF1DAC2_DRC_ENA */ +#define WM8995_AIF1DAC2_DRC_ENA_SHIFT 2 /* AIF1DAC2_DRC_ENA */ +#define WM8995_AIF1DAC2_DRC_ENA_WIDTH 1 /* AIF1DAC2_DRC_ENA */ +#define WM8995_AIF1ADC2L_DRC_ENA 0x0002 /* AIF1ADC2L_DRC_ENA */ +#define WM8995_AIF1ADC2L_DRC_ENA_MASK 0x0002 /* AIF1ADC2L_DRC_ENA */ +#define WM8995_AIF1ADC2L_DRC_ENA_SHIFT 1 /* AIF1ADC2L_DRC_ENA */ +#define WM8995_AIF1ADC2L_DRC_ENA_WIDTH 1 /* AIF1ADC2L_DRC_ENA */ +#define WM8995_AIF1ADC2R_DRC_ENA 0x0001 /* AIF1ADC2R_DRC_ENA */ +#define WM8995_AIF1ADC2R_DRC_ENA_MASK 0x0001 /* AIF1ADC2R_DRC_ENA */ +#define WM8995_AIF1ADC2R_DRC_ENA_SHIFT 0 /* AIF1ADC2R_DRC_ENA */ +#define WM8995_AIF1ADC2R_DRC_ENA_WIDTH 1 /* AIF1ADC2R_DRC_ENA */ + +/* + * R1105 (0x451) - AIF1 DRC2 (2) + */ +#define WM8995_AIF1DRC2_ATK_MASK 0x1E00 /* AIF1DRC2_ATK - [12:9] */ +#define WM8995_AIF1DRC2_ATK_SHIFT 9 /* AIF1DRC2_ATK - [12:9] */ +#define WM8995_AIF1DRC2_ATK_WIDTH 4 /* AIF1DRC2_ATK - [12:9] */ +#define WM8995_AIF1DRC2_DCY_MASK 0x01E0 /* AIF1DRC2_DCY - [8:5] */ +#define WM8995_AIF1DRC2_DCY_SHIFT 5 /* AIF1DRC2_DCY - [8:5] */ +#define WM8995_AIF1DRC2_DCY_WIDTH 4 /* AIF1DRC2_DCY - [8:5] */ +#define WM8995_AIF1DRC2_MINGAIN_MASK 0x001C /* AIF1DRC2_MINGAIN - [4:2] */ +#define WM8995_AIF1DRC2_MINGAIN_SHIFT 2 /* AIF1DRC2_MINGAIN - [4:2] */ +#define WM8995_AIF1DRC2_MINGAIN_WIDTH 3 /* AIF1DRC2_MINGAIN - [4:2] */ +#define WM8995_AIF1DRC2_MAXGAIN_MASK 0x0003 /* AIF1DRC2_MAXGAIN - [1:0] */ +#define WM8995_AIF1DRC2_MAXGAIN_SHIFT 0 /* AIF1DRC2_MAXGAIN - [1:0] */ +#define WM8995_AIF1DRC2_MAXGAIN_WIDTH 2 /* AIF1DRC2_MAXGAIN - [1:0] */ + +/* + * R1106 (0x452) - AIF1 DRC2 (3) + */ +#define WM8995_AIF1DRC2_NG_MINGAIN_MASK 0xF000 /* AIF1DRC2_NG_MINGAIN - [15:12] */ +#define WM8995_AIF1DRC2_NG_MINGAIN_SHIFT 12 /* AIF1DRC2_NG_MINGAIN - [15:12] */ +#define WM8995_AIF1DRC2_NG_MINGAIN_WIDTH 4 /* AIF1DRC2_NG_MINGAIN - [15:12] */ +#define WM8995_AIF1DRC2_NG_EXP_MASK 0x0C00 /* AIF1DRC2_NG_EXP - [11:10] */ +#define WM8995_AIF1DRC2_NG_EXP_SHIFT 10 /* AIF1DRC2_NG_EXP - [11:10] */ +#define WM8995_AIF1DRC2_NG_EXP_WIDTH 2 /* AIF1DRC2_NG_EXP - [11:10] */ +#define WM8995_AIF1DRC2_QR_THR_MASK 0x0300 /* AIF1DRC2_QR_THR - [9:8] */ +#define WM8995_AIF1DRC2_QR_THR_SHIFT 8 /* AIF1DRC2_QR_THR - [9:8] */ +#define WM8995_AIF1DRC2_QR_THR_WIDTH 2 /* AIF1DRC2_QR_THR - [9:8] */ +#define WM8995_AIF1DRC2_QR_DCY_MASK 0x00C0 /* AIF1DRC2_QR_DCY - [7:6] */ +#define WM8995_AIF1DRC2_QR_DCY_SHIFT 6 /* AIF1DRC2_QR_DCY - [7:6] */ +#define WM8995_AIF1DRC2_QR_DCY_WIDTH 2 /* AIF1DRC2_QR_DCY - [7:6] */ +#define WM8995_AIF1DRC2_HI_COMP_MASK 0x0038 /* AIF1DRC2_HI_COMP - [5:3] */ +#define WM8995_AIF1DRC2_HI_COMP_SHIFT 3 /* AIF1DRC2_HI_COMP - [5:3] */ +#define WM8995_AIF1DRC2_HI_COMP_WIDTH 3 /* AIF1DRC2_HI_COMP - [5:3] */ +#define WM8995_AIF1DRC2_LO_COMP_MASK 0x0007 /* AIF1DRC2_LO_COMP - [2:0] */ +#define WM8995_AIF1DRC2_LO_COMP_SHIFT 0 /* AIF1DRC2_LO_COMP - [2:0] */ +#define WM8995_AIF1DRC2_LO_COMP_WIDTH 3 /* AIF1DRC2_LO_COMP - [2:0] */ + +/* + * R1107 (0x453) - AIF1 DRC2 (4) + */ +#define WM8995_AIF1DRC2_KNEE_IP_MASK 0x07E0 /* AIF1DRC2_KNEE_IP - [10:5] */ +#define WM8995_AIF1DRC2_KNEE_IP_SHIFT 5 /* AIF1DRC2_KNEE_IP - [10:5] */ +#define WM8995_AIF1DRC2_KNEE_IP_WIDTH 6 /* AIF1DRC2_KNEE_IP - [10:5] */ +#define WM8995_AIF1DRC2_KNEE_OP_MASK 0x001F /* AIF1DRC2_KNEE_OP - [4:0] */ +#define WM8995_AIF1DRC2_KNEE_OP_SHIFT 0 /* AIF1DRC2_KNEE_OP - [4:0] */ +#define WM8995_AIF1DRC2_KNEE_OP_WIDTH 5 /* AIF1DRC2_KNEE_OP - [4:0] */ + +/* + * R1108 (0x454) - AIF1 DRC2 (5) + */ +#define WM8995_AIF1DRC2_KNEE2_IP_MASK 0x03E0 /* AIF1DRC2_KNEE2_IP - [9:5] */ +#define WM8995_AIF1DRC2_KNEE2_IP_SHIFT 5 /* AIF1DRC2_KNEE2_IP - [9:5] */ +#define WM8995_AIF1DRC2_KNEE2_IP_WIDTH 5 /* AIF1DRC2_KNEE2_IP - [9:5] */ +#define WM8995_AIF1DRC2_KNEE2_OP_MASK 0x001F /* AIF1DRC2_KNEE2_OP - [4:0] */ +#define WM8995_AIF1DRC2_KNEE2_OP_SHIFT 0 /* AIF1DRC2_KNEE2_OP - [4:0] */ +#define WM8995_AIF1DRC2_KNEE2_OP_WIDTH 5 /* AIF1DRC2_KNEE2_OP - [4:0] */ + +/* + * R1152 (0x480) - AIF1 DAC1 EQ Gains (1) + */ +#define WM8995_AIF1DAC1_EQ_B1_GAIN_MASK 0xF800 /* AIF1DAC1_EQ_B1_GAIN - [15:11] */ +#define WM8995_AIF1DAC1_EQ_B1_GAIN_SHIFT 11 /* AIF1DAC1_EQ_B1_GAIN - [15:11] */ +#define WM8995_AIF1DAC1_EQ_B1_GAIN_WIDTH 5 /* AIF1DAC1_EQ_B1_GAIN - [15:11] */ +#define WM8995_AIF1DAC1_EQ_B2_GAIN_MASK 0x07C0 /* AIF1DAC1_EQ_B2_GAIN - [10:6] */ +#define WM8995_AIF1DAC1_EQ_B2_GAIN_SHIFT 6 /* AIF1DAC1_EQ_B2_GAIN - [10:6] */ +#define WM8995_AIF1DAC1_EQ_B2_GAIN_WIDTH 5 /* AIF1DAC1_EQ_B2_GAIN - [10:6] */ +#define WM8995_AIF1DAC1_EQ_B3_GAIN_MASK 0x003E /* AIF1DAC1_EQ_B3_GAIN - [5:1] */ +#define WM8995_AIF1DAC1_EQ_B3_GAIN_SHIFT 1 /* AIF1DAC1_EQ_B3_GAIN - [5:1] */ +#define WM8995_AIF1DAC1_EQ_B3_GAIN_WIDTH 5 /* AIF1DAC1_EQ_B3_GAIN - [5:1] */ +#define WM8995_AIF1DAC1_EQ_ENA 0x0001 /* AIF1DAC1_EQ_ENA */ +#define WM8995_AIF1DAC1_EQ_ENA_MASK 0x0001 /* AIF1DAC1_EQ_ENA */ +#define WM8995_AIF1DAC1_EQ_ENA_SHIFT 0 /* AIF1DAC1_EQ_ENA */ +#define WM8995_AIF1DAC1_EQ_ENA_WIDTH 1 /* AIF1DAC1_EQ_ENA */ + +/* + * R1153 (0x481) - AIF1 DAC1 EQ Gains (2) + */ +#define WM8995_AIF1DAC1_EQ_B4_GAIN_MASK 0xF800 /* AIF1DAC1_EQ_B4_GAIN - [15:11] */ +#define WM8995_AIF1DAC1_EQ_B4_GAIN_SHIFT 11 /* AIF1DAC1_EQ_B4_GAIN - [15:11] */ +#define WM8995_AIF1DAC1_EQ_B4_GAIN_WIDTH 5 /* AIF1DAC1_EQ_B4_GAIN - [15:11] */ +#define WM8995_AIF1DAC1_EQ_B5_GAIN_MASK 0x07C0 /* AIF1DAC1_EQ_B5_GAIN - [10:6] */ +#define WM8995_AIF1DAC1_EQ_B5_GAIN_SHIFT 6 /* AIF1DAC1_EQ_B5_GAIN - [10:6] */ +#define WM8995_AIF1DAC1_EQ_B5_GAIN_WIDTH 5 /* AIF1DAC1_EQ_B5_GAIN - [10:6] */ + +/* + * R1154 (0x482) - AIF1 DAC1 EQ Band 1 A + */ +#define WM8995_AIF1DAC1_EQ_B1_A_MASK 0xFFFF /* AIF1DAC1_EQ_B1_A - [15:0] */ +#define WM8995_AIF1DAC1_EQ_B1_A_SHIFT 0 /* AIF1DAC1_EQ_B1_A - [15:0] */ +#define WM8995_AIF1DAC1_EQ_B1_A_WIDTH 16 /* AIF1DAC1_EQ_B1_A - [15:0] */ + +/* + * R1155 (0x483) - AIF1 DAC1 EQ Band 1 B + */ +#define WM8995_AIF1DAC1_EQ_B1_B_MASK 0xFFFF /* AIF1DAC1_EQ_B1_B - [15:0] */ +#define WM8995_AIF1DAC1_EQ_B1_B_SHIFT 0 /* AIF1DAC1_EQ_B1_B - [15:0] */ +#define WM8995_AIF1DAC1_EQ_B1_B_WIDTH 16 /* AIF1DAC1_EQ_B1_B - [15:0] */ + +/* + * R1156 (0x484) - AIF1 DAC1 EQ Band 1 PG + */ +#define WM8995_AIF1DAC1_EQ_B1_PG_MASK 0xFFFF /* AIF1DAC1_EQ_B1_PG - [15:0] */ +#define WM8995_AIF1DAC1_EQ_B1_PG_SHIFT 0 /* AIF1DAC1_EQ_B1_PG - [15:0] */ +#define WM8995_AIF1DAC1_EQ_B1_PG_WIDTH 16 /* AIF1DAC1_EQ_B1_PG - [15:0] */ + +/* + * R1157 (0x485) - AIF1 DAC1 EQ Band 2 A + */ +#define WM8995_AIF1DAC1_EQ_B2_A_MASK 0xFFFF /* AIF1DAC1_EQ_B2_A - [15:0] */ +#define WM8995_AIF1DAC1_EQ_B2_A_SHIFT 0 /* AIF1DAC1_EQ_B2_A - [15:0] */ +#define WM8995_AIF1DAC1_EQ_B2_A_WIDTH 16 /* AIF1DAC1_EQ_B2_A - [15:0] */ + +/* + * R1158 (0x486) - AIF1 DAC1 EQ Band 2 B + */ +#define WM8995_AIF1DAC1_EQ_B2_B_MASK 0xFFFF /* AIF1DAC1_EQ_B2_B - [15:0] */ +#define WM8995_AIF1DAC1_EQ_B2_B_SHIFT 0 /* AIF1DAC1_EQ_B2_B - [15:0] */ +#define WM8995_AIF1DAC1_EQ_B2_B_WIDTH 16 /* AIF1DAC1_EQ_B2_B - [15:0] */ + +/* + * R1159 (0x487) - AIF1 DAC1 EQ Band 2 C + */ +#define WM8995_AIF1DAC1_EQ_B2_C_MASK 0xFFFF /* AIF1DAC1_EQ_B2_C - [15:0] */ +#define WM8995_AIF1DAC1_EQ_B2_C_SHIFT 0 /* AIF1DAC1_EQ_B2_C - [15:0] */ +#define WM8995_AIF1DAC1_EQ_B2_C_WIDTH 16 /* AIF1DAC1_EQ_B2_C - [15:0] */ + +/* + * R1160 (0x488) - AIF1 DAC1 EQ Band 2 PG + */ +#define WM8995_AIF1DAC1_EQ_B2_PG_MASK 0xFFFF /* AIF1DAC1_EQ_B2_PG - [15:0] */ +#define WM8995_AIF1DAC1_EQ_B2_PG_SHIFT 0 /* AIF1DAC1_EQ_B2_PG - [15:0] */ +#define WM8995_AIF1DAC1_EQ_B2_PG_WIDTH 16 /* AIF1DAC1_EQ_B2_PG - [15:0] */ + +/* + * R1161 (0x489) - AIF1 DAC1 EQ Band 3 A + */ +#define WM8995_AIF1DAC1_EQ_B3_A_MASK 0xFFFF /* AIF1DAC1_EQ_B3_A - [15:0] */ +#define WM8995_AIF1DAC1_EQ_B3_A_SHIFT 0 /* AIF1DAC1_EQ_B3_A - [15:0] */ +#define WM8995_AIF1DAC1_EQ_B3_A_WIDTH 16 /* AIF1DAC1_EQ_B3_A - [15:0] */ + +/* + * R1162 (0x48A) - AIF1 DAC1 EQ Band 3 B + */ +#define WM8995_AIF1DAC1_EQ_B3_B_MASK 0xFFFF /* AIF1DAC1_EQ_B3_B - [15:0] */ +#define WM8995_AIF1DAC1_EQ_B3_B_SHIFT 0 /* AIF1DAC1_EQ_B3_B - [15:0] */ +#define WM8995_AIF1DAC1_EQ_B3_B_WIDTH 16 /* AIF1DAC1_EQ_B3_B - [15:0] */ + +/* + * R1163 (0x48B) - AIF1 DAC1 EQ Band 3 C + */ +#define WM8995_AIF1DAC1_EQ_B3_C_MASK 0xFFFF /* AIF1DAC1_EQ_B3_C - [15:0] */ +#define WM8995_AIF1DAC1_EQ_B3_C_SHIFT 0 /* AIF1DAC1_EQ_B3_C - [15:0] */ +#define WM8995_AIF1DAC1_EQ_B3_C_WIDTH 16 /* AIF1DAC1_EQ_B3_C - [15:0] */ + +/* + * R1164 (0x48C) - AIF1 DAC1 EQ Band 3 PG + */ +#define WM8995_AIF1DAC1_EQ_B3_PG_MASK 0xFFFF /* AIF1DAC1_EQ_B3_PG - [15:0] */ +#define WM8995_AIF1DAC1_EQ_B3_PG_SHIFT 0 /* AIF1DAC1_EQ_B3_PG - [15:0] */ +#define WM8995_AIF1DAC1_EQ_B3_PG_WIDTH 16 /* AIF1DAC1_EQ_B3_PG - [15:0] */ + +/* + * R1165 (0x48D) - AIF1 DAC1 EQ Band 4 A + */ +#define WM8995_AIF1DAC1_EQ_B4_A_MASK 0xFFFF /* AIF1DAC1_EQ_B4_A - [15:0] */ +#define WM8995_AIF1DAC1_EQ_B4_A_SHIFT 0 /* AIF1DAC1_EQ_B4_A - [15:0] */ +#define WM8995_AIF1DAC1_EQ_B4_A_WIDTH 16 /* AIF1DAC1_EQ_B4_A - [15:0] */ + +/* + * R1166 (0x48E) - AIF1 DAC1 EQ Band 4 B + */ +#define WM8995_AIF1DAC1_EQ_B4_B_MASK 0xFFFF /* AIF1DAC1_EQ_B4_B - [15:0] */ +#define WM8995_AIF1DAC1_EQ_B4_B_SHIFT 0 /* AIF1DAC1_EQ_B4_B - [15:0] */ +#define WM8995_AIF1DAC1_EQ_B4_B_WIDTH 16 /* AIF1DAC1_EQ_B4_B - [15:0] */ + +/* + * R1167 (0x48F) - AIF1 DAC1 EQ Band 4 C + */ +#define WM8995_AIF1DAC1_EQ_B4_C_MASK 0xFFFF /* AIF1DAC1_EQ_B4_C - [15:0] */ +#define WM8995_AIF1DAC1_EQ_B4_C_SHIFT 0 /* AIF1DAC1_EQ_B4_C - [15:0] */ +#define WM8995_AIF1DAC1_EQ_B4_C_WIDTH 16 /* AIF1DAC1_EQ_B4_C - [15:0] */ + +/* + * R1168 (0x490) - AIF1 DAC1 EQ Band 4 PG + */ +#define WM8995_AIF1DAC1_EQ_B4_PG_MASK 0xFFFF /* AIF1DAC1_EQ_B4_PG - [15:0] */ +#define WM8995_AIF1DAC1_EQ_B4_PG_SHIFT 0 /* AIF1DAC1_EQ_B4_PG - [15:0] */ +#define WM8995_AIF1DAC1_EQ_B4_PG_WIDTH 16 /* AIF1DAC1_EQ_B4_PG - [15:0] */ + +/* + * R1169 (0x491) - AIF1 DAC1 EQ Band 5 A + */ +#define WM8995_AIF1DAC1_EQ_B5_A_MASK 0xFFFF /* AIF1DAC1_EQ_B5_A - [15:0] */ +#define WM8995_AIF1DAC1_EQ_B5_A_SHIFT 0 /* AIF1DAC1_EQ_B5_A - [15:0] */ +#define WM8995_AIF1DAC1_EQ_B5_A_WIDTH 16 /* AIF1DAC1_EQ_B5_A - [15:0] */ + +/* + * R1170 (0x492) - AIF1 DAC1 EQ Band 5 B + */ +#define WM8995_AIF1DAC1_EQ_B5_B_MASK 0xFFFF /* AIF1DAC1_EQ_B5_B - [15:0] */ +#define WM8995_AIF1DAC1_EQ_B5_B_SHIFT 0 /* AIF1DAC1_EQ_B5_B - [15:0] */ +#define WM8995_AIF1DAC1_EQ_B5_B_WIDTH 16 /* AIF1DAC1_EQ_B5_B - [15:0] */ + +/* + * R1171 (0x493) - AIF1 DAC1 EQ Band 5 PG + */ +#define WM8995_AIF1DAC1_EQ_B5_PG_MASK 0xFFFF /* AIF1DAC1_EQ_B5_PG - [15:0] */ +#define WM8995_AIF1DAC1_EQ_B5_PG_SHIFT 0 /* AIF1DAC1_EQ_B5_PG - [15:0] */ +#define WM8995_AIF1DAC1_EQ_B5_PG_WIDTH 16 /* AIF1DAC1_EQ_B5_PG - [15:0] */ + +/* + * R1184 (0x4A0) - AIF1 DAC2 EQ Gains (1) + */ +#define WM8995_AIF1DAC2_EQ_B1_GAIN_MASK 0xF800 /* AIF1DAC2_EQ_B1_GAIN - [15:11] */ +#define WM8995_AIF1DAC2_EQ_B1_GAIN_SHIFT 11 /* AIF1DAC2_EQ_B1_GAIN - [15:11] */ +#define WM8995_AIF1DAC2_EQ_B1_GAIN_WIDTH 5 /* AIF1DAC2_EQ_B1_GAIN - [15:11] */ +#define WM8995_AIF1DAC2_EQ_B2_GAIN_MASK 0x07C0 /* AIF1DAC2_EQ_B2_GAIN - [10:6] */ +#define WM8995_AIF1DAC2_EQ_B2_GAIN_SHIFT 6 /* AIF1DAC2_EQ_B2_GAIN - [10:6] */ +#define WM8995_AIF1DAC2_EQ_B2_GAIN_WIDTH 5 /* AIF1DAC2_EQ_B2_GAIN - [10:6] */ +#define WM8995_AIF1DAC2_EQ_B3_GAIN_MASK 0x003E /* AIF1DAC2_EQ_B3_GAIN - [5:1] */ +#define WM8995_AIF1DAC2_EQ_B3_GAIN_SHIFT 1 /* AIF1DAC2_EQ_B3_GAIN - [5:1] */ +#define WM8995_AIF1DAC2_EQ_B3_GAIN_WIDTH 5 /* AIF1DAC2_EQ_B3_GAIN - [5:1] */ +#define WM8995_AIF1DAC2_EQ_ENA 0x0001 /* AIF1DAC2_EQ_ENA */ +#define WM8995_AIF1DAC2_EQ_ENA_MASK 0x0001 /* AIF1DAC2_EQ_ENA */ +#define WM8995_AIF1DAC2_EQ_ENA_SHIFT 0 /* AIF1DAC2_EQ_ENA */ +#define WM8995_AIF1DAC2_EQ_ENA_WIDTH 1 /* AIF1DAC2_EQ_ENA */ + +/* + * R1185 (0x4A1) - AIF1 DAC2 EQ Gains (2) + */ +#define WM8995_AIF1DAC2_EQ_B4_GAIN_MASK 0xF800 /* AIF1DAC2_EQ_B4_GAIN - [15:11] */ +#define WM8995_AIF1DAC2_EQ_B4_GAIN_SHIFT 11 /* AIF1DAC2_EQ_B4_GAIN - [15:11] */ +#define WM8995_AIF1DAC2_EQ_B4_GAIN_WIDTH 5 /* AIF1DAC2_EQ_B4_GAIN - [15:11] */ +#define WM8995_AIF1DAC2_EQ_B5_GAIN_MASK 0x07C0 /* AIF1DAC2_EQ_B5_GAIN - [10:6] */ +#define WM8995_AIF1DAC2_EQ_B5_GAIN_SHIFT 6 /* AIF1DAC2_EQ_B5_GAIN - [10:6] */ +#define WM8995_AIF1DAC2_EQ_B5_GAIN_WIDTH 5 /* AIF1DAC2_EQ_B5_GAIN - [10:6] */ + +/* + * R1186 (0x4A2) - AIF1 DAC2 EQ Band 1 A + */ +#define WM8995_AIF1DAC2_EQ_B1_A_MASK 0xFFFF /* AIF1DAC2_EQ_B1_A - [15:0] */ +#define WM8995_AIF1DAC2_EQ_B1_A_SHIFT 0 /* AIF1DAC2_EQ_B1_A - [15:0] */ +#define WM8995_AIF1DAC2_EQ_B1_A_WIDTH 16 /* AIF1DAC2_EQ_B1_A - [15:0] */ + +/* + * R1187 (0x4A3) - AIF1 DAC2 EQ Band 1 B + */ +#define WM8995_AIF1DAC2_EQ_B1_B_MASK 0xFFFF /* AIF1DAC2_EQ_B1_B - [15:0] */ +#define WM8995_AIF1DAC2_EQ_B1_B_SHIFT 0 /* AIF1DAC2_EQ_B1_B - [15:0] */ +#define WM8995_AIF1DAC2_EQ_B1_B_WIDTH 16 /* AIF1DAC2_EQ_B1_B - [15:0] */ + +/* + * R1188 (0x4A4) - AIF1 DAC2 EQ Band 1 PG + */ +#define WM8995_AIF1DAC2_EQ_B1_PG_MASK 0xFFFF /* AIF1DAC2_EQ_B1_PG - [15:0] */ +#define WM8995_AIF1DAC2_EQ_B1_PG_SHIFT 0 /* AIF1DAC2_EQ_B1_PG - [15:0] */ +#define WM8995_AIF1DAC2_EQ_B1_PG_WIDTH 16 /* AIF1DAC2_EQ_B1_PG - [15:0] */ + +/* + * R1189 (0x4A5) - AIF1 DAC2 EQ Band 2 A + */ +#define WM8995_AIF1DAC2_EQ_B2_A_MASK 0xFFFF /* AIF1DAC2_EQ_B2_A - [15:0] */ +#define WM8995_AIF1DAC2_EQ_B2_A_SHIFT 0 /* AIF1DAC2_EQ_B2_A - [15:0] */ +#define WM8995_AIF1DAC2_EQ_B2_A_WIDTH 16 /* AIF1DAC2_EQ_B2_A - [15:0] */ + +/* + * R1190 (0x4A6) - AIF1 DAC2 EQ Band 2 B + */ +#define WM8995_AIF1DAC2_EQ_B2_B_MASK 0xFFFF /* AIF1DAC2_EQ_B2_B - [15:0] */ +#define WM8995_AIF1DAC2_EQ_B2_B_SHIFT 0 /* AIF1DAC2_EQ_B2_B - [15:0] */ +#define WM8995_AIF1DAC2_EQ_B2_B_WIDTH 16 /* AIF1DAC2_EQ_B2_B - [15:0] */ + +/* + * R1191 (0x4A7) - AIF1 DAC2 EQ Band 2 C + */ +#define WM8995_AIF1DAC2_EQ_B2_C_MASK 0xFFFF /* AIF1DAC2_EQ_B2_C - [15:0] */ +#define WM8995_AIF1DAC2_EQ_B2_C_SHIFT 0 /* AIF1DAC2_EQ_B2_C - [15:0] */ +#define WM8995_AIF1DAC2_EQ_B2_C_WIDTH 16 /* AIF1DAC2_EQ_B2_C - [15:0] */ + +/* + * R1192 (0x4A8) - AIF1 DAC2 EQ Band 2 PG + */ +#define WM8995_AIF1DAC2_EQ_B2_PG_MASK 0xFFFF /* AIF1DAC2_EQ_B2_PG - [15:0] */ +#define WM8995_AIF1DAC2_EQ_B2_PG_SHIFT 0 /* AIF1DAC2_EQ_B2_PG - [15:0] */ +#define WM8995_AIF1DAC2_EQ_B2_PG_WIDTH 16 /* AIF1DAC2_EQ_B2_PG - [15:0] */ + +/* + * R1193 (0x4A9) - AIF1 DAC2 EQ Band 3 A + */ +#define WM8995_AIF1DAC2_EQ_B3_A_MASK 0xFFFF /* AIF1DAC2_EQ_B3_A - [15:0] */ +#define WM8995_AIF1DAC2_EQ_B3_A_SHIFT 0 /* AIF1DAC2_EQ_B3_A - [15:0] */ +#define WM8995_AIF1DAC2_EQ_B3_A_WIDTH 16 /* AIF1DAC2_EQ_B3_A - [15:0] */ + +/* + * R1194 (0x4AA) - AIF1 DAC2 EQ Band 3 B + */ +#define WM8995_AIF1DAC2_EQ_B3_B_MASK 0xFFFF /* AIF1DAC2_EQ_B3_B - [15:0] */ +#define WM8995_AIF1DAC2_EQ_B3_B_SHIFT 0 /* AIF1DAC2_EQ_B3_B - [15:0] */ +#define WM8995_AIF1DAC2_EQ_B3_B_WIDTH 16 /* AIF1DAC2_EQ_B3_B - [15:0] */ + +/* + * R1195 (0x4AB) - AIF1 DAC2 EQ Band 3 C + */ +#define WM8995_AIF1DAC2_EQ_B3_C_MASK 0xFFFF /* AIF1DAC2_EQ_B3_C - [15:0] */ +#define WM8995_AIF1DAC2_EQ_B3_C_SHIFT 0 /* AIF1DAC2_EQ_B3_C - [15:0] */ +#define WM8995_AIF1DAC2_EQ_B3_C_WIDTH 16 /* AIF1DAC2_EQ_B3_C - [15:0] */ + +/* + * R1196 (0x4AC) - AIF1 DAC2 EQ Band 3 PG + */ +#define WM8995_AIF1DAC2_EQ_B3_PG_MASK 0xFFFF /* AIF1DAC2_EQ_B3_PG - [15:0] */ +#define WM8995_AIF1DAC2_EQ_B3_PG_SHIFT 0 /* AIF1DAC2_EQ_B3_PG - [15:0] */ +#define WM8995_AIF1DAC2_EQ_B3_PG_WIDTH 16 /* AIF1DAC2_EQ_B3_PG - [15:0] */ + +/* + * R1197 (0x4AD) - AIF1 DAC2 EQ Band 4 A + */ +#define WM8995_AIF1DAC2_EQ_B4_A_MASK 0xFFFF /* AIF1DAC2_EQ_B4_A - [15:0] */ +#define WM8995_AIF1DAC2_EQ_B4_A_SHIFT 0 /* AIF1DAC2_EQ_B4_A - [15:0] */ +#define WM8995_AIF1DAC2_EQ_B4_A_WIDTH 16 /* AIF1DAC2_EQ_B4_A - [15:0] */ + +/* + * R1198 (0x4AE) - AIF1 DAC2 EQ Band 4 B + */ +#define WM8995_AIF1DAC2_EQ_B4_B_MASK 0xFFFF /* AIF1DAC2_EQ_B4_B - [15:0] */ +#define WM8995_AIF1DAC2_EQ_B4_B_SHIFT 0 /* AIF1DAC2_EQ_B4_B - [15:0] */ +#define WM8995_AIF1DAC2_EQ_B4_B_WIDTH 16 /* AIF1DAC2_EQ_B4_B - [15:0] */ + +/* + * R1199 (0x4AF) - AIF1 DAC2 EQ Band 4 C + */ +#define WM8995_AIF1DAC2_EQ_B4_C_MASK 0xFFFF /* AIF1DAC2_EQ_B4_C - [15:0] */ +#define WM8995_AIF1DAC2_EQ_B4_C_SHIFT 0 /* AIF1DAC2_EQ_B4_C - [15:0] */ +#define WM8995_AIF1DAC2_EQ_B4_C_WIDTH 16 /* AIF1DAC2_EQ_B4_C - [15:0] */ + +/* + * R1200 (0x4B0) - AIF1 DAC2 EQ Band 4 PG + */ +#define WM8995_AIF1DAC2_EQ_B4_PG_MASK 0xFFFF /* AIF1DAC2_EQ_B4_PG - [15:0] */ +#define WM8995_AIF1DAC2_EQ_B4_PG_SHIFT 0 /* AIF1DAC2_EQ_B4_PG - [15:0] */ +#define WM8995_AIF1DAC2_EQ_B4_PG_WIDTH 16 /* AIF1DAC2_EQ_B4_PG - [15:0] */ + +/* + * R1201 (0x4B1) - AIF1 DAC2 EQ Band 5 A + */ +#define WM8995_AIF1DAC2_EQ_B5_A_MASK 0xFFFF /* AIF1DAC2_EQ_B5_A - [15:0] */ +#define WM8995_AIF1DAC2_EQ_B5_A_SHIFT 0 /* AIF1DAC2_EQ_B5_A - [15:0] */ +#define WM8995_AIF1DAC2_EQ_B5_A_WIDTH 16 /* AIF1DAC2_EQ_B5_A - [15:0] */ + +/* + * R1202 (0x4B2) - AIF1 DAC2 EQ Band 5 B + */ +#define WM8995_AIF1DAC2_EQ_B5_B_MASK 0xFFFF /* AIF1DAC2_EQ_B5_B - [15:0] */ +#define WM8995_AIF1DAC2_EQ_B5_B_SHIFT 0 /* AIF1DAC2_EQ_B5_B - [15:0] */ +#define WM8995_AIF1DAC2_EQ_B5_B_WIDTH 16 /* AIF1DAC2_EQ_B5_B - [15:0] */ + +/* + * R1203 (0x4B3) - AIF1 DAC2 EQ Band 5 PG + */ +#define WM8995_AIF1DAC2_EQ_B5_PG_MASK 0xFFFF /* AIF1DAC2_EQ_B5_PG - [15:0] */ +#define WM8995_AIF1DAC2_EQ_B5_PG_SHIFT 0 /* AIF1DAC2_EQ_B5_PG - [15:0] */ +#define WM8995_AIF1DAC2_EQ_B5_PG_WIDTH 16 /* AIF1DAC2_EQ_B5_PG - [15:0] */ + +/* + * R1280 (0x500) - AIF2 ADC Left Volume + */ +#define WM8995_AIF2ADC_VU 0x0100 /* AIF2ADC_VU */ +#define WM8995_AIF2ADC_VU_MASK 0x0100 /* AIF2ADC_VU */ +#define WM8995_AIF2ADC_VU_SHIFT 8 /* AIF2ADC_VU */ +#define WM8995_AIF2ADC_VU_WIDTH 1 /* AIF2ADC_VU */ +#define WM8995_AIF2ADCL_VOL_MASK 0x00FF /* AIF2ADCL_VOL - [7:0] */ +#define WM8995_AIF2ADCL_VOL_SHIFT 0 /* AIF2ADCL_VOL - [7:0] */ +#define WM8995_AIF2ADCL_VOL_WIDTH 8 /* AIF2ADCL_VOL - [7:0] */ + +/* + * R1281 (0x501) - AIF2 ADC Right Volume + */ +#define WM8995_AIF2ADC_VU 0x0100 /* AIF2ADC_VU */ +#define WM8995_AIF2ADC_VU_MASK 0x0100 /* AIF2ADC_VU */ +#define WM8995_AIF2ADC_VU_SHIFT 8 /* AIF2ADC_VU */ +#define WM8995_AIF2ADC_VU_WIDTH 1 /* AIF2ADC_VU */ +#define WM8995_AIF2ADCR_VOL_MASK 0x00FF /* AIF2ADCR_VOL - [7:0] */ +#define WM8995_AIF2ADCR_VOL_SHIFT 0 /* AIF2ADCR_VOL - [7:0] */ +#define WM8995_AIF2ADCR_VOL_WIDTH 8 /* AIF2ADCR_VOL - [7:0] */ + +/* + * R1282 (0x502) - AIF2 DAC Left Volume + */ +#define WM8995_AIF2DAC_VU 0x0100 /* AIF2DAC_VU */ +#define WM8995_AIF2DAC_VU_MASK 0x0100 /* AIF2DAC_VU */ +#define WM8995_AIF2DAC_VU_SHIFT 8 /* AIF2DAC_VU */ +#define WM8995_AIF2DAC_VU_WIDTH 1 /* AIF2DAC_VU */ +#define WM8995_AIF2DACL_VOL_MASK 0x00FF /* AIF2DACL_VOL - [7:0] */ +#define WM8995_AIF2DACL_VOL_SHIFT 0 /* AIF2DACL_VOL - [7:0] */ +#define WM8995_AIF2DACL_VOL_WIDTH 8 /* AIF2DACL_VOL - [7:0] */ + +/* + * R1283 (0x503) - AIF2 DAC Right Volume + */ +#define WM8995_AIF2DAC_VU 0x0100 /* AIF2DAC_VU */ +#define WM8995_AIF2DAC_VU_MASK 0x0100 /* AIF2DAC_VU */ +#define WM8995_AIF2DAC_VU_SHIFT 8 /* AIF2DAC_VU */ +#define WM8995_AIF2DAC_VU_WIDTH 1 /* AIF2DAC_VU */ +#define WM8995_AIF2DACR_VOL_MASK 0x00FF /* AIF2DACR_VOL - [7:0] */ +#define WM8995_AIF2DACR_VOL_SHIFT 0 /* AIF2DACR_VOL - [7:0] */ +#define WM8995_AIF2DACR_VOL_WIDTH 8 /* AIF2DACR_VOL - [7:0] */ + +/* + * R1296 (0x510) - AIF2 ADC Filters + */ +#define WM8995_AIF2ADC_4FS 0x8000 /* AIF2ADC_4FS */ +#define WM8995_AIF2ADC_4FS_MASK 0x8000 /* AIF2ADC_4FS */ +#define WM8995_AIF2ADC_4FS_SHIFT 15 /* AIF2ADC_4FS */ +#define WM8995_AIF2ADC_4FS_WIDTH 1 /* AIF2ADC_4FS */ +#define WM8995_AIF2ADCL_HPF 0x1000 /* AIF2ADCL_HPF */ +#define WM8995_AIF2ADCL_HPF_MASK 0x1000 /* AIF2ADCL_HPF */ +#define WM8995_AIF2ADCL_HPF_SHIFT 12 /* AIF2ADCL_HPF */ +#define WM8995_AIF2ADCL_HPF_WIDTH 1 /* AIF2ADCL_HPF */ +#define WM8995_AIF2ADCR_HPF 0x0800 /* AIF2ADCR_HPF */ +#define WM8995_AIF2ADCR_HPF_MASK 0x0800 /* AIF2ADCR_HPF */ +#define WM8995_AIF2ADCR_HPF_SHIFT 11 /* AIF2ADCR_HPF */ +#define WM8995_AIF2ADCR_HPF_WIDTH 1 /* AIF2ADCR_HPF */ +#define WM8995_AIF2ADC_HPF_MODE 0x0008 /* AIF2ADC_HPF_MODE */ +#define WM8995_AIF2ADC_HPF_MODE_MASK 0x0008 /* AIF2ADC_HPF_MODE */ +#define WM8995_AIF2ADC_HPF_MODE_SHIFT 3 /* AIF2ADC_HPF_MODE */ +#define WM8995_AIF2ADC_HPF_MODE_WIDTH 1 /* AIF2ADC_HPF_MODE */ +#define WM8995_AIF2ADC_HPF_CUT_MASK 0x0007 /* AIF2ADC_HPF_CUT - [2:0] */ +#define WM8995_AIF2ADC_HPF_CUT_SHIFT 0 /* AIF2ADC_HPF_CUT - [2:0] */ +#define WM8995_AIF2ADC_HPF_CUT_WIDTH 3 /* AIF2ADC_HPF_CUT - [2:0] */ + +/* + * R1312 (0x520) - AIF2 DAC Filters (1) + */ +#define WM8995_AIF2DAC_MUTE 0x0200 /* AIF2DAC_MUTE */ +#define WM8995_AIF2DAC_MUTE_MASK 0x0200 /* AIF2DAC_MUTE */ +#define WM8995_AIF2DAC_MUTE_SHIFT 9 /* AIF2DAC_MUTE */ +#define WM8995_AIF2DAC_MUTE_WIDTH 1 /* AIF2DAC_MUTE */ +#define WM8995_AIF2DAC_MONO 0x0080 /* AIF2DAC_MONO */ +#define WM8995_AIF2DAC_MONO_MASK 0x0080 /* AIF2DAC_MONO */ +#define WM8995_AIF2DAC_MONO_SHIFT 7 /* AIF2DAC_MONO */ +#define WM8995_AIF2DAC_MONO_WIDTH 1 /* AIF2DAC_MONO */ +#define WM8995_AIF2DAC_MUTERATE 0x0020 /* AIF2DAC_MUTERATE */ +#define WM8995_AIF2DAC_MUTERATE_MASK 0x0020 /* AIF2DAC_MUTERATE */ +#define WM8995_AIF2DAC_MUTERATE_SHIFT 5 /* AIF2DAC_MUTERATE */ +#define WM8995_AIF2DAC_MUTERATE_WIDTH 1 /* AIF2DAC_MUTERATE */ +#define WM8995_AIF2DAC_UNMUTE_RAMP 0x0010 /* AIF2DAC_UNMUTE_RAMP */ +#define WM8995_AIF2DAC_UNMUTE_RAMP_MASK 0x0010 /* AIF2DAC_UNMUTE_RAMP */ +#define WM8995_AIF2DAC_UNMUTE_RAMP_SHIFT 4 /* AIF2DAC_UNMUTE_RAMP */ +#define WM8995_AIF2DAC_UNMUTE_RAMP_WIDTH 1 /* AIF2DAC_UNMUTE_RAMP */ +#define WM8995_AIF2DAC_DEEMP_MASK 0x0006 /* AIF2DAC_DEEMP - [2:1] */ +#define WM8995_AIF2DAC_DEEMP_SHIFT 1 /* AIF2DAC_DEEMP - [2:1] */ +#define WM8995_AIF2DAC_DEEMP_WIDTH 2 /* AIF2DAC_DEEMP - [2:1] */ + +/* + * R1313 (0x521) - AIF2 DAC Filters (2) + */ +#define WM8995_AIF2DAC_3D_GAIN_MASK 0x3E00 /* AIF2DAC_3D_GAIN - [13:9] */ +#define WM8995_AIF2DAC_3D_GAIN_SHIFT 9 /* AIF2DAC_3D_GAIN - [13:9] */ +#define WM8995_AIF2DAC_3D_GAIN_WIDTH 5 /* AIF2DAC_3D_GAIN - [13:9] */ +#define WM8995_AIF2DAC_3D_ENA 0x0100 /* AIF2DAC_3D_ENA */ +#define WM8995_AIF2DAC_3D_ENA_MASK 0x0100 /* AIF2DAC_3D_ENA */ +#define WM8995_AIF2DAC_3D_ENA_SHIFT 8 /* AIF2DAC_3D_ENA */ +#define WM8995_AIF2DAC_3D_ENA_WIDTH 1 /* AIF2DAC_3D_ENA */ + +/* + * R1344 (0x540) - AIF2 DRC (1) + */ +#define WM8995_AIF2DRC_SIG_DET_RMS_MASK 0xF800 /* AIF2DRC_SIG_DET_RMS - [15:11] */ +#define WM8995_AIF2DRC_SIG_DET_RMS_SHIFT 11 /* AIF2DRC_SIG_DET_RMS - [15:11] */ +#define WM8995_AIF2DRC_SIG_DET_RMS_WIDTH 5 /* AIF2DRC_SIG_DET_RMS - [15:11] */ +#define WM8995_AIF2DRC_SIG_DET_PK_MASK 0x0600 /* AIF2DRC_SIG_DET_PK - [10:9] */ +#define WM8995_AIF2DRC_SIG_DET_PK_SHIFT 9 /* AIF2DRC_SIG_DET_PK - [10:9] */ +#define WM8995_AIF2DRC_SIG_DET_PK_WIDTH 2 /* AIF2DRC_SIG_DET_PK - [10:9] */ +#define WM8995_AIF2DRC_NG_ENA 0x0100 /* AIF2DRC_NG_ENA */ +#define WM8995_AIF2DRC_NG_ENA_MASK 0x0100 /* AIF2DRC_NG_ENA */ +#define WM8995_AIF2DRC_NG_ENA_SHIFT 8 /* AIF2DRC_NG_ENA */ +#define WM8995_AIF2DRC_NG_ENA_WIDTH 1 /* AIF2DRC_NG_ENA */ +#define WM8995_AIF2DRC_SIG_DET_MODE 0x0080 /* AIF2DRC_SIG_DET_MODE */ +#define WM8995_AIF2DRC_SIG_DET_MODE_MASK 0x0080 /* AIF2DRC_SIG_DET_MODE */ +#define WM8995_AIF2DRC_SIG_DET_MODE_SHIFT 7 /* AIF2DRC_SIG_DET_MODE */ +#define WM8995_AIF2DRC_SIG_DET_MODE_WIDTH 1 /* AIF2DRC_SIG_DET_MODE */ +#define WM8995_AIF2DRC_SIG_DET 0x0040 /* AIF2DRC_SIG_DET */ +#define WM8995_AIF2DRC_SIG_DET_MASK 0x0040 /* AIF2DRC_SIG_DET */ +#define WM8995_AIF2DRC_SIG_DET_SHIFT 6 /* AIF2DRC_SIG_DET */ +#define WM8995_AIF2DRC_SIG_DET_WIDTH 1 /* AIF2DRC_SIG_DET */ +#define WM8995_AIF2DRC_KNEE2_OP_ENA 0x0020 /* AIF2DRC_KNEE2_OP_ENA */ +#define WM8995_AIF2DRC_KNEE2_OP_ENA_MASK 0x0020 /* AIF2DRC_KNEE2_OP_ENA */ +#define WM8995_AIF2DRC_KNEE2_OP_ENA_SHIFT 5 /* AIF2DRC_KNEE2_OP_ENA */ +#define WM8995_AIF2DRC_KNEE2_OP_ENA_WIDTH 1 /* AIF2DRC_KNEE2_OP_ENA */ +#define WM8995_AIF2DRC_QR 0x0010 /* AIF2DRC_QR */ +#define WM8995_AIF2DRC_QR_MASK 0x0010 /* AIF2DRC_QR */ +#define WM8995_AIF2DRC_QR_SHIFT 4 /* AIF2DRC_QR */ +#define WM8995_AIF2DRC_QR_WIDTH 1 /* AIF2DRC_QR */ +#define WM8995_AIF2DRC_ANTICLIP 0x0008 /* AIF2DRC_ANTICLIP */ +#define WM8995_AIF2DRC_ANTICLIP_MASK 0x0008 /* AIF2DRC_ANTICLIP */ +#define WM8995_AIF2DRC_ANTICLIP_SHIFT 3 /* AIF2DRC_ANTICLIP */ +#define WM8995_AIF2DRC_ANTICLIP_WIDTH 1 /* AIF2DRC_ANTICLIP */ +#define WM8995_AIF2DAC_DRC_ENA 0x0004 /* AIF2DAC_DRC_ENA */ +#define WM8995_AIF2DAC_DRC_ENA_MASK 0x0004 /* AIF2DAC_DRC_ENA */ +#define WM8995_AIF2DAC_DRC_ENA_SHIFT 2 /* AIF2DAC_DRC_ENA */ +#define WM8995_AIF2DAC_DRC_ENA_WIDTH 1 /* AIF2DAC_DRC_ENA */ +#define WM8995_AIF2ADCL_DRC_ENA 0x0002 /* AIF2ADCL_DRC_ENA */ +#define WM8995_AIF2ADCL_DRC_ENA_MASK 0x0002 /* AIF2ADCL_DRC_ENA */ +#define WM8995_AIF2ADCL_DRC_ENA_SHIFT 1 /* AIF2ADCL_DRC_ENA */ +#define WM8995_AIF2ADCL_DRC_ENA_WIDTH 1 /* AIF2ADCL_DRC_ENA */ +#define WM8995_AIF2ADCR_DRC_ENA 0x0001 /* AIF2ADCR_DRC_ENA */ +#define WM8995_AIF2ADCR_DRC_ENA_MASK 0x0001 /* AIF2ADCR_DRC_ENA */ +#define WM8995_AIF2ADCR_DRC_ENA_SHIFT 0 /* AIF2ADCR_DRC_ENA */ +#define WM8995_AIF2ADCR_DRC_ENA_WIDTH 1 /* AIF2ADCR_DRC_ENA */ + +/* + * R1345 (0x541) - AIF2 DRC (2) + */ +#define WM8995_AIF2DRC_ATK_MASK 0x1E00 /* AIF2DRC_ATK - [12:9] */ +#define WM8995_AIF2DRC_ATK_SHIFT 9 /* AIF2DRC_ATK - [12:9] */ +#define WM8995_AIF2DRC_ATK_WIDTH 4 /* AIF2DRC_ATK - [12:9] */ +#define WM8995_AIF2DRC_DCY_MASK 0x01E0 /* AIF2DRC_DCY - [8:5] */ +#define WM8995_AIF2DRC_DCY_SHIFT 5 /* AIF2DRC_DCY - [8:5] */ +#define WM8995_AIF2DRC_DCY_WIDTH 4 /* AIF2DRC_DCY - [8:5] */ +#define WM8995_AIF2DRC_MINGAIN_MASK 0x001C /* AIF2DRC_MINGAIN - [4:2] */ +#define WM8995_AIF2DRC_MINGAIN_SHIFT 2 /* AIF2DRC_MINGAIN - [4:2] */ +#define WM8995_AIF2DRC_MINGAIN_WIDTH 3 /* AIF2DRC_MINGAIN - [4:2] */ +#define WM8995_AIF2DRC_MAXGAIN_MASK 0x0003 /* AIF2DRC_MAXGAIN - [1:0] */ +#define WM8995_AIF2DRC_MAXGAIN_SHIFT 0 /* AIF2DRC_MAXGAIN - [1:0] */ +#define WM8995_AIF2DRC_MAXGAIN_WIDTH 2 /* AIF2DRC_MAXGAIN - [1:0] */ + +/* + * R1346 (0x542) - AIF2 DRC (3) + */ +#define WM8995_AIF2DRC_NG_MINGAIN_MASK 0xF000 /* AIF2DRC_NG_MINGAIN - [15:12] */ +#define WM8995_AIF2DRC_NG_MINGAIN_SHIFT 12 /* AIF2DRC_NG_MINGAIN - [15:12] */ +#define WM8995_AIF2DRC_NG_MINGAIN_WIDTH 4 /* AIF2DRC_NG_MINGAIN - [15:12] */ +#define WM8995_AIF2DRC_NG_EXP_MASK 0x0C00 /* AIF2DRC_NG_EXP - [11:10] */ +#define WM8995_AIF2DRC_NG_EXP_SHIFT 10 /* AIF2DRC_NG_EXP - [11:10] */ +#define WM8995_AIF2DRC_NG_EXP_WIDTH 2 /* AIF2DRC_NG_EXP - [11:10] */ +#define WM8995_AIF2DRC_QR_THR_MASK 0x0300 /* AIF2DRC_QR_THR - [9:8] */ +#define WM8995_AIF2DRC_QR_THR_SHIFT 8 /* AIF2DRC_QR_THR - [9:8] */ +#define WM8995_AIF2DRC_QR_THR_WIDTH 2 /* AIF2DRC_QR_THR - [9:8] */ +#define WM8995_AIF2DRC_QR_DCY_MASK 0x00C0 /* AIF2DRC_QR_DCY - [7:6] */ +#define WM8995_AIF2DRC_QR_DCY_SHIFT 6 /* AIF2DRC_QR_DCY - [7:6] */ +#define WM8995_AIF2DRC_QR_DCY_WIDTH 2 /* AIF2DRC_QR_DCY - [7:6] */ +#define WM8995_AIF2DRC_HI_COMP_MASK 0x0038 /* AIF2DRC_HI_COMP - [5:3] */ +#define WM8995_AIF2DRC_HI_COMP_SHIFT 3 /* AIF2DRC_HI_COMP - [5:3] */ +#define WM8995_AIF2DRC_HI_COMP_WIDTH 3 /* AIF2DRC_HI_COMP - [5:3] */ +#define WM8995_AIF2DRC_LO_COMP_MASK 0x0007 /* AIF2DRC_LO_COMP - [2:0] */ +#define WM8995_AIF2DRC_LO_COMP_SHIFT 0 /* AIF2DRC_LO_COMP - [2:0] */ +#define WM8995_AIF2DRC_LO_COMP_WIDTH 3 /* AIF2DRC_LO_COMP - [2:0] */ + +/* + * R1347 (0x543) - AIF2 DRC (4) + */ +#define WM8995_AIF2DRC_KNEE_IP_MASK 0x07E0 /* AIF2DRC_KNEE_IP - [10:5] */ +#define WM8995_AIF2DRC_KNEE_IP_SHIFT 5 /* AIF2DRC_KNEE_IP - [10:5] */ +#define WM8995_AIF2DRC_KNEE_IP_WIDTH 6 /* AIF2DRC_KNEE_IP - [10:5] */ +#define WM8995_AIF2DRC_KNEE_OP_MASK 0x001F /* AIF2DRC_KNEE_OP - [4:0] */ +#define WM8995_AIF2DRC_KNEE_OP_SHIFT 0 /* AIF2DRC_KNEE_OP - [4:0] */ +#define WM8995_AIF2DRC_KNEE_OP_WIDTH 5 /* AIF2DRC_KNEE_OP - [4:0] */ + +/* + * R1348 (0x544) - AIF2 DRC (5) + */ +#define WM8995_AIF2DRC_KNEE2_IP_MASK 0x03E0 /* AIF2DRC_KNEE2_IP - [9:5] */ +#define WM8995_AIF2DRC_KNEE2_IP_SHIFT 5 /* AIF2DRC_KNEE2_IP - [9:5] */ +#define WM8995_AIF2DRC_KNEE2_IP_WIDTH 5 /* AIF2DRC_KNEE2_IP - [9:5] */ +#define WM8995_AIF2DRC_KNEE2_OP_MASK 0x001F /* AIF2DRC_KNEE2_OP - [4:0] */ +#define WM8995_AIF2DRC_KNEE2_OP_SHIFT 0 /* AIF2DRC_KNEE2_OP - [4:0] */ +#define WM8995_AIF2DRC_KNEE2_OP_WIDTH 5 /* AIF2DRC_KNEE2_OP - [4:0] */ + +/* + * R1408 (0x580) - AIF2 EQ Gains (1) + */ +#define WM8995_AIF2DAC_EQ_B1_GAIN_MASK 0xF800 /* AIF2DAC_EQ_B1_GAIN - [15:11] */ +#define WM8995_AIF2DAC_EQ_B1_GAIN_SHIFT 11 /* AIF2DAC_EQ_B1_GAIN - [15:11] */ +#define WM8995_AIF2DAC_EQ_B1_GAIN_WIDTH 5 /* AIF2DAC_EQ_B1_GAIN - [15:11] */ +#define WM8995_AIF2DAC_EQ_B2_GAIN_MASK 0x07C0 /* AIF2DAC_EQ_B2_GAIN - [10:6] */ +#define WM8995_AIF2DAC_EQ_B2_GAIN_SHIFT 6 /* AIF2DAC_EQ_B2_GAIN - [10:6] */ +#define WM8995_AIF2DAC_EQ_B2_GAIN_WIDTH 5 /* AIF2DAC_EQ_B2_GAIN - [10:6] */ +#define WM8995_AIF2DAC_EQ_B3_GAIN_MASK 0x003E /* AIF2DAC_EQ_B3_GAIN - [5:1] */ +#define WM8995_AIF2DAC_EQ_B3_GAIN_SHIFT 1 /* AIF2DAC_EQ_B3_GAIN - [5:1] */ +#define WM8995_AIF2DAC_EQ_B3_GAIN_WIDTH 5 /* AIF2DAC_EQ_B3_GAIN - [5:1] */ +#define WM8995_AIF2DAC_EQ_ENA 0x0001 /* AIF2DAC_EQ_ENA */ +#define WM8995_AIF2DAC_EQ_ENA_MASK 0x0001 /* AIF2DAC_EQ_ENA */ +#define WM8995_AIF2DAC_EQ_ENA_SHIFT 0 /* AIF2DAC_EQ_ENA */ +#define WM8995_AIF2DAC_EQ_ENA_WIDTH 1 /* AIF2DAC_EQ_ENA */ + +/* + * R1409 (0x581) - AIF2 EQ Gains (2) + */ +#define WM8995_AIF2DAC_EQ_B4_GAIN_MASK 0xF800 /* AIF2DAC_EQ_B4_GAIN - [15:11] */ +#define WM8995_AIF2DAC_EQ_B4_GAIN_SHIFT 11 /* AIF2DAC_EQ_B4_GAIN - [15:11] */ +#define WM8995_AIF2DAC_EQ_B4_GAIN_WIDTH 5 /* AIF2DAC_EQ_B4_GAIN - [15:11] */ +#define WM8995_AIF2DAC_EQ_B5_GAIN_MASK 0x07C0 /* AIF2DAC_EQ_B5_GAIN - [10:6] */ +#define WM8995_AIF2DAC_EQ_B5_GAIN_SHIFT 6 /* AIF2DAC_EQ_B5_GAIN - [10:6] */ +#define WM8995_AIF2DAC_EQ_B5_GAIN_WIDTH 5 /* AIF2DAC_EQ_B5_GAIN - [10:6] */ + +/* + * R1410 (0x582) - AIF2 EQ Band 1 A + */ +#define WM8995_AIF2DAC_EQ_B1_A_MASK 0xFFFF /* AIF2DAC_EQ_B1_A - [15:0] */ +#define WM8995_AIF2DAC_EQ_B1_A_SHIFT 0 /* AIF2DAC_EQ_B1_A - [15:0] */ +#define WM8995_AIF2DAC_EQ_B1_A_WIDTH 16 /* AIF2DAC_EQ_B1_A - [15:0] */ + +/* + * R1411 (0x583) - AIF2 EQ Band 1 B + */ +#define WM8995_AIF2DAC_EQ_B1_B_MASK 0xFFFF /* AIF2DAC_EQ_B1_B - [15:0] */ +#define WM8995_AIF2DAC_EQ_B1_B_SHIFT 0 /* AIF2DAC_EQ_B1_B - [15:0] */ +#define WM8995_AIF2DAC_EQ_B1_B_WIDTH 16 /* AIF2DAC_EQ_B1_B - [15:0] */ + +/* + * R1412 (0x584) - AIF2 EQ Band 1 PG + */ +#define WM8995_AIF2DAC_EQ_B1_PG_MASK 0xFFFF /* AIF2DAC_EQ_B1_PG - [15:0] */ +#define WM8995_AIF2DAC_EQ_B1_PG_SHIFT 0 /* AIF2DAC_EQ_B1_PG - [15:0] */ +#define WM8995_AIF2DAC_EQ_B1_PG_WIDTH 16 /* AIF2DAC_EQ_B1_PG - [15:0] */ + +/* + * R1413 (0x585) - AIF2 EQ Band 2 A + */ +#define WM8995_AIF2DAC_EQ_B2_A_MASK 0xFFFF /* AIF2DAC_EQ_B2_A - [15:0] */ +#define WM8995_AIF2DAC_EQ_B2_A_SHIFT 0 /* AIF2DAC_EQ_B2_A - [15:0] */ +#define WM8995_AIF2DAC_EQ_B2_A_WIDTH 16 /* AIF2DAC_EQ_B2_A - [15:0] */ + +/* + * R1414 (0x586) - AIF2 EQ Band 2 B + */ +#define WM8995_AIF2DAC_EQ_B2_B_MASK 0xFFFF /* AIF2DAC_EQ_B2_B - [15:0] */ +#define WM8995_AIF2DAC_EQ_B2_B_SHIFT 0 /* AIF2DAC_EQ_B2_B - [15:0] */ +#define WM8995_AIF2DAC_EQ_B2_B_WIDTH 16 /* AIF2DAC_EQ_B2_B - [15:0] */ + +/* + * R1415 (0x587) - AIF2 EQ Band 2 C + */ +#define WM8995_AIF2DAC_EQ_B2_C_MASK 0xFFFF /* AIF2DAC_EQ_B2_C - [15:0] */ +#define WM8995_AIF2DAC_EQ_B2_C_SHIFT 0 /* AIF2DAC_EQ_B2_C - [15:0] */ +#define WM8995_AIF2DAC_EQ_B2_C_WIDTH 16 /* AIF2DAC_EQ_B2_C - [15:0] */ + +/* + * R1416 (0x588) - AIF2 EQ Band 2 PG + */ +#define WM8995_AIF2DAC_EQ_B2_PG_MASK 0xFFFF /* AIF2DAC_EQ_B2_PG - [15:0] */ +#define WM8995_AIF2DAC_EQ_B2_PG_SHIFT 0 /* AIF2DAC_EQ_B2_PG - [15:0] */ +#define WM8995_AIF2DAC_EQ_B2_PG_WIDTH 16 /* AIF2DAC_EQ_B2_PG - [15:0] */ + +/* + * R1417 (0x589) - AIF2 EQ Band 3 A + */ +#define WM8995_AIF2DAC_EQ_B3_A_MASK 0xFFFF /* AIF2DAC_EQ_B3_A - [15:0] */ +#define WM8995_AIF2DAC_EQ_B3_A_SHIFT 0 /* AIF2DAC_EQ_B3_A - [15:0] */ +#define WM8995_AIF2DAC_EQ_B3_A_WIDTH 16 /* AIF2DAC_EQ_B3_A - [15:0] */ + +/* + * R1418 (0x58A) - AIF2 EQ Band 3 B + */ +#define WM8995_AIF2DAC_EQ_B3_B_MASK 0xFFFF /* AIF2DAC_EQ_B3_B - [15:0] */ +#define WM8995_AIF2DAC_EQ_B3_B_SHIFT 0 /* AIF2DAC_EQ_B3_B - [15:0] */ +#define WM8995_AIF2DAC_EQ_B3_B_WIDTH 16 /* AIF2DAC_EQ_B3_B - [15:0] */ + +/* + * R1419 (0x58B) - AIF2 EQ Band 3 C + */ +#define WM8995_AIF2DAC_EQ_B3_C_MASK 0xFFFF /* AIF2DAC_EQ_B3_C - [15:0] */ +#define WM8995_AIF2DAC_EQ_B3_C_SHIFT 0 /* AIF2DAC_EQ_B3_C - [15:0] */ +#define WM8995_AIF2DAC_EQ_B3_C_WIDTH 16 /* AIF2DAC_EQ_B3_C - [15:0] */ + +/* + * R1420 (0x58C) - AIF2 EQ Band 3 PG + */ +#define WM8995_AIF2DAC_EQ_B3_PG_MASK 0xFFFF /* AIF2DAC_EQ_B3_PG - [15:0] */ +#define WM8995_AIF2DAC_EQ_B3_PG_SHIFT 0 /* AIF2DAC_EQ_B3_PG - [15:0] */ +#define WM8995_AIF2DAC_EQ_B3_PG_WIDTH 16 /* AIF2DAC_EQ_B3_PG - [15:0] */ + +/* + * R1421 (0x58D) - AIF2 EQ Band 4 A + */ +#define WM8995_AIF2DAC_EQ_B4_A_MASK 0xFFFF /* AIF2DAC_EQ_B4_A - [15:0] */ +#define WM8995_AIF2DAC_EQ_B4_A_SHIFT 0 /* AIF2DAC_EQ_B4_A - [15:0] */ +#define WM8995_AIF2DAC_EQ_B4_A_WIDTH 16 /* AIF2DAC_EQ_B4_A - [15:0] */ + +/* + * R1422 (0x58E) - AIF2 EQ Band 4 B + */ +#define WM8995_AIF2DAC_EQ_B4_B_MASK 0xFFFF /* AIF2DAC_EQ_B4_B - [15:0] */ +#define WM8995_AIF2DAC_EQ_B4_B_SHIFT 0 /* AIF2DAC_EQ_B4_B - [15:0] */ +#define WM8995_AIF2DAC_EQ_B4_B_WIDTH 16 /* AIF2DAC_EQ_B4_B - [15:0] */ + +/* + * R1423 (0x58F) - AIF2 EQ Band 4 C + */ +#define WM8995_AIF2DAC_EQ_B4_C_MASK 0xFFFF /* AIF2DAC_EQ_B4_C - [15:0] */ +#define WM8995_AIF2DAC_EQ_B4_C_SHIFT 0 /* AIF2DAC_EQ_B4_C - [15:0] */ +#define WM8995_AIF2DAC_EQ_B4_C_WIDTH 16 /* AIF2DAC_EQ_B4_C - [15:0] */ + +/* + * R1424 (0x590) - AIF2 EQ Band 4 PG + */ +#define WM8995_AIF2DAC_EQ_B4_PG_MASK 0xFFFF /* AIF2DAC_EQ_B4_PG - [15:0] */ +#define WM8995_AIF2DAC_EQ_B4_PG_SHIFT 0 /* AIF2DAC_EQ_B4_PG - [15:0] */ +#define WM8995_AIF2DAC_EQ_B4_PG_WIDTH 16 /* AIF2DAC_EQ_B4_PG - [15:0] */ + +/* + * R1425 (0x591) - AIF2 EQ Band 5 A + */ +#define WM8995_AIF2DAC_EQ_B5_A_MASK 0xFFFF /* AIF2DAC_EQ_B5_A - [15:0] */ +#define WM8995_AIF2DAC_EQ_B5_A_SHIFT 0 /* AIF2DAC_EQ_B5_A - [15:0] */ +#define WM8995_AIF2DAC_EQ_B5_A_WIDTH 16 /* AIF2DAC_EQ_B5_A - [15:0] */ + +/* + * R1426 (0x592) - AIF2 EQ Band 5 B + */ +#define WM8995_AIF2DAC_EQ_B5_B_MASK 0xFFFF /* AIF2DAC_EQ_B5_B - [15:0] */ +#define WM8995_AIF2DAC_EQ_B5_B_SHIFT 0 /* AIF2DAC_EQ_B5_B - [15:0] */ +#define WM8995_AIF2DAC_EQ_B5_B_WIDTH 16 /* AIF2DAC_EQ_B5_B - [15:0] */ + +/* + * R1427 (0x593) - AIF2 EQ Band 5 PG + */ +#define WM8995_AIF2DAC_EQ_B5_PG_MASK 0xFFFF /* AIF2DAC_EQ_B5_PG - [15:0] */ +#define WM8995_AIF2DAC_EQ_B5_PG_SHIFT 0 /* AIF2DAC_EQ_B5_PG - [15:0] */ +#define WM8995_AIF2DAC_EQ_B5_PG_WIDTH 16 /* AIF2DAC_EQ_B5_PG - [15:0] */ + +/* + * R1536 (0x600) - DAC1 Mixer Volumes + */ +#define WM8995_ADCR_DAC1_VOL_MASK 0x03E0 /* ADCR_DAC1_VOL - [9:5] */ +#define WM8995_ADCR_DAC1_VOL_SHIFT 5 /* ADCR_DAC1_VOL - [9:5] */ +#define WM8995_ADCR_DAC1_VOL_WIDTH 5 /* ADCR_DAC1_VOL - [9:5] */ +#define WM8995_ADCL_DAC1_VOL_MASK 0x001F /* ADCL_DAC1_VOL - [4:0] */ +#define WM8995_ADCL_DAC1_VOL_SHIFT 0 /* ADCL_DAC1_VOL - [4:0] */ +#define WM8995_ADCL_DAC1_VOL_WIDTH 5 /* ADCL_DAC1_VOL - [4:0] */ + +/* + * R1537 (0x601) - DAC1 Left Mixer Routing + */ +#define WM8995_ADCR_TO_DAC1L 0x0020 /* ADCR_TO_DAC1L */ +#define WM8995_ADCR_TO_DAC1L_MASK 0x0020 /* ADCR_TO_DAC1L */ +#define WM8995_ADCR_TO_DAC1L_SHIFT 5 /* ADCR_TO_DAC1L */ +#define WM8995_ADCR_TO_DAC1L_WIDTH 1 /* ADCR_TO_DAC1L */ +#define WM8995_ADCL_TO_DAC1L 0x0010 /* ADCL_TO_DAC1L */ +#define WM8995_ADCL_TO_DAC1L_MASK 0x0010 /* ADCL_TO_DAC1L */ +#define WM8995_ADCL_TO_DAC1L_SHIFT 4 /* ADCL_TO_DAC1L */ +#define WM8995_ADCL_TO_DAC1L_WIDTH 1 /* ADCL_TO_DAC1L */ +#define WM8995_AIF2DACL_TO_DAC1L 0x0004 /* AIF2DACL_TO_DAC1L */ +#define WM8995_AIF2DACL_TO_DAC1L_MASK 0x0004 /* AIF2DACL_TO_DAC1L */ +#define WM8995_AIF2DACL_TO_DAC1L_SHIFT 2 /* AIF2DACL_TO_DAC1L */ +#define WM8995_AIF2DACL_TO_DAC1L_WIDTH 1 /* AIF2DACL_TO_DAC1L */ +#define WM8995_AIF1DAC2L_TO_DAC1L 0x0002 /* AIF1DAC2L_TO_DAC1L */ +#define WM8995_AIF1DAC2L_TO_DAC1L_MASK 0x0002 /* AIF1DAC2L_TO_DAC1L */ +#define WM8995_AIF1DAC2L_TO_DAC1L_SHIFT 1 /* AIF1DAC2L_TO_DAC1L */ +#define WM8995_AIF1DAC2L_TO_DAC1L_WIDTH 1 /* AIF1DAC2L_TO_DAC1L */ +#define WM8995_AIF1DAC1L_TO_DAC1L 0x0001 /* AIF1DAC1L_TO_DAC1L */ +#define WM8995_AIF1DAC1L_TO_DAC1L_MASK 0x0001 /* AIF1DAC1L_TO_DAC1L */ +#define WM8995_AIF1DAC1L_TO_DAC1L_SHIFT 0 /* AIF1DAC1L_TO_DAC1L */ +#define WM8995_AIF1DAC1L_TO_DAC1L_WIDTH 1 /* AIF1DAC1L_TO_DAC1L */ + +/* + * R1538 (0x602) - DAC1 Right Mixer Routing + */ +#define WM8995_ADCR_TO_DAC1R 0x0020 /* ADCR_TO_DAC1R */ +#define WM8995_ADCR_TO_DAC1R_MASK 0x0020 /* ADCR_TO_DAC1R */ +#define WM8995_ADCR_TO_DAC1R_SHIFT 5 /* ADCR_TO_DAC1R */ +#define WM8995_ADCR_TO_DAC1R_WIDTH 1 /* ADCR_TO_DAC1R */ +#define WM8995_ADCL_TO_DAC1R 0x0010 /* ADCL_TO_DAC1R */ +#define WM8995_ADCL_TO_DAC1R_MASK 0x0010 /* ADCL_TO_DAC1R */ +#define WM8995_ADCL_TO_DAC1R_SHIFT 4 /* ADCL_TO_DAC1R */ +#define WM8995_ADCL_TO_DAC1R_WIDTH 1 /* ADCL_TO_DAC1R */ +#define WM8995_AIF2DACR_TO_DAC1R 0x0004 /* AIF2DACR_TO_DAC1R */ +#define WM8995_AIF2DACR_TO_DAC1R_MASK 0x0004 /* AIF2DACR_TO_DAC1R */ +#define WM8995_AIF2DACR_TO_DAC1R_SHIFT 2 /* AIF2DACR_TO_DAC1R */ +#define WM8995_AIF2DACR_TO_DAC1R_WIDTH 1 /* AIF2DACR_TO_DAC1R */ +#define WM8995_AIF1DAC2R_TO_DAC1R 0x0002 /* AIF1DAC2R_TO_DAC1R */ +#define WM8995_AIF1DAC2R_TO_DAC1R_MASK 0x0002 /* AIF1DAC2R_TO_DAC1R */ +#define WM8995_AIF1DAC2R_TO_DAC1R_SHIFT 1 /* AIF1DAC2R_TO_DAC1R */ +#define WM8995_AIF1DAC2R_TO_DAC1R_WIDTH 1 /* AIF1DAC2R_TO_DAC1R */ +#define WM8995_AIF1DAC1R_TO_DAC1R 0x0001 /* AIF1DAC1R_TO_DAC1R */ +#define WM8995_AIF1DAC1R_TO_DAC1R_MASK 0x0001 /* AIF1DAC1R_TO_DAC1R */ +#define WM8995_AIF1DAC1R_TO_DAC1R_SHIFT 0 /* AIF1DAC1R_TO_DAC1R */ +#define WM8995_AIF1DAC1R_TO_DAC1R_WIDTH 1 /* AIF1DAC1R_TO_DAC1R */ + +/* + * R1539 (0x603) - DAC2 Mixer Volumes + */ +#define WM8995_ADCR_DAC2_VOL_MASK 0x03E0 /* ADCR_DAC2_VOL - [9:5] */ +#define WM8995_ADCR_DAC2_VOL_SHIFT 5 /* ADCR_DAC2_VOL - [9:5] */ +#define WM8995_ADCR_DAC2_VOL_WIDTH 5 /* ADCR_DAC2_VOL - [9:5] */ +#define WM8995_ADCL_DAC2_VOL_MASK 0x001F /* ADCL_DAC2_VOL - [4:0] */ +#define WM8995_ADCL_DAC2_VOL_SHIFT 0 /* ADCL_DAC2_VOL - [4:0] */ +#define WM8995_ADCL_DAC2_VOL_WIDTH 5 /* ADCL_DAC2_VOL - [4:0] */ + +/* + * R1540 (0x604) - DAC2 Left Mixer Routing + */ +#define WM8995_ADCR_TO_DAC2L 0x0020 /* ADCR_TO_DAC2L */ +#define WM8995_ADCR_TO_DAC2L_MASK 0x0020 /* ADCR_TO_DAC2L */ +#define WM8995_ADCR_TO_DAC2L_SHIFT 5 /* ADCR_TO_DAC2L */ +#define WM8995_ADCR_TO_DAC2L_WIDTH 1 /* ADCR_TO_DAC2L */ +#define WM8995_ADCL_TO_DAC2L 0x0010 /* ADCL_TO_DAC2L */ +#define WM8995_ADCL_TO_DAC2L_MASK 0x0010 /* ADCL_TO_DAC2L */ +#define WM8995_ADCL_TO_DAC2L_SHIFT 4 /* ADCL_TO_DAC2L */ +#define WM8995_ADCL_TO_DAC2L_WIDTH 1 /* ADCL_TO_DAC2L */ +#define WM8995_AIF2DACL_TO_DAC2L 0x0004 /* AIF2DACL_TO_DAC2L */ +#define WM8995_AIF2DACL_TO_DAC2L_MASK 0x0004 /* AIF2DACL_TO_DAC2L */ +#define WM8995_AIF2DACL_TO_DAC2L_SHIFT 2 /* AIF2DACL_TO_DAC2L */ +#define WM8995_AIF2DACL_TO_DAC2L_WIDTH 1 /* AIF2DACL_TO_DAC2L */ +#define WM8995_AIF1DAC2L_TO_DAC2L 0x0002 /* AIF1DAC2L_TO_DAC2L */ +#define WM8995_AIF1DAC2L_TO_DAC2L_MASK 0x0002 /* AIF1DAC2L_TO_DAC2L */ +#define WM8995_AIF1DAC2L_TO_DAC2L_SHIFT 1 /* AIF1DAC2L_TO_DAC2L */ +#define WM8995_AIF1DAC2L_TO_DAC2L_WIDTH 1 /* AIF1DAC2L_TO_DAC2L */ +#define WM8995_AIF1DAC1L_TO_DAC2L 0x0001 /* AIF1DAC1L_TO_DAC2L */ +#define WM8995_AIF1DAC1L_TO_DAC2L_MASK 0x0001 /* AIF1DAC1L_TO_DAC2L */ +#define WM8995_AIF1DAC1L_TO_DAC2L_SHIFT 0 /* AIF1DAC1L_TO_DAC2L */ +#define WM8995_AIF1DAC1L_TO_DAC2L_WIDTH 1 /* AIF1DAC1L_TO_DAC2L */ + +/* + * R1541 (0x605) - DAC2 Right Mixer Routing + */ +#define WM8995_ADCR_TO_DAC2R 0x0020 /* ADCR_TO_DAC2R */ +#define WM8995_ADCR_TO_DAC2R_MASK 0x0020 /* ADCR_TO_DAC2R */ +#define WM8995_ADCR_TO_DAC2R_SHIFT 5 /* ADCR_TO_DAC2R */ +#define WM8995_ADCR_TO_DAC2R_WIDTH 1 /* ADCR_TO_DAC2R */ +#define WM8995_ADCL_TO_DAC2R 0x0010 /* ADCL_TO_DAC2R */ +#define WM8995_ADCL_TO_DAC2R_MASK 0x0010 /* ADCL_TO_DAC2R */ +#define WM8995_ADCL_TO_DAC2R_SHIFT 4 /* ADCL_TO_DAC2R */ +#define WM8995_ADCL_TO_DAC2R_WIDTH 1 /* ADCL_TO_DAC2R */ +#define WM8995_AIF2DACR_TO_DAC2R 0x0004 /* AIF2DACR_TO_DAC2R */ +#define WM8995_AIF2DACR_TO_DAC2R_MASK 0x0004 /* AIF2DACR_TO_DAC2R */ +#define WM8995_AIF2DACR_TO_DAC2R_SHIFT 2 /* AIF2DACR_TO_DAC2R */ +#define WM8995_AIF2DACR_TO_DAC2R_WIDTH 1 /* AIF2DACR_TO_DAC2R */ +#define WM8995_AIF1DAC2R_TO_DAC2R 0x0002 /* AIF1DAC2R_TO_DAC2R */ +#define WM8995_AIF1DAC2R_TO_DAC2R_MASK 0x0002 /* AIF1DAC2R_TO_DAC2R */ +#define WM8995_AIF1DAC2R_TO_DAC2R_SHIFT 1 /* AIF1DAC2R_TO_DAC2R */ +#define WM8995_AIF1DAC2R_TO_DAC2R_WIDTH 1 /* AIF1DAC2R_TO_DAC2R */ +#define WM8995_AIF1DAC1R_TO_DAC2R 0x0001 /* AIF1DAC1R_TO_DAC2R */ +#define WM8995_AIF1DAC1R_TO_DAC2R_MASK 0x0001 /* AIF1DAC1R_TO_DAC2R */ +#define WM8995_AIF1DAC1R_TO_DAC2R_SHIFT 0 /* AIF1DAC1R_TO_DAC2R */ +#define WM8995_AIF1DAC1R_TO_DAC2R_WIDTH 1 /* AIF1DAC1R_TO_DAC2R */ + +/* + * R1542 (0x606) - AIF1 ADC1 Left Mixer Routing + */ +#define WM8995_ADC1L_TO_AIF1ADC1L 0x0002 /* ADC1L_TO_AIF1ADC1L */ +#define WM8995_ADC1L_TO_AIF1ADC1L_MASK 0x0002 /* ADC1L_TO_AIF1ADC1L */ +#define WM8995_ADC1L_TO_AIF1ADC1L_SHIFT 1 /* ADC1L_TO_AIF1ADC1L */ +#define WM8995_ADC1L_TO_AIF1ADC1L_WIDTH 1 /* ADC1L_TO_AIF1ADC1L */ +#define WM8995_AIF2DACL_TO_AIF1ADC1L 0x0001 /* AIF2DACL_TO_AIF1ADC1L */ +#define WM8995_AIF2DACL_TO_AIF1ADC1L_MASK 0x0001 /* AIF2DACL_TO_AIF1ADC1L */ +#define WM8995_AIF2DACL_TO_AIF1ADC1L_SHIFT 0 /* AIF2DACL_TO_AIF1ADC1L */ +#define WM8995_AIF2DACL_TO_AIF1ADC1L_WIDTH 1 /* AIF2DACL_TO_AIF1ADC1L */ + +/* + * R1543 (0x607) - AIF1 ADC1 Right Mixer Routing + */ +#define WM8995_ADC1R_TO_AIF1ADC1R 0x0002 /* ADC1R_TO_AIF1ADC1R */ +#define WM8995_ADC1R_TO_AIF1ADC1R_MASK 0x0002 /* ADC1R_TO_AIF1ADC1R */ +#define WM8995_ADC1R_TO_AIF1ADC1R_SHIFT 1 /* ADC1R_TO_AIF1ADC1R */ +#define WM8995_ADC1R_TO_AIF1ADC1R_WIDTH 1 /* ADC1R_TO_AIF1ADC1R */ +#define WM8995_AIF2DACR_TO_AIF1ADC1R 0x0001 /* AIF2DACR_TO_AIF1ADC1R */ +#define WM8995_AIF2DACR_TO_AIF1ADC1R_MASK 0x0001 /* AIF2DACR_TO_AIF1ADC1R */ +#define WM8995_AIF2DACR_TO_AIF1ADC1R_SHIFT 0 /* AIF2DACR_TO_AIF1ADC1R */ +#define WM8995_AIF2DACR_TO_AIF1ADC1R_WIDTH 1 /* AIF2DACR_TO_AIF1ADC1R */ + +/* + * R1544 (0x608) - AIF1 ADC2 Left Mixer Routing + */ +#define WM8995_ADC2L_TO_AIF1ADC2L 0x0002 /* ADC2L_TO_AIF1ADC2L */ +#define WM8995_ADC2L_TO_AIF1ADC2L_MASK 0x0002 /* ADC2L_TO_AIF1ADC2L */ +#define WM8995_ADC2L_TO_AIF1ADC2L_SHIFT 1 /* ADC2L_TO_AIF1ADC2L */ +#define WM8995_ADC2L_TO_AIF1ADC2L_WIDTH 1 /* ADC2L_TO_AIF1ADC2L */ +#define WM8995_AIF2DACL_TO_AIF1ADC2L 0x0001 /* AIF2DACL_TO_AIF1ADC2L */ +#define WM8995_AIF2DACL_TO_AIF1ADC2L_MASK 0x0001 /* AIF2DACL_TO_AIF1ADC2L */ +#define WM8995_AIF2DACL_TO_AIF1ADC2L_SHIFT 0 /* AIF2DACL_TO_AIF1ADC2L */ +#define WM8995_AIF2DACL_TO_AIF1ADC2L_WIDTH 1 /* AIF2DACL_TO_AIF1ADC2L */ + +/* + * R1545 (0x609) - AIF1 ADC2 Right mixer Routing + */ +#define WM8995_ADC2R_TO_AIF1ADC2R 0x0002 /* ADC2R_TO_AIF1ADC2R */ +#define WM8995_ADC2R_TO_AIF1ADC2R_MASK 0x0002 /* ADC2R_TO_AIF1ADC2R */ +#define WM8995_ADC2R_TO_AIF1ADC2R_SHIFT 1 /* ADC2R_TO_AIF1ADC2R */ +#define WM8995_ADC2R_TO_AIF1ADC2R_WIDTH 1 /* ADC2R_TO_AIF1ADC2R */ +#define WM8995_AIF2DACR_TO_AIF1ADC2R 0x0001 /* AIF2DACR_TO_AIF1ADC2R */ +#define WM8995_AIF2DACR_TO_AIF1ADC2R_MASK 0x0001 /* AIF2DACR_TO_AIF1ADC2R */ +#define WM8995_AIF2DACR_TO_AIF1ADC2R_SHIFT 0 /* AIF2DACR_TO_AIF1ADC2R */ +#define WM8995_AIF2DACR_TO_AIF1ADC2R_WIDTH 1 /* AIF2DACR_TO_AIF1ADC2R */ + +/* + * R1552 (0x610) - DAC Softmute + */ +#define WM8995_DAC_SOFTMUTEMODE 0x0002 /* DAC_SOFTMUTEMODE */ +#define WM8995_DAC_SOFTMUTEMODE_MASK 0x0002 /* DAC_SOFTMUTEMODE */ +#define WM8995_DAC_SOFTMUTEMODE_SHIFT 1 /* DAC_SOFTMUTEMODE */ +#define WM8995_DAC_SOFTMUTEMODE_WIDTH 1 /* DAC_SOFTMUTEMODE */ +#define WM8995_DAC_MUTERATE 0x0001 /* DAC_MUTERATE */ +#define WM8995_DAC_MUTERATE_MASK 0x0001 /* DAC_MUTERATE */ +#define WM8995_DAC_MUTERATE_SHIFT 0 /* DAC_MUTERATE */ +#define WM8995_DAC_MUTERATE_WIDTH 1 /* DAC_MUTERATE */ + +/* + * R1568 (0x620) - Oversampling + */ +#define WM8995_ADC_OSR128 0x0002 /* ADC_OSR128 */ +#define WM8995_ADC_OSR128_MASK 0x0002 /* ADC_OSR128 */ +#define WM8995_ADC_OSR128_SHIFT 1 /* ADC_OSR128 */ +#define WM8995_ADC_OSR128_WIDTH 1 /* ADC_OSR128 */ +#define WM8995_DAC_OSR128 0x0001 /* DAC_OSR128 */ +#define WM8995_DAC_OSR128_MASK 0x0001 /* DAC_OSR128 */ +#define WM8995_DAC_OSR128_SHIFT 0 /* DAC_OSR128 */ +#define WM8995_DAC_OSR128_WIDTH 1 /* DAC_OSR128 */ + +/* + * R1569 (0x621) - Sidetone + */ +#define WM8995_ST_LPF 0x1000 /* ST_LPF */ +#define WM8995_ST_LPF_MASK 0x1000 /* ST_LPF */ +#define WM8995_ST_LPF_SHIFT 12 /* ST_LPF */ +#define WM8995_ST_LPF_WIDTH 1 /* ST_LPF */ +#define WM8995_ST_HPF_CUT_MASK 0x0380 /* ST_HPF_CUT - [9:7] */ +#define WM8995_ST_HPF_CUT_SHIFT 7 /* ST_HPF_CUT - [9:7] */ +#define WM8995_ST_HPF_CUT_WIDTH 3 /* ST_HPF_CUT - [9:7] */ +#define WM8995_ST_HPF 0x0040 /* ST_HPF */ +#define WM8995_ST_HPF_MASK 0x0040 /* ST_HPF */ +#define WM8995_ST_HPF_SHIFT 6 /* ST_HPF */ +#define WM8995_ST_HPF_WIDTH 1 /* ST_HPF */ +#define WM8995_STR_SEL 0x0002 /* STR_SEL */ +#define WM8995_STR_SEL_MASK 0x0002 /* STR_SEL */ +#define WM8995_STR_SEL_SHIFT 1 /* STR_SEL */ +#define WM8995_STR_SEL_WIDTH 1 /* STR_SEL */ +#define WM8995_STL_SEL 0x0001 /* STL_SEL */ +#define WM8995_STL_SEL_MASK 0x0001 /* STL_SEL */ +#define WM8995_STL_SEL_SHIFT 0 /* STL_SEL */ +#define WM8995_STL_SEL_WIDTH 1 /* STL_SEL */ + +/* + * R1792 (0x700) - GPIO 1 + */ +#define WM8995_GP1_DIR 0x8000 /* GP1_DIR */ +#define WM8995_GP1_DIR_MASK 0x8000 /* GP1_DIR */ +#define WM8995_GP1_DIR_SHIFT 15 /* GP1_DIR */ +#define WM8995_GP1_DIR_WIDTH 1 /* GP1_DIR */ +#define WM8995_GP1_PU 0x4000 /* GP1_PU */ +#define WM8995_GP1_PU_MASK 0x4000 /* GP1_PU */ +#define WM8995_GP1_PU_SHIFT 14 /* GP1_PU */ +#define WM8995_GP1_PU_WIDTH 1 /* GP1_PU */ +#define WM8995_GP1_PD 0x2000 /* GP1_PD */ +#define WM8995_GP1_PD_MASK 0x2000 /* GP1_PD */ +#define WM8995_GP1_PD_SHIFT 13 /* GP1_PD */ +#define WM8995_GP1_PD_WIDTH 1 /* GP1_PD */ +#define WM8995_GP1_POL 0x0400 /* GP1_POL */ +#define WM8995_GP1_POL_MASK 0x0400 /* GP1_POL */ +#define WM8995_GP1_POL_SHIFT 10 /* GP1_POL */ +#define WM8995_GP1_POL_WIDTH 1 /* GP1_POL */ +#define WM8995_GP1_OP_CFG 0x0200 /* GP1_OP_CFG */ +#define WM8995_GP1_OP_CFG_MASK 0x0200 /* GP1_OP_CFG */ +#define WM8995_GP1_OP_CFG_SHIFT 9 /* GP1_OP_CFG */ +#define WM8995_GP1_OP_CFG_WIDTH 1 /* GP1_OP_CFG */ +#define WM8995_GP1_DB 0x0100 /* GP1_DB */ +#define WM8995_GP1_DB_MASK 0x0100 /* GP1_DB */ +#define WM8995_GP1_DB_SHIFT 8 /* GP1_DB */ +#define WM8995_GP1_DB_WIDTH 1 /* GP1_DB */ +#define WM8995_GP1_LVL 0x0040 /* GP1_LVL */ +#define WM8995_GP1_LVL_MASK 0x0040 /* GP1_LVL */ +#define WM8995_GP1_LVL_SHIFT 6 /* GP1_LVL */ +#define WM8995_GP1_LVL_WIDTH 1 /* GP1_LVL */ +#define WM8995_GP1_FN_MASK 0x001F /* GP1_FN - [4:0] */ +#define WM8995_GP1_FN_SHIFT 0 /* GP1_FN - [4:0] */ +#define WM8995_GP1_FN_WIDTH 5 /* GP1_FN - [4:0] */ + +/* + * R1793 (0x701) - GPIO 2 + */ +#define WM8995_GP2_DIR 0x8000 /* GP2_DIR */ +#define WM8995_GP2_DIR_MASK 0x8000 /* GP2_DIR */ +#define WM8995_GP2_DIR_SHIFT 15 /* GP2_DIR */ +#define WM8995_GP2_DIR_WIDTH 1 /* GP2_DIR */ +#define WM8995_GP2_PU 0x4000 /* GP2_PU */ +#define WM8995_GP2_PU_MASK 0x4000 /* GP2_PU */ +#define WM8995_GP2_PU_SHIFT 14 /* GP2_PU */ +#define WM8995_GP2_PU_WIDTH 1 /* GP2_PU */ +#define WM8995_GP2_PD 0x2000 /* GP2_PD */ +#define WM8995_GP2_PD_MASK 0x2000 /* GP2_PD */ +#define WM8995_GP2_PD_SHIFT 13 /* GP2_PD */ +#define WM8995_GP2_PD_WIDTH 1 /* GP2_PD */ +#define WM8995_GP2_POL 0x0400 /* GP2_POL */ +#define WM8995_GP2_POL_MASK 0x0400 /* GP2_POL */ +#define WM8995_GP2_POL_SHIFT 10 /* GP2_POL */ +#define WM8995_GP2_POL_WIDTH 1 /* GP2_POL */ +#define WM8995_GP2_OP_CFG 0x0200 /* GP2_OP_CFG */ +#define WM8995_GP2_OP_CFG_MASK 0x0200 /* GP2_OP_CFG */ +#define WM8995_GP2_OP_CFG_SHIFT 9 /* GP2_OP_CFG */ +#define WM8995_GP2_OP_CFG_WIDTH 1 /* GP2_OP_CFG */ +#define WM8995_GP2_DB 0x0100 /* GP2_DB */ +#define WM8995_GP2_DB_MASK 0x0100 /* GP2_DB */ +#define WM8995_GP2_DB_SHIFT 8 /* GP2_DB */ +#define WM8995_GP2_DB_WIDTH 1 /* GP2_DB */ +#define WM8995_GP2_LVL 0x0040 /* GP2_LVL */ +#define WM8995_GP2_LVL_MASK 0x0040 /* GP2_LVL */ +#define WM8995_GP2_LVL_SHIFT 6 /* GP2_LVL */ +#define WM8995_GP2_LVL_WIDTH 1 /* GP2_LVL */ +#define WM8995_GP2_FN_MASK 0x001F /* GP2_FN - [4:0] */ +#define WM8995_GP2_FN_SHIFT 0 /* GP2_FN - [4:0] */ +#define WM8995_GP2_FN_WIDTH 5 /* GP2_FN - [4:0] */ + +/* + * R1794 (0x702) - GPIO 3 + */ +#define WM8995_GP3_DIR 0x8000 /* GP3_DIR */ +#define WM8995_GP3_DIR_MASK 0x8000 /* GP3_DIR */ +#define WM8995_GP3_DIR_SHIFT 15 /* GP3_DIR */ +#define WM8995_GP3_DIR_WIDTH 1 /* GP3_DIR */ +#define WM8995_GP3_PU 0x4000 /* GP3_PU */ +#define WM8995_GP3_PU_MASK 0x4000 /* GP3_PU */ +#define WM8995_GP3_PU_SHIFT 14 /* GP3_PU */ +#define WM8995_GP3_PU_WIDTH 1 /* GP3_PU */ +#define WM8995_GP3_PD 0x2000 /* GP3_PD */ +#define WM8995_GP3_PD_MASK 0x2000 /* GP3_PD */ +#define WM8995_GP3_PD_SHIFT 13 /* GP3_PD */ +#define WM8995_GP3_PD_WIDTH 1 /* GP3_PD */ +#define WM8995_GP3_POL 0x0400 /* GP3_POL */ +#define WM8995_GP3_POL_MASK 0x0400 /* GP3_POL */ +#define WM8995_GP3_POL_SHIFT 10 /* GP3_POL */ +#define WM8995_GP3_POL_WIDTH 1 /* GP3_POL */ +#define WM8995_GP3_OP_CFG 0x0200 /* GP3_OP_CFG */ +#define WM8995_GP3_OP_CFG_MASK 0x0200 /* GP3_OP_CFG */ +#define WM8995_GP3_OP_CFG_SHIFT 9 /* GP3_OP_CFG */ +#define WM8995_GP3_OP_CFG_WIDTH 1 /* GP3_OP_CFG */ +#define WM8995_GP3_DB 0x0100 /* GP3_DB */ +#define WM8995_GP3_DB_MASK 0x0100 /* GP3_DB */ +#define WM8995_GP3_DB_SHIFT 8 /* GP3_DB */ +#define WM8995_GP3_DB_WIDTH 1 /* GP3_DB */ +#define WM8995_GP3_LVL 0x0040 /* GP3_LVL */ +#define WM8995_GP3_LVL_MASK 0x0040 /* GP3_LVL */ +#define WM8995_GP3_LVL_SHIFT 6 /* GP3_LVL */ +#define WM8995_GP3_LVL_WIDTH 1 /* GP3_LVL */ +#define WM8995_GP3_FN_MASK 0x001F /* GP3_FN - [4:0] */ +#define WM8995_GP3_FN_SHIFT 0 /* GP3_FN - [4:0] */ +#define WM8995_GP3_FN_WIDTH 5 /* GP3_FN - [4:0] */ + +/* + * R1795 (0x703) - GPIO 4 + */ +#define WM8995_GP4_DIR 0x8000 /* GP4_DIR */ +#define WM8995_GP4_DIR_MASK 0x8000 /* GP4_DIR */ +#define WM8995_GP4_DIR_SHIFT 15 /* GP4_DIR */ +#define WM8995_GP4_DIR_WIDTH 1 /* GP4_DIR */ +#define WM8995_GP4_PU 0x4000 /* GP4_PU */ +#define WM8995_GP4_PU_MASK 0x4000 /* GP4_PU */ +#define WM8995_GP4_PU_SHIFT 14 /* GP4_PU */ +#define WM8995_GP4_PU_WIDTH 1 /* GP4_PU */ +#define WM8995_GP4_PD 0x2000 /* GP4_PD */ +#define WM8995_GP4_PD_MASK 0x2000 /* GP4_PD */ +#define WM8995_GP4_PD_SHIFT 13 /* GP4_PD */ +#define WM8995_GP4_PD_WIDTH 1 /* GP4_PD */ +#define WM8995_GP4_POL 0x0400 /* GP4_POL */ +#define WM8995_GP4_POL_MASK 0x0400 /* GP4_POL */ +#define WM8995_GP4_POL_SHIFT 10 /* GP4_POL */ +#define WM8995_GP4_POL_WIDTH 1 /* GP4_POL */ +#define WM8995_GP4_OP_CFG 0x0200 /* GP4_OP_CFG */ +#define WM8995_GP4_OP_CFG_MASK 0x0200 /* GP4_OP_CFG */ +#define WM8995_GP4_OP_CFG_SHIFT 9 /* GP4_OP_CFG */ +#define WM8995_GP4_OP_CFG_WIDTH 1 /* GP4_OP_CFG */ +#define WM8995_GP4_DB 0x0100 /* GP4_DB */ +#define WM8995_GP4_DB_MASK 0x0100 /* GP4_DB */ +#define WM8995_GP4_DB_SHIFT 8 /* GP4_DB */ +#define WM8995_GP4_DB_WIDTH 1 /* GP4_DB */ +#define WM8995_GP4_LVL 0x0040 /* GP4_LVL */ +#define WM8995_GP4_LVL_MASK 0x0040 /* GP4_LVL */ +#define WM8995_GP4_LVL_SHIFT 6 /* GP4_LVL */ +#define WM8995_GP4_LVL_WIDTH 1 /* GP4_LVL */ +#define WM8995_GP4_FN_MASK 0x001F /* GP4_FN - [4:0] */ +#define WM8995_GP4_FN_SHIFT 0 /* GP4_FN - [4:0] */ +#define WM8995_GP4_FN_WIDTH 5 /* GP4_FN - [4:0] */ + +/* + * R1796 (0x704) - GPIO 5 + */ +#define WM8995_GP5_DIR 0x8000 /* GP5_DIR */ +#define WM8995_GP5_DIR_MASK 0x8000 /* GP5_DIR */ +#define WM8995_GP5_DIR_SHIFT 15 /* GP5_DIR */ +#define WM8995_GP5_DIR_WIDTH 1 /* GP5_DIR */ +#define WM8995_GP5_PU 0x4000 /* GP5_PU */ +#define WM8995_GP5_PU_MASK 0x4000 /* GP5_PU */ +#define WM8995_GP5_PU_SHIFT 14 /* GP5_PU */ +#define WM8995_GP5_PU_WIDTH 1 /* GP5_PU */ +#define WM8995_GP5_PD 0x2000 /* GP5_PD */ +#define WM8995_GP5_PD_MASK 0x2000 /* GP5_PD */ +#define WM8995_GP5_PD_SHIFT 13 /* GP5_PD */ +#define WM8995_GP5_PD_WIDTH 1 /* GP5_PD */ +#define WM8995_GP5_POL 0x0400 /* GP5_POL */ +#define WM8995_GP5_POL_MASK 0x0400 /* GP5_POL */ +#define WM8995_GP5_POL_SHIFT 10 /* GP5_POL */ +#define WM8995_GP5_POL_WIDTH 1 /* GP5_POL */ +#define WM8995_GP5_OP_CFG 0x0200 /* GP5_OP_CFG */ +#define WM8995_GP5_OP_CFG_MASK 0x0200 /* GP5_OP_CFG */ +#define WM8995_GP5_OP_CFG_SHIFT 9 /* GP5_OP_CFG */ +#define WM8995_GP5_OP_CFG_WIDTH 1 /* GP5_OP_CFG */ +#define WM8995_GP5_DB 0x0100 /* GP5_DB */ +#define WM8995_GP5_DB_MASK 0x0100 /* GP5_DB */ +#define WM8995_GP5_DB_SHIFT 8 /* GP5_DB */ +#define WM8995_GP5_DB_WIDTH 1 /* GP5_DB */ +#define WM8995_GP5_LVL 0x0040 /* GP5_LVL */ +#define WM8995_GP5_LVL_MASK 0x0040 /* GP5_LVL */ +#define WM8995_GP5_LVL_SHIFT 6 /* GP5_LVL */ +#define WM8995_GP5_LVL_WIDTH 1 /* GP5_LVL */ +#define WM8995_GP5_FN_MASK 0x001F /* GP5_FN - [4:0] */ +#define WM8995_GP5_FN_SHIFT 0 /* GP5_FN - [4:0] */ +#define WM8995_GP5_FN_WIDTH 5 /* GP5_FN - [4:0] */ + +/* + * R1797 (0x705) - GPIO 6 + */ +#define WM8995_GP6_DIR 0x8000 /* GP6_DIR */ +#define WM8995_GP6_DIR_MASK 0x8000 /* GP6_DIR */ +#define WM8995_GP6_DIR_SHIFT 15 /* GP6_DIR */ +#define WM8995_GP6_DIR_WIDTH 1 /* GP6_DIR */ +#define WM8995_GP6_PU 0x4000 /* GP6_PU */ +#define WM8995_GP6_PU_MASK 0x4000 /* GP6_PU */ +#define WM8995_GP6_PU_SHIFT 14 /* GP6_PU */ +#define WM8995_GP6_PU_WIDTH 1 /* GP6_PU */ +#define WM8995_GP6_PD 0x2000 /* GP6_PD */ +#define WM8995_GP6_PD_MASK 0x2000 /* GP6_PD */ +#define WM8995_GP6_PD_SHIFT 13 /* GP6_PD */ +#define WM8995_GP6_PD_WIDTH 1 /* GP6_PD */ +#define WM8995_GP6_POL 0x0400 /* GP6_POL */ +#define WM8995_GP6_POL_MASK 0x0400 /* GP6_POL */ +#define WM8995_GP6_POL_SHIFT 10 /* GP6_POL */ +#define WM8995_GP6_POL_WIDTH 1 /* GP6_POL */ +#define WM8995_GP6_OP_CFG 0x0200 /* GP6_OP_CFG */ +#define WM8995_GP6_OP_CFG_MASK 0x0200 /* GP6_OP_CFG */ +#define WM8995_GP6_OP_CFG_SHIFT 9 /* GP6_OP_CFG */ +#define WM8995_GP6_OP_CFG_WIDTH 1 /* GP6_OP_CFG */ +#define WM8995_GP6_DB 0x0100 /* GP6_DB */ +#define WM8995_GP6_DB_MASK 0x0100 /* GP6_DB */ +#define WM8995_GP6_DB_SHIFT 8 /* GP6_DB */ +#define WM8995_GP6_DB_WIDTH 1 /* GP6_DB */ +#define WM8995_GP6_LVL 0x0040 /* GP6_LVL */ +#define WM8995_GP6_LVL_MASK 0x0040 /* GP6_LVL */ +#define WM8995_GP6_LVL_SHIFT 6 /* GP6_LVL */ +#define WM8995_GP6_LVL_WIDTH 1 /* GP6_LVL */ +#define WM8995_GP6_FN_MASK 0x001F /* GP6_FN - [4:0] */ +#define WM8995_GP6_FN_SHIFT 0 /* GP6_FN - [4:0] */ +#define WM8995_GP6_FN_WIDTH 5 /* GP6_FN - [4:0] */ + +/* + * R1798 (0x706) - GPIO 7 + */ +#define WM8995_GP7_DIR 0x8000 /* GP7_DIR */ +#define WM8995_GP7_DIR_MASK 0x8000 /* GP7_DIR */ +#define WM8995_GP7_DIR_SHIFT 15 /* GP7_DIR */ +#define WM8995_GP7_DIR_WIDTH 1 /* GP7_DIR */ +#define WM8995_GP7_PU 0x4000 /* GP7_PU */ +#define WM8995_GP7_PU_MASK 0x4000 /* GP7_PU */ +#define WM8995_GP7_PU_SHIFT 14 /* GP7_PU */ +#define WM8995_GP7_PU_WIDTH 1 /* GP7_PU */ +#define WM8995_GP7_PD 0x2000 /* GP7_PD */ +#define WM8995_GP7_PD_MASK 0x2000 /* GP7_PD */ +#define WM8995_GP7_PD_SHIFT 13 /* GP7_PD */ +#define WM8995_GP7_PD_WIDTH 1 /* GP7_PD */ +#define WM8995_GP7_POL 0x0400 /* GP7_POL */ +#define WM8995_GP7_POL_MASK 0x0400 /* GP7_POL */ +#define WM8995_GP7_POL_SHIFT 10 /* GP7_POL */ +#define WM8995_GP7_POL_WIDTH 1 /* GP7_POL */ +#define WM8995_GP7_OP_CFG 0x0200 /* GP7_OP_CFG */ +#define WM8995_GP7_OP_CFG_MASK 0x0200 /* GP7_OP_CFG */ +#define WM8995_GP7_OP_CFG_SHIFT 9 /* GP7_OP_CFG */ +#define WM8995_GP7_OP_CFG_WIDTH 1 /* GP7_OP_CFG */ +#define WM8995_GP7_DB 0x0100 /* GP7_DB */ +#define WM8995_GP7_DB_MASK 0x0100 /* GP7_DB */ +#define WM8995_GP7_DB_SHIFT 8 /* GP7_DB */ +#define WM8995_GP7_DB_WIDTH 1 /* GP7_DB */ +#define WM8995_GP7_LVL 0x0040 /* GP7_LVL */ +#define WM8995_GP7_LVL_MASK 0x0040 /* GP7_LVL */ +#define WM8995_GP7_LVL_SHIFT 6 /* GP7_LVL */ +#define WM8995_GP7_LVL_WIDTH 1 /* GP7_LVL */ +#define WM8995_GP7_FN_MASK 0x001F /* GP7_FN - [4:0] */ +#define WM8995_GP7_FN_SHIFT 0 /* GP7_FN - [4:0] */ +#define WM8995_GP7_FN_WIDTH 5 /* GP7_FN - [4:0] */ + +/* + * R1799 (0x707) - GPIO 8 + */ +#define WM8995_GP8_DIR 0x8000 /* GP8_DIR */ +#define WM8995_GP8_DIR_MASK 0x8000 /* GP8_DIR */ +#define WM8995_GP8_DIR_SHIFT 15 /* GP8_DIR */ +#define WM8995_GP8_DIR_WIDTH 1 /* GP8_DIR */ +#define WM8995_GP8_PU 0x4000 /* GP8_PU */ +#define WM8995_GP8_PU_MASK 0x4000 /* GP8_PU */ +#define WM8995_GP8_PU_SHIFT 14 /* GP8_PU */ +#define WM8995_GP8_PU_WIDTH 1 /* GP8_PU */ +#define WM8995_GP8_PD 0x2000 /* GP8_PD */ +#define WM8995_GP8_PD_MASK 0x2000 /* GP8_PD */ +#define WM8995_GP8_PD_SHIFT 13 /* GP8_PD */ +#define WM8995_GP8_PD_WIDTH 1 /* GP8_PD */ +#define WM8995_GP8_POL 0x0400 /* GP8_POL */ +#define WM8995_GP8_POL_MASK 0x0400 /* GP8_POL */ +#define WM8995_GP8_POL_SHIFT 10 /* GP8_POL */ +#define WM8995_GP8_POL_WIDTH 1 /* GP8_POL */ +#define WM8995_GP8_OP_CFG 0x0200 /* GP8_OP_CFG */ +#define WM8995_GP8_OP_CFG_MASK 0x0200 /* GP8_OP_CFG */ +#define WM8995_GP8_OP_CFG_SHIFT 9 /* GP8_OP_CFG */ +#define WM8995_GP8_OP_CFG_WIDTH 1 /* GP8_OP_CFG */ +#define WM8995_GP8_DB 0x0100 /* GP8_DB */ +#define WM8995_GP8_DB_MASK 0x0100 /* GP8_DB */ +#define WM8995_GP8_DB_SHIFT 8 /* GP8_DB */ +#define WM8995_GP8_DB_WIDTH 1 /* GP8_DB */ +#define WM8995_GP8_LVL 0x0040 /* GP8_LVL */ +#define WM8995_GP8_LVL_MASK 0x0040 /* GP8_LVL */ +#define WM8995_GP8_LVL_SHIFT 6 /* GP8_LVL */ +#define WM8995_GP8_LVL_WIDTH 1 /* GP8_LVL */ +#define WM8995_GP8_FN_MASK 0x001F /* GP8_FN - [4:0] */ +#define WM8995_GP8_FN_SHIFT 0 /* GP8_FN - [4:0] */ +#define WM8995_GP8_FN_WIDTH 5 /* GP8_FN - [4:0] */ + +/* + * R1800 (0x708) - GPIO 9 + */ +#define WM8995_GP9_DIR 0x8000 /* GP9_DIR */ +#define WM8995_GP9_DIR_MASK 0x8000 /* GP9_DIR */ +#define WM8995_GP9_DIR_SHIFT 15 /* GP9_DIR */ +#define WM8995_GP9_DIR_WIDTH 1 /* GP9_DIR */ +#define WM8995_GP9_PU 0x4000 /* GP9_PU */ +#define WM8995_GP9_PU_MASK 0x4000 /* GP9_PU */ +#define WM8995_GP9_PU_SHIFT 14 /* GP9_PU */ +#define WM8995_GP9_PU_WIDTH 1 /* GP9_PU */ +#define WM8995_GP9_PD 0x2000 /* GP9_PD */ +#define WM8995_GP9_PD_MASK 0x2000 /* GP9_PD */ +#define WM8995_GP9_PD_SHIFT 13 /* GP9_PD */ +#define WM8995_GP9_PD_WIDTH 1 /* GP9_PD */ +#define WM8995_GP9_POL 0x0400 /* GP9_POL */ +#define WM8995_GP9_POL_MASK 0x0400 /* GP9_POL */ +#define WM8995_GP9_POL_SHIFT 10 /* GP9_POL */ +#define WM8995_GP9_POL_WIDTH 1 /* GP9_POL */ +#define WM8995_GP9_OP_CFG 0x0200 /* GP9_OP_CFG */ +#define WM8995_GP9_OP_CFG_MASK 0x0200 /* GP9_OP_CFG */ +#define WM8995_GP9_OP_CFG_SHIFT 9 /* GP9_OP_CFG */ +#define WM8995_GP9_OP_CFG_WIDTH 1 /* GP9_OP_CFG */ +#define WM8995_GP9_DB 0x0100 /* GP9_DB */ +#define WM8995_GP9_DB_MASK 0x0100 /* GP9_DB */ +#define WM8995_GP9_DB_SHIFT 8 /* GP9_DB */ +#define WM8995_GP9_DB_WIDTH 1 /* GP9_DB */ +#define WM8995_GP9_LVL 0x0040 /* GP9_LVL */ +#define WM8995_GP9_LVL_MASK 0x0040 /* GP9_LVL */ +#define WM8995_GP9_LVL_SHIFT 6 /* GP9_LVL */ +#define WM8995_GP9_LVL_WIDTH 1 /* GP9_LVL */ +#define WM8995_GP9_FN_MASK 0x001F /* GP9_FN - [4:0] */ +#define WM8995_GP9_FN_SHIFT 0 /* GP9_FN - [4:0] */ +#define WM8995_GP9_FN_WIDTH 5 /* GP9_FN - [4:0] */ + +/* + * R1801 (0x709) - GPIO 10 + */ +#define WM8995_GP10_DIR 0x8000 /* GP10_DIR */ +#define WM8995_GP10_DIR_MASK 0x8000 /* GP10_DIR */ +#define WM8995_GP10_DIR_SHIFT 15 /* GP10_DIR */ +#define WM8995_GP10_DIR_WIDTH 1 /* GP10_DIR */ +#define WM8995_GP10_PU 0x4000 /* GP10_PU */ +#define WM8995_GP10_PU_MASK 0x4000 /* GP10_PU */ +#define WM8995_GP10_PU_SHIFT 14 /* GP10_PU */ +#define WM8995_GP10_PU_WIDTH 1 /* GP10_PU */ +#define WM8995_GP10_PD 0x2000 /* GP10_PD */ +#define WM8995_GP10_PD_MASK 0x2000 /* GP10_PD */ +#define WM8995_GP10_PD_SHIFT 13 /* GP10_PD */ +#define WM8995_GP10_PD_WIDTH 1 /* GP10_PD */ +#define WM8995_GP10_POL 0x0400 /* GP10_POL */ +#define WM8995_GP10_POL_MASK 0x0400 /* GP10_POL */ +#define WM8995_GP10_POL_SHIFT 10 /* GP10_POL */ +#define WM8995_GP10_POL_WIDTH 1 /* GP10_POL */ +#define WM8995_GP10_OP_CFG 0x0200 /* GP10_OP_CFG */ +#define WM8995_GP10_OP_CFG_MASK 0x0200 /* GP10_OP_CFG */ +#define WM8995_GP10_OP_CFG_SHIFT 9 /* GP10_OP_CFG */ +#define WM8995_GP10_OP_CFG_WIDTH 1 /* GP10_OP_CFG */ +#define WM8995_GP10_DB 0x0100 /* GP10_DB */ +#define WM8995_GP10_DB_MASK 0x0100 /* GP10_DB */ +#define WM8995_GP10_DB_SHIFT 8 /* GP10_DB */ +#define WM8995_GP10_DB_WIDTH 1 /* GP10_DB */ +#define WM8995_GP10_LVL 0x0040 /* GP10_LVL */ +#define WM8995_GP10_LVL_MASK 0x0040 /* GP10_LVL */ +#define WM8995_GP10_LVL_SHIFT 6 /* GP10_LVL */ +#define WM8995_GP10_LVL_WIDTH 1 /* GP10_LVL */ +#define WM8995_GP10_FN_MASK 0x001F /* GP10_FN - [4:0] */ +#define WM8995_GP10_FN_SHIFT 0 /* GP10_FN - [4:0] */ +#define WM8995_GP10_FN_WIDTH 5 /* GP10_FN - [4:0] */ + +/* + * R1802 (0x70A) - GPIO 11 + */ +#define WM8995_GP11_DIR 0x8000 /* GP11_DIR */ +#define WM8995_GP11_DIR_MASK 0x8000 /* GP11_DIR */ +#define WM8995_GP11_DIR_SHIFT 15 /* GP11_DIR */ +#define WM8995_GP11_DIR_WIDTH 1 /* GP11_DIR */ +#define WM8995_GP11_PU 0x4000 /* GP11_PU */ +#define WM8995_GP11_PU_MASK 0x4000 /* GP11_PU */ +#define WM8995_GP11_PU_SHIFT 14 /* GP11_PU */ +#define WM8995_GP11_PU_WIDTH 1 /* GP11_PU */ +#define WM8995_GP11_PD 0x2000 /* GP11_PD */ +#define WM8995_GP11_PD_MASK 0x2000 /* GP11_PD */ +#define WM8995_GP11_PD_SHIFT 13 /* GP11_PD */ +#define WM8995_GP11_PD_WIDTH 1 /* GP11_PD */ +#define WM8995_GP11_POL 0x0400 /* GP11_POL */ +#define WM8995_GP11_POL_MASK 0x0400 /* GP11_POL */ +#define WM8995_GP11_POL_SHIFT 10 /* GP11_POL */ +#define WM8995_GP11_POL_WIDTH 1 /* GP11_POL */ +#define WM8995_GP11_OP_CFG 0x0200 /* GP11_OP_CFG */ +#define WM8995_GP11_OP_CFG_MASK 0x0200 /* GP11_OP_CFG */ +#define WM8995_GP11_OP_CFG_SHIFT 9 /* GP11_OP_CFG */ +#define WM8995_GP11_OP_CFG_WIDTH 1 /* GP11_OP_CFG */ +#define WM8995_GP11_DB 0x0100 /* GP11_DB */ +#define WM8995_GP11_DB_MASK 0x0100 /* GP11_DB */ +#define WM8995_GP11_DB_SHIFT 8 /* GP11_DB */ +#define WM8995_GP11_DB_WIDTH 1 /* GP11_DB */ +#define WM8995_GP11_LVL 0x0040 /* GP11_LVL */ +#define WM8995_GP11_LVL_MASK 0x0040 /* GP11_LVL */ +#define WM8995_GP11_LVL_SHIFT 6 /* GP11_LVL */ +#define WM8995_GP11_LVL_WIDTH 1 /* GP11_LVL */ +#define WM8995_GP11_FN_MASK 0x001F /* GP11_FN - [4:0] */ +#define WM8995_GP11_FN_SHIFT 0 /* GP11_FN - [4:0] */ +#define WM8995_GP11_FN_WIDTH 5 /* GP11_FN - [4:0] */ + +/* + * R1803 (0x70B) - GPIO 12 + */ +#define WM8995_GP12_DIR 0x8000 /* GP12_DIR */ +#define WM8995_GP12_DIR_MASK 0x8000 /* GP12_DIR */ +#define WM8995_GP12_DIR_SHIFT 15 /* GP12_DIR */ +#define WM8995_GP12_DIR_WIDTH 1 /* GP12_DIR */ +#define WM8995_GP12_PU 0x4000 /* GP12_PU */ +#define WM8995_GP12_PU_MASK 0x4000 /* GP12_PU */ +#define WM8995_GP12_PU_SHIFT 14 /* GP12_PU */ +#define WM8995_GP12_PU_WIDTH 1 /* GP12_PU */ +#define WM8995_GP12_PD 0x2000 /* GP12_PD */ +#define WM8995_GP12_PD_MASK 0x2000 /* GP12_PD */ +#define WM8995_GP12_PD_SHIFT 13 /* GP12_PD */ +#define WM8995_GP12_PD_WIDTH 1 /* GP12_PD */ +#define WM8995_GP12_POL 0x0400 /* GP12_POL */ +#define WM8995_GP12_POL_MASK 0x0400 /* GP12_POL */ +#define WM8995_GP12_POL_SHIFT 10 /* GP12_POL */ +#define WM8995_GP12_POL_WIDTH 1 /* GP12_POL */ +#define WM8995_GP12_OP_CFG 0x0200 /* GP12_OP_CFG */ +#define WM8995_GP12_OP_CFG_MASK 0x0200 /* GP12_OP_CFG */ +#define WM8995_GP12_OP_CFG_SHIFT 9 /* GP12_OP_CFG */ +#define WM8995_GP12_OP_CFG_WIDTH 1 /* GP12_OP_CFG */ +#define WM8995_GP12_DB 0x0100 /* GP12_DB */ +#define WM8995_GP12_DB_MASK 0x0100 /* GP12_DB */ +#define WM8995_GP12_DB_SHIFT 8 /* GP12_DB */ +#define WM8995_GP12_DB_WIDTH 1 /* GP12_DB */ +#define WM8995_GP12_LVL 0x0040 /* GP12_LVL */ +#define WM8995_GP12_LVL_MASK 0x0040 /* GP12_LVL */ +#define WM8995_GP12_LVL_SHIFT 6 /* GP12_LVL */ +#define WM8995_GP12_LVL_WIDTH 1 /* GP12_LVL */ +#define WM8995_GP12_FN_MASK 0x001F /* GP12_FN - [4:0] */ +#define WM8995_GP12_FN_SHIFT 0 /* GP12_FN - [4:0] */ +#define WM8995_GP12_FN_WIDTH 5 /* GP12_FN - [4:0] */ + +/* + * R1804 (0x70C) - GPIO 13 + */ +#define WM8995_GP13_DIR 0x8000 /* GP13_DIR */ +#define WM8995_GP13_DIR_MASK 0x8000 /* GP13_DIR */ +#define WM8995_GP13_DIR_SHIFT 15 /* GP13_DIR */ +#define WM8995_GP13_DIR_WIDTH 1 /* GP13_DIR */ +#define WM8995_GP13_PU 0x4000 /* GP13_PU */ +#define WM8995_GP13_PU_MASK 0x4000 /* GP13_PU */ +#define WM8995_GP13_PU_SHIFT 14 /* GP13_PU */ +#define WM8995_GP13_PU_WIDTH 1 /* GP13_PU */ +#define WM8995_GP13_PD 0x2000 /* GP13_PD */ +#define WM8995_GP13_PD_MASK 0x2000 /* GP13_PD */ +#define WM8995_GP13_PD_SHIFT 13 /* GP13_PD */ +#define WM8995_GP13_PD_WIDTH 1 /* GP13_PD */ +#define WM8995_GP13_POL 0x0400 /* GP13_POL */ +#define WM8995_GP13_POL_MASK 0x0400 /* GP13_POL */ +#define WM8995_GP13_POL_SHIFT 10 /* GP13_POL */ +#define WM8995_GP13_POL_WIDTH 1 /* GP13_POL */ +#define WM8995_GP13_OP_CFG 0x0200 /* GP13_OP_CFG */ +#define WM8995_GP13_OP_CFG_MASK 0x0200 /* GP13_OP_CFG */ +#define WM8995_GP13_OP_CFG_SHIFT 9 /* GP13_OP_CFG */ +#define WM8995_GP13_OP_CFG_WIDTH 1 /* GP13_OP_CFG */ +#define WM8995_GP13_DB 0x0100 /* GP13_DB */ +#define WM8995_GP13_DB_MASK 0x0100 /* GP13_DB */ +#define WM8995_GP13_DB_SHIFT 8 /* GP13_DB */ +#define WM8995_GP13_DB_WIDTH 1 /* GP13_DB */ +#define WM8995_GP13_LVL 0x0040 /* GP13_LVL */ +#define WM8995_GP13_LVL_MASK 0x0040 /* GP13_LVL */ +#define WM8995_GP13_LVL_SHIFT 6 /* GP13_LVL */ +#define WM8995_GP13_LVL_WIDTH 1 /* GP13_LVL */ +#define WM8995_GP13_FN_MASK 0x001F /* GP13_FN - [4:0] */ +#define WM8995_GP13_FN_SHIFT 0 /* GP13_FN - [4:0] */ +#define WM8995_GP13_FN_WIDTH 5 /* GP13_FN - [4:0] */ + +/* + * R1805 (0x70D) - GPIO 14 + */ +#define WM8995_GP14_DIR 0x8000 /* GP14_DIR */ +#define WM8995_GP14_DIR_MASK 0x8000 /* GP14_DIR */ +#define WM8995_GP14_DIR_SHIFT 15 /* GP14_DIR */ +#define WM8995_GP14_DIR_WIDTH 1 /* GP14_DIR */ +#define WM8995_GP14_PU 0x4000 /* GP14_PU */ +#define WM8995_GP14_PU_MASK 0x4000 /* GP14_PU */ +#define WM8995_GP14_PU_SHIFT 14 /* GP14_PU */ +#define WM8995_GP14_PU_WIDTH 1 /* GP14_PU */ +#define WM8995_GP14_PD 0x2000 /* GP14_PD */ +#define WM8995_GP14_PD_MASK 0x2000 /* GP14_PD */ +#define WM8995_GP14_PD_SHIFT 13 /* GP14_PD */ +#define WM8995_GP14_PD_WIDTH 1 /* GP14_PD */ +#define WM8995_GP14_POL 0x0400 /* GP14_POL */ +#define WM8995_GP14_POL_MASK 0x0400 /* GP14_POL */ +#define WM8995_GP14_POL_SHIFT 10 /* GP14_POL */ +#define WM8995_GP14_POL_WIDTH 1 /* GP14_POL */ +#define WM8995_GP14_OP_CFG 0x0200 /* GP14_OP_CFG */ +#define WM8995_GP14_OP_CFG_MASK 0x0200 /* GP14_OP_CFG */ +#define WM8995_GP14_OP_CFG_SHIFT 9 /* GP14_OP_CFG */ +#define WM8995_GP14_OP_CFG_WIDTH 1 /* GP14_OP_CFG */ +#define WM8995_GP14_DB 0x0100 /* GP14_DB */ +#define WM8995_GP14_DB_MASK 0x0100 /* GP14_DB */ +#define WM8995_GP14_DB_SHIFT 8 /* GP14_DB */ +#define WM8995_GP14_DB_WIDTH 1 /* GP14_DB */ +#define WM8995_GP14_LVL 0x0040 /* GP14_LVL */ +#define WM8995_GP14_LVL_MASK 0x0040 /* GP14_LVL */ +#define WM8995_GP14_LVL_SHIFT 6 /* GP14_LVL */ +#define WM8995_GP14_LVL_WIDTH 1 /* GP14_LVL */ +#define WM8995_GP14_FN_MASK 0x001F /* GP14_FN - [4:0] */ +#define WM8995_GP14_FN_SHIFT 0 /* GP14_FN - [4:0] */ +#define WM8995_GP14_FN_WIDTH 5 /* GP14_FN - [4:0] */ + +/* + * R1824 (0x720) - Pull Control (1) + */ +#define WM8995_DMICDAT3_PD 0x4000 /* DMICDAT3_PD */ +#define WM8995_DMICDAT3_PD_MASK 0x4000 /* DMICDAT3_PD */ +#define WM8995_DMICDAT3_PD_SHIFT 14 /* DMICDAT3_PD */ +#define WM8995_DMICDAT3_PD_WIDTH 1 /* DMICDAT3_PD */ +#define WM8995_DMICDAT2_PD 0x1000 /* DMICDAT2_PD */ +#define WM8995_DMICDAT2_PD_MASK 0x1000 /* DMICDAT2_PD */ +#define WM8995_DMICDAT2_PD_SHIFT 12 /* DMICDAT2_PD */ +#define WM8995_DMICDAT2_PD_WIDTH 1 /* DMICDAT2_PD */ +#define WM8995_DMICDAT1_PD 0x0400 /* DMICDAT1_PD */ +#define WM8995_DMICDAT1_PD_MASK 0x0400 /* DMICDAT1_PD */ +#define WM8995_DMICDAT1_PD_SHIFT 10 /* DMICDAT1_PD */ +#define WM8995_DMICDAT1_PD_WIDTH 1 /* DMICDAT1_PD */ +#define WM8995_MCLK2_PU 0x0200 /* MCLK2_PU */ +#define WM8995_MCLK2_PU_MASK 0x0200 /* MCLK2_PU */ +#define WM8995_MCLK2_PU_SHIFT 9 /* MCLK2_PU */ +#define WM8995_MCLK2_PU_WIDTH 1 /* MCLK2_PU */ +#define WM8995_MCLK2_PD 0x0100 /* MCLK2_PD */ +#define WM8995_MCLK2_PD_MASK 0x0100 /* MCLK2_PD */ +#define WM8995_MCLK2_PD_SHIFT 8 /* MCLK2_PD */ +#define WM8995_MCLK2_PD_WIDTH 1 /* MCLK2_PD */ +#define WM8995_MCLK1_PU 0x0080 /* MCLK1_PU */ +#define WM8995_MCLK1_PU_MASK 0x0080 /* MCLK1_PU */ +#define WM8995_MCLK1_PU_SHIFT 7 /* MCLK1_PU */ +#define WM8995_MCLK1_PU_WIDTH 1 /* MCLK1_PU */ +#define WM8995_MCLK1_PD 0x0040 /* MCLK1_PD */ +#define WM8995_MCLK1_PD_MASK 0x0040 /* MCLK1_PD */ +#define WM8995_MCLK1_PD_SHIFT 6 /* MCLK1_PD */ +#define WM8995_MCLK1_PD_WIDTH 1 /* MCLK1_PD */ +#define WM8995_DACDAT1_PU 0x0020 /* DACDAT1_PU */ +#define WM8995_DACDAT1_PU_MASK 0x0020 /* DACDAT1_PU */ +#define WM8995_DACDAT1_PU_SHIFT 5 /* DACDAT1_PU */ +#define WM8995_DACDAT1_PU_WIDTH 1 /* DACDAT1_PU */ +#define WM8995_DACDAT1_PD 0x0010 /* DACDAT1_PD */ +#define WM8995_DACDAT1_PD_MASK 0x0010 /* DACDAT1_PD */ +#define WM8995_DACDAT1_PD_SHIFT 4 /* DACDAT1_PD */ +#define WM8995_DACDAT1_PD_WIDTH 1 /* DACDAT1_PD */ +#define WM8995_DACLRCLK1_PU 0x0008 /* DACLRCLK1_PU */ +#define WM8995_DACLRCLK1_PU_MASK 0x0008 /* DACLRCLK1_PU */ +#define WM8995_DACLRCLK1_PU_SHIFT 3 /* DACLRCLK1_PU */ +#define WM8995_DACLRCLK1_PU_WIDTH 1 /* DACLRCLK1_PU */ +#define WM8995_DACLRCLK1_PD 0x0004 /* DACLRCLK1_PD */ +#define WM8995_DACLRCLK1_PD_MASK 0x0004 /* DACLRCLK1_PD */ +#define WM8995_DACLRCLK1_PD_SHIFT 2 /* DACLRCLK1_PD */ +#define WM8995_DACLRCLK1_PD_WIDTH 1 /* DACLRCLK1_PD */ +#define WM8995_BCLK1_PU 0x0002 /* BCLK1_PU */ +#define WM8995_BCLK1_PU_MASK 0x0002 /* BCLK1_PU */ +#define WM8995_BCLK1_PU_SHIFT 1 /* BCLK1_PU */ +#define WM8995_BCLK1_PU_WIDTH 1 /* BCLK1_PU */ +#define WM8995_BCLK1_PD 0x0001 /* BCLK1_PD */ +#define WM8995_BCLK1_PD_MASK 0x0001 /* BCLK1_PD */ +#define WM8995_BCLK1_PD_SHIFT 0 /* BCLK1_PD */ +#define WM8995_BCLK1_PD_WIDTH 1 /* BCLK1_PD */ + +/* + * R1825 (0x721) - Pull Control (2) + */ +#define WM8995_LDO1ENA_PD 0x0010 /* LDO1ENA_PD */ +#define WM8995_LDO1ENA_PD_MASK 0x0010 /* LDO1ENA_PD */ +#define WM8995_LDO1ENA_PD_SHIFT 4 /* LDO1ENA_PD */ +#define WM8995_LDO1ENA_PD_WIDTH 1 /* LDO1ENA_PD */ +#define WM8995_MODE_PD 0x0004 /* MODE_PD */ +#define WM8995_MODE_PD_MASK 0x0004 /* MODE_PD */ +#define WM8995_MODE_PD_SHIFT 2 /* MODE_PD */ +#define WM8995_MODE_PD_WIDTH 1 /* MODE_PD */ +#define WM8995_CSNADDR_PD 0x0001 /* CSNADDR_PD */ +#define WM8995_CSNADDR_PD_MASK 0x0001 /* CSNADDR_PD */ +#define WM8995_CSNADDR_PD_SHIFT 0 /* CSNADDR_PD */ +#define WM8995_CSNADDR_PD_WIDTH 1 /* CSNADDR_PD */ + +/* + * R1840 (0x730) - Interrupt Status 1 + */ +#define WM8995_GP14_EINT 0x2000 /* GP14_EINT */ +#define WM8995_GP14_EINT_MASK 0x2000 /* GP14_EINT */ +#define WM8995_GP14_EINT_SHIFT 13 /* GP14_EINT */ +#define WM8995_GP14_EINT_WIDTH 1 /* GP14_EINT */ +#define WM8995_GP13_EINT 0x1000 /* GP13_EINT */ +#define WM8995_GP13_EINT_MASK 0x1000 /* GP13_EINT */ +#define WM8995_GP13_EINT_SHIFT 12 /* GP13_EINT */ +#define WM8995_GP13_EINT_WIDTH 1 /* GP13_EINT */ +#define WM8995_GP12_EINT 0x0800 /* GP12_EINT */ +#define WM8995_GP12_EINT_MASK 0x0800 /* GP12_EINT */ +#define WM8995_GP12_EINT_SHIFT 11 /* GP12_EINT */ +#define WM8995_GP12_EINT_WIDTH 1 /* GP12_EINT */ +#define WM8995_GP11_EINT 0x0400 /* GP11_EINT */ +#define WM8995_GP11_EINT_MASK 0x0400 /* GP11_EINT */ +#define WM8995_GP11_EINT_SHIFT 10 /* GP11_EINT */ +#define WM8995_GP11_EINT_WIDTH 1 /* GP11_EINT */ +#define WM8995_GP10_EINT 0x0200 /* GP10_EINT */ +#define WM8995_GP10_EINT_MASK 0x0200 /* GP10_EINT */ +#define WM8995_GP10_EINT_SHIFT 9 /* GP10_EINT */ +#define WM8995_GP10_EINT_WIDTH 1 /* GP10_EINT */ +#define WM8995_GP9_EINT 0x0100 /* GP9_EINT */ +#define WM8995_GP9_EINT_MASK 0x0100 /* GP9_EINT */ +#define WM8995_GP9_EINT_SHIFT 8 /* GP9_EINT */ +#define WM8995_GP9_EINT_WIDTH 1 /* GP9_EINT */ +#define WM8995_GP8_EINT 0x0080 /* GP8_EINT */ +#define WM8995_GP8_EINT_MASK 0x0080 /* GP8_EINT */ +#define WM8995_GP8_EINT_SHIFT 7 /* GP8_EINT */ +#define WM8995_GP8_EINT_WIDTH 1 /* GP8_EINT */ +#define WM8995_GP7_EINT 0x0040 /* GP7_EINT */ +#define WM8995_GP7_EINT_MASK 0x0040 /* GP7_EINT */ +#define WM8995_GP7_EINT_SHIFT 6 /* GP7_EINT */ +#define WM8995_GP7_EINT_WIDTH 1 /* GP7_EINT */ +#define WM8995_GP6_EINT 0x0020 /* GP6_EINT */ +#define WM8995_GP6_EINT_MASK 0x0020 /* GP6_EINT */ +#define WM8995_GP6_EINT_SHIFT 5 /* GP6_EINT */ +#define WM8995_GP6_EINT_WIDTH 1 /* GP6_EINT */ +#define WM8995_GP5_EINT 0x0010 /* GP5_EINT */ +#define WM8995_GP5_EINT_MASK 0x0010 /* GP5_EINT */ +#define WM8995_GP5_EINT_SHIFT 4 /* GP5_EINT */ +#define WM8995_GP5_EINT_WIDTH 1 /* GP5_EINT */ +#define WM8995_GP4_EINT 0x0008 /* GP4_EINT */ +#define WM8995_GP4_EINT_MASK 0x0008 /* GP4_EINT */ +#define WM8995_GP4_EINT_SHIFT 3 /* GP4_EINT */ +#define WM8995_GP4_EINT_WIDTH 1 /* GP4_EINT */ +#define WM8995_GP3_EINT 0x0004 /* GP3_EINT */ +#define WM8995_GP3_EINT_MASK 0x0004 /* GP3_EINT */ +#define WM8995_GP3_EINT_SHIFT 2 /* GP3_EINT */ +#define WM8995_GP3_EINT_WIDTH 1 /* GP3_EINT */ +#define WM8995_GP2_EINT 0x0002 /* GP2_EINT */ +#define WM8995_GP2_EINT_MASK 0x0002 /* GP2_EINT */ +#define WM8995_GP2_EINT_SHIFT 1 /* GP2_EINT */ +#define WM8995_GP2_EINT_WIDTH 1 /* GP2_EINT */ +#define WM8995_GP1_EINT 0x0001 /* GP1_EINT */ +#define WM8995_GP1_EINT_MASK 0x0001 /* GP1_EINT */ +#define WM8995_GP1_EINT_SHIFT 0 /* GP1_EINT */ +#define WM8995_GP1_EINT_WIDTH 1 /* GP1_EINT */ + +/* + * R1841 (0x731) - Interrupt Status 2 + */ +#define WM8995_DCS_DONE_23_EINT 0x1000 /* DCS_DONE_23_EINT */ +#define WM8995_DCS_DONE_23_EINT_MASK 0x1000 /* DCS_DONE_23_EINT */ +#define WM8995_DCS_DONE_23_EINT_SHIFT 12 /* DCS_DONE_23_EINT */ +#define WM8995_DCS_DONE_23_EINT_WIDTH 1 /* DCS_DONE_23_EINT */ +#define WM8995_DCS_DONE_01_EINT 0x0800 /* DCS_DONE_01_EINT */ +#define WM8995_DCS_DONE_01_EINT_MASK 0x0800 /* DCS_DONE_01_EINT */ +#define WM8995_DCS_DONE_01_EINT_SHIFT 11 /* DCS_DONE_01_EINT */ +#define WM8995_DCS_DONE_01_EINT_WIDTH 1 /* DCS_DONE_01_EINT */ +#define WM8995_WSEQ_DONE_EINT 0x0400 /* WSEQ_DONE_EINT */ +#define WM8995_WSEQ_DONE_EINT_MASK 0x0400 /* WSEQ_DONE_EINT */ +#define WM8995_WSEQ_DONE_EINT_SHIFT 10 /* WSEQ_DONE_EINT */ +#define WM8995_WSEQ_DONE_EINT_WIDTH 1 /* WSEQ_DONE_EINT */ +#define WM8995_FIFOS_ERR_EINT 0x0200 /* FIFOS_ERR_EINT */ +#define WM8995_FIFOS_ERR_EINT_MASK 0x0200 /* FIFOS_ERR_EINT */ +#define WM8995_FIFOS_ERR_EINT_SHIFT 9 /* FIFOS_ERR_EINT */ +#define WM8995_FIFOS_ERR_EINT_WIDTH 1 /* FIFOS_ERR_EINT */ +#define WM8995_AIF2DRC_SIG_DET_EINT 0x0100 /* AIF2DRC_SIG_DET_EINT */ +#define WM8995_AIF2DRC_SIG_DET_EINT_MASK 0x0100 /* AIF2DRC_SIG_DET_EINT */ +#define WM8995_AIF2DRC_SIG_DET_EINT_SHIFT 8 /* AIF2DRC_SIG_DET_EINT */ +#define WM8995_AIF2DRC_SIG_DET_EINT_WIDTH 1 /* AIF2DRC_SIG_DET_EINT */ +#define WM8995_AIF1DRC2_SIG_DET_EINT 0x0080 /* AIF1DRC2_SIG_DET_EINT */ +#define WM8995_AIF1DRC2_SIG_DET_EINT_MASK 0x0080 /* AIF1DRC2_SIG_DET_EINT */ +#define WM8995_AIF1DRC2_SIG_DET_EINT_SHIFT 7 /* AIF1DRC2_SIG_DET_EINT */ +#define WM8995_AIF1DRC2_SIG_DET_EINT_WIDTH 1 /* AIF1DRC2_SIG_DET_EINT */ +#define WM8995_AIF1DRC1_SIG_DET_EINT 0x0040 /* AIF1DRC1_SIG_DET_EINT */ +#define WM8995_AIF1DRC1_SIG_DET_EINT_MASK 0x0040 /* AIF1DRC1_SIG_DET_EINT */ +#define WM8995_AIF1DRC1_SIG_DET_EINT_SHIFT 6 /* AIF1DRC1_SIG_DET_EINT */ +#define WM8995_AIF1DRC1_SIG_DET_EINT_WIDTH 1 /* AIF1DRC1_SIG_DET_EINT */ +#define WM8995_SRC2_LOCK_EINT 0x0020 /* SRC2_LOCK_EINT */ +#define WM8995_SRC2_LOCK_EINT_MASK 0x0020 /* SRC2_LOCK_EINT */ +#define WM8995_SRC2_LOCK_EINT_SHIFT 5 /* SRC2_LOCK_EINT */ +#define WM8995_SRC2_LOCK_EINT_WIDTH 1 /* SRC2_LOCK_EINT */ +#define WM8995_SRC1_LOCK_EINT 0x0010 /* SRC1_LOCK_EINT */ +#define WM8995_SRC1_LOCK_EINT_MASK 0x0010 /* SRC1_LOCK_EINT */ +#define WM8995_SRC1_LOCK_EINT_SHIFT 4 /* SRC1_LOCK_EINT */ +#define WM8995_SRC1_LOCK_EINT_WIDTH 1 /* SRC1_LOCK_EINT */ +#define WM8995_FLL2_LOCK_EINT 0x0008 /* FLL2_LOCK_EINT */ +#define WM8995_FLL2_LOCK_EINT_MASK 0x0008 /* FLL2_LOCK_EINT */ +#define WM8995_FLL2_LOCK_EINT_SHIFT 3 /* FLL2_LOCK_EINT */ +#define WM8995_FLL2_LOCK_EINT_WIDTH 1 /* FLL2_LOCK_EINT */ +#define WM8995_FLL1_LOCK_EINT 0x0004 /* FLL1_LOCK_EINT */ +#define WM8995_FLL1_LOCK_EINT_MASK 0x0004 /* FLL1_LOCK_EINT */ +#define WM8995_FLL1_LOCK_EINT_SHIFT 2 /* FLL1_LOCK_EINT */ +#define WM8995_FLL1_LOCK_EINT_WIDTH 1 /* FLL1_LOCK_EINT */ +#define WM8995_HP_DONE_EINT 0x0002 /* HP_DONE_EINT */ +#define WM8995_HP_DONE_EINT_MASK 0x0002 /* HP_DONE_EINT */ +#define WM8995_HP_DONE_EINT_SHIFT 1 /* HP_DONE_EINT */ +#define WM8995_HP_DONE_EINT_WIDTH 1 /* HP_DONE_EINT */ +#define WM8995_MICD_EINT 0x0001 /* MICD_EINT */ +#define WM8995_MICD_EINT_MASK 0x0001 /* MICD_EINT */ +#define WM8995_MICD_EINT_SHIFT 0 /* MICD_EINT */ +#define WM8995_MICD_EINT_WIDTH 1 /* MICD_EINT */ + +/* + * R1842 (0x732) - Interrupt Raw Status 2 + */ +#define WM8995_DCS_DONE_23_STS 0x1000 /* DCS_DONE_23_STS */ +#define WM8995_DCS_DONE_23_STS_MASK 0x1000 /* DCS_DONE_23_STS */ +#define WM8995_DCS_DONE_23_STS_SHIFT 12 /* DCS_DONE_23_STS */ +#define WM8995_DCS_DONE_23_STS_WIDTH 1 /* DCS_DONE_23_STS */ +#define WM8995_DCS_DONE_01_STS 0x0800 /* DCS_DONE_01_STS */ +#define WM8995_DCS_DONE_01_STS_MASK 0x0800 /* DCS_DONE_01_STS */ +#define WM8995_DCS_DONE_01_STS_SHIFT 11 /* DCS_DONE_01_STS */ +#define WM8995_DCS_DONE_01_STS_WIDTH 1 /* DCS_DONE_01_STS */ +#define WM8995_WSEQ_DONE_STS 0x0400 /* WSEQ_DONE_STS */ +#define WM8995_WSEQ_DONE_STS_MASK 0x0400 /* WSEQ_DONE_STS */ +#define WM8995_WSEQ_DONE_STS_SHIFT 10 /* WSEQ_DONE_STS */ +#define WM8995_WSEQ_DONE_STS_WIDTH 1 /* WSEQ_DONE_STS */ +#define WM8995_FIFOS_ERR_STS 0x0200 /* FIFOS_ERR_STS */ +#define WM8995_FIFOS_ERR_STS_MASK 0x0200 /* FIFOS_ERR_STS */ +#define WM8995_FIFOS_ERR_STS_SHIFT 9 /* FIFOS_ERR_STS */ +#define WM8995_FIFOS_ERR_STS_WIDTH 1 /* FIFOS_ERR_STS */ +#define WM8995_AIF2DRC_SIG_DET_STS 0x0100 /* AIF2DRC_SIG_DET_STS */ +#define WM8995_AIF2DRC_SIG_DET_STS_MASK 0x0100 /* AIF2DRC_SIG_DET_STS */ +#define WM8995_AIF2DRC_SIG_DET_STS_SHIFT 8 /* AIF2DRC_SIG_DET_STS */ +#define WM8995_AIF2DRC_SIG_DET_STS_WIDTH 1 /* AIF2DRC_SIG_DET_STS */ +#define WM8995_AIF1DRC2_SIG_DET_STS 0x0080 /* AIF1DRC2_SIG_DET_STS */ +#define WM8995_AIF1DRC2_SIG_DET_STS_MASK 0x0080 /* AIF1DRC2_SIG_DET_STS */ +#define WM8995_AIF1DRC2_SIG_DET_STS_SHIFT 7 /* AIF1DRC2_SIG_DET_STS */ +#define WM8995_AIF1DRC2_SIG_DET_STS_WIDTH 1 /* AIF1DRC2_SIG_DET_STS */ +#define WM8995_AIF1DRC1_SIG_DET_STS 0x0040 /* AIF1DRC1_SIG_DET_STS */ +#define WM8995_AIF1DRC1_SIG_DET_STS_MASK 0x0040 /* AIF1DRC1_SIG_DET_STS */ +#define WM8995_AIF1DRC1_SIG_DET_STS_SHIFT 6 /* AIF1DRC1_SIG_DET_STS */ +#define WM8995_AIF1DRC1_SIG_DET_STS_WIDTH 1 /* AIF1DRC1_SIG_DET_STS */ +#define WM8995_SRC2_LOCK_STS 0x0020 /* SRC2_LOCK_STS */ +#define WM8995_SRC2_LOCK_STS_MASK 0x0020 /* SRC2_LOCK_STS */ +#define WM8995_SRC2_LOCK_STS_SHIFT 5 /* SRC2_LOCK_STS */ +#define WM8995_SRC2_LOCK_STS_WIDTH 1 /* SRC2_LOCK_STS */ +#define WM8995_SRC1_LOCK_STS 0x0010 /* SRC1_LOCK_STS */ +#define WM8995_SRC1_LOCK_STS_MASK 0x0010 /* SRC1_LOCK_STS */ +#define WM8995_SRC1_LOCK_STS_SHIFT 4 /* SRC1_LOCK_STS */ +#define WM8995_SRC1_LOCK_STS_WIDTH 1 /* SRC1_LOCK_STS */ +#define WM8995_FLL2_LOCK_STS 0x0008 /* FLL2_LOCK_STS */ +#define WM8995_FLL2_LOCK_STS_MASK 0x0008 /* FLL2_LOCK_STS */ +#define WM8995_FLL2_LOCK_STS_SHIFT 3 /* FLL2_LOCK_STS */ +#define WM8995_FLL2_LOCK_STS_WIDTH 1 /* FLL2_LOCK_STS */ +#define WM8995_FLL1_LOCK_STS 0x0004 /* FLL1_LOCK_STS */ +#define WM8995_FLL1_LOCK_STS_MASK 0x0004 /* FLL1_LOCK_STS */ +#define WM8995_FLL1_LOCK_STS_SHIFT 2 /* FLL1_LOCK_STS */ +#define WM8995_FLL1_LOCK_STS_WIDTH 1 /* FLL1_LOCK_STS */ + +/* + * R1848 (0x738) - Interrupt Status 1 Mask + */ +#define WM8995_IM_GP14_EINT 0x2000 /* IM_GP14_EINT */ +#define WM8995_IM_GP14_EINT_MASK 0x2000 /* IM_GP14_EINT */ +#define WM8995_IM_GP14_EINT_SHIFT 13 /* IM_GP14_EINT */ +#define WM8995_IM_GP14_EINT_WIDTH 1 /* IM_GP14_EINT */ +#define WM8995_IM_GP13_EINT 0x1000 /* IM_GP13_EINT */ +#define WM8995_IM_GP13_EINT_MASK 0x1000 /* IM_GP13_EINT */ +#define WM8995_IM_GP13_EINT_SHIFT 12 /* IM_GP13_EINT */ +#define WM8995_IM_GP13_EINT_WIDTH 1 /* IM_GP13_EINT */ +#define WM8995_IM_GP12_EINT 0x0800 /* IM_GP12_EINT */ +#define WM8995_IM_GP12_EINT_MASK 0x0800 /* IM_GP12_EINT */ +#define WM8995_IM_GP12_EINT_SHIFT 11 /* IM_GP12_EINT */ +#define WM8995_IM_GP12_EINT_WIDTH 1 /* IM_GP12_EINT */ +#define WM8995_IM_GP11_EINT 0x0400 /* IM_GP11_EINT */ +#define WM8995_IM_GP11_EINT_MASK 0x0400 /* IM_GP11_EINT */ +#define WM8995_IM_GP11_EINT_SHIFT 10 /* IM_GP11_EINT */ +#define WM8995_IM_GP11_EINT_WIDTH 1 /* IM_GP11_EINT */ +#define WM8995_IM_GP10_EINT 0x0200 /* IM_GP10_EINT */ +#define WM8995_IM_GP10_EINT_MASK 0x0200 /* IM_GP10_EINT */ +#define WM8995_IM_GP10_EINT_SHIFT 9 /* IM_GP10_EINT */ +#define WM8995_IM_GP10_EINT_WIDTH 1 /* IM_GP10_EINT */ +#define WM8995_IM_GP9_EINT 0x0100 /* IM_GP9_EINT */ +#define WM8995_IM_GP9_EINT_MASK 0x0100 /* IM_GP9_EINT */ +#define WM8995_IM_GP9_EINT_SHIFT 8 /* IM_GP9_EINT */ +#define WM8995_IM_GP9_EINT_WIDTH 1 /* IM_GP9_EINT */ +#define WM8995_IM_GP8_EINT 0x0080 /* IM_GP8_EINT */ +#define WM8995_IM_GP8_EINT_MASK 0x0080 /* IM_GP8_EINT */ +#define WM8995_IM_GP8_EINT_SHIFT 7 /* IM_GP8_EINT */ +#define WM8995_IM_GP8_EINT_WIDTH 1 /* IM_GP8_EINT */ +#define WM8995_IM_GP7_EINT 0x0040 /* IM_GP7_EINT */ +#define WM8995_IM_GP7_EINT_MASK 0x0040 /* IM_GP7_EINT */ +#define WM8995_IM_GP7_EINT_SHIFT 6 /* IM_GP7_EINT */ +#define WM8995_IM_GP7_EINT_WIDTH 1 /* IM_GP7_EINT */ +#define WM8995_IM_GP6_EINT 0x0020 /* IM_GP6_EINT */ +#define WM8995_IM_GP6_EINT_MASK 0x0020 /* IM_GP6_EINT */ +#define WM8995_IM_GP6_EINT_SHIFT 5 /* IM_GP6_EINT */ +#define WM8995_IM_GP6_EINT_WIDTH 1 /* IM_GP6_EINT */ +#define WM8995_IM_GP5_EINT 0x0010 /* IM_GP5_EINT */ +#define WM8995_IM_GP5_EINT_MASK 0x0010 /* IM_GP5_EINT */ +#define WM8995_IM_GP5_EINT_SHIFT 4 /* IM_GP5_EINT */ +#define WM8995_IM_GP5_EINT_WIDTH 1 /* IM_GP5_EINT */ +#define WM8995_IM_GP4_EINT 0x0008 /* IM_GP4_EINT */ +#define WM8995_IM_GP4_EINT_MASK 0x0008 /* IM_GP4_EINT */ +#define WM8995_IM_GP4_EINT_SHIFT 3 /* IM_GP4_EINT */ +#define WM8995_IM_GP4_EINT_WIDTH 1 /* IM_GP4_EINT */ +#define WM8995_IM_GP3_EINT 0x0004 /* IM_GP3_EINT */ +#define WM8995_IM_GP3_EINT_MASK 0x0004 /* IM_GP3_EINT */ +#define WM8995_IM_GP3_EINT_SHIFT 2 /* IM_GP3_EINT */ +#define WM8995_IM_GP3_EINT_WIDTH 1 /* IM_GP3_EINT */ +#define WM8995_IM_GP2_EINT 0x0002 /* IM_GP2_EINT */ +#define WM8995_IM_GP2_EINT_MASK 0x0002 /* IM_GP2_EINT */ +#define WM8995_IM_GP2_EINT_SHIFT 1 /* IM_GP2_EINT */ +#define WM8995_IM_GP2_EINT_WIDTH 1 /* IM_GP2_EINT */ +#define WM8995_IM_GP1_EINT 0x0001 /* IM_GP1_EINT */ +#define WM8995_IM_GP1_EINT_MASK 0x0001 /* IM_GP1_EINT */ +#define WM8995_IM_GP1_EINT_SHIFT 0 /* IM_GP1_EINT */ +#define WM8995_IM_GP1_EINT_WIDTH 1 /* IM_GP1_EINT */ + +/* + * R1849 (0x739) - Interrupt Status 2 Mask + */ +#define WM8995_IM_DCS_DONE_23_EINT 0x1000 /* IM_DCS_DONE_23_EINT */ +#define WM8995_IM_DCS_DONE_23_EINT_MASK 0x1000 /* IM_DCS_DONE_23_EINT */ +#define WM8995_IM_DCS_DONE_23_EINT_SHIFT 12 /* IM_DCS_DONE_23_EINT */ +#define WM8995_IM_DCS_DONE_23_EINT_WIDTH 1 /* IM_DCS_DONE_23_EINT */ +#define WM8995_IM_DCS_DONE_01_EINT 0x0800 /* IM_DCS_DONE_01_EINT */ +#define WM8995_IM_DCS_DONE_01_EINT_MASK 0x0800 /* IM_DCS_DONE_01_EINT */ +#define WM8995_IM_DCS_DONE_01_EINT_SHIFT 11 /* IM_DCS_DONE_01_EINT */ +#define WM8995_IM_DCS_DONE_01_EINT_WIDTH 1 /* IM_DCS_DONE_01_EINT */ +#define WM8995_IM_WSEQ_DONE_EINT 0x0400 /* IM_WSEQ_DONE_EINT */ +#define WM8995_IM_WSEQ_DONE_EINT_MASK 0x0400 /* IM_WSEQ_DONE_EINT */ +#define WM8995_IM_WSEQ_DONE_EINT_SHIFT 10 /* IM_WSEQ_DONE_EINT */ +#define WM8995_IM_WSEQ_DONE_EINT_WIDTH 1 /* IM_WSEQ_DONE_EINT */ +#define WM8995_IM_FIFOS_ERR_EINT 0x0200 /* IM_FIFOS_ERR_EINT */ +#define WM8995_IM_FIFOS_ERR_EINT_MASK 0x0200 /* IM_FIFOS_ERR_EINT */ +#define WM8995_IM_FIFOS_ERR_EINT_SHIFT 9 /* IM_FIFOS_ERR_EINT */ +#define WM8995_IM_FIFOS_ERR_EINT_WIDTH 1 /* IM_FIFOS_ERR_EINT */ +#define WM8995_IM_AIF2DRC_SIG_DET_EINT 0x0100 /* IM_AIF2DRC_SIG_DET_EINT */ +#define WM8995_IM_AIF2DRC_SIG_DET_EINT_MASK 0x0100 /* IM_AIF2DRC_SIG_DET_EINT */ +#define WM8995_IM_AIF2DRC_SIG_DET_EINT_SHIFT 8 /* IM_AIF2DRC_SIG_DET_EINT */ +#define WM8995_IM_AIF2DRC_SIG_DET_EINT_WIDTH 1 /* IM_AIF2DRC_SIG_DET_EINT */ +#define WM8995_IM_AIF1DRC2_SIG_DET_EINT 0x0080 /* IM_AIF1DRC2_SIG_DET_EINT */ +#define WM8995_IM_AIF1DRC2_SIG_DET_EINT_MASK 0x0080 /* IM_AIF1DRC2_SIG_DET_EINT */ +#define WM8995_IM_AIF1DRC2_SIG_DET_EINT_SHIFT 7 /* IM_AIF1DRC2_SIG_DET_EINT */ +#define WM8995_IM_AIF1DRC2_SIG_DET_EINT_WIDTH 1 /* IM_AIF1DRC2_SIG_DET_EINT */ +#define WM8995_IM_AIF1DRC1_SIG_DET_EINT 0x0040 /* IM_AIF1DRC1_SIG_DET_EINT */ +#define WM8995_IM_AIF1DRC1_SIG_DET_EINT_MASK 0x0040 /* IM_AIF1DRC1_SIG_DET_EINT */ +#define WM8995_IM_AIF1DRC1_SIG_DET_EINT_SHIFT 6 /* IM_AIF1DRC1_SIG_DET_EINT */ +#define WM8995_IM_AIF1DRC1_SIG_DET_EINT_WIDTH 1 /* IM_AIF1DRC1_SIG_DET_EINT */ +#define WM8995_IM_SRC2_LOCK_EINT 0x0020 /* IM_SRC2_LOCK_EINT */ +#define WM8995_IM_SRC2_LOCK_EINT_MASK 0x0020 /* IM_SRC2_LOCK_EINT */ +#define WM8995_IM_SRC2_LOCK_EINT_SHIFT 5 /* IM_SRC2_LOCK_EINT */ +#define WM8995_IM_SRC2_LOCK_EINT_WIDTH 1 /* IM_SRC2_LOCK_EINT */ +#define WM8995_IM_SRC1_LOCK_EINT 0x0010 /* IM_SRC1_LOCK_EINT */ +#define WM8995_IM_SRC1_LOCK_EINT_MASK 0x0010 /* IM_SRC1_LOCK_EINT */ +#define WM8995_IM_SRC1_LOCK_EINT_SHIFT 4 /* IM_SRC1_LOCK_EINT */ +#define WM8995_IM_SRC1_LOCK_EINT_WIDTH 1 /* IM_SRC1_LOCK_EINT */ +#define WM8995_IM_FLL2_LOCK_EINT 0x0008 /* IM_FLL2_LOCK_EINT */ +#define WM8995_IM_FLL2_LOCK_EINT_MASK 0x0008 /* IM_FLL2_LOCK_EINT */ +#define WM8995_IM_FLL2_LOCK_EINT_SHIFT 3 /* IM_FLL2_LOCK_EINT */ +#define WM8995_IM_FLL2_LOCK_EINT_WIDTH 1 /* IM_FLL2_LOCK_EINT */ +#define WM8995_IM_FLL1_LOCK_EINT 0x0004 /* IM_FLL1_LOCK_EINT */ +#define WM8995_IM_FLL1_LOCK_EINT_MASK 0x0004 /* IM_FLL1_LOCK_EINT */ +#define WM8995_IM_FLL1_LOCK_EINT_SHIFT 2 /* IM_FLL1_LOCK_EINT */ +#define WM8995_IM_FLL1_LOCK_EINT_WIDTH 1 /* IM_FLL1_LOCK_EINT */ +#define WM8995_IM_HP_DONE_EINT 0x0002 /* IM_HP_DONE_EINT */ +#define WM8995_IM_HP_DONE_EINT_MASK 0x0002 /* IM_HP_DONE_EINT */ +#define WM8995_IM_HP_DONE_EINT_SHIFT 1 /* IM_HP_DONE_EINT */ +#define WM8995_IM_HP_DONE_EINT_WIDTH 1 /* IM_HP_DONE_EINT */ +#define WM8995_IM_MICD_EINT 0x0001 /* IM_MICD_EINT */ +#define WM8995_IM_MICD_EINT_MASK 0x0001 /* IM_MICD_EINT */ +#define WM8995_IM_MICD_EINT_SHIFT 0 /* IM_MICD_EINT */ +#define WM8995_IM_MICD_EINT_WIDTH 1 /* IM_MICD_EINT */ + +/* + * R1856 (0x740) - Interrupt Control + */ +#define WM8995_IM_IRQ 0x0001 /* IM_IRQ */ +#define WM8995_IM_IRQ_MASK 0x0001 /* IM_IRQ */ +#define WM8995_IM_IRQ_SHIFT 0 /* IM_IRQ */ +#define WM8995_IM_IRQ_WIDTH 1 /* IM_IRQ */ + +/* + * R2048 (0x800) - Left PDM Speaker 1 + */ +#define WM8995_SPK1L_ENA 0x0010 /* SPK1L_ENA */ +#define WM8995_SPK1L_ENA_MASK 0x0010 /* SPK1L_ENA */ +#define WM8995_SPK1L_ENA_SHIFT 4 /* SPK1L_ENA */ +#define WM8995_SPK1L_ENA_WIDTH 1 /* SPK1L_ENA */ +#define WM8995_SPK1L_MUTE 0x0008 /* SPK1L_MUTE */ +#define WM8995_SPK1L_MUTE_MASK 0x0008 /* SPK1L_MUTE */ +#define WM8995_SPK1L_MUTE_SHIFT 3 /* SPK1L_MUTE */ +#define WM8995_SPK1L_MUTE_WIDTH 1 /* SPK1L_MUTE */ +#define WM8995_SPK1L_MUTE_ZC 0x0004 /* SPK1L_MUTE_ZC */ +#define WM8995_SPK1L_MUTE_ZC_MASK 0x0004 /* SPK1L_MUTE_ZC */ +#define WM8995_SPK1L_MUTE_ZC_SHIFT 2 /* SPK1L_MUTE_ZC */ +#define WM8995_SPK1L_MUTE_ZC_WIDTH 1 /* SPK1L_MUTE_ZC */ +#define WM8995_SPK1L_SRC_MASK 0x0003 /* SPK1L_SRC - [1:0] */ +#define WM8995_SPK1L_SRC_SHIFT 0 /* SPK1L_SRC - [1:0] */ +#define WM8995_SPK1L_SRC_WIDTH 2 /* SPK1L_SRC - [1:0] */ + +/* + * R2049 (0x801) - Right PDM Speaker 1 + */ +#define WM8995_SPK1R_ENA 0x0010 /* SPK1R_ENA */ +#define WM8995_SPK1R_ENA_MASK 0x0010 /* SPK1R_ENA */ +#define WM8995_SPK1R_ENA_SHIFT 4 /* SPK1R_ENA */ +#define WM8995_SPK1R_ENA_WIDTH 1 /* SPK1R_ENA */ +#define WM8995_SPK1R_MUTE 0x0008 /* SPK1R_MUTE */ +#define WM8995_SPK1R_MUTE_MASK 0x0008 /* SPK1R_MUTE */ +#define WM8995_SPK1R_MUTE_SHIFT 3 /* SPK1R_MUTE */ +#define WM8995_SPK1R_MUTE_WIDTH 1 /* SPK1R_MUTE */ +#define WM8995_SPK1R_MUTE_ZC 0x0004 /* SPK1R_MUTE_ZC */ +#define WM8995_SPK1R_MUTE_ZC_MASK 0x0004 /* SPK1R_MUTE_ZC */ +#define WM8995_SPK1R_MUTE_ZC_SHIFT 2 /* SPK1R_MUTE_ZC */ +#define WM8995_SPK1R_MUTE_ZC_WIDTH 1 /* SPK1R_MUTE_ZC */ +#define WM8995_SPK1R_SRC_MASK 0x0003 /* SPK1R_SRC - [1:0] */ +#define WM8995_SPK1R_SRC_SHIFT 0 /* SPK1R_SRC - [1:0] */ +#define WM8995_SPK1R_SRC_WIDTH 2 /* SPK1R_SRC - [1:0] */ + +/* + * R2050 (0x802) - PDM Speaker 1 Mute Sequence + */ +#define WM8995_SPK1_MUTE_SEQ1_MASK 0x00FF /* SPK1_MUTE_SEQ1 - [7:0] */ +#define WM8995_SPK1_MUTE_SEQ1_SHIFT 0 /* SPK1_MUTE_SEQ1 - [7:0] */ +#define WM8995_SPK1_MUTE_SEQ1_WIDTH 8 /* SPK1_MUTE_SEQ1 - [7:0] */ + +/* + * R2056 (0x808) - Left PDM Speaker 2 + */ +#define WM8995_SPK2L_ENA 0x0010 /* SPK2L_ENA */ +#define WM8995_SPK2L_ENA_MASK 0x0010 /* SPK2L_ENA */ +#define WM8995_SPK2L_ENA_SHIFT 4 /* SPK2L_ENA */ +#define WM8995_SPK2L_ENA_WIDTH 1 /* SPK2L_ENA */ +#define WM8995_SPK2L_MUTE 0x0008 /* SPK2L_MUTE */ +#define WM8995_SPK2L_MUTE_MASK 0x0008 /* SPK2L_MUTE */ +#define WM8995_SPK2L_MUTE_SHIFT 3 /* SPK2L_MUTE */ +#define WM8995_SPK2L_MUTE_WIDTH 1 /* SPK2L_MUTE */ +#define WM8995_SPK2L_MUTE_ZC 0x0004 /* SPK2L_MUTE_ZC */ +#define WM8995_SPK2L_MUTE_ZC_MASK 0x0004 /* SPK2L_MUTE_ZC */ +#define WM8995_SPK2L_MUTE_ZC_SHIFT 2 /* SPK2L_MUTE_ZC */ +#define WM8995_SPK2L_MUTE_ZC_WIDTH 1 /* SPK2L_MUTE_ZC */ +#define WM8995_SPK2L_SRC_MASK 0x0003 /* SPK2L_SRC - [1:0] */ +#define WM8995_SPK2L_SRC_SHIFT 0 /* SPK2L_SRC - [1:0] */ +#define WM8995_SPK2L_SRC_WIDTH 2 /* SPK2L_SRC - [1:0] */ + +/* + * R2057 (0x809) - Right PDM Speaker 2 + */ +#define WM8995_SPK2R_ENA 0x0010 /* SPK2R_ENA */ +#define WM8995_SPK2R_ENA_MASK 0x0010 /* SPK2R_ENA */ +#define WM8995_SPK2R_ENA_SHIFT 4 /* SPK2R_ENA */ +#define WM8995_SPK2R_ENA_WIDTH 1 /* SPK2R_ENA */ +#define WM8995_SPK2R_MUTE 0x0008 /* SPK2R_MUTE */ +#define WM8995_SPK2R_MUTE_MASK 0x0008 /* SPK2R_MUTE */ +#define WM8995_SPK2R_MUTE_SHIFT 3 /* SPK2R_MUTE */ +#define WM8995_SPK2R_MUTE_WIDTH 1 /* SPK2R_MUTE */ +#define WM8995_SPK2R_MUTE_ZC 0x0004 /* SPK2R_MUTE_ZC */ +#define WM8995_SPK2R_MUTE_ZC_MASK 0x0004 /* SPK2R_MUTE_ZC */ +#define WM8995_SPK2R_MUTE_ZC_SHIFT 2 /* SPK2R_MUTE_ZC */ +#define WM8995_SPK2R_MUTE_ZC_WIDTH 1 /* SPK2R_MUTE_ZC */ +#define WM8995_SPK2R_SRC_MASK 0x0003 /* SPK2R_SRC - [1:0] */ +#define WM8995_SPK2R_SRC_SHIFT 0 /* SPK2R_SRC - [1:0] */ +#define WM8995_SPK2R_SRC_WIDTH 2 /* SPK2R_SRC - [1:0] */ + +/* + * R2058 (0x80A) - PDM Speaker 2 Mute Sequence + */ +#define WM8995_SPK2_MUTE_SEQ1_MASK 0x00FF /* SPK2_MUTE_SEQ1 - [7:0] */ +#define WM8995_SPK2_MUTE_SEQ1_SHIFT 0 /* SPK2_MUTE_SEQ1 - [7:0] */ +#define WM8995_SPK2_MUTE_SEQ1_WIDTH 8 /* SPK2_MUTE_SEQ1 - [7:0] */ + +/* + * R12288 (0x3000) - Write Sequencer 0 + */ +#define WM8995_WSEQ_ADDR0_MASK 0x3FFF /* WSEQ_ADDR0 - [13:0] */ +#define WM8995_WSEQ_ADDR0_SHIFT 0 /* WSEQ_ADDR0 - [13:0] */ +#define WM8995_WSEQ_ADDR0_WIDTH 14 /* WSEQ_ADDR0 - [13:0] */ + +/* + * R12289 (0x3001) - Write Sequencer 1 + */ +#define WM8995_WSEQ_DATA0_MASK 0x00FF /* WSEQ_DATA0 - [7:0] */ +#define WM8995_WSEQ_DATA0_SHIFT 0 /* WSEQ_DATA0 - [7:0] */ +#define WM8995_WSEQ_DATA0_WIDTH 8 /* WSEQ_DATA0 - [7:0] */ + +/* + * R12290 (0x3002) - Write Sequencer 2 + */ +#define WM8995_WSEQ_DATA_WIDTH0_MASK 0x0700 /* WSEQ_DATA_WIDTH0 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH0_SHIFT 8 /* WSEQ_DATA_WIDTH0 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH0_WIDTH 3 /* WSEQ_DATA_WIDTH0 - [10:8] */ +#define WM8995_WSEQ_DATA_START0_MASK 0x000F /* WSEQ_DATA_START0 - [3:0] */ +#define WM8995_WSEQ_DATA_START0_SHIFT 0 /* WSEQ_DATA_START0 - [3:0] */ +#define WM8995_WSEQ_DATA_START0_WIDTH 4 /* WSEQ_DATA_START0 - [3:0] */ + +/* + * R12291 (0x3003) - Write Sequencer 3 + */ +#define WM8995_WSEQ_EOS0 0x0100 /* WSEQ_EOS0 */ +#define WM8995_WSEQ_EOS0_MASK 0x0100 /* WSEQ_EOS0 */ +#define WM8995_WSEQ_EOS0_SHIFT 8 /* WSEQ_EOS0 */ +#define WM8995_WSEQ_EOS0_WIDTH 1 /* WSEQ_EOS0 */ +#define WM8995_WSEQ_DELAY0_MASK 0x000F /* WSEQ_DELAY0 - [3:0] */ +#define WM8995_WSEQ_DELAY0_SHIFT 0 /* WSEQ_DELAY0 - [3:0] */ +#define WM8995_WSEQ_DELAY0_WIDTH 4 /* WSEQ_DELAY0 - [3:0] */ + +/* + * R12292 (0x3004) - Write Sequencer 4 + */ +#define WM8995_WSEQ_ADDR1_MASK 0x3FFF /* WSEQ_ADDR1 - [13:0] */ +#define WM8995_WSEQ_ADDR1_SHIFT 0 /* WSEQ_ADDR1 - [13:0] */ +#define WM8995_WSEQ_ADDR1_WIDTH 14 /* WSEQ_ADDR1 - [13:0] */ + +/* + * R12293 (0x3005) - Write Sequencer 5 + */ +#define WM8995_WSEQ_DATA1_MASK 0x00FF /* WSEQ_DATA1 - [7:0] */ +#define WM8995_WSEQ_DATA1_SHIFT 0 /* WSEQ_DATA1 - [7:0] */ +#define WM8995_WSEQ_DATA1_WIDTH 8 /* WSEQ_DATA1 - [7:0] */ + +/* + * R12294 (0x3006) - Write Sequencer 6 + */ +#define WM8995_WSEQ_DATA_WIDTH1_MASK 0x0700 /* WSEQ_DATA_WIDTH1 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH1_SHIFT 8 /* WSEQ_DATA_WIDTH1 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH1_WIDTH 3 /* WSEQ_DATA_WIDTH1 - [10:8] */ +#define WM8995_WSEQ_DATA_START1_MASK 0x000F /* WSEQ_DATA_START1 - [3:0] */ +#define WM8995_WSEQ_DATA_START1_SHIFT 0 /* WSEQ_DATA_START1 - [3:0] */ +#define WM8995_WSEQ_DATA_START1_WIDTH 4 /* WSEQ_DATA_START1 - [3:0] */ + +/* + * R12295 (0x3007) - Write Sequencer 7 + */ +#define WM8995_WSEQ_EOS1 0x0100 /* WSEQ_EOS1 */ +#define WM8995_WSEQ_EOS1_MASK 0x0100 /* WSEQ_EOS1 */ +#define WM8995_WSEQ_EOS1_SHIFT 8 /* WSEQ_EOS1 */ +#define WM8995_WSEQ_EOS1_WIDTH 1 /* WSEQ_EOS1 */ +#define WM8995_WSEQ_DELAY1_MASK 0x000F /* WSEQ_DELAY1 - [3:0] */ +#define WM8995_WSEQ_DELAY1_SHIFT 0 /* WSEQ_DELAY1 - [3:0] */ +#define WM8995_WSEQ_DELAY1_WIDTH 4 /* WSEQ_DELAY1 - [3:0] */ + +/* + * R12296 (0x3008) - Write Sequencer 8 + */ +#define WM8995_WSEQ_ADDR2_MASK 0x3FFF /* WSEQ_ADDR2 - [13:0] */ +#define WM8995_WSEQ_ADDR2_SHIFT 0 /* WSEQ_ADDR2 - [13:0] */ +#define WM8995_WSEQ_ADDR2_WIDTH 14 /* WSEQ_ADDR2 - [13:0] */ + +/* + * R12297 (0x3009) - Write Sequencer 9 + */ +#define WM8995_WSEQ_DATA2_MASK 0x00FF /* WSEQ_DATA2 - [7:0] */ +#define WM8995_WSEQ_DATA2_SHIFT 0 /* WSEQ_DATA2 - [7:0] */ +#define WM8995_WSEQ_DATA2_WIDTH 8 /* WSEQ_DATA2 - [7:0] */ + +/* + * R12298 (0x300A) - Write Sequencer 10 + */ +#define WM8995_WSEQ_DATA_WIDTH2_MASK 0x0700 /* WSEQ_DATA_WIDTH2 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH2_SHIFT 8 /* WSEQ_DATA_WIDTH2 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH2_WIDTH 3 /* WSEQ_DATA_WIDTH2 - [10:8] */ +#define WM8995_WSEQ_DATA_START2_MASK 0x000F /* WSEQ_DATA_START2 - [3:0] */ +#define WM8995_WSEQ_DATA_START2_SHIFT 0 /* WSEQ_DATA_START2 - [3:0] */ +#define WM8995_WSEQ_DATA_START2_WIDTH 4 /* WSEQ_DATA_START2 - [3:0] */ + +/* + * R12299 (0x300B) - Write Sequencer 11 + */ +#define WM8995_WSEQ_EOS2 0x0100 /* WSEQ_EOS2 */ +#define WM8995_WSEQ_EOS2_MASK 0x0100 /* WSEQ_EOS2 */ +#define WM8995_WSEQ_EOS2_SHIFT 8 /* WSEQ_EOS2 */ +#define WM8995_WSEQ_EOS2_WIDTH 1 /* WSEQ_EOS2 */ +#define WM8995_WSEQ_DELAY2_MASK 0x000F /* WSEQ_DELAY2 - [3:0] */ +#define WM8995_WSEQ_DELAY2_SHIFT 0 /* WSEQ_DELAY2 - [3:0] */ +#define WM8995_WSEQ_DELAY2_WIDTH 4 /* WSEQ_DELAY2 - [3:0] */ + +/* + * R12300 (0x300C) - Write Sequencer 12 + */ +#define WM8995_WSEQ_ADDR3_MASK 0x3FFF /* WSEQ_ADDR3 - [13:0] */ +#define WM8995_WSEQ_ADDR3_SHIFT 0 /* WSEQ_ADDR3 - [13:0] */ +#define WM8995_WSEQ_ADDR3_WIDTH 14 /* WSEQ_ADDR3 - [13:0] */ + +/* + * R12301 (0x300D) - Write Sequencer 13 + */ +#define WM8995_WSEQ_DATA3_MASK 0x00FF /* WSEQ_DATA3 - [7:0] */ +#define WM8995_WSEQ_DATA3_SHIFT 0 /* WSEQ_DATA3 - [7:0] */ +#define WM8995_WSEQ_DATA3_WIDTH 8 /* WSEQ_DATA3 - [7:0] */ + +/* + * R12302 (0x300E) - Write Sequencer 14 + */ +#define WM8995_WSEQ_DATA_WIDTH3_MASK 0x0700 /* WSEQ_DATA_WIDTH3 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH3_SHIFT 8 /* WSEQ_DATA_WIDTH3 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH3_WIDTH 3 /* WSEQ_DATA_WIDTH3 - [10:8] */ +#define WM8995_WSEQ_DATA_START3_MASK 0x000F /* WSEQ_DATA_START3 - [3:0] */ +#define WM8995_WSEQ_DATA_START3_SHIFT 0 /* WSEQ_DATA_START3 - [3:0] */ +#define WM8995_WSEQ_DATA_START3_WIDTH 4 /* WSEQ_DATA_START3 - [3:0] */ + +/* + * R12303 (0x300F) - Write Sequencer 15 + */ +#define WM8995_WSEQ_EOS3 0x0100 /* WSEQ_EOS3 */ +#define WM8995_WSEQ_EOS3_MASK 0x0100 /* WSEQ_EOS3 */ +#define WM8995_WSEQ_EOS3_SHIFT 8 /* WSEQ_EOS3 */ +#define WM8995_WSEQ_EOS3_WIDTH 1 /* WSEQ_EOS3 */ +#define WM8995_WSEQ_DELAY3_MASK 0x000F /* WSEQ_DELAY3 - [3:0] */ +#define WM8995_WSEQ_DELAY3_SHIFT 0 /* WSEQ_DELAY3 - [3:0] */ +#define WM8995_WSEQ_DELAY3_WIDTH 4 /* WSEQ_DELAY3 - [3:0] */ + +/* + * R12304 (0x3010) - Write Sequencer 16 + */ +#define WM8995_WSEQ_ADDR4_MASK 0x3FFF /* WSEQ_ADDR4 - [13:0] */ +#define WM8995_WSEQ_ADDR4_SHIFT 0 /* WSEQ_ADDR4 - [13:0] */ +#define WM8995_WSEQ_ADDR4_WIDTH 14 /* WSEQ_ADDR4 - [13:0] */ + +/* + * R12305 (0x3011) - Write Sequencer 17 + */ +#define WM8995_WSEQ_DATA4_MASK 0x00FF /* WSEQ_DATA4 - [7:0] */ +#define WM8995_WSEQ_DATA4_SHIFT 0 /* WSEQ_DATA4 - [7:0] */ +#define WM8995_WSEQ_DATA4_WIDTH 8 /* WSEQ_DATA4 - [7:0] */ + +/* + * R12306 (0x3012) - Write Sequencer 18 + */ +#define WM8995_WSEQ_DATA_WIDTH4_MASK 0x0700 /* WSEQ_DATA_WIDTH4 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH4_SHIFT 8 /* WSEQ_DATA_WIDTH4 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH4_WIDTH 3 /* WSEQ_DATA_WIDTH4 - [10:8] */ +#define WM8995_WSEQ_DATA_START4_MASK 0x000F /* WSEQ_DATA_START4 - [3:0] */ +#define WM8995_WSEQ_DATA_START4_SHIFT 0 /* WSEQ_DATA_START4 - [3:0] */ +#define WM8995_WSEQ_DATA_START4_WIDTH 4 /* WSEQ_DATA_START4 - [3:0] */ + +/* + * R12307 (0x3013) - Write Sequencer 19 + */ +#define WM8995_WSEQ_EOS4 0x0100 /* WSEQ_EOS4 */ +#define WM8995_WSEQ_EOS4_MASK 0x0100 /* WSEQ_EOS4 */ +#define WM8995_WSEQ_EOS4_SHIFT 8 /* WSEQ_EOS4 */ +#define WM8995_WSEQ_EOS4_WIDTH 1 /* WSEQ_EOS4 */ +#define WM8995_WSEQ_DELAY4_MASK 0x000F /* WSEQ_DELAY4 - [3:0] */ +#define WM8995_WSEQ_DELAY4_SHIFT 0 /* WSEQ_DELAY4 - [3:0] */ +#define WM8995_WSEQ_DELAY4_WIDTH 4 /* WSEQ_DELAY4 - [3:0] */ + +/* + * R12308 (0x3014) - Write Sequencer 20 + */ +#define WM8995_WSEQ_ADDR5_MASK 0x3FFF /* WSEQ_ADDR5 - [13:0] */ +#define WM8995_WSEQ_ADDR5_SHIFT 0 /* WSEQ_ADDR5 - [13:0] */ +#define WM8995_WSEQ_ADDR5_WIDTH 14 /* WSEQ_ADDR5 - [13:0] */ + +/* + * R12309 (0x3015) - Write Sequencer 21 + */ +#define WM8995_WSEQ_DATA5_MASK 0x00FF /* WSEQ_DATA5 - [7:0] */ +#define WM8995_WSEQ_DATA5_SHIFT 0 /* WSEQ_DATA5 - [7:0] */ +#define WM8995_WSEQ_DATA5_WIDTH 8 /* WSEQ_DATA5 - [7:0] */ + +/* + * R12310 (0x3016) - Write Sequencer 22 + */ +#define WM8995_WSEQ_DATA_WIDTH5_MASK 0x0700 /* WSEQ_DATA_WIDTH5 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH5_SHIFT 8 /* WSEQ_DATA_WIDTH5 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH5_WIDTH 3 /* WSEQ_DATA_WIDTH5 - [10:8] */ +#define WM8995_WSEQ_DATA_START5_MASK 0x000F /* WSEQ_DATA_START5 - [3:0] */ +#define WM8995_WSEQ_DATA_START5_SHIFT 0 /* WSEQ_DATA_START5 - [3:0] */ +#define WM8995_WSEQ_DATA_START5_WIDTH 4 /* WSEQ_DATA_START5 - [3:0] */ + +/* + * R12311 (0x3017) - Write Sequencer 23 + */ +#define WM8995_WSEQ_EOS5 0x0100 /* WSEQ_EOS5 */ +#define WM8995_WSEQ_EOS5_MASK 0x0100 /* WSEQ_EOS5 */ +#define WM8995_WSEQ_EOS5_SHIFT 8 /* WSEQ_EOS5 */ +#define WM8995_WSEQ_EOS5_WIDTH 1 /* WSEQ_EOS5 */ +#define WM8995_WSEQ_DELAY5_MASK 0x000F /* WSEQ_DELAY5 - [3:0] */ +#define WM8995_WSEQ_DELAY5_SHIFT 0 /* WSEQ_DELAY5 - [3:0] */ +#define WM8995_WSEQ_DELAY5_WIDTH 4 /* WSEQ_DELAY5 - [3:0] */ + +/* + * R12312 (0x3018) - Write Sequencer 24 + */ +#define WM8995_WSEQ_ADDR6_MASK 0x3FFF /* WSEQ_ADDR6 - [13:0] */ +#define WM8995_WSEQ_ADDR6_SHIFT 0 /* WSEQ_ADDR6 - [13:0] */ +#define WM8995_WSEQ_ADDR6_WIDTH 14 /* WSEQ_ADDR6 - [13:0] */ + +/* + * R12313 (0x3019) - Write Sequencer 25 + */ +#define WM8995_WSEQ_DATA6_MASK 0x00FF /* WSEQ_DATA6 - [7:0] */ +#define WM8995_WSEQ_DATA6_SHIFT 0 /* WSEQ_DATA6 - [7:0] */ +#define WM8995_WSEQ_DATA6_WIDTH 8 /* WSEQ_DATA6 - [7:0] */ + +/* + * R12314 (0x301A) - Write Sequencer 26 + */ +#define WM8995_WSEQ_DATA_WIDTH6_MASK 0x0700 /* WSEQ_DATA_WIDTH6 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH6_SHIFT 8 /* WSEQ_DATA_WIDTH6 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH6_WIDTH 3 /* WSEQ_DATA_WIDTH6 - [10:8] */ +#define WM8995_WSEQ_DATA_START6_MASK 0x000F /* WSEQ_DATA_START6 - [3:0] */ +#define WM8995_WSEQ_DATA_START6_SHIFT 0 /* WSEQ_DATA_START6 - [3:0] */ +#define WM8995_WSEQ_DATA_START6_WIDTH 4 /* WSEQ_DATA_START6 - [3:0] */ + +/* + * R12315 (0x301B) - Write Sequencer 27 + */ +#define WM8995_WSEQ_EOS6 0x0100 /* WSEQ_EOS6 */ +#define WM8995_WSEQ_EOS6_MASK 0x0100 /* WSEQ_EOS6 */ +#define WM8995_WSEQ_EOS6_SHIFT 8 /* WSEQ_EOS6 */ +#define WM8995_WSEQ_EOS6_WIDTH 1 /* WSEQ_EOS6 */ +#define WM8995_WSEQ_DELAY6_MASK 0x000F /* WSEQ_DELAY6 - [3:0] */ +#define WM8995_WSEQ_DELAY6_SHIFT 0 /* WSEQ_DELAY6 - [3:0] */ +#define WM8995_WSEQ_DELAY6_WIDTH 4 /* WSEQ_DELAY6 - [3:0] */ + +/* + * R12316 (0x301C) - Write Sequencer 28 + */ +#define WM8995_WSEQ_ADDR7_MASK 0x3FFF /* WSEQ_ADDR7 - [13:0] */ +#define WM8995_WSEQ_ADDR7_SHIFT 0 /* WSEQ_ADDR7 - [13:0] */ +#define WM8995_WSEQ_ADDR7_WIDTH 14 /* WSEQ_ADDR7 - [13:0] */ + +/* + * R12317 (0x301D) - Write Sequencer 29 + */ +#define WM8995_WSEQ_DATA7_MASK 0x00FF /* WSEQ_DATA7 - [7:0] */ +#define WM8995_WSEQ_DATA7_SHIFT 0 /* WSEQ_DATA7 - [7:0] */ +#define WM8995_WSEQ_DATA7_WIDTH 8 /* WSEQ_DATA7 - [7:0] */ + +/* + * R12318 (0x301E) - Write Sequencer 30 + */ +#define WM8995_WSEQ_DATA_WIDTH7_MASK 0x0700 /* WSEQ_DATA_WIDTH7 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH7_SHIFT 8 /* WSEQ_DATA_WIDTH7 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH7_WIDTH 3 /* WSEQ_DATA_WIDTH7 - [10:8] */ +#define WM8995_WSEQ_DATA_START7_MASK 0x000F /* WSEQ_DATA_START7 - [3:0] */ +#define WM8995_WSEQ_DATA_START7_SHIFT 0 /* WSEQ_DATA_START7 - [3:0] */ +#define WM8995_WSEQ_DATA_START7_WIDTH 4 /* WSEQ_DATA_START7 - [3:0] */ + +/* + * R12319 (0x301F) - Write Sequencer 31 + */ +#define WM8995_WSEQ_EOS7 0x0100 /* WSEQ_EOS7 */ +#define WM8995_WSEQ_EOS7_MASK 0x0100 /* WSEQ_EOS7 */ +#define WM8995_WSEQ_EOS7_SHIFT 8 /* WSEQ_EOS7 */ +#define WM8995_WSEQ_EOS7_WIDTH 1 /* WSEQ_EOS7 */ +#define WM8995_WSEQ_DELAY7_MASK 0x000F /* WSEQ_DELAY7 - [3:0] */ +#define WM8995_WSEQ_DELAY7_SHIFT 0 /* WSEQ_DELAY7 - [3:0] */ +#define WM8995_WSEQ_DELAY7_WIDTH 4 /* WSEQ_DELAY7 - [3:0] */ + +/* + * R12320 (0x3020) - Write Sequencer 32 + */ +#define WM8995_WSEQ_ADDR8_MASK 0x3FFF /* WSEQ_ADDR8 - [13:0] */ +#define WM8995_WSEQ_ADDR8_SHIFT 0 /* WSEQ_ADDR8 - [13:0] */ +#define WM8995_WSEQ_ADDR8_WIDTH 14 /* WSEQ_ADDR8 - [13:0] */ + +/* + * R12321 (0x3021) - Write Sequencer 33 + */ +#define WM8995_WSEQ_DATA8_MASK 0x00FF /* WSEQ_DATA8 - [7:0] */ +#define WM8995_WSEQ_DATA8_SHIFT 0 /* WSEQ_DATA8 - [7:0] */ +#define WM8995_WSEQ_DATA8_WIDTH 8 /* WSEQ_DATA8 - [7:0] */ + +/* + * R12322 (0x3022) - Write Sequencer 34 + */ +#define WM8995_WSEQ_DATA_WIDTH8_MASK 0x0700 /* WSEQ_DATA_WIDTH8 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH8_SHIFT 8 /* WSEQ_DATA_WIDTH8 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH8_WIDTH 3 /* WSEQ_DATA_WIDTH8 - [10:8] */ +#define WM8995_WSEQ_DATA_START8_MASK 0x000F /* WSEQ_DATA_START8 - [3:0] */ +#define WM8995_WSEQ_DATA_START8_SHIFT 0 /* WSEQ_DATA_START8 - [3:0] */ +#define WM8995_WSEQ_DATA_START8_WIDTH 4 /* WSEQ_DATA_START8 - [3:0] */ + +/* + * R12323 (0x3023) - Write Sequencer 35 + */ +#define WM8995_WSEQ_EOS8 0x0100 /* WSEQ_EOS8 */ +#define WM8995_WSEQ_EOS8_MASK 0x0100 /* WSEQ_EOS8 */ +#define WM8995_WSEQ_EOS8_SHIFT 8 /* WSEQ_EOS8 */ +#define WM8995_WSEQ_EOS8_WIDTH 1 /* WSEQ_EOS8 */ +#define WM8995_WSEQ_DELAY8_MASK 0x000F /* WSEQ_DELAY8 - [3:0] */ +#define WM8995_WSEQ_DELAY8_SHIFT 0 /* WSEQ_DELAY8 - [3:0] */ +#define WM8995_WSEQ_DELAY8_WIDTH 4 /* WSEQ_DELAY8 - [3:0] */ + +/* + * R12324 (0x3024) - Write Sequencer 36 + */ +#define WM8995_WSEQ_ADDR9_MASK 0x3FFF /* WSEQ_ADDR9 - [13:0] */ +#define WM8995_WSEQ_ADDR9_SHIFT 0 /* WSEQ_ADDR9 - [13:0] */ +#define WM8995_WSEQ_ADDR9_WIDTH 14 /* WSEQ_ADDR9 - [13:0] */ + +/* + * R12325 (0x3025) - Write Sequencer 37 + */ +#define WM8995_WSEQ_DATA9_MASK 0x00FF /* WSEQ_DATA9 - [7:0] */ +#define WM8995_WSEQ_DATA9_SHIFT 0 /* WSEQ_DATA9 - [7:0] */ +#define WM8995_WSEQ_DATA9_WIDTH 8 /* WSEQ_DATA9 - [7:0] */ + +/* + * R12326 (0x3026) - Write Sequencer 38 + */ +#define WM8995_WSEQ_DATA_WIDTH9_MASK 0x0700 /* WSEQ_DATA_WIDTH9 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH9_SHIFT 8 /* WSEQ_DATA_WIDTH9 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH9_WIDTH 3 /* WSEQ_DATA_WIDTH9 - [10:8] */ +#define WM8995_WSEQ_DATA_START9_MASK 0x000F /* WSEQ_DATA_START9 - [3:0] */ +#define WM8995_WSEQ_DATA_START9_SHIFT 0 /* WSEQ_DATA_START9 - [3:0] */ +#define WM8995_WSEQ_DATA_START9_WIDTH 4 /* WSEQ_DATA_START9 - [3:0] */ + +/* + * R12327 (0x3027) - Write Sequencer 39 + */ +#define WM8995_WSEQ_EOS9 0x0100 /* WSEQ_EOS9 */ +#define WM8995_WSEQ_EOS9_MASK 0x0100 /* WSEQ_EOS9 */ +#define WM8995_WSEQ_EOS9_SHIFT 8 /* WSEQ_EOS9 */ +#define WM8995_WSEQ_EOS9_WIDTH 1 /* WSEQ_EOS9 */ +#define WM8995_WSEQ_DELAY9_MASK 0x000F /* WSEQ_DELAY9 - [3:0] */ +#define WM8995_WSEQ_DELAY9_SHIFT 0 /* WSEQ_DELAY9 - [3:0] */ +#define WM8995_WSEQ_DELAY9_WIDTH 4 /* WSEQ_DELAY9 - [3:0] */ + +/* + * R12328 (0x3028) - Write Sequencer 40 + */ +#define WM8995_WSEQ_ADDR10_MASK 0x3FFF /* WSEQ_ADDR10 - [13:0] */ +#define WM8995_WSEQ_ADDR10_SHIFT 0 /* WSEQ_ADDR10 - [13:0] */ +#define WM8995_WSEQ_ADDR10_WIDTH 14 /* WSEQ_ADDR10 - [13:0] */ + +/* + * R12329 (0x3029) - Write Sequencer 41 + */ +#define WM8995_WSEQ_DATA10_MASK 0x00FF /* WSEQ_DATA10 - [7:0] */ +#define WM8995_WSEQ_DATA10_SHIFT 0 /* WSEQ_DATA10 - [7:0] */ +#define WM8995_WSEQ_DATA10_WIDTH 8 /* WSEQ_DATA10 - [7:0] */ + +/* + * R12330 (0x302A) - Write Sequencer 42 + */ +#define WM8995_WSEQ_DATA_WIDTH10_MASK 0x0700 /* WSEQ_DATA_WIDTH10 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH10_SHIFT 8 /* WSEQ_DATA_WIDTH10 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH10_WIDTH 3 /* WSEQ_DATA_WIDTH10 - [10:8] */ +#define WM8995_WSEQ_DATA_START10_MASK 0x000F /* WSEQ_DATA_START10 - [3:0] */ +#define WM8995_WSEQ_DATA_START10_SHIFT 0 /* WSEQ_DATA_START10 - [3:0] */ +#define WM8995_WSEQ_DATA_START10_WIDTH 4 /* WSEQ_DATA_START10 - [3:0] */ + +/* + * R12331 (0x302B) - Write Sequencer 43 + */ +#define WM8995_WSEQ_EOS10 0x0100 /* WSEQ_EOS10 */ +#define WM8995_WSEQ_EOS10_MASK 0x0100 /* WSEQ_EOS10 */ +#define WM8995_WSEQ_EOS10_SHIFT 8 /* WSEQ_EOS10 */ +#define WM8995_WSEQ_EOS10_WIDTH 1 /* WSEQ_EOS10 */ +#define WM8995_WSEQ_DELAY10_MASK 0x000F /* WSEQ_DELAY10 - [3:0] */ +#define WM8995_WSEQ_DELAY10_SHIFT 0 /* WSEQ_DELAY10 - [3:0] */ +#define WM8995_WSEQ_DELAY10_WIDTH 4 /* WSEQ_DELAY10 - [3:0] */ + +/* + * R12332 (0x302C) - Write Sequencer 44 + */ +#define WM8995_WSEQ_ADDR11_MASK 0x3FFF /* WSEQ_ADDR11 - [13:0] */ +#define WM8995_WSEQ_ADDR11_SHIFT 0 /* WSEQ_ADDR11 - [13:0] */ +#define WM8995_WSEQ_ADDR11_WIDTH 14 /* WSEQ_ADDR11 - [13:0] */ + +/* + * R12333 (0x302D) - Write Sequencer 45 + */ +#define WM8995_WSEQ_DATA11_MASK 0x00FF /* WSEQ_DATA11 - [7:0] */ +#define WM8995_WSEQ_DATA11_SHIFT 0 /* WSEQ_DATA11 - [7:0] */ +#define WM8995_WSEQ_DATA11_WIDTH 8 /* WSEQ_DATA11 - [7:0] */ + +/* + * R12334 (0x302E) - Write Sequencer 46 + */ +#define WM8995_WSEQ_DATA_WIDTH11_MASK 0x0700 /* WSEQ_DATA_WIDTH11 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH11_SHIFT 8 /* WSEQ_DATA_WIDTH11 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH11_WIDTH 3 /* WSEQ_DATA_WIDTH11 - [10:8] */ +#define WM8995_WSEQ_DATA_START11_MASK 0x000F /* WSEQ_DATA_START11 - [3:0] */ +#define WM8995_WSEQ_DATA_START11_SHIFT 0 /* WSEQ_DATA_START11 - [3:0] */ +#define WM8995_WSEQ_DATA_START11_WIDTH 4 /* WSEQ_DATA_START11 - [3:0] */ + +/* + * R12335 (0x302F) - Write Sequencer 47 + */ +#define WM8995_WSEQ_EOS11 0x0100 /* WSEQ_EOS11 */ +#define WM8995_WSEQ_EOS11_MASK 0x0100 /* WSEQ_EOS11 */ +#define WM8995_WSEQ_EOS11_SHIFT 8 /* WSEQ_EOS11 */ +#define WM8995_WSEQ_EOS11_WIDTH 1 /* WSEQ_EOS11 */ +#define WM8995_WSEQ_DELAY11_MASK 0x000F /* WSEQ_DELAY11 - [3:0] */ +#define WM8995_WSEQ_DELAY11_SHIFT 0 /* WSEQ_DELAY11 - [3:0] */ +#define WM8995_WSEQ_DELAY11_WIDTH 4 /* WSEQ_DELAY11 - [3:0] */ + +/* + * R12336 (0x3030) - Write Sequencer 48 + */ +#define WM8995_WSEQ_ADDR12_MASK 0x3FFF /* WSEQ_ADDR12 - [13:0] */ +#define WM8995_WSEQ_ADDR12_SHIFT 0 /* WSEQ_ADDR12 - [13:0] */ +#define WM8995_WSEQ_ADDR12_WIDTH 14 /* WSEQ_ADDR12 - [13:0] */ + +/* + * R12337 (0x3031) - Write Sequencer 49 + */ +#define WM8995_WSEQ_DATA12_MASK 0x00FF /* WSEQ_DATA12 - [7:0] */ +#define WM8995_WSEQ_DATA12_SHIFT 0 /* WSEQ_DATA12 - [7:0] */ +#define WM8995_WSEQ_DATA12_WIDTH 8 /* WSEQ_DATA12 - [7:0] */ + +/* + * R12338 (0x3032) - Write Sequencer 50 + */ +#define WM8995_WSEQ_DATA_WIDTH12_MASK 0x0700 /* WSEQ_DATA_WIDTH12 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH12_SHIFT 8 /* WSEQ_DATA_WIDTH12 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH12_WIDTH 3 /* WSEQ_DATA_WIDTH12 - [10:8] */ +#define WM8995_WSEQ_DATA_START12_MASK 0x000F /* WSEQ_DATA_START12 - [3:0] */ +#define WM8995_WSEQ_DATA_START12_SHIFT 0 /* WSEQ_DATA_START12 - [3:0] */ +#define WM8995_WSEQ_DATA_START12_WIDTH 4 /* WSEQ_DATA_START12 - [3:0] */ + +/* + * R12339 (0x3033) - Write Sequencer 51 + */ +#define WM8995_WSEQ_EOS12 0x0100 /* WSEQ_EOS12 */ +#define WM8995_WSEQ_EOS12_MASK 0x0100 /* WSEQ_EOS12 */ +#define WM8995_WSEQ_EOS12_SHIFT 8 /* WSEQ_EOS12 */ +#define WM8995_WSEQ_EOS12_WIDTH 1 /* WSEQ_EOS12 */ +#define WM8995_WSEQ_DELAY12_MASK 0x000F /* WSEQ_DELAY12 - [3:0] */ +#define WM8995_WSEQ_DELAY12_SHIFT 0 /* WSEQ_DELAY12 - [3:0] */ +#define WM8995_WSEQ_DELAY12_WIDTH 4 /* WSEQ_DELAY12 - [3:0] */ + +/* + * R12340 (0x3034) - Write Sequencer 52 + */ +#define WM8995_WSEQ_ADDR13_MASK 0x3FFF /* WSEQ_ADDR13 - [13:0] */ +#define WM8995_WSEQ_ADDR13_SHIFT 0 /* WSEQ_ADDR13 - [13:0] */ +#define WM8995_WSEQ_ADDR13_WIDTH 14 /* WSEQ_ADDR13 - [13:0] */ + +/* + * R12341 (0x3035) - Write Sequencer 53 + */ +#define WM8995_WSEQ_DATA13_MASK 0x00FF /* WSEQ_DATA13 - [7:0] */ +#define WM8995_WSEQ_DATA13_SHIFT 0 /* WSEQ_DATA13 - [7:0] */ +#define WM8995_WSEQ_DATA13_WIDTH 8 /* WSEQ_DATA13 - [7:0] */ + +/* + * R12342 (0x3036) - Write Sequencer 54 + */ +#define WM8995_WSEQ_DATA_WIDTH13_MASK 0x0700 /* WSEQ_DATA_WIDTH13 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH13_SHIFT 8 /* WSEQ_DATA_WIDTH13 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH13_WIDTH 3 /* WSEQ_DATA_WIDTH13 - [10:8] */ +#define WM8995_WSEQ_DATA_START13_MASK 0x000F /* WSEQ_DATA_START13 - [3:0] */ +#define WM8995_WSEQ_DATA_START13_SHIFT 0 /* WSEQ_DATA_START13 - [3:0] */ +#define WM8995_WSEQ_DATA_START13_WIDTH 4 /* WSEQ_DATA_START13 - [3:0] */ + +/* + * R12343 (0x3037) - Write Sequencer 55 + */ +#define WM8995_WSEQ_EOS13 0x0100 /* WSEQ_EOS13 */ +#define WM8995_WSEQ_EOS13_MASK 0x0100 /* WSEQ_EOS13 */ +#define WM8995_WSEQ_EOS13_SHIFT 8 /* WSEQ_EOS13 */ +#define WM8995_WSEQ_EOS13_WIDTH 1 /* WSEQ_EOS13 */ +#define WM8995_WSEQ_DELAY13_MASK 0x000F /* WSEQ_DELAY13 - [3:0] */ +#define WM8995_WSEQ_DELAY13_SHIFT 0 /* WSEQ_DELAY13 - [3:0] */ +#define WM8995_WSEQ_DELAY13_WIDTH 4 /* WSEQ_DELAY13 - [3:0] */ + +/* + * R12344 (0x3038) - Write Sequencer 56 + */ +#define WM8995_WSEQ_ADDR14_MASK 0x3FFF /* WSEQ_ADDR14 - [13:0] */ +#define WM8995_WSEQ_ADDR14_SHIFT 0 /* WSEQ_ADDR14 - [13:0] */ +#define WM8995_WSEQ_ADDR14_WIDTH 14 /* WSEQ_ADDR14 - [13:0] */ + +/* + * R12345 (0x3039) - Write Sequencer 57 + */ +#define WM8995_WSEQ_DATA14_MASK 0x00FF /* WSEQ_DATA14 - [7:0] */ +#define WM8995_WSEQ_DATA14_SHIFT 0 /* WSEQ_DATA14 - [7:0] */ +#define WM8995_WSEQ_DATA14_WIDTH 8 /* WSEQ_DATA14 - [7:0] */ + +/* + * R12346 (0x303A) - Write Sequencer 58 + */ +#define WM8995_WSEQ_DATA_WIDTH14_MASK 0x0700 /* WSEQ_DATA_WIDTH14 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH14_SHIFT 8 /* WSEQ_DATA_WIDTH14 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH14_WIDTH 3 /* WSEQ_DATA_WIDTH14 - [10:8] */ +#define WM8995_WSEQ_DATA_START14_MASK 0x000F /* WSEQ_DATA_START14 - [3:0] */ +#define WM8995_WSEQ_DATA_START14_SHIFT 0 /* WSEQ_DATA_START14 - [3:0] */ +#define WM8995_WSEQ_DATA_START14_WIDTH 4 /* WSEQ_DATA_START14 - [3:0] */ + +/* + * R12347 (0x303B) - Write Sequencer 59 + */ +#define WM8995_WSEQ_EOS14 0x0100 /* WSEQ_EOS14 */ +#define WM8995_WSEQ_EOS14_MASK 0x0100 /* WSEQ_EOS14 */ +#define WM8995_WSEQ_EOS14_SHIFT 8 /* WSEQ_EOS14 */ +#define WM8995_WSEQ_EOS14_WIDTH 1 /* WSEQ_EOS14 */ +#define WM8995_WSEQ_DELAY14_MASK 0x000F /* WSEQ_DELAY14 - [3:0] */ +#define WM8995_WSEQ_DELAY14_SHIFT 0 /* WSEQ_DELAY14 - [3:0] */ +#define WM8995_WSEQ_DELAY14_WIDTH 4 /* WSEQ_DELAY14 - [3:0] */ + +/* + * R12348 (0x303C) - Write Sequencer 60 + */ +#define WM8995_WSEQ_ADDR15_MASK 0x3FFF /* WSEQ_ADDR15 - [13:0] */ +#define WM8995_WSEQ_ADDR15_SHIFT 0 /* WSEQ_ADDR15 - [13:0] */ +#define WM8995_WSEQ_ADDR15_WIDTH 14 /* WSEQ_ADDR15 - [13:0] */ + +/* + * R12349 (0x303D) - Write Sequencer 61 + */ +#define WM8995_WSEQ_DATA15_MASK 0x00FF /* WSEQ_DATA15 - [7:0] */ +#define WM8995_WSEQ_DATA15_SHIFT 0 /* WSEQ_DATA15 - [7:0] */ +#define WM8995_WSEQ_DATA15_WIDTH 8 /* WSEQ_DATA15 - [7:0] */ + +/* + * R12350 (0x303E) - Write Sequencer 62 + */ +#define WM8995_WSEQ_DATA_WIDTH15_MASK 0x0700 /* WSEQ_DATA_WIDTH15 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH15_SHIFT 8 /* WSEQ_DATA_WIDTH15 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH15_WIDTH 3 /* WSEQ_DATA_WIDTH15 - [10:8] */ +#define WM8995_WSEQ_DATA_START15_MASK 0x000F /* WSEQ_DATA_START15 - [3:0] */ +#define WM8995_WSEQ_DATA_START15_SHIFT 0 /* WSEQ_DATA_START15 - [3:0] */ +#define WM8995_WSEQ_DATA_START15_WIDTH 4 /* WSEQ_DATA_START15 - [3:0] */ + +/* + * R12351 (0x303F) - Write Sequencer 63 + */ +#define WM8995_WSEQ_EOS15 0x0100 /* WSEQ_EOS15 */ +#define WM8995_WSEQ_EOS15_MASK 0x0100 /* WSEQ_EOS15 */ +#define WM8995_WSEQ_EOS15_SHIFT 8 /* WSEQ_EOS15 */ +#define WM8995_WSEQ_EOS15_WIDTH 1 /* WSEQ_EOS15 */ +#define WM8995_WSEQ_DELAY15_MASK 0x000F /* WSEQ_DELAY15 - [3:0] */ +#define WM8995_WSEQ_DELAY15_SHIFT 0 /* WSEQ_DELAY15 - [3:0] */ +#define WM8995_WSEQ_DELAY15_WIDTH 4 /* WSEQ_DELAY15 - [3:0] */ + +/* + * R12352 (0x3040) - Write Sequencer 64 + */ +#define WM8995_WSEQ_ADDR16_MASK 0x3FFF /* WSEQ_ADDR16 - [13:0] */ +#define WM8995_WSEQ_ADDR16_SHIFT 0 /* WSEQ_ADDR16 - [13:0] */ +#define WM8995_WSEQ_ADDR16_WIDTH 14 /* WSEQ_ADDR16 - [13:0] */ + +/* + * R12353 (0x3041) - Write Sequencer 65 + */ +#define WM8995_WSEQ_DATA16_MASK 0x00FF /* WSEQ_DATA16 - [7:0] */ +#define WM8995_WSEQ_DATA16_SHIFT 0 /* WSEQ_DATA16 - [7:0] */ +#define WM8995_WSEQ_DATA16_WIDTH 8 /* WSEQ_DATA16 - [7:0] */ + +/* + * R12354 (0x3042) - Write Sequencer 66 + */ +#define WM8995_WSEQ_DATA_WIDTH16_MASK 0x0700 /* WSEQ_DATA_WIDTH16 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH16_SHIFT 8 /* WSEQ_DATA_WIDTH16 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH16_WIDTH 3 /* WSEQ_DATA_WIDTH16 - [10:8] */ +#define WM8995_WSEQ_DATA_START16_MASK 0x000F /* WSEQ_DATA_START16 - [3:0] */ +#define WM8995_WSEQ_DATA_START16_SHIFT 0 /* WSEQ_DATA_START16 - [3:0] */ +#define WM8995_WSEQ_DATA_START16_WIDTH 4 /* WSEQ_DATA_START16 - [3:0] */ + +/* + * R12355 (0x3043) - Write Sequencer 67 + */ +#define WM8995_WSEQ_EOS16 0x0100 /* WSEQ_EOS16 */ +#define WM8995_WSEQ_EOS16_MASK 0x0100 /* WSEQ_EOS16 */ +#define WM8995_WSEQ_EOS16_SHIFT 8 /* WSEQ_EOS16 */ +#define WM8995_WSEQ_EOS16_WIDTH 1 /* WSEQ_EOS16 */ +#define WM8995_WSEQ_DELAY16_MASK 0x000F /* WSEQ_DELAY16 - [3:0] */ +#define WM8995_WSEQ_DELAY16_SHIFT 0 /* WSEQ_DELAY16 - [3:0] */ +#define WM8995_WSEQ_DELAY16_WIDTH 4 /* WSEQ_DELAY16 - [3:0] */ + +/* + * R12356 (0x3044) - Write Sequencer 68 + */ +#define WM8995_WSEQ_ADDR17_MASK 0x3FFF /* WSEQ_ADDR17 - [13:0] */ +#define WM8995_WSEQ_ADDR17_SHIFT 0 /* WSEQ_ADDR17 - [13:0] */ +#define WM8995_WSEQ_ADDR17_WIDTH 14 /* WSEQ_ADDR17 - [13:0] */ + +/* + * R12357 (0x3045) - Write Sequencer 69 + */ +#define WM8995_WSEQ_DATA17_MASK 0x00FF /* WSEQ_DATA17 - [7:0] */ +#define WM8995_WSEQ_DATA17_SHIFT 0 /* WSEQ_DATA17 - [7:0] */ +#define WM8995_WSEQ_DATA17_WIDTH 8 /* WSEQ_DATA17 - [7:0] */ + +/* + * R12358 (0x3046) - Write Sequencer 70 + */ +#define WM8995_WSEQ_DATA_WIDTH17_MASK 0x0700 /* WSEQ_DATA_WIDTH17 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH17_SHIFT 8 /* WSEQ_DATA_WIDTH17 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH17_WIDTH 3 /* WSEQ_DATA_WIDTH17 - [10:8] */ +#define WM8995_WSEQ_DATA_START17_MASK 0x000F /* WSEQ_DATA_START17 - [3:0] */ +#define WM8995_WSEQ_DATA_START17_SHIFT 0 /* WSEQ_DATA_START17 - [3:0] */ +#define WM8995_WSEQ_DATA_START17_WIDTH 4 /* WSEQ_DATA_START17 - [3:0] */ + +/* + * R12359 (0x3047) - Write Sequencer 71 + */ +#define WM8995_WSEQ_EOS17 0x0100 /* WSEQ_EOS17 */ +#define WM8995_WSEQ_EOS17_MASK 0x0100 /* WSEQ_EOS17 */ +#define WM8995_WSEQ_EOS17_SHIFT 8 /* WSEQ_EOS17 */ +#define WM8995_WSEQ_EOS17_WIDTH 1 /* WSEQ_EOS17 */ +#define WM8995_WSEQ_DELAY17_MASK 0x000F /* WSEQ_DELAY17 - [3:0] */ +#define WM8995_WSEQ_DELAY17_SHIFT 0 /* WSEQ_DELAY17 - [3:0] */ +#define WM8995_WSEQ_DELAY17_WIDTH 4 /* WSEQ_DELAY17 - [3:0] */ + +/* + * R12360 (0x3048) - Write Sequencer 72 + */ +#define WM8995_WSEQ_ADDR18_MASK 0x3FFF /* WSEQ_ADDR18 - [13:0] */ +#define WM8995_WSEQ_ADDR18_SHIFT 0 /* WSEQ_ADDR18 - [13:0] */ +#define WM8995_WSEQ_ADDR18_WIDTH 14 /* WSEQ_ADDR18 - [13:0] */ + +/* + * R12361 (0x3049) - Write Sequencer 73 + */ +#define WM8995_WSEQ_DATA18_MASK 0x00FF /* WSEQ_DATA18 - [7:0] */ +#define WM8995_WSEQ_DATA18_SHIFT 0 /* WSEQ_DATA18 - [7:0] */ +#define WM8995_WSEQ_DATA18_WIDTH 8 /* WSEQ_DATA18 - [7:0] */ + +/* + * R12362 (0x304A) - Write Sequencer 74 + */ +#define WM8995_WSEQ_DATA_WIDTH18_MASK 0x0700 /* WSEQ_DATA_WIDTH18 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH18_SHIFT 8 /* WSEQ_DATA_WIDTH18 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH18_WIDTH 3 /* WSEQ_DATA_WIDTH18 - [10:8] */ +#define WM8995_WSEQ_DATA_START18_MASK 0x000F /* WSEQ_DATA_START18 - [3:0] */ +#define WM8995_WSEQ_DATA_START18_SHIFT 0 /* WSEQ_DATA_START18 - [3:0] */ +#define WM8995_WSEQ_DATA_START18_WIDTH 4 /* WSEQ_DATA_START18 - [3:0] */ + +/* + * R12363 (0x304B) - Write Sequencer 75 + */ +#define WM8995_WSEQ_EOS18 0x0100 /* WSEQ_EOS18 */ +#define WM8995_WSEQ_EOS18_MASK 0x0100 /* WSEQ_EOS18 */ +#define WM8995_WSEQ_EOS18_SHIFT 8 /* WSEQ_EOS18 */ +#define WM8995_WSEQ_EOS18_WIDTH 1 /* WSEQ_EOS18 */ +#define WM8995_WSEQ_DELAY18_MASK 0x000F /* WSEQ_DELAY18 - [3:0] */ +#define WM8995_WSEQ_DELAY18_SHIFT 0 /* WSEQ_DELAY18 - [3:0] */ +#define WM8995_WSEQ_DELAY18_WIDTH 4 /* WSEQ_DELAY18 - [3:0] */ + +/* + * R12364 (0x304C) - Write Sequencer 76 + */ +#define WM8995_WSEQ_ADDR19_MASK 0x3FFF /* WSEQ_ADDR19 - [13:0] */ +#define WM8995_WSEQ_ADDR19_SHIFT 0 /* WSEQ_ADDR19 - [13:0] */ +#define WM8995_WSEQ_ADDR19_WIDTH 14 /* WSEQ_ADDR19 - [13:0] */ + +/* + * R12365 (0x304D) - Write Sequencer 77 + */ +#define WM8995_WSEQ_DATA19_MASK 0x00FF /* WSEQ_DATA19 - [7:0] */ +#define WM8995_WSEQ_DATA19_SHIFT 0 /* WSEQ_DATA19 - [7:0] */ +#define WM8995_WSEQ_DATA19_WIDTH 8 /* WSEQ_DATA19 - [7:0] */ + +/* + * R12366 (0x304E) - Write Sequencer 78 + */ +#define WM8995_WSEQ_DATA_WIDTH19_MASK 0x0700 /* WSEQ_DATA_WIDTH19 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH19_SHIFT 8 /* WSEQ_DATA_WIDTH19 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH19_WIDTH 3 /* WSEQ_DATA_WIDTH19 - [10:8] */ +#define WM8995_WSEQ_DATA_START19_MASK 0x000F /* WSEQ_DATA_START19 - [3:0] */ +#define WM8995_WSEQ_DATA_START19_SHIFT 0 /* WSEQ_DATA_START19 - [3:0] */ +#define WM8995_WSEQ_DATA_START19_WIDTH 4 /* WSEQ_DATA_START19 - [3:0] */ + +/* + * R12367 (0x304F) - Write Sequencer 79 + */ +#define WM8995_WSEQ_EOS19 0x0100 /* WSEQ_EOS19 */ +#define WM8995_WSEQ_EOS19_MASK 0x0100 /* WSEQ_EOS19 */ +#define WM8995_WSEQ_EOS19_SHIFT 8 /* WSEQ_EOS19 */ +#define WM8995_WSEQ_EOS19_WIDTH 1 /* WSEQ_EOS19 */ +#define WM8995_WSEQ_DELAY19_MASK 0x000F /* WSEQ_DELAY19 - [3:0] */ +#define WM8995_WSEQ_DELAY19_SHIFT 0 /* WSEQ_DELAY19 - [3:0] */ +#define WM8995_WSEQ_DELAY19_WIDTH 4 /* WSEQ_DELAY19 - [3:0] */ + +/* + * R12368 (0x3050) - Write Sequencer 80 + */ +#define WM8995_WSEQ_ADDR20_MASK 0x3FFF /* WSEQ_ADDR20 - [13:0] */ +#define WM8995_WSEQ_ADDR20_SHIFT 0 /* WSEQ_ADDR20 - [13:0] */ +#define WM8995_WSEQ_ADDR20_WIDTH 14 /* WSEQ_ADDR20 - [13:0] */ + +/* + * R12369 (0x3051) - Write Sequencer 81 + */ +#define WM8995_WSEQ_DATA20_MASK 0x00FF /* WSEQ_DATA20 - [7:0] */ +#define WM8995_WSEQ_DATA20_SHIFT 0 /* WSEQ_DATA20 - [7:0] */ +#define WM8995_WSEQ_DATA20_WIDTH 8 /* WSEQ_DATA20 - [7:0] */ + +/* + * R12370 (0x3052) - Write Sequencer 82 + */ +#define WM8995_WSEQ_DATA_WIDTH20_MASK 0x0700 /* WSEQ_DATA_WIDTH20 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH20_SHIFT 8 /* WSEQ_DATA_WIDTH20 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH20_WIDTH 3 /* WSEQ_DATA_WIDTH20 - [10:8] */ +#define WM8995_WSEQ_DATA_START20_MASK 0x000F /* WSEQ_DATA_START20 - [3:0] */ +#define WM8995_WSEQ_DATA_START20_SHIFT 0 /* WSEQ_DATA_START20 - [3:0] */ +#define WM8995_WSEQ_DATA_START20_WIDTH 4 /* WSEQ_DATA_START20 - [3:0] */ + +/* + * R12371 (0x3053) - Write Sequencer 83 + */ +#define WM8995_WSEQ_EOS20 0x0100 /* WSEQ_EOS20 */ +#define WM8995_WSEQ_EOS20_MASK 0x0100 /* WSEQ_EOS20 */ +#define WM8995_WSEQ_EOS20_SHIFT 8 /* WSEQ_EOS20 */ +#define WM8995_WSEQ_EOS20_WIDTH 1 /* WSEQ_EOS20 */ +#define WM8995_WSEQ_DELAY20_MASK 0x000F /* WSEQ_DELAY20 - [3:0] */ +#define WM8995_WSEQ_DELAY20_SHIFT 0 /* WSEQ_DELAY20 - [3:0] */ +#define WM8995_WSEQ_DELAY20_WIDTH 4 /* WSEQ_DELAY20 - [3:0] */ + +/* + * R12372 (0x3054) - Write Sequencer 84 + */ +#define WM8995_WSEQ_ADDR21_MASK 0x3FFF /* WSEQ_ADDR21 - [13:0] */ +#define WM8995_WSEQ_ADDR21_SHIFT 0 /* WSEQ_ADDR21 - [13:0] */ +#define WM8995_WSEQ_ADDR21_WIDTH 14 /* WSEQ_ADDR21 - [13:0] */ + +/* + * R12373 (0x3055) - Write Sequencer 85 + */ +#define WM8995_WSEQ_DATA21_MASK 0x00FF /* WSEQ_DATA21 - [7:0] */ +#define WM8995_WSEQ_DATA21_SHIFT 0 /* WSEQ_DATA21 - [7:0] */ +#define WM8995_WSEQ_DATA21_WIDTH 8 /* WSEQ_DATA21 - [7:0] */ + +/* + * R12374 (0x3056) - Write Sequencer 86 + */ +#define WM8995_WSEQ_DATA_WIDTH21_MASK 0x0700 /* WSEQ_DATA_WIDTH21 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH21_SHIFT 8 /* WSEQ_DATA_WIDTH21 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH21_WIDTH 3 /* WSEQ_DATA_WIDTH21 - [10:8] */ +#define WM8995_WSEQ_DATA_START21_MASK 0x000F /* WSEQ_DATA_START21 - [3:0] */ +#define WM8995_WSEQ_DATA_START21_SHIFT 0 /* WSEQ_DATA_START21 - [3:0] */ +#define WM8995_WSEQ_DATA_START21_WIDTH 4 /* WSEQ_DATA_START21 - [3:0] */ + +/* + * R12375 (0x3057) - Write Sequencer 87 + */ +#define WM8995_WSEQ_EOS21 0x0100 /* WSEQ_EOS21 */ +#define WM8995_WSEQ_EOS21_MASK 0x0100 /* WSEQ_EOS21 */ +#define WM8995_WSEQ_EOS21_SHIFT 8 /* WSEQ_EOS21 */ +#define WM8995_WSEQ_EOS21_WIDTH 1 /* WSEQ_EOS21 */ +#define WM8995_WSEQ_DELAY21_MASK 0x000F /* WSEQ_DELAY21 - [3:0] */ +#define WM8995_WSEQ_DELAY21_SHIFT 0 /* WSEQ_DELAY21 - [3:0] */ +#define WM8995_WSEQ_DELAY21_WIDTH 4 /* WSEQ_DELAY21 - [3:0] */ + +/* + * R12376 (0x3058) - Write Sequencer 88 + */ +#define WM8995_WSEQ_ADDR22_MASK 0x3FFF /* WSEQ_ADDR22 - [13:0] */ +#define WM8995_WSEQ_ADDR22_SHIFT 0 /* WSEQ_ADDR22 - [13:0] */ +#define WM8995_WSEQ_ADDR22_WIDTH 14 /* WSEQ_ADDR22 - [13:0] */ + +/* + * R12377 (0x3059) - Write Sequencer 89 + */ +#define WM8995_WSEQ_DATA22_MASK 0x00FF /* WSEQ_DATA22 - [7:0] */ +#define WM8995_WSEQ_DATA22_SHIFT 0 /* WSEQ_DATA22 - [7:0] */ +#define WM8995_WSEQ_DATA22_WIDTH 8 /* WSEQ_DATA22 - [7:0] */ + +/* + * R12378 (0x305A) - Write Sequencer 90 + */ +#define WM8995_WSEQ_DATA_WIDTH22_MASK 0x0700 /* WSEQ_DATA_WIDTH22 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH22_SHIFT 8 /* WSEQ_DATA_WIDTH22 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH22_WIDTH 3 /* WSEQ_DATA_WIDTH22 - [10:8] */ +#define WM8995_WSEQ_DATA_START22_MASK 0x000F /* WSEQ_DATA_START22 - [3:0] */ +#define WM8995_WSEQ_DATA_START22_SHIFT 0 /* WSEQ_DATA_START22 - [3:0] */ +#define WM8995_WSEQ_DATA_START22_WIDTH 4 /* WSEQ_DATA_START22 - [3:0] */ + +/* + * R12379 (0x305B) - Write Sequencer 91 + */ +#define WM8995_WSEQ_EOS22 0x0100 /* WSEQ_EOS22 */ +#define WM8995_WSEQ_EOS22_MASK 0x0100 /* WSEQ_EOS22 */ +#define WM8995_WSEQ_EOS22_SHIFT 8 /* WSEQ_EOS22 */ +#define WM8995_WSEQ_EOS22_WIDTH 1 /* WSEQ_EOS22 */ +#define WM8995_WSEQ_DELAY22_MASK 0x000F /* WSEQ_DELAY22 - [3:0] */ +#define WM8995_WSEQ_DELAY22_SHIFT 0 /* WSEQ_DELAY22 - [3:0] */ +#define WM8995_WSEQ_DELAY22_WIDTH 4 /* WSEQ_DELAY22 - [3:0] */ + +/* + * R12380 (0x305C) - Write Sequencer 92 + */ +#define WM8995_WSEQ_ADDR23_MASK 0x3FFF /* WSEQ_ADDR23 - [13:0] */ +#define WM8995_WSEQ_ADDR23_SHIFT 0 /* WSEQ_ADDR23 - [13:0] */ +#define WM8995_WSEQ_ADDR23_WIDTH 14 /* WSEQ_ADDR23 - [13:0] */ + +/* + * R12381 (0x305D) - Write Sequencer 93 + */ +#define WM8995_WSEQ_DATA23_MASK 0x00FF /* WSEQ_DATA23 - [7:0] */ +#define WM8995_WSEQ_DATA23_SHIFT 0 /* WSEQ_DATA23 - [7:0] */ +#define WM8995_WSEQ_DATA23_WIDTH 8 /* WSEQ_DATA23 - [7:0] */ + +/* + * R12382 (0x305E) - Write Sequencer 94 + */ +#define WM8995_WSEQ_DATA_WIDTH23_MASK 0x0700 /* WSEQ_DATA_WIDTH23 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH23_SHIFT 8 /* WSEQ_DATA_WIDTH23 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH23_WIDTH 3 /* WSEQ_DATA_WIDTH23 - [10:8] */ +#define WM8995_WSEQ_DATA_START23_MASK 0x000F /* WSEQ_DATA_START23 - [3:0] */ +#define WM8995_WSEQ_DATA_START23_SHIFT 0 /* WSEQ_DATA_START23 - [3:0] */ +#define WM8995_WSEQ_DATA_START23_WIDTH 4 /* WSEQ_DATA_START23 - [3:0] */ + +/* + * R12383 (0x305F) - Write Sequencer 95 + */ +#define WM8995_WSEQ_EOS23 0x0100 /* WSEQ_EOS23 */ +#define WM8995_WSEQ_EOS23_MASK 0x0100 /* WSEQ_EOS23 */ +#define WM8995_WSEQ_EOS23_SHIFT 8 /* WSEQ_EOS23 */ +#define WM8995_WSEQ_EOS23_WIDTH 1 /* WSEQ_EOS23 */ +#define WM8995_WSEQ_DELAY23_MASK 0x000F /* WSEQ_DELAY23 - [3:0] */ +#define WM8995_WSEQ_DELAY23_SHIFT 0 /* WSEQ_DELAY23 - [3:0] */ +#define WM8995_WSEQ_DELAY23_WIDTH 4 /* WSEQ_DELAY23 - [3:0] */ + +/* + * R12384 (0x3060) - Write Sequencer 96 + */ +#define WM8995_WSEQ_ADDR24_MASK 0x3FFF /* WSEQ_ADDR24 - [13:0] */ +#define WM8995_WSEQ_ADDR24_SHIFT 0 /* WSEQ_ADDR24 - [13:0] */ +#define WM8995_WSEQ_ADDR24_WIDTH 14 /* WSEQ_ADDR24 - [13:0] */ + +/* + * R12385 (0x3061) - Write Sequencer 97 + */ +#define WM8995_WSEQ_DATA24_MASK 0x00FF /* WSEQ_DATA24 - [7:0] */ +#define WM8995_WSEQ_DATA24_SHIFT 0 /* WSEQ_DATA24 - [7:0] */ +#define WM8995_WSEQ_DATA24_WIDTH 8 /* WSEQ_DATA24 - [7:0] */ + +/* + * R12386 (0x3062) - Write Sequencer 98 + */ +#define WM8995_WSEQ_DATA_WIDTH24_MASK 0x0700 /* WSEQ_DATA_WIDTH24 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH24_SHIFT 8 /* WSEQ_DATA_WIDTH24 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH24_WIDTH 3 /* WSEQ_DATA_WIDTH24 - [10:8] */ +#define WM8995_WSEQ_DATA_START24_MASK 0x000F /* WSEQ_DATA_START24 - [3:0] */ +#define WM8995_WSEQ_DATA_START24_SHIFT 0 /* WSEQ_DATA_START24 - [3:0] */ +#define WM8995_WSEQ_DATA_START24_WIDTH 4 /* WSEQ_DATA_START24 - [3:0] */ + +/* + * R12387 (0x3063) - Write Sequencer 99 + */ +#define WM8995_WSEQ_EOS24 0x0100 /* WSEQ_EOS24 */ +#define WM8995_WSEQ_EOS24_MASK 0x0100 /* WSEQ_EOS24 */ +#define WM8995_WSEQ_EOS24_SHIFT 8 /* WSEQ_EOS24 */ +#define WM8995_WSEQ_EOS24_WIDTH 1 /* WSEQ_EOS24 */ +#define WM8995_WSEQ_DELAY24_MASK 0x000F /* WSEQ_DELAY24 - [3:0] */ +#define WM8995_WSEQ_DELAY24_SHIFT 0 /* WSEQ_DELAY24 - [3:0] */ +#define WM8995_WSEQ_DELAY24_WIDTH 4 /* WSEQ_DELAY24 - [3:0] */ + +/* + * R12388 (0x3064) - Write Sequencer 100 + */ +#define WM8995_WSEQ_ADDR25_MASK 0x3FFF /* WSEQ_ADDR25 - [13:0] */ +#define WM8995_WSEQ_ADDR25_SHIFT 0 /* WSEQ_ADDR25 - [13:0] */ +#define WM8995_WSEQ_ADDR25_WIDTH 14 /* WSEQ_ADDR25 - [13:0] */ + +/* + * R12389 (0x3065) - Write Sequencer 101 + */ +#define WM8995_WSEQ_DATA25_MASK 0x00FF /* WSEQ_DATA25 - [7:0] */ +#define WM8995_WSEQ_DATA25_SHIFT 0 /* WSEQ_DATA25 - [7:0] */ +#define WM8995_WSEQ_DATA25_WIDTH 8 /* WSEQ_DATA25 - [7:0] */ + +/* + * R12390 (0x3066) - Write Sequencer 102 + */ +#define WM8995_WSEQ_DATA_WIDTH25_MASK 0x0700 /* WSEQ_DATA_WIDTH25 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH25_SHIFT 8 /* WSEQ_DATA_WIDTH25 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH25_WIDTH 3 /* WSEQ_DATA_WIDTH25 - [10:8] */ +#define WM8995_WSEQ_DATA_START25_MASK 0x000F /* WSEQ_DATA_START25 - [3:0] */ +#define WM8995_WSEQ_DATA_START25_SHIFT 0 /* WSEQ_DATA_START25 - [3:0] */ +#define WM8995_WSEQ_DATA_START25_WIDTH 4 /* WSEQ_DATA_START25 - [3:0] */ + +/* + * R12391 (0x3067) - Write Sequencer 103 + */ +#define WM8995_WSEQ_EOS25 0x0100 /* WSEQ_EOS25 */ +#define WM8995_WSEQ_EOS25_MASK 0x0100 /* WSEQ_EOS25 */ +#define WM8995_WSEQ_EOS25_SHIFT 8 /* WSEQ_EOS25 */ +#define WM8995_WSEQ_EOS25_WIDTH 1 /* WSEQ_EOS25 */ +#define WM8995_WSEQ_DELAY25_MASK 0x000F /* WSEQ_DELAY25 - [3:0] */ +#define WM8995_WSEQ_DELAY25_SHIFT 0 /* WSEQ_DELAY25 - [3:0] */ +#define WM8995_WSEQ_DELAY25_WIDTH 4 /* WSEQ_DELAY25 - [3:0] */ + +/* + * R12392 (0x3068) - Write Sequencer 104 + */ +#define WM8995_WSEQ_ADDR26_MASK 0x3FFF /* WSEQ_ADDR26 - [13:0] */ +#define WM8995_WSEQ_ADDR26_SHIFT 0 /* WSEQ_ADDR26 - [13:0] */ +#define WM8995_WSEQ_ADDR26_WIDTH 14 /* WSEQ_ADDR26 - [13:0] */ + +/* + * R12393 (0x3069) - Write Sequencer 105 + */ +#define WM8995_WSEQ_DATA26_MASK 0x00FF /* WSEQ_DATA26 - [7:0] */ +#define WM8995_WSEQ_DATA26_SHIFT 0 /* WSEQ_DATA26 - [7:0] */ +#define WM8995_WSEQ_DATA26_WIDTH 8 /* WSEQ_DATA26 - [7:0] */ + +/* + * R12394 (0x306A) - Write Sequencer 106 + */ +#define WM8995_WSEQ_DATA_WIDTH26_MASK 0x0700 /* WSEQ_DATA_WIDTH26 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH26_SHIFT 8 /* WSEQ_DATA_WIDTH26 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH26_WIDTH 3 /* WSEQ_DATA_WIDTH26 - [10:8] */ +#define WM8995_WSEQ_DATA_START26_MASK 0x000F /* WSEQ_DATA_START26 - [3:0] */ +#define WM8995_WSEQ_DATA_START26_SHIFT 0 /* WSEQ_DATA_START26 - [3:0] */ +#define WM8995_WSEQ_DATA_START26_WIDTH 4 /* WSEQ_DATA_START26 - [3:0] */ + +/* + * R12395 (0x306B) - Write Sequencer 107 + */ +#define WM8995_WSEQ_EOS26 0x0100 /* WSEQ_EOS26 */ +#define WM8995_WSEQ_EOS26_MASK 0x0100 /* WSEQ_EOS26 */ +#define WM8995_WSEQ_EOS26_SHIFT 8 /* WSEQ_EOS26 */ +#define WM8995_WSEQ_EOS26_WIDTH 1 /* WSEQ_EOS26 */ +#define WM8995_WSEQ_DELAY26_MASK 0x000F /* WSEQ_DELAY26 - [3:0] */ +#define WM8995_WSEQ_DELAY26_SHIFT 0 /* WSEQ_DELAY26 - [3:0] */ +#define WM8995_WSEQ_DELAY26_WIDTH 4 /* WSEQ_DELAY26 - [3:0] */ + +/* + * R12396 (0x306C) - Write Sequencer 108 + */ +#define WM8995_WSEQ_ADDR27_MASK 0x3FFF /* WSEQ_ADDR27 - [13:0] */ +#define WM8995_WSEQ_ADDR27_SHIFT 0 /* WSEQ_ADDR27 - [13:0] */ +#define WM8995_WSEQ_ADDR27_WIDTH 14 /* WSEQ_ADDR27 - [13:0] */ + +/* + * R12397 (0x306D) - Write Sequencer 109 + */ +#define WM8995_WSEQ_DATA27_MASK 0x00FF /* WSEQ_DATA27 - [7:0] */ +#define WM8995_WSEQ_DATA27_SHIFT 0 /* WSEQ_DATA27 - [7:0] */ +#define WM8995_WSEQ_DATA27_WIDTH 8 /* WSEQ_DATA27 - [7:0] */ + +/* + * R12398 (0x306E) - Write Sequencer 110 + */ +#define WM8995_WSEQ_DATA_WIDTH27_MASK 0x0700 /* WSEQ_DATA_WIDTH27 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH27_SHIFT 8 /* WSEQ_DATA_WIDTH27 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH27_WIDTH 3 /* WSEQ_DATA_WIDTH27 - [10:8] */ +#define WM8995_WSEQ_DATA_START27_MASK 0x000F /* WSEQ_DATA_START27 - [3:0] */ +#define WM8995_WSEQ_DATA_START27_SHIFT 0 /* WSEQ_DATA_START27 - [3:0] */ +#define WM8995_WSEQ_DATA_START27_WIDTH 4 /* WSEQ_DATA_START27 - [3:0] */ + +/* + * R12399 (0x306F) - Write Sequencer 111 + */ +#define WM8995_WSEQ_EOS27 0x0100 /* WSEQ_EOS27 */ +#define WM8995_WSEQ_EOS27_MASK 0x0100 /* WSEQ_EOS27 */ +#define WM8995_WSEQ_EOS27_SHIFT 8 /* WSEQ_EOS27 */ +#define WM8995_WSEQ_EOS27_WIDTH 1 /* WSEQ_EOS27 */ +#define WM8995_WSEQ_DELAY27_MASK 0x000F /* WSEQ_DELAY27 - [3:0] */ +#define WM8995_WSEQ_DELAY27_SHIFT 0 /* WSEQ_DELAY27 - [3:0] */ +#define WM8995_WSEQ_DELAY27_WIDTH 4 /* WSEQ_DELAY27 - [3:0] */ + +/* + * R12400 (0x3070) - Write Sequencer 112 + */ +#define WM8995_WSEQ_ADDR28_MASK 0x3FFF /* WSEQ_ADDR28 - [13:0] */ +#define WM8995_WSEQ_ADDR28_SHIFT 0 /* WSEQ_ADDR28 - [13:0] */ +#define WM8995_WSEQ_ADDR28_WIDTH 14 /* WSEQ_ADDR28 - [13:0] */ + +/* + * R12401 (0x3071) - Write Sequencer 113 + */ +#define WM8995_WSEQ_DATA28_MASK 0x00FF /* WSEQ_DATA28 - [7:0] */ +#define WM8995_WSEQ_DATA28_SHIFT 0 /* WSEQ_DATA28 - [7:0] */ +#define WM8995_WSEQ_DATA28_WIDTH 8 /* WSEQ_DATA28 - [7:0] */ + +/* + * R12402 (0x3072) - Write Sequencer 114 + */ +#define WM8995_WSEQ_DATA_WIDTH28_MASK 0x0700 /* WSEQ_DATA_WIDTH28 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH28_SHIFT 8 /* WSEQ_DATA_WIDTH28 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH28_WIDTH 3 /* WSEQ_DATA_WIDTH28 - [10:8] */ +#define WM8995_WSEQ_DATA_START28_MASK 0x000F /* WSEQ_DATA_START28 - [3:0] */ +#define WM8995_WSEQ_DATA_START28_SHIFT 0 /* WSEQ_DATA_START28 - [3:0] */ +#define WM8995_WSEQ_DATA_START28_WIDTH 4 /* WSEQ_DATA_START28 - [3:0] */ + +/* + * R12403 (0x3073) - Write Sequencer 115 + */ +#define WM8995_WSEQ_EOS28 0x0100 /* WSEQ_EOS28 */ +#define WM8995_WSEQ_EOS28_MASK 0x0100 /* WSEQ_EOS28 */ +#define WM8995_WSEQ_EOS28_SHIFT 8 /* WSEQ_EOS28 */ +#define WM8995_WSEQ_EOS28_WIDTH 1 /* WSEQ_EOS28 */ +#define WM8995_WSEQ_DELAY28_MASK 0x000F /* WSEQ_DELAY28 - [3:0] */ +#define WM8995_WSEQ_DELAY28_SHIFT 0 /* WSEQ_DELAY28 - [3:0] */ +#define WM8995_WSEQ_DELAY28_WIDTH 4 /* WSEQ_DELAY28 - [3:0] */ + +/* + * R12404 (0x3074) - Write Sequencer 116 + */ +#define WM8995_WSEQ_ADDR29_MASK 0x3FFF /* WSEQ_ADDR29 - [13:0] */ +#define WM8995_WSEQ_ADDR29_SHIFT 0 /* WSEQ_ADDR29 - [13:0] */ +#define WM8995_WSEQ_ADDR29_WIDTH 14 /* WSEQ_ADDR29 - [13:0] */ + +/* + * R12405 (0x3075) - Write Sequencer 117 + */ +#define WM8995_WSEQ_DATA29_MASK 0x00FF /* WSEQ_DATA29 - [7:0] */ +#define WM8995_WSEQ_DATA29_SHIFT 0 /* WSEQ_DATA29 - [7:0] */ +#define WM8995_WSEQ_DATA29_WIDTH 8 /* WSEQ_DATA29 - [7:0] */ + +/* + * R12406 (0x3076) - Write Sequencer 118 + */ +#define WM8995_WSEQ_DATA_WIDTH29_MASK 0x0700 /* WSEQ_DATA_WIDTH29 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH29_SHIFT 8 /* WSEQ_DATA_WIDTH29 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH29_WIDTH 3 /* WSEQ_DATA_WIDTH29 - [10:8] */ +#define WM8995_WSEQ_DATA_START29_MASK 0x000F /* WSEQ_DATA_START29 - [3:0] */ +#define WM8995_WSEQ_DATA_START29_SHIFT 0 /* WSEQ_DATA_START29 - [3:0] */ +#define WM8995_WSEQ_DATA_START29_WIDTH 4 /* WSEQ_DATA_START29 - [3:0] */ + +/* + * R12407 (0x3077) - Write Sequencer 119 + */ +#define WM8995_WSEQ_EOS29 0x0100 /* WSEQ_EOS29 */ +#define WM8995_WSEQ_EOS29_MASK 0x0100 /* WSEQ_EOS29 */ +#define WM8995_WSEQ_EOS29_SHIFT 8 /* WSEQ_EOS29 */ +#define WM8995_WSEQ_EOS29_WIDTH 1 /* WSEQ_EOS29 */ +#define WM8995_WSEQ_DELAY29_MASK 0x000F /* WSEQ_DELAY29 - [3:0] */ +#define WM8995_WSEQ_DELAY29_SHIFT 0 /* WSEQ_DELAY29 - [3:0] */ +#define WM8995_WSEQ_DELAY29_WIDTH 4 /* WSEQ_DELAY29 - [3:0] */ + +/* + * R12408 (0x3078) - Write Sequencer 120 + */ +#define WM8995_WSEQ_ADDR30_MASK 0x3FFF /* WSEQ_ADDR30 - [13:0] */ +#define WM8995_WSEQ_ADDR30_SHIFT 0 /* WSEQ_ADDR30 - [13:0] */ +#define WM8995_WSEQ_ADDR30_WIDTH 14 /* WSEQ_ADDR30 - [13:0] */ + +/* + * R12409 (0x3079) - Write Sequencer 121 + */ +#define WM8995_WSEQ_DATA30_MASK 0x00FF /* WSEQ_DATA30 - [7:0] */ +#define WM8995_WSEQ_DATA30_SHIFT 0 /* WSEQ_DATA30 - [7:0] */ +#define WM8995_WSEQ_DATA30_WIDTH 8 /* WSEQ_DATA30 - [7:0] */ + +/* + * R12410 (0x307A) - Write Sequencer 122 + */ +#define WM8995_WSEQ_DATA_WIDTH30_MASK 0x0700 /* WSEQ_DATA_WIDTH30 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH30_SHIFT 8 /* WSEQ_DATA_WIDTH30 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH30_WIDTH 3 /* WSEQ_DATA_WIDTH30 - [10:8] */ +#define WM8995_WSEQ_DATA_START30_MASK 0x000F /* WSEQ_DATA_START30 - [3:0] */ +#define WM8995_WSEQ_DATA_START30_SHIFT 0 /* WSEQ_DATA_START30 - [3:0] */ +#define WM8995_WSEQ_DATA_START30_WIDTH 4 /* WSEQ_DATA_START30 - [3:0] */ + +/* + * R12411 (0x307B) - Write Sequencer 123 + */ +#define WM8995_WSEQ_EOS30 0x0100 /* WSEQ_EOS30 */ +#define WM8995_WSEQ_EOS30_MASK 0x0100 /* WSEQ_EOS30 */ +#define WM8995_WSEQ_EOS30_SHIFT 8 /* WSEQ_EOS30 */ +#define WM8995_WSEQ_EOS30_WIDTH 1 /* WSEQ_EOS30 */ +#define WM8995_WSEQ_DELAY30_MASK 0x000F /* WSEQ_DELAY30 - [3:0] */ +#define WM8995_WSEQ_DELAY30_SHIFT 0 /* WSEQ_DELAY30 - [3:0] */ +#define WM8995_WSEQ_DELAY30_WIDTH 4 /* WSEQ_DELAY30 - [3:0] */ + +/* + * R12412 (0x307C) - Write Sequencer 124 + */ +#define WM8995_WSEQ_ADDR31_MASK 0x3FFF /* WSEQ_ADDR31 - [13:0] */ +#define WM8995_WSEQ_ADDR31_SHIFT 0 /* WSEQ_ADDR31 - [13:0] */ +#define WM8995_WSEQ_ADDR31_WIDTH 14 /* WSEQ_ADDR31 - [13:0] */ + +/* + * R12413 (0x307D) - Write Sequencer 125 + */ +#define WM8995_WSEQ_DATA31_MASK 0x00FF /* WSEQ_DATA31 - [7:0] */ +#define WM8995_WSEQ_DATA31_SHIFT 0 /* WSEQ_DATA31 - [7:0] */ +#define WM8995_WSEQ_DATA31_WIDTH 8 /* WSEQ_DATA31 - [7:0] */ + +/* + * R12414 (0x307E) - Write Sequencer 126 + */ +#define WM8995_WSEQ_DATA_WIDTH31_MASK 0x0700 /* WSEQ_DATA_WIDTH31 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH31_SHIFT 8 /* WSEQ_DATA_WIDTH31 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH31_WIDTH 3 /* WSEQ_DATA_WIDTH31 - [10:8] */ +#define WM8995_WSEQ_DATA_START31_MASK 0x000F /* WSEQ_DATA_START31 - [3:0] */ +#define WM8995_WSEQ_DATA_START31_SHIFT 0 /* WSEQ_DATA_START31 - [3:0] */ +#define WM8995_WSEQ_DATA_START31_WIDTH 4 /* WSEQ_DATA_START31 - [3:0] */ + +/* + * R12415 (0x307F) - Write Sequencer 127 + */ +#define WM8995_WSEQ_EOS31 0x0100 /* WSEQ_EOS31 */ +#define WM8995_WSEQ_EOS31_MASK 0x0100 /* WSEQ_EOS31 */ +#define WM8995_WSEQ_EOS31_SHIFT 8 /* WSEQ_EOS31 */ +#define WM8995_WSEQ_EOS31_WIDTH 1 /* WSEQ_EOS31 */ +#define WM8995_WSEQ_DELAY31_MASK 0x000F /* WSEQ_DELAY31 - [3:0] */ +#define WM8995_WSEQ_DELAY31_SHIFT 0 /* WSEQ_DELAY31 - [3:0] */ +#define WM8995_WSEQ_DELAY31_WIDTH 4 /* WSEQ_DELAY31 - [3:0] */ + +/* + * R12416 (0x3080) - Write Sequencer 128 + */ +#define WM8995_WSEQ_ADDR32_MASK 0x3FFF /* WSEQ_ADDR32 - [13:0] */ +#define WM8995_WSEQ_ADDR32_SHIFT 0 /* WSEQ_ADDR32 - [13:0] */ +#define WM8995_WSEQ_ADDR32_WIDTH 14 /* WSEQ_ADDR32 - [13:0] */ + +/* + * R12417 (0x3081) - Write Sequencer 129 + */ +#define WM8995_WSEQ_DATA32_MASK 0x00FF /* WSEQ_DATA32 - [7:0] */ +#define WM8995_WSEQ_DATA32_SHIFT 0 /* WSEQ_DATA32 - [7:0] */ +#define WM8995_WSEQ_DATA32_WIDTH 8 /* WSEQ_DATA32 - [7:0] */ + +/* + * R12418 (0x3082) - Write Sequencer 130 + */ +#define WM8995_WSEQ_DATA_WIDTH32_MASK 0x0700 /* WSEQ_DATA_WIDTH32 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH32_SHIFT 8 /* WSEQ_DATA_WIDTH32 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH32_WIDTH 3 /* WSEQ_DATA_WIDTH32 - [10:8] */ +#define WM8995_WSEQ_DATA_START32_MASK 0x000F /* WSEQ_DATA_START32 - [3:0] */ +#define WM8995_WSEQ_DATA_START32_SHIFT 0 /* WSEQ_DATA_START32 - [3:0] */ +#define WM8995_WSEQ_DATA_START32_WIDTH 4 /* WSEQ_DATA_START32 - [3:0] */ + +/* + * R12419 (0x3083) - Write Sequencer 131 + */ +#define WM8995_WSEQ_EOS32 0x0100 /* WSEQ_EOS32 */ +#define WM8995_WSEQ_EOS32_MASK 0x0100 /* WSEQ_EOS32 */ +#define WM8995_WSEQ_EOS32_SHIFT 8 /* WSEQ_EOS32 */ +#define WM8995_WSEQ_EOS32_WIDTH 1 /* WSEQ_EOS32 */ +#define WM8995_WSEQ_DELAY32_MASK 0x000F /* WSEQ_DELAY32 - [3:0] */ +#define WM8995_WSEQ_DELAY32_SHIFT 0 /* WSEQ_DELAY32 - [3:0] */ +#define WM8995_WSEQ_DELAY32_WIDTH 4 /* WSEQ_DELAY32 - [3:0] */ + +/* + * R12420 (0x3084) - Write Sequencer 132 + */ +#define WM8995_WSEQ_ADDR33_MASK 0x3FFF /* WSEQ_ADDR33 - [13:0] */ +#define WM8995_WSEQ_ADDR33_SHIFT 0 /* WSEQ_ADDR33 - [13:0] */ +#define WM8995_WSEQ_ADDR33_WIDTH 14 /* WSEQ_ADDR33 - [13:0] */ + +/* + * R12421 (0x3085) - Write Sequencer 133 + */ +#define WM8995_WSEQ_DATA33_MASK 0x00FF /* WSEQ_DATA33 - [7:0] */ +#define WM8995_WSEQ_DATA33_SHIFT 0 /* WSEQ_DATA33 - [7:0] */ +#define WM8995_WSEQ_DATA33_WIDTH 8 /* WSEQ_DATA33 - [7:0] */ + +/* + * R12422 (0x3086) - Write Sequencer 134 + */ +#define WM8995_WSEQ_DATA_WIDTH33_MASK 0x0700 /* WSEQ_DATA_WIDTH33 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH33_SHIFT 8 /* WSEQ_DATA_WIDTH33 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH33_WIDTH 3 /* WSEQ_DATA_WIDTH33 - [10:8] */ +#define WM8995_WSEQ_DATA_START33_MASK 0x000F /* WSEQ_DATA_START33 - [3:0] */ +#define WM8995_WSEQ_DATA_START33_SHIFT 0 /* WSEQ_DATA_START33 - [3:0] */ +#define WM8995_WSEQ_DATA_START33_WIDTH 4 /* WSEQ_DATA_START33 - [3:0] */ + +/* + * R12423 (0x3087) - Write Sequencer 135 + */ +#define WM8995_WSEQ_EOS33 0x0100 /* WSEQ_EOS33 */ +#define WM8995_WSEQ_EOS33_MASK 0x0100 /* WSEQ_EOS33 */ +#define WM8995_WSEQ_EOS33_SHIFT 8 /* WSEQ_EOS33 */ +#define WM8995_WSEQ_EOS33_WIDTH 1 /* WSEQ_EOS33 */ +#define WM8995_WSEQ_DELAY33_MASK 0x000F /* WSEQ_DELAY33 - [3:0] */ +#define WM8995_WSEQ_DELAY33_SHIFT 0 /* WSEQ_DELAY33 - [3:0] */ +#define WM8995_WSEQ_DELAY33_WIDTH 4 /* WSEQ_DELAY33 - [3:0] */ + +/* + * R12424 (0x3088) - Write Sequencer 136 + */ +#define WM8995_WSEQ_ADDR34_MASK 0x3FFF /* WSEQ_ADDR34 - [13:0] */ +#define WM8995_WSEQ_ADDR34_SHIFT 0 /* WSEQ_ADDR34 - [13:0] */ +#define WM8995_WSEQ_ADDR34_WIDTH 14 /* WSEQ_ADDR34 - [13:0] */ + +/* + * R12425 (0x3089) - Write Sequencer 137 + */ +#define WM8995_WSEQ_DATA34_MASK 0x00FF /* WSEQ_DATA34 - [7:0] */ +#define WM8995_WSEQ_DATA34_SHIFT 0 /* WSEQ_DATA34 - [7:0] */ +#define WM8995_WSEQ_DATA34_WIDTH 8 /* WSEQ_DATA34 - [7:0] */ + +/* + * R12426 (0x308A) - Write Sequencer 138 + */ +#define WM8995_WSEQ_DATA_WIDTH34_MASK 0x0700 /* WSEQ_DATA_WIDTH34 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH34_SHIFT 8 /* WSEQ_DATA_WIDTH34 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH34_WIDTH 3 /* WSEQ_DATA_WIDTH34 - [10:8] */ +#define WM8995_WSEQ_DATA_START34_MASK 0x000F /* WSEQ_DATA_START34 - [3:0] */ +#define WM8995_WSEQ_DATA_START34_SHIFT 0 /* WSEQ_DATA_START34 - [3:0] */ +#define WM8995_WSEQ_DATA_START34_WIDTH 4 /* WSEQ_DATA_START34 - [3:0] */ + +/* + * R12427 (0x308B) - Write Sequencer 139 + */ +#define WM8995_WSEQ_EOS34 0x0100 /* WSEQ_EOS34 */ +#define WM8995_WSEQ_EOS34_MASK 0x0100 /* WSEQ_EOS34 */ +#define WM8995_WSEQ_EOS34_SHIFT 8 /* WSEQ_EOS34 */ +#define WM8995_WSEQ_EOS34_WIDTH 1 /* WSEQ_EOS34 */ +#define WM8995_WSEQ_DELAY34_MASK 0x000F /* WSEQ_DELAY34 - [3:0] */ +#define WM8995_WSEQ_DELAY34_SHIFT 0 /* WSEQ_DELAY34 - [3:0] */ +#define WM8995_WSEQ_DELAY34_WIDTH 4 /* WSEQ_DELAY34 - [3:0] */ + +/* + * R12428 (0x308C) - Write Sequencer 140 + */ +#define WM8995_WSEQ_ADDR35_MASK 0x3FFF /* WSEQ_ADDR35 - [13:0] */ +#define WM8995_WSEQ_ADDR35_SHIFT 0 /* WSEQ_ADDR35 - [13:0] */ +#define WM8995_WSEQ_ADDR35_WIDTH 14 /* WSEQ_ADDR35 - [13:0] */ + +/* + * R12429 (0x308D) - Write Sequencer 141 + */ +#define WM8995_WSEQ_DATA35_MASK 0x00FF /* WSEQ_DATA35 - [7:0] */ +#define WM8995_WSEQ_DATA35_SHIFT 0 /* WSEQ_DATA35 - [7:0] */ +#define WM8995_WSEQ_DATA35_WIDTH 8 /* WSEQ_DATA35 - [7:0] */ + +/* + * R12430 (0x308E) - Write Sequencer 142 + */ +#define WM8995_WSEQ_DATA_WIDTH35_MASK 0x0700 /* WSEQ_DATA_WIDTH35 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH35_SHIFT 8 /* WSEQ_DATA_WIDTH35 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH35_WIDTH 3 /* WSEQ_DATA_WIDTH35 - [10:8] */ +#define WM8995_WSEQ_DATA_START35_MASK 0x000F /* WSEQ_DATA_START35 - [3:0] */ +#define WM8995_WSEQ_DATA_START35_SHIFT 0 /* WSEQ_DATA_START35 - [3:0] */ +#define WM8995_WSEQ_DATA_START35_WIDTH 4 /* WSEQ_DATA_START35 - [3:0] */ + +/* + * R12431 (0x308F) - Write Sequencer 143 + */ +#define WM8995_WSEQ_EOS35 0x0100 /* WSEQ_EOS35 */ +#define WM8995_WSEQ_EOS35_MASK 0x0100 /* WSEQ_EOS35 */ +#define WM8995_WSEQ_EOS35_SHIFT 8 /* WSEQ_EOS35 */ +#define WM8995_WSEQ_EOS35_WIDTH 1 /* WSEQ_EOS35 */ +#define WM8995_WSEQ_DELAY35_MASK 0x000F /* WSEQ_DELAY35 - [3:0] */ +#define WM8995_WSEQ_DELAY35_SHIFT 0 /* WSEQ_DELAY35 - [3:0] */ +#define WM8995_WSEQ_DELAY35_WIDTH 4 /* WSEQ_DELAY35 - [3:0] */ + +/* + * R12432 (0x3090) - Write Sequencer 144 + */ +#define WM8995_WSEQ_ADDR36_MASK 0x3FFF /* WSEQ_ADDR36 - [13:0] */ +#define WM8995_WSEQ_ADDR36_SHIFT 0 /* WSEQ_ADDR36 - [13:0] */ +#define WM8995_WSEQ_ADDR36_WIDTH 14 /* WSEQ_ADDR36 - [13:0] */ + +/* + * R12433 (0x3091) - Write Sequencer 145 + */ +#define WM8995_WSEQ_DATA36_MASK 0x00FF /* WSEQ_DATA36 - [7:0] */ +#define WM8995_WSEQ_DATA36_SHIFT 0 /* WSEQ_DATA36 - [7:0] */ +#define WM8995_WSEQ_DATA36_WIDTH 8 /* WSEQ_DATA36 - [7:0] */ + +/* + * R12434 (0x3092) - Write Sequencer 146 + */ +#define WM8995_WSEQ_DATA_WIDTH36_MASK 0x0700 /* WSEQ_DATA_WIDTH36 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH36_SHIFT 8 /* WSEQ_DATA_WIDTH36 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH36_WIDTH 3 /* WSEQ_DATA_WIDTH36 - [10:8] */ +#define WM8995_WSEQ_DATA_START36_MASK 0x000F /* WSEQ_DATA_START36 - [3:0] */ +#define WM8995_WSEQ_DATA_START36_SHIFT 0 /* WSEQ_DATA_START36 - [3:0] */ +#define WM8995_WSEQ_DATA_START36_WIDTH 4 /* WSEQ_DATA_START36 - [3:0] */ + +/* + * R12435 (0x3093) - Write Sequencer 147 + */ +#define WM8995_WSEQ_EOS36 0x0100 /* WSEQ_EOS36 */ +#define WM8995_WSEQ_EOS36_MASK 0x0100 /* WSEQ_EOS36 */ +#define WM8995_WSEQ_EOS36_SHIFT 8 /* WSEQ_EOS36 */ +#define WM8995_WSEQ_EOS36_WIDTH 1 /* WSEQ_EOS36 */ +#define WM8995_WSEQ_DELAY36_MASK 0x000F /* WSEQ_DELAY36 - [3:0] */ +#define WM8995_WSEQ_DELAY36_SHIFT 0 /* WSEQ_DELAY36 - [3:0] */ +#define WM8995_WSEQ_DELAY36_WIDTH 4 /* WSEQ_DELAY36 - [3:0] */ + +/* + * R12436 (0x3094) - Write Sequencer 148 + */ +#define WM8995_WSEQ_ADDR37_MASK 0x3FFF /* WSEQ_ADDR37 - [13:0] */ +#define WM8995_WSEQ_ADDR37_SHIFT 0 /* WSEQ_ADDR37 - [13:0] */ +#define WM8995_WSEQ_ADDR37_WIDTH 14 /* WSEQ_ADDR37 - [13:0] */ + +/* + * R12437 (0x3095) - Write Sequencer 149 + */ +#define WM8995_WSEQ_DATA37_MASK 0x00FF /* WSEQ_DATA37 - [7:0] */ +#define WM8995_WSEQ_DATA37_SHIFT 0 /* WSEQ_DATA37 - [7:0] */ +#define WM8995_WSEQ_DATA37_WIDTH 8 /* WSEQ_DATA37 - [7:0] */ + +/* + * R12438 (0x3096) - Write Sequencer 150 + */ +#define WM8995_WSEQ_DATA_WIDTH37_MASK 0x0700 /* WSEQ_DATA_WIDTH37 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH37_SHIFT 8 /* WSEQ_DATA_WIDTH37 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH37_WIDTH 3 /* WSEQ_DATA_WIDTH37 - [10:8] */ +#define WM8995_WSEQ_DATA_START37_MASK 0x000F /* WSEQ_DATA_START37 - [3:0] */ +#define WM8995_WSEQ_DATA_START37_SHIFT 0 /* WSEQ_DATA_START37 - [3:0] */ +#define WM8995_WSEQ_DATA_START37_WIDTH 4 /* WSEQ_DATA_START37 - [3:0] */ + +/* + * R12439 (0x3097) - Write Sequencer 151 + */ +#define WM8995_WSEQ_EOS37 0x0100 /* WSEQ_EOS37 */ +#define WM8995_WSEQ_EOS37_MASK 0x0100 /* WSEQ_EOS37 */ +#define WM8995_WSEQ_EOS37_SHIFT 8 /* WSEQ_EOS37 */ +#define WM8995_WSEQ_EOS37_WIDTH 1 /* WSEQ_EOS37 */ +#define WM8995_WSEQ_DELAY37_MASK 0x000F /* WSEQ_DELAY37 - [3:0] */ +#define WM8995_WSEQ_DELAY37_SHIFT 0 /* WSEQ_DELAY37 - [3:0] */ +#define WM8995_WSEQ_DELAY37_WIDTH 4 /* WSEQ_DELAY37 - [3:0] */ + +/* + * R12440 (0x3098) - Write Sequencer 152 + */ +#define WM8995_WSEQ_ADDR38_MASK 0x3FFF /* WSEQ_ADDR38 - [13:0] */ +#define WM8995_WSEQ_ADDR38_SHIFT 0 /* WSEQ_ADDR38 - [13:0] */ +#define WM8995_WSEQ_ADDR38_WIDTH 14 /* WSEQ_ADDR38 - [13:0] */ + +/* + * R12441 (0x3099) - Write Sequencer 153 + */ +#define WM8995_WSEQ_DATA38_MASK 0x00FF /* WSEQ_DATA38 - [7:0] */ +#define WM8995_WSEQ_DATA38_SHIFT 0 /* WSEQ_DATA38 - [7:0] */ +#define WM8995_WSEQ_DATA38_WIDTH 8 /* WSEQ_DATA38 - [7:0] */ + +/* + * R12442 (0x309A) - Write Sequencer 154 + */ +#define WM8995_WSEQ_DATA_WIDTH38_MASK 0x0700 /* WSEQ_DATA_WIDTH38 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH38_SHIFT 8 /* WSEQ_DATA_WIDTH38 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH38_WIDTH 3 /* WSEQ_DATA_WIDTH38 - [10:8] */ +#define WM8995_WSEQ_DATA_START38_MASK 0x000F /* WSEQ_DATA_START38 - [3:0] */ +#define WM8995_WSEQ_DATA_START38_SHIFT 0 /* WSEQ_DATA_START38 - [3:0] */ +#define WM8995_WSEQ_DATA_START38_WIDTH 4 /* WSEQ_DATA_START38 - [3:0] */ + +/* + * R12443 (0x309B) - Write Sequencer 155 + */ +#define WM8995_WSEQ_EOS38 0x0100 /* WSEQ_EOS38 */ +#define WM8995_WSEQ_EOS38_MASK 0x0100 /* WSEQ_EOS38 */ +#define WM8995_WSEQ_EOS38_SHIFT 8 /* WSEQ_EOS38 */ +#define WM8995_WSEQ_EOS38_WIDTH 1 /* WSEQ_EOS38 */ +#define WM8995_WSEQ_DELAY38_MASK 0x000F /* WSEQ_DELAY38 - [3:0] */ +#define WM8995_WSEQ_DELAY38_SHIFT 0 /* WSEQ_DELAY38 - [3:0] */ +#define WM8995_WSEQ_DELAY38_WIDTH 4 /* WSEQ_DELAY38 - [3:0] */ + +/* + * R12444 (0x309C) - Write Sequencer 156 + */ +#define WM8995_WSEQ_ADDR39_MASK 0x3FFF /* WSEQ_ADDR39 - [13:0] */ +#define WM8995_WSEQ_ADDR39_SHIFT 0 /* WSEQ_ADDR39 - [13:0] */ +#define WM8995_WSEQ_ADDR39_WIDTH 14 /* WSEQ_ADDR39 - [13:0] */ + +/* + * R12445 (0x309D) - Write Sequencer 157 + */ +#define WM8995_WSEQ_DATA39_MASK 0x00FF /* WSEQ_DATA39 - [7:0] */ +#define WM8995_WSEQ_DATA39_SHIFT 0 /* WSEQ_DATA39 - [7:0] */ +#define WM8995_WSEQ_DATA39_WIDTH 8 /* WSEQ_DATA39 - [7:0] */ + +/* + * R12446 (0x309E) - Write Sequencer 158 + */ +#define WM8995_WSEQ_DATA_WIDTH39_MASK 0x0700 /* WSEQ_DATA_WIDTH39 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH39_SHIFT 8 /* WSEQ_DATA_WIDTH39 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH39_WIDTH 3 /* WSEQ_DATA_WIDTH39 - [10:8] */ +#define WM8995_WSEQ_DATA_START39_MASK 0x000F /* WSEQ_DATA_START39 - [3:0] */ +#define WM8995_WSEQ_DATA_START39_SHIFT 0 /* WSEQ_DATA_START39 - [3:0] */ +#define WM8995_WSEQ_DATA_START39_WIDTH 4 /* WSEQ_DATA_START39 - [3:0] */ + +/* + * R12447 (0x309F) - Write Sequencer 159 + */ +#define WM8995_WSEQ_EOS39 0x0100 /* WSEQ_EOS39 */ +#define WM8995_WSEQ_EOS39_MASK 0x0100 /* WSEQ_EOS39 */ +#define WM8995_WSEQ_EOS39_SHIFT 8 /* WSEQ_EOS39 */ +#define WM8995_WSEQ_EOS39_WIDTH 1 /* WSEQ_EOS39 */ +#define WM8995_WSEQ_DELAY39_MASK 0x000F /* WSEQ_DELAY39 - [3:0] */ +#define WM8995_WSEQ_DELAY39_SHIFT 0 /* WSEQ_DELAY39 - [3:0] */ +#define WM8995_WSEQ_DELAY39_WIDTH 4 /* WSEQ_DELAY39 - [3:0] */ + +/* + * R12448 (0x30A0) - Write Sequencer 160 + */ +#define WM8995_WSEQ_ADDR40_MASK 0x3FFF /* WSEQ_ADDR40 - [13:0] */ +#define WM8995_WSEQ_ADDR40_SHIFT 0 /* WSEQ_ADDR40 - [13:0] */ +#define WM8995_WSEQ_ADDR40_WIDTH 14 /* WSEQ_ADDR40 - [13:0] */ + +/* + * R12449 (0x30A1) - Write Sequencer 161 + */ +#define WM8995_WSEQ_DATA40_MASK 0x00FF /* WSEQ_DATA40 - [7:0] */ +#define WM8995_WSEQ_DATA40_SHIFT 0 /* WSEQ_DATA40 - [7:0] */ +#define WM8995_WSEQ_DATA40_WIDTH 8 /* WSEQ_DATA40 - [7:0] */ + +/* + * R12450 (0x30A2) - Write Sequencer 162 + */ +#define WM8995_WSEQ_DATA_WIDTH40_MASK 0x0700 /* WSEQ_DATA_WIDTH40 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH40_SHIFT 8 /* WSEQ_DATA_WIDTH40 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH40_WIDTH 3 /* WSEQ_DATA_WIDTH40 - [10:8] */ +#define WM8995_WSEQ_DATA_START40_MASK 0x000F /* WSEQ_DATA_START40 - [3:0] */ +#define WM8995_WSEQ_DATA_START40_SHIFT 0 /* WSEQ_DATA_START40 - [3:0] */ +#define WM8995_WSEQ_DATA_START40_WIDTH 4 /* WSEQ_DATA_START40 - [3:0] */ + +/* + * R12451 (0x30A3) - Write Sequencer 163 + */ +#define WM8995_WSEQ_EOS40 0x0100 /* WSEQ_EOS40 */ +#define WM8995_WSEQ_EOS40_MASK 0x0100 /* WSEQ_EOS40 */ +#define WM8995_WSEQ_EOS40_SHIFT 8 /* WSEQ_EOS40 */ +#define WM8995_WSEQ_EOS40_WIDTH 1 /* WSEQ_EOS40 */ +#define WM8995_WSEQ_DELAY40_MASK 0x000F /* WSEQ_DELAY40 - [3:0] */ +#define WM8995_WSEQ_DELAY40_SHIFT 0 /* WSEQ_DELAY40 - [3:0] */ +#define WM8995_WSEQ_DELAY40_WIDTH 4 /* WSEQ_DELAY40 - [3:0] */ + +/* + * R12452 (0x30A4) - Write Sequencer 164 + */ +#define WM8995_WSEQ_ADDR41_MASK 0x3FFF /* WSEQ_ADDR41 - [13:0] */ +#define WM8995_WSEQ_ADDR41_SHIFT 0 /* WSEQ_ADDR41 - [13:0] */ +#define WM8995_WSEQ_ADDR41_WIDTH 14 /* WSEQ_ADDR41 - [13:0] */ + +/* + * R12453 (0x30A5) - Write Sequencer 165 + */ +#define WM8995_WSEQ_DATA41_MASK 0x00FF /* WSEQ_DATA41 - [7:0] */ +#define WM8995_WSEQ_DATA41_SHIFT 0 /* WSEQ_DATA41 - [7:0] */ +#define WM8995_WSEQ_DATA41_WIDTH 8 /* WSEQ_DATA41 - [7:0] */ + +/* + * R12454 (0x30A6) - Write Sequencer 166 + */ +#define WM8995_WSEQ_DATA_WIDTH41_MASK 0x0700 /* WSEQ_DATA_WIDTH41 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH41_SHIFT 8 /* WSEQ_DATA_WIDTH41 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH41_WIDTH 3 /* WSEQ_DATA_WIDTH41 - [10:8] */ +#define WM8995_WSEQ_DATA_START41_MASK 0x000F /* WSEQ_DATA_START41 - [3:0] */ +#define WM8995_WSEQ_DATA_START41_SHIFT 0 /* WSEQ_DATA_START41 - [3:0] */ +#define WM8995_WSEQ_DATA_START41_WIDTH 4 /* WSEQ_DATA_START41 - [3:0] */ + +/* + * R12455 (0x30A7) - Write Sequencer 167 + */ +#define WM8995_WSEQ_EOS41 0x0100 /* WSEQ_EOS41 */ +#define WM8995_WSEQ_EOS41_MASK 0x0100 /* WSEQ_EOS41 */ +#define WM8995_WSEQ_EOS41_SHIFT 8 /* WSEQ_EOS41 */ +#define WM8995_WSEQ_EOS41_WIDTH 1 /* WSEQ_EOS41 */ +#define WM8995_WSEQ_DELAY41_MASK 0x000F /* WSEQ_DELAY41 - [3:0] */ +#define WM8995_WSEQ_DELAY41_SHIFT 0 /* WSEQ_DELAY41 - [3:0] */ +#define WM8995_WSEQ_DELAY41_WIDTH 4 /* WSEQ_DELAY41 - [3:0] */ + +/* + * R12456 (0x30A8) - Write Sequencer 168 + */ +#define WM8995_WSEQ_ADDR42_MASK 0x3FFF /* WSEQ_ADDR42 - [13:0] */ +#define WM8995_WSEQ_ADDR42_SHIFT 0 /* WSEQ_ADDR42 - [13:0] */ +#define WM8995_WSEQ_ADDR42_WIDTH 14 /* WSEQ_ADDR42 - [13:0] */ + +/* + * R12457 (0x30A9) - Write Sequencer 169 + */ +#define WM8995_WSEQ_DATA42_MASK 0x00FF /* WSEQ_DATA42 - [7:0] */ +#define WM8995_WSEQ_DATA42_SHIFT 0 /* WSEQ_DATA42 - [7:0] */ +#define WM8995_WSEQ_DATA42_WIDTH 8 /* WSEQ_DATA42 - [7:0] */ + +/* + * R12458 (0x30AA) - Write Sequencer 170 + */ +#define WM8995_WSEQ_DATA_WIDTH42_MASK 0x0700 /* WSEQ_DATA_WIDTH42 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH42_SHIFT 8 /* WSEQ_DATA_WIDTH42 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH42_WIDTH 3 /* WSEQ_DATA_WIDTH42 - [10:8] */ +#define WM8995_WSEQ_DATA_START42_MASK 0x000F /* WSEQ_DATA_START42 - [3:0] */ +#define WM8995_WSEQ_DATA_START42_SHIFT 0 /* WSEQ_DATA_START42 - [3:0] */ +#define WM8995_WSEQ_DATA_START42_WIDTH 4 /* WSEQ_DATA_START42 - [3:0] */ + +/* + * R12459 (0x30AB) - Write Sequencer 171 + */ +#define WM8995_WSEQ_EOS42 0x0100 /* WSEQ_EOS42 */ +#define WM8995_WSEQ_EOS42_MASK 0x0100 /* WSEQ_EOS42 */ +#define WM8995_WSEQ_EOS42_SHIFT 8 /* WSEQ_EOS42 */ +#define WM8995_WSEQ_EOS42_WIDTH 1 /* WSEQ_EOS42 */ +#define WM8995_WSEQ_DELAY42_MASK 0x000F /* WSEQ_DELAY42 - [3:0] */ +#define WM8995_WSEQ_DELAY42_SHIFT 0 /* WSEQ_DELAY42 - [3:0] */ +#define WM8995_WSEQ_DELAY42_WIDTH 4 /* WSEQ_DELAY42 - [3:0] */ + +/* + * R12460 (0x30AC) - Write Sequencer 172 + */ +#define WM8995_WSEQ_ADDR43_MASK 0x3FFF /* WSEQ_ADDR43 - [13:0] */ +#define WM8995_WSEQ_ADDR43_SHIFT 0 /* WSEQ_ADDR43 - [13:0] */ +#define WM8995_WSEQ_ADDR43_WIDTH 14 /* WSEQ_ADDR43 - [13:0] */ + +/* + * R12461 (0x30AD) - Write Sequencer 173 + */ +#define WM8995_WSEQ_DATA43_MASK 0x00FF /* WSEQ_DATA43 - [7:0] */ +#define WM8995_WSEQ_DATA43_SHIFT 0 /* WSEQ_DATA43 - [7:0] */ +#define WM8995_WSEQ_DATA43_WIDTH 8 /* WSEQ_DATA43 - [7:0] */ + +/* + * R12462 (0x30AE) - Write Sequencer 174 + */ +#define WM8995_WSEQ_DATA_WIDTH43_MASK 0x0700 /* WSEQ_DATA_WIDTH43 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH43_SHIFT 8 /* WSEQ_DATA_WIDTH43 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH43_WIDTH 3 /* WSEQ_DATA_WIDTH43 - [10:8] */ +#define WM8995_WSEQ_DATA_START43_MASK 0x000F /* WSEQ_DATA_START43 - [3:0] */ +#define WM8995_WSEQ_DATA_START43_SHIFT 0 /* WSEQ_DATA_START43 - [3:0] */ +#define WM8995_WSEQ_DATA_START43_WIDTH 4 /* WSEQ_DATA_START43 - [3:0] */ + +/* + * R12463 (0x30AF) - Write Sequencer 175 + */ +#define WM8995_WSEQ_EOS43 0x0100 /* WSEQ_EOS43 */ +#define WM8995_WSEQ_EOS43_MASK 0x0100 /* WSEQ_EOS43 */ +#define WM8995_WSEQ_EOS43_SHIFT 8 /* WSEQ_EOS43 */ +#define WM8995_WSEQ_EOS43_WIDTH 1 /* WSEQ_EOS43 */ +#define WM8995_WSEQ_DELAY43_MASK 0x000F /* WSEQ_DELAY43 - [3:0] */ +#define WM8995_WSEQ_DELAY43_SHIFT 0 /* WSEQ_DELAY43 - [3:0] */ +#define WM8995_WSEQ_DELAY43_WIDTH 4 /* WSEQ_DELAY43 - [3:0] */ + +/* + * R12464 (0x30B0) - Write Sequencer 176 + */ +#define WM8995_WSEQ_ADDR44_MASK 0x3FFF /* WSEQ_ADDR44 - [13:0] */ +#define WM8995_WSEQ_ADDR44_SHIFT 0 /* WSEQ_ADDR44 - [13:0] */ +#define WM8995_WSEQ_ADDR44_WIDTH 14 /* WSEQ_ADDR44 - [13:0] */ + +/* + * R12465 (0x30B1) - Write Sequencer 177 + */ +#define WM8995_WSEQ_DATA44_MASK 0x00FF /* WSEQ_DATA44 - [7:0] */ +#define WM8995_WSEQ_DATA44_SHIFT 0 /* WSEQ_DATA44 - [7:0] */ +#define WM8995_WSEQ_DATA44_WIDTH 8 /* WSEQ_DATA44 - [7:0] */ + +/* + * R12466 (0x30B2) - Write Sequencer 178 + */ +#define WM8995_WSEQ_DATA_WIDTH44_MASK 0x0700 /* WSEQ_DATA_WIDTH44 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH44_SHIFT 8 /* WSEQ_DATA_WIDTH44 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH44_WIDTH 3 /* WSEQ_DATA_WIDTH44 - [10:8] */ +#define WM8995_WSEQ_DATA_START44_MASK 0x000F /* WSEQ_DATA_START44 - [3:0] */ +#define WM8995_WSEQ_DATA_START44_SHIFT 0 /* WSEQ_DATA_START44 - [3:0] */ +#define WM8995_WSEQ_DATA_START44_WIDTH 4 /* WSEQ_DATA_START44 - [3:0] */ + +/* + * R12467 (0x30B3) - Write Sequencer 179 + */ +#define WM8995_WSEQ_EOS44 0x0100 /* WSEQ_EOS44 */ +#define WM8995_WSEQ_EOS44_MASK 0x0100 /* WSEQ_EOS44 */ +#define WM8995_WSEQ_EOS44_SHIFT 8 /* WSEQ_EOS44 */ +#define WM8995_WSEQ_EOS44_WIDTH 1 /* WSEQ_EOS44 */ +#define WM8995_WSEQ_DELAY44_MASK 0x000F /* WSEQ_DELAY44 - [3:0] */ +#define WM8995_WSEQ_DELAY44_SHIFT 0 /* WSEQ_DELAY44 - [3:0] */ +#define WM8995_WSEQ_DELAY44_WIDTH 4 /* WSEQ_DELAY44 - [3:0] */ + +/* + * R12468 (0x30B4) - Write Sequencer 180 + */ +#define WM8995_WSEQ_ADDR45_MASK 0x3FFF /* WSEQ_ADDR45 - [13:0] */ +#define WM8995_WSEQ_ADDR45_SHIFT 0 /* WSEQ_ADDR45 - [13:0] */ +#define WM8995_WSEQ_ADDR45_WIDTH 14 /* WSEQ_ADDR45 - [13:0] */ + +/* + * R12469 (0x30B5) - Write Sequencer 181 + */ +#define WM8995_WSEQ_DATA45_MASK 0x00FF /* WSEQ_DATA45 - [7:0] */ +#define WM8995_WSEQ_DATA45_SHIFT 0 /* WSEQ_DATA45 - [7:0] */ +#define WM8995_WSEQ_DATA45_WIDTH 8 /* WSEQ_DATA45 - [7:0] */ + +/* + * R12470 (0x30B6) - Write Sequencer 182 + */ +#define WM8995_WSEQ_DATA_WIDTH45_MASK 0x0700 /* WSEQ_DATA_WIDTH45 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH45_SHIFT 8 /* WSEQ_DATA_WIDTH45 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH45_WIDTH 3 /* WSEQ_DATA_WIDTH45 - [10:8] */ +#define WM8995_WSEQ_DATA_START45_MASK 0x000F /* WSEQ_DATA_START45 - [3:0] */ +#define WM8995_WSEQ_DATA_START45_SHIFT 0 /* WSEQ_DATA_START45 - [3:0] */ +#define WM8995_WSEQ_DATA_START45_WIDTH 4 /* WSEQ_DATA_START45 - [3:0] */ + +/* + * R12471 (0x30B7) - Write Sequencer 183 + */ +#define WM8995_WSEQ_EOS45 0x0100 /* WSEQ_EOS45 */ +#define WM8995_WSEQ_EOS45_MASK 0x0100 /* WSEQ_EOS45 */ +#define WM8995_WSEQ_EOS45_SHIFT 8 /* WSEQ_EOS45 */ +#define WM8995_WSEQ_EOS45_WIDTH 1 /* WSEQ_EOS45 */ +#define WM8995_WSEQ_DELAY45_MASK 0x000F /* WSEQ_DELAY45 - [3:0] */ +#define WM8995_WSEQ_DELAY45_SHIFT 0 /* WSEQ_DELAY45 - [3:0] */ +#define WM8995_WSEQ_DELAY45_WIDTH 4 /* WSEQ_DELAY45 - [3:0] */ + +/* + * R12472 (0x30B8) - Write Sequencer 184 + */ +#define WM8995_WSEQ_ADDR46_MASK 0x3FFF /* WSEQ_ADDR46 - [13:0] */ +#define WM8995_WSEQ_ADDR46_SHIFT 0 /* WSEQ_ADDR46 - [13:0] */ +#define WM8995_WSEQ_ADDR46_WIDTH 14 /* WSEQ_ADDR46 - [13:0] */ + +/* + * R12473 (0x30B9) - Write Sequencer 185 + */ +#define WM8995_WSEQ_DATA46_MASK 0x00FF /* WSEQ_DATA46 - [7:0] */ +#define WM8995_WSEQ_DATA46_SHIFT 0 /* WSEQ_DATA46 - [7:0] */ +#define WM8995_WSEQ_DATA46_WIDTH 8 /* WSEQ_DATA46 - [7:0] */ + +/* + * R12474 (0x30BA) - Write Sequencer 186 + */ +#define WM8995_WSEQ_DATA_WIDTH46_MASK 0x0700 /* WSEQ_DATA_WIDTH46 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH46_SHIFT 8 /* WSEQ_DATA_WIDTH46 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH46_WIDTH 3 /* WSEQ_DATA_WIDTH46 - [10:8] */ +#define WM8995_WSEQ_DATA_START46_MASK 0x000F /* WSEQ_DATA_START46 - [3:0] */ +#define WM8995_WSEQ_DATA_START46_SHIFT 0 /* WSEQ_DATA_START46 - [3:0] */ +#define WM8995_WSEQ_DATA_START46_WIDTH 4 /* WSEQ_DATA_START46 - [3:0] */ + +/* + * R12475 (0x30BB) - Write Sequencer 187 + */ +#define WM8995_WSEQ_EOS46 0x0100 /* WSEQ_EOS46 */ +#define WM8995_WSEQ_EOS46_MASK 0x0100 /* WSEQ_EOS46 */ +#define WM8995_WSEQ_EOS46_SHIFT 8 /* WSEQ_EOS46 */ +#define WM8995_WSEQ_EOS46_WIDTH 1 /* WSEQ_EOS46 */ +#define WM8995_WSEQ_DELAY46_MASK 0x000F /* WSEQ_DELAY46 - [3:0] */ +#define WM8995_WSEQ_DELAY46_SHIFT 0 /* WSEQ_DELAY46 - [3:0] */ +#define WM8995_WSEQ_DELAY46_WIDTH 4 /* WSEQ_DELAY46 - [3:0] */ + +/* + * R12476 (0x30BC) - Write Sequencer 188 + */ +#define WM8995_WSEQ_ADDR47_MASK 0x3FFF /* WSEQ_ADDR47 - [13:0] */ +#define WM8995_WSEQ_ADDR47_SHIFT 0 /* WSEQ_ADDR47 - [13:0] */ +#define WM8995_WSEQ_ADDR47_WIDTH 14 /* WSEQ_ADDR47 - [13:0] */ + +/* + * R12477 (0x30BD) - Write Sequencer 189 + */ +#define WM8995_WSEQ_DATA47_MASK 0x00FF /* WSEQ_DATA47 - [7:0] */ +#define WM8995_WSEQ_DATA47_SHIFT 0 /* WSEQ_DATA47 - [7:0] */ +#define WM8995_WSEQ_DATA47_WIDTH 8 /* WSEQ_DATA47 - [7:0] */ + +/* + * R12478 (0x30BE) - Write Sequencer 190 + */ +#define WM8995_WSEQ_DATA_WIDTH47_MASK 0x0700 /* WSEQ_DATA_WIDTH47 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH47_SHIFT 8 /* WSEQ_DATA_WIDTH47 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH47_WIDTH 3 /* WSEQ_DATA_WIDTH47 - [10:8] */ +#define WM8995_WSEQ_DATA_START47_MASK 0x000F /* WSEQ_DATA_START47 - [3:0] */ +#define WM8995_WSEQ_DATA_START47_SHIFT 0 /* WSEQ_DATA_START47 - [3:0] */ +#define WM8995_WSEQ_DATA_START47_WIDTH 4 /* WSEQ_DATA_START47 - [3:0] */ + +/* + * R12479 (0x30BF) - Write Sequencer 191 + */ +#define WM8995_WSEQ_EOS47 0x0100 /* WSEQ_EOS47 */ +#define WM8995_WSEQ_EOS47_MASK 0x0100 /* WSEQ_EOS47 */ +#define WM8995_WSEQ_EOS47_SHIFT 8 /* WSEQ_EOS47 */ +#define WM8995_WSEQ_EOS47_WIDTH 1 /* WSEQ_EOS47 */ +#define WM8995_WSEQ_DELAY47_MASK 0x000F /* WSEQ_DELAY47 - [3:0] */ +#define WM8995_WSEQ_DELAY47_SHIFT 0 /* WSEQ_DELAY47 - [3:0] */ +#define WM8995_WSEQ_DELAY47_WIDTH 4 /* WSEQ_DELAY47 - [3:0] */ + +/* + * R12480 (0x30C0) - Write Sequencer 192 + */ +#define WM8995_WSEQ_ADDR48_MASK 0x3FFF /* WSEQ_ADDR48 - [13:0] */ +#define WM8995_WSEQ_ADDR48_SHIFT 0 /* WSEQ_ADDR48 - [13:0] */ +#define WM8995_WSEQ_ADDR48_WIDTH 14 /* WSEQ_ADDR48 - [13:0] */ + +/* + * R12481 (0x30C1) - Write Sequencer 193 + */ +#define WM8995_WSEQ_DATA48_MASK 0x00FF /* WSEQ_DATA48 - [7:0] */ +#define WM8995_WSEQ_DATA48_SHIFT 0 /* WSEQ_DATA48 - [7:0] */ +#define WM8995_WSEQ_DATA48_WIDTH 8 /* WSEQ_DATA48 - [7:0] */ + +/* + * R12482 (0x30C2) - Write Sequencer 194 + */ +#define WM8995_WSEQ_DATA_WIDTH48_MASK 0x0700 /* WSEQ_DATA_WIDTH48 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH48_SHIFT 8 /* WSEQ_DATA_WIDTH48 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH48_WIDTH 3 /* WSEQ_DATA_WIDTH48 - [10:8] */ +#define WM8995_WSEQ_DATA_START48_MASK 0x000F /* WSEQ_DATA_START48 - [3:0] */ +#define WM8995_WSEQ_DATA_START48_SHIFT 0 /* WSEQ_DATA_START48 - [3:0] */ +#define WM8995_WSEQ_DATA_START48_WIDTH 4 /* WSEQ_DATA_START48 - [3:0] */ + +/* + * R12483 (0x30C3) - Write Sequencer 195 + */ +#define WM8995_WSEQ_EOS48 0x0100 /* WSEQ_EOS48 */ +#define WM8995_WSEQ_EOS48_MASK 0x0100 /* WSEQ_EOS48 */ +#define WM8995_WSEQ_EOS48_SHIFT 8 /* WSEQ_EOS48 */ +#define WM8995_WSEQ_EOS48_WIDTH 1 /* WSEQ_EOS48 */ +#define WM8995_WSEQ_DELAY48_MASK 0x000F /* WSEQ_DELAY48 - [3:0] */ +#define WM8995_WSEQ_DELAY48_SHIFT 0 /* WSEQ_DELAY48 - [3:0] */ +#define WM8995_WSEQ_DELAY48_WIDTH 4 /* WSEQ_DELAY48 - [3:0] */ + +/* + * R12484 (0x30C4) - Write Sequencer 196 + */ +#define WM8995_WSEQ_ADDR49_MASK 0x3FFF /* WSEQ_ADDR49 - [13:0] */ +#define WM8995_WSEQ_ADDR49_SHIFT 0 /* WSEQ_ADDR49 - [13:0] */ +#define WM8995_WSEQ_ADDR49_WIDTH 14 /* WSEQ_ADDR49 - [13:0] */ + +/* + * R12485 (0x30C5) - Write Sequencer 197 + */ +#define WM8995_WSEQ_DATA49_MASK 0x00FF /* WSEQ_DATA49 - [7:0] */ +#define WM8995_WSEQ_DATA49_SHIFT 0 /* WSEQ_DATA49 - [7:0] */ +#define WM8995_WSEQ_DATA49_WIDTH 8 /* WSEQ_DATA49 - [7:0] */ + +/* + * R12486 (0x30C6) - Write Sequencer 198 + */ +#define WM8995_WSEQ_DATA_WIDTH49_MASK 0x0700 /* WSEQ_DATA_WIDTH49 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH49_SHIFT 8 /* WSEQ_DATA_WIDTH49 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH49_WIDTH 3 /* WSEQ_DATA_WIDTH49 - [10:8] */ +#define WM8995_WSEQ_DATA_START49_MASK 0x000F /* WSEQ_DATA_START49 - [3:0] */ +#define WM8995_WSEQ_DATA_START49_SHIFT 0 /* WSEQ_DATA_START49 - [3:0] */ +#define WM8995_WSEQ_DATA_START49_WIDTH 4 /* WSEQ_DATA_START49 - [3:0] */ + +/* + * R12487 (0x30C7) - Write Sequencer 199 + */ +#define WM8995_WSEQ_EOS49 0x0100 /* WSEQ_EOS49 */ +#define WM8995_WSEQ_EOS49_MASK 0x0100 /* WSEQ_EOS49 */ +#define WM8995_WSEQ_EOS49_SHIFT 8 /* WSEQ_EOS49 */ +#define WM8995_WSEQ_EOS49_WIDTH 1 /* WSEQ_EOS49 */ +#define WM8995_WSEQ_DELAY49_MASK 0x000F /* WSEQ_DELAY49 - [3:0] */ +#define WM8995_WSEQ_DELAY49_SHIFT 0 /* WSEQ_DELAY49 - [3:0] */ +#define WM8995_WSEQ_DELAY49_WIDTH 4 /* WSEQ_DELAY49 - [3:0] */ + +/* + * R12488 (0x30C8) - Write Sequencer 200 + */ +#define WM8995_WSEQ_ADDR50_MASK 0x3FFF /* WSEQ_ADDR50 - [13:0] */ +#define WM8995_WSEQ_ADDR50_SHIFT 0 /* WSEQ_ADDR50 - [13:0] */ +#define WM8995_WSEQ_ADDR50_WIDTH 14 /* WSEQ_ADDR50 - [13:0] */ + +/* + * R12489 (0x30C9) - Write Sequencer 201 + */ +#define WM8995_WSEQ_DATA50_MASK 0x00FF /* WSEQ_DATA50 - [7:0] */ +#define WM8995_WSEQ_DATA50_SHIFT 0 /* WSEQ_DATA50 - [7:0] */ +#define WM8995_WSEQ_DATA50_WIDTH 8 /* WSEQ_DATA50 - [7:0] */ + +/* + * R12490 (0x30CA) - Write Sequencer 202 + */ +#define WM8995_WSEQ_DATA_WIDTH50_MASK 0x0700 /* WSEQ_DATA_WIDTH50 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH50_SHIFT 8 /* WSEQ_DATA_WIDTH50 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH50_WIDTH 3 /* WSEQ_DATA_WIDTH50 - [10:8] */ +#define WM8995_WSEQ_DATA_START50_MASK 0x000F /* WSEQ_DATA_START50 - [3:0] */ +#define WM8995_WSEQ_DATA_START50_SHIFT 0 /* WSEQ_DATA_START50 - [3:0] */ +#define WM8995_WSEQ_DATA_START50_WIDTH 4 /* WSEQ_DATA_START50 - [3:0] */ + +/* + * R12491 (0x30CB) - Write Sequencer 203 + */ +#define WM8995_WSEQ_EOS50 0x0100 /* WSEQ_EOS50 */ +#define WM8995_WSEQ_EOS50_MASK 0x0100 /* WSEQ_EOS50 */ +#define WM8995_WSEQ_EOS50_SHIFT 8 /* WSEQ_EOS50 */ +#define WM8995_WSEQ_EOS50_WIDTH 1 /* WSEQ_EOS50 */ +#define WM8995_WSEQ_DELAY50_MASK 0x000F /* WSEQ_DELAY50 - [3:0] */ +#define WM8995_WSEQ_DELAY50_SHIFT 0 /* WSEQ_DELAY50 - [3:0] */ +#define WM8995_WSEQ_DELAY50_WIDTH 4 /* WSEQ_DELAY50 - [3:0] */ + +/* + * R12492 (0x30CC) - Write Sequencer 204 + */ +#define WM8995_WSEQ_ADDR51_MASK 0x3FFF /* WSEQ_ADDR51 - [13:0] */ +#define WM8995_WSEQ_ADDR51_SHIFT 0 /* WSEQ_ADDR51 - [13:0] */ +#define WM8995_WSEQ_ADDR51_WIDTH 14 /* WSEQ_ADDR51 - [13:0] */ + +/* + * R12493 (0x30CD) - Write Sequencer 205 + */ +#define WM8995_WSEQ_DATA51_MASK 0x00FF /* WSEQ_DATA51 - [7:0] */ +#define WM8995_WSEQ_DATA51_SHIFT 0 /* WSEQ_DATA51 - [7:0] */ +#define WM8995_WSEQ_DATA51_WIDTH 8 /* WSEQ_DATA51 - [7:0] */ + +/* + * R12494 (0x30CE) - Write Sequencer 206 + */ +#define WM8995_WSEQ_DATA_WIDTH51_MASK 0x0700 /* WSEQ_DATA_WIDTH51 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH51_SHIFT 8 /* WSEQ_DATA_WIDTH51 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH51_WIDTH 3 /* WSEQ_DATA_WIDTH51 - [10:8] */ +#define WM8995_WSEQ_DATA_START51_MASK 0x000F /* WSEQ_DATA_START51 - [3:0] */ +#define WM8995_WSEQ_DATA_START51_SHIFT 0 /* WSEQ_DATA_START51 - [3:0] */ +#define WM8995_WSEQ_DATA_START51_WIDTH 4 /* WSEQ_DATA_START51 - [3:0] */ + +/* + * R12495 (0x30CF) - Write Sequencer 207 + */ +#define WM8995_WSEQ_EOS51 0x0100 /* WSEQ_EOS51 */ +#define WM8995_WSEQ_EOS51_MASK 0x0100 /* WSEQ_EOS51 */ +#define WM8995_WSEQ_EOS51_SHIFT 8 /* WSEQ_EOS51 */ +#define WM8995_WSEQ_EOS51_WIDTH 1 /* WSEQ_EOS51 */ +#define WM8995_WSEQ_DELAY51_MASK 0x000F /* WSEQ_DELAY51 - [3:0] */ +#define WM8995_WSEQ_DELAY51_SHIFT 0 /* WSEQ_DELAY51 - [3:0] */ +#define WM8995_WSEQ_DELAY51_WIDTH 4 /* WSEQ_DELAY51 - [3:0] */ + +/* + * R12496 (0x30D0) - Write Sequencer 208 + */ +#define WM8995_WSEQ_ADDR52_MASK 0x3FFF /* WSEQ_ADDR52 - [13:0] */ +#define WM8995_WSEQ_ADDR52_SHIFT 0 /* WSEQ_ADDR52 - [13:0] */ +#define WM8995_WSEQ_ADDR52_WIDTH 14 /* WSEQ_ADDR52 - [13:0] */ + +/* + * R12497 (0x30D1) - Write Sequencer 209 + */ +#define WM8995_WSEQ_DATA52_MASK 0x00FF /* WSEQ_DATA52 - [7:0] */ +#define WM8995_WSEQ_DATA52_SHIFT 0 /* WSEQ_DATA52 - [7:0] */ +#define WM8995_WSEQ_DATA52_WIDTH 8 /* WSEQ_DATA52 - [7:0] */ + +/* + * R12498 (0x30D2) - Write Sequencer 210 + */ +#define WM8995_WSEQ_DATA_WIDTH52_MASK 0x0700 /* WSEQ_DATA_WIDTH52 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH52_SHIFT 8 /* WSEQ_DATA_WIDTH52 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH52_WIDTH 3 /* WSEQ_DATA_WIDTH52 - [10:8] */ +#define WM8995_WSEQ_DATA_START52_MASK 0x000F /* WSEQ_DATA_START52 - [3:0] */ +#define WM8995_WSEQ_DATA_START52_SHIFT 0 /* WSEQ_DATA_START52 - [3:0] */ +#define WM8995_WSEQ_DATA_START52_WIDTH 4 /* WSEQ_DATA_START52 - [3:0] */ + +/* + * R12499 (0x30D3) - Write Sequencer 211 + */ +#define WM8995_WSEQ_EOS52 0x0100 /* WSEQ_EOS52 */ +#define WM8995_WSEQ_EOS52_MASK 0x0100 /* WSEQ_EOS52 */ +#define WM8995_WSEQ_EOS52_SHIFT 8 /* WSEQ_EOS52 */ +#define WM8995_WSEQ_EOS52_WIDTH 1 /* WSEQ_EOS52 */ +#define WM8995_WSEQ_DELAY52_MASK 0x000F /* WSEQ_DELAY52 - [3:0] */ +#define WM8995_WSEQ_DELAY52_SHIFT 0 /* WSEQ_DELAY52 - [3:0] */ +#define WM8995_WSEQ_DELAY52_WIDTH 4 /* WSEQ_DELAY52 - [3:0] */ + +/* + * R12500 (0x30D4) - Write Sequencer 212 + */ +#define WM8995_WSEQ_ADDR53_MASK 0x3FFF /* WSEQ_ADDR53 - [13:0] */ +#define WM8995_WSEQ_ADDR53_SHIFT 0 /* WSEQ_ADDR53 - [13:0] */ +#define WM8995_WSEQ_ADDR53_WIDTH 14 /* WSEQ_ADDR53 - [13:0] */ + +/* + * R12501 (0x30D5) - Write Sequencer 213 + */ +#define WM8995_WSEQ_DATA53_MASK 0x00FF /* WSEQ_DATA53 - [7:0] */ +#define WM8995_WSEQ_DATA53_SHIFT 0 /* WSEQ_DATA53 - [7:0] */ +#define WM8995_WSEQ_DATA53_WIDTH 8 /* WSEQ_DATA53 - [7:0] */ + +/* + * R12502 (0x30D6) - Write Sequencer 214 + */ +#define WM8995_WSEQ_DATA_WIDTH53_MASK 0x0700 /* WSEQ_DATA_WIDTH53 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH53_SHIFT 8 /* WSEQ_DATA_WIDTH53 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH53_WIDTH 3 /* WSEQ_DATA_WIDTH53 - [10:8] */ +#define WM8995_WSEQ_DATA_START53_MASK 0x000F /* WSEQ_DATA_START53 - [3:0] */ +#define WM8995_WSEQ_DATA_START53_SHIFT 0 /* WSEQ_DATA_START53 - [3:0] */ +#define WM8995_WSEQ_DATA_START53_WIDTH 4 /* WSEQ_DATA_START53 - [3:0] */ + +/* + * R12503 (0x30D7) - Write Sequencer 215 + */ +#define WM8995_WSEQ_EOS53 0x0100 /* WSEQ_EOS53 */ +#define WM8995_WSEQ_EOS53_MASK 0x0100 /* WSEQ_EOS53 */ +#define WM8995_WSEQ_EOS53_SHIFT 8 /* WSEQ_EOS53 */ +#define WM8995_WSEQ_EOS53_WIDTH 1 /* WSEQ_EOS53 */ +#define WM8995_WSEQ_DELAY53_MASK 0x000F /* WSEQ_DELAY53 - [3:0] */ +#define WM8995_WSEQ_DELAY53_SHIFT 0 /* WSEQ_DELAY53 - [3:0] */ +#define WM8995_WSEQ_DELAY53_WIDTH 4 /* WSEQ_DELAY53 - [3:0] */ + +/* + * R12504 (0x30D8) - Write Sequencer 216 + */ +#define WM8995_WSEQ_ADDR54_MASK 0x3FFF /* WSEQ_ADDR54 - [13:0] */ +#define WM8995_WSEQ_ADDR54_SHIFT 0 /* WSEQ_ADDR54 - [13:0] */ +#define WM8995_WSEQ_ADDR54_WIDTH 14 /* WSEQ_ADDR54 - [13:0] */ + +/* + * R12505 (0x30D9) - Write Sequencer 217 + */ +#define WM8995_WSEQ_DATA54_MASK 0x00FF /* WSEQ_DATA54 - [7:0] */ +#define WM8995_WSEQ_DATA54_SHIFT 0 /* WSEQ_DATA54 - [7:0] */ +#define WM8995_WSEQ_DATA54_WIDTH 8 /* WSEQ_DATA54 - [7:0] */ + +/* + * R12506 (0x30DA) - Write Sequencer 218 + */ +#define WM8995_WSEQ_DATA_WIDTH54_MASK 0x0700 /* WSEQ_DATA_WIDTH54 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH54_SHIFT 8 /* WSEQ_DATA_WIDTH54 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH54_WIDTH 3 /* WSEQ_DATA_WIDTH54 - [10:8] */ +#define WM8995_WSEQ_DATA_START54_MASK 0x000F /* WSEQ_DATA_START54 - [3:0] */ +#define WM8995_WSEQ_DATA_START54_SHIFT 0 /* WSEQ_DATA_START54 - [3:0] */ +#define WM8995_WSEQ_DATA_START54_WIDTH 4 /* WSEQ_DATA_START54 - [3:0] */ + +/* + * R12507 (0x30DB) - Write Sequencer 219 + */ +#define WM8995_WSEQ_EOS54 0x0100 /* WSEQ_EOS54 */ +#define WM8995_WSEQ_EOS54_MASK 0x0100 /* WSEQ_EOS54 */ +#define WM8995_WSEQ_EOS54_SHIFT 8 /* WSEQ_EOS54 */ +#define WM8995_WSEQ_EOS54_WIDTH 1 /* WSEQ_EOS54 */ +#define WM8995_WSEQ_DELAY54_MASK 0x000F /* WSEQ_DELAY54 - [3:0] */ +#define WM8995_WSEQ_DELAY54_SHIFT 0 /* WSEQ_DELAY54 - [3:0] */ +#define WM8995_WSEQ_DELAY54_WIDTH 4 /* WSEQ_DELAY54 - [3:0] */ + +/* + * R12508 (0x30DC) - Write Sequencer 220 + */ +#define WM8995_WSEQ_ADDR55_MASK 0x3FFF /* WSEQ_ADDR55 - [13:0] */ +#define WM8995_WSEQ_ADDR55_SHIFT 0 /* WSEQ_ADDR55 - [13:0] */ +#define WM8995_WSEQ_ADDR55_WIDTH 14 /* WSEQ_ADDR55 - [13:0] */ + +/* + * R12509 (0x30DD) - Write Sequencer 221 + */ +#define WM8995_WSEQ_DATA55_MASK 0x00FF /* WSEQ_DATA55 - [7:0] */ +#define WM8995_WSEQ_DATA55_SHIFT 0 /* WSEQ_DATA55 - [7:0] */ +#define WM8995_WSEQ_DATA55_WIDTH 8 /* WSEQ_DATA55 - [7:0] */ + +/* + * R12510 (0x30DE) - Write Sequencer 222 + */ +#define WM8995_WSEQ_DATA_WIDTH55_MASK 0x0700 /* WSEQ_DATA_WIDTH55 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH55_SHIFT 8 /* WSEQ_DATA_WIDTH55 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH55_WIDTH 3 /* WSEQ_DATA_WIDTH55 - [10:8] */ +#define WM8995_WSEQ_DATA_START55_MASK 0x000F /* WSEQ_DATA_START55 - [3:0] */ +#define WM8995_WSEQ_DATA_START55_SHIFT 0 /* WSEQ_DATA_START55 - [3:0] */ +#define WM8995_WSEQ_DATA_START55_WIDTH 4 /* WSEQ_DATA_START55 - [3:0] */ + +/* + * R12511 (0x30DF) - Write Sequencer 223 + */ +#define WM8995_WSEQ_EOS55 0x0100 /* WSEQ_EOS55 */ +#define WM8995_WSEQ_EOS55_MASK 0x0100 /* WSEQ_EOS55 */ +#define WM8995_WSEQ_EOS55_SHIFT 8 /* WSEQ_EOS55 */ +#define WM8995_WSEQ_EOS55_WIDTH 1 /* WSEQ_EOS55 */ +#define WM8995_WSEQ_DELAY55_MASK 0x000F /* WSEQ_DELAY55 - [3:0] */ +#define WM8995_WSEQ_DELAY55_SHIFT 0 /* WSEQ_DELAY55 - [3:0] */ +#define WM8995_WSEQ_DELAY55_WIDTH 4 /* WSEQ_DELAY55 - [3:0] */ + +/* + * R12512 (0x30E0) - Write Sequencer 224 + */ +#define WM8995_WSEQ_ADDR56_MASK 0x3FFF /* WSEQ_ADDR56 - [13:0] */ +#define WM8995_WSEQ_ADDR56_SHIFT 0 /* WSEQ_ADDR56 - [13:0] */ +#define WM8995_WSEQ_ADDR56_WIDTH 14 /* WSEQ_ADDR56 - [13:0] */ + +/* + * R12513 (0x30E1) - Write Sequencer 225 + */ +#define WM8995_WSEQ_DATA56_MASK 0x00FF /* WSEQ_DATA56 - [7:0] */ +#define WM8995_WSEQ_DATA56_SHIFT 0 /* WSEQ_DATA56 - [7:0] */ +#define WM8995_WSEQ_DATA56_WIDTH 8 /* WSEQ_DATA56 - [7:0] */ + +/* + * R12514 (0x30E2) - Write Sequencer 226 + */ +#define WM8995_WSEQ_DATA_WIDTH56_MASK 0x0700 /* WSEQ_DATA_WIDTH56 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH56_SHIFT 8 /* WSEQ_DATA_WIDTH56 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH56_WIDTH 3 /* WSEQ_DATA_WIDTH56 - [10:8] */ +#define WM8995_WSEQ_DATA_START56_MASK 0x000F /* WSEQ_DATA_START56 - [3:0] */ +#define WM8995_WSEQ_DATA_START56_SHIFT 0 /* WSEQ_DATA_START56 - [3:0] */ +#define WM8995_WSEQ_DATA_START56_WIDTH 4 /* WSEQ_DATA_START56 - [3:0] */ + +/* + * R12515 (0x30E3) - Write Sequencer 227 + */ +#define WM8995_WSEQ_EOS56 0x0100 /* WSEQ_EOS56 */ +#define WM8995_WSEQ_EOS56_MASK 0x0100 /* WSEQ_EOS56 */ +#define WM8995_WSEQ_EOS56_SHIFT 8 /* WSEQ_EOS56 */ +#define WM8995_WSEQ_EOS56_WIDTH 1 /* WSEQ_EOS56 */ +#define WM8995_WSEQ_DELAY56_MASK 0x000F /* WSEQ_DELAY56 - [3:0] */ +#define WM8995_WSEQ_DELAY56_SHIFT 0 /* WSEQ_DELAY56 - [3:0] */ +#define WM8995_WSEQ_DELAY56_WIDTH 4 /* WSEQ_DELAY56 - [3:0] */ + +/* + * R12516 (0x30E4) - Write Sequencer 228 + */ +#define WM8995_WSEQ_ADDR57_MASK 0x3FFF /* WSEQ_ADDR57 - [13:0] */ +#define WM8995_WSEQ_ADDR57_SHIFT 0 /* WSEQ_ADDR57 - [13:0] */ +#define WM8995_WSEQ_ADDR57_WIDTH 14 /* WSEQ_ADDR57 - [13:0] */ + +/* + * R12517 (0x30E5) - Write Sequencer 229 + */ +#define WM8995_WSEQ_DATA57_MASK 0x00FF /* WSEQ_DATA57 - [7:0] */ +#define WM8995_WSEQ_DATA57_SHIFT 0 /* WSEQ_DATA57 - [7:0] */ +#define WM8995_WSEQ_DATA57_WIDTH 8 /* WSEQ_DATA57 - [7:0] */ + +/* + * R12518 (0x30E6) - Write Sequencer 230 + */ +#define WM8995_WSEQ_DATA_WIDTH57_MASK 0x0700 /* WSEQ_DATA_WIDTH57 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH57_SHIFT 8 /* WSEQ_DATA_WIDTH57 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH57_WIDTH 3 /* WSEQ_DATA_WIDTH57 - [10:8] */ +#define WM8995_WSEQ_DATA_START57_MASK 0x000F /* WSEQ_DATA_START57 - [3:0] */ +#define WM8995_WSEQ_DATA_START57_SHIFT 0 /* WSEQ_DATA_START57 - [3:0] */ +#define WM8995_WSEQ_DATA_START57_WIDTH 4 /* WSEQ_DATA_START57 - [3:0] */ + +/* + * R12519 (0x30E7) - Write Sequencer 231 + */ +#define WM8995_WSEQ_EOS57 0x0100 /* WSEQ_EOS57 */ +#define WM8995_WSEQ_EOS57_MASK 0x0100 /* WSEQ_EOS57 */ +#define WM8995_WSEQ_EOS57_SHIFT 8 /* WSEQ_EOS57 */ +#define WM8995_WSEQ_EOS57_WIDTH 1 /* WSEQ_EOS57 */ +#define WM8995_WSEQ_DELAY57_MASK 0x000F /* WSEQ_DELAY57 - [3:0] */ +#define WM8995_WSEQ_DELAY57_SHIFT 0 /* WSEQ_DELAY57 - [3:0] */ +#define WM8995_WSEQ_DELAY57_WIDTH 4 /* WSEQ_DELAY57 - [3:0] */ + +/* + * R12520 (0x30E8) - Write Sequencer 232 + */ +#define WM8995_WSEQ_ADDR58_MASK 0x3FFF /* WSEQ_ADDR58 - [13:0] */ +#define WM8995_WSEQ_ADDR58_SHIFT 0 /* WSEQ_ADDR58 - [13:0] */ +#define WM8995_WSEQ_ADDR58_WIDTH 14 /* WSEQ_ADDR58 - [13:0] */ + +/* + * R12521 (0x30E9) - Write Sequencer 233 + */ +#define WM8995_WSEQ_DATA58_MASK 0x00FF /* WSEQ_DATA58 - [7:0] */ +#define WM8995_WSEQ_DATA58_SHIFT 0 /* WSEQ_DATA58 - [7:0] */ +#define WM8995_WSEQ_DATA58_WIDTH 8 /* WSEQ_DATA58 - [7:0] */ + +/* + * R12522 (0x30EA) - Write Sequencer 234 + */ +#define WM8995_WSEQ_DATA_WIDTH58_MASK 0x0700 /* WSEQ_DATA_WIDTH58 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH58_SHIFT 8 /* WSEQ_DATA_WIDTH58 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH58_WIDTH 3 /* WSEQ_DATA_WIDTH58 - [10:8] */ +#define WM8995_WSEQ_DATA_START58_MASK 0x000F /* WSEQ_DATA_START58 - [3:0] */ +#define WM8995_WSEQ_DATA_START58_SHIFT 0 /* WSEQ_DATA_START58 - [3:0] */ +#define WM8995_WSEQ_DATA_START58_WIDTH 4 /* WSEQ_DATA_START58 - [3:0] */ + +/* + * R12523 (0x30EB) - Write Sequencer 235 + */ +#define WM8995_WSEQ_EOS58 0x0100 /* WSEQ_EOS58 */ +#define WM8995_WSEQ_EOS58_MASK 0x0100 /* WSEQ_EOS58 */ +#define WM8995_WSEQ_EOS58_SHIFT 8 /* WSEQ_EOS58 */ +#define WM8995_WSEQ_EOS58_WIDTH 1 /* WSEQ_EOS58 */ +#define WM8995_WSEQ_DELAY58_MASK 0x000F /* WSEQ_DELAY58 - [3:0] */ +#define WM8995_WSEQ_DELAY58_SHIFT 0 /* WSEQ_DELAY58 - [3:0] */ +#define WM8995_WSEQ_DELAY58_WIDTH 4 /* WSEQ_DELAY58 - [3:0] */ + +/* + * R12524 (0x30EC) - Write Sequencer 236 + */ +#define WM8995_WSEQ_ADDR59_MASK 0x3FFF /* WSEQ_ADDR59 - [13:0] */ +#define WM8995_WSEQ_ADDR59_SHIFT 0 /* WSEQ_ADDR59 - [13:0] */ +#define WM8995_WSEQ_ADDR59_WIDTH 14 /* WSEQ_ADDR59 - [13:0] */ + +/* + * R12525 (0x30ED) - Write Sequencer 237 + */ +#define WM8995_WSEQ_DATA59_MASK 0x00FF /* WSEQ_DATA59 - [7:0] */ +#define WM8995_WSEQ_DATA59_SHIFT 0 /* WSEQ_DATA59 - [7:0] */ +#define WM8995_WSEQ_DATA59_WIDTH 8 /* WSEQ_DATA59 - [7:0] */ + +/* + * R12526 (0x30EE) - Write Sequencer 238 + */ +#define WM8995_WSEQ_DATA_WIDTH59_MASK 0x0700 /* WSEQ_DATA_WIDTH59 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH59_SHIFT 8 /* WSEQ_DATA_WIDTH59 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH59_WIDTH 3 /* WSEQ_DATA_WIDTH59 - [10:8] */ +#define WM8995_WSEQ_DATA_START59_MASK 0x000F /* WSEQ_DATA_START59 - [3:0] */ +#define WM8995_WSEQ_DATA_START59_SHIFT 0 /* WSEQ_DATA_START59 - [3:0] */ +#define WM8995_WSEQ_DATA_START59_WIDTH 4 /* WSEQ_DATA_START59 - [3:0] */ + +/* + * R12527 (0x30EF) - Write Sequencer 239 + */ +#define WM8995_WSEQ_EOS59 0x0100 /* WSEQ_EOS59 */ +#define WM8995_WSEQ_EOS59_MASK 0x0100 /* WSEQ_EOS59 */ +#define WM8995_WSEQ_EOS59_SHIFT 8 /* WSEQ_EOS59 */ +#define WM8995_WSEQ_EOS59_WIDTH 1 /* WSEQ_EOS59 */ +#define WM8995_WSEQ_DELAY59_MASK 0x000F /* WSEQ_DELAY59 - [3:0] */ +#define WM8995_WSEQ_DELAY59_SHIFT 0 /* WSEQ_DELAY59 - [3:0] */ +#define WM8995_WSEQ_DELAY59_WIDTH 4 /* WSEQ_DELAY59 - [3:0] */ + +/* + * R12528 (0x30F0) - Write Sequencer 240 + */ +#define WM8995_WSEQ_ADDR60_MASK 0x3FFF /* WSEQ_ADDR60 - [13:0] */ +#define WM8995_WSEQ_ADDR60_SHIFT 0 /* WSEQ_ADDR60 - [13:0] */ +#define WM8995_WSEQ_ADDR60_WIDTH 14 /* WSEQ_ADDR60 - [13:0] */ + +/* + * R12529 (0x30F1) - Write Sequencer 241 + */ +#define WM8995_WSEQ_DATA60_MASK 0x00FF /* WSEQ_DATA60 - [7:0] */ +#define WM8995_WSEQ_DATA60_SHIFT 0 /* WSEQ_DATA60 - [7:0] */ +#define WM8995_WSEQ_DATA60_WIDTH 8 /* WSEQ_DATA60 - [7:0] */ + +/* + * R12530 (0x30F2) - Write Sequencer 242 + */ +#define WM8995_WSEQ_DATA_WIDTH60_MASK 0x0700 /* WSEQ_DATA_WIDTH60 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH60_SHIFT 8 /* WSEQ_DATA_WIDTH60 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH60_WIDTH 3 /* WSEQ_DATA_WIDTH60 - [10:8] */ +#define WM8995_WSEQ_DATA_START60_MASK 0x000F /* WSEQ_DATA_START60 - [3:0] */ +#define WM8995_WSEQ_DATA_START60_SHIFT 0 /* WSEQ_DATA_START60 - [3:0] */ +#define WM8995_WSEQ_DATA_START60_WIDTH 4 /* WSEQ_DATA_START60 - [3:0] */ + +/* + * R12531 (0x30F3) - Write Sequencer 243 + */ +#define WM8995_WSEQ_EOS60 0x0100 /* WSEQ_EOS60 */ +#define WM8995_WSEQ_EOS60_MASK 0x0100 /* WSEQ_EOS60 */ +#define WM8995_WSEQ_EOS60_SHIFT 8 /* WSEQ_EOS60 */ +#define WM8995_WSEQ_EOS60_WIDTH 1 /* WSEQ_EOS60 */ +#define WM8995_WSEQ_DELAY60_MASK 0x000F /* WSEQ_DELAY60 - [3:0] */ +#define WM8995_WSEQ_DELAY60_SHIFT 0 /* WSEQ_DELAY60 - [3:0] */ +#define WM8995_WSEQ_DELAY60_WIDTH 4 /* WSEQ_DELAY60 - [3:0] */ + +/* + * R12532 (0x30F4) - Write Sequencer 244 + */ +#define WM8995_WSEQ_ADDR61_MASK 0x3FFF /* WSEQ_ADDR61 - [13:0] */ +#define WM8995_WSEQ_ADDR61_SHIFT 0 /* WSEQ_ADDR61 - [13:0] */ +#define WM8995_WSEQ_ADDR61_WIDTH 14 /* WSEQ_ADDR61 - [13:0] */ + +/* + * R12533 (0x30F5) - Write Sequencer 245 + */ +#define WM8995_WSEQ_DATA61_MASK 0x00FF /* WSEQ_DATA61 - [7:0] */ +#define WM8995_WSEQ_DATA61_SHIFT 0 /* WSEQ_DATA61 - [7:0] */ +#define WM8995_WSEQ_DATA61_WIDTH 8 /* WSEQ_DATA61 - [7:0] */ + +/* + * R12534 (0x30F6) - Write Sequencer 246 + */ +#define WM8995_WSEQ_DATA_WIDTH61_MASK 0x0700 /* WSEQ_DATA_WIDTH61 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH61_SHIFT 8 /* WSEQ_DATA_WIDTH61 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH61_WIDTH 3 /* WSEQ_DATA_WIDTH61 - [10:8] */ +#define WM8995_WSEQ_DATA_START61_MASK 0x000F /* WSEQ_DATA_START61 - [3:0] */ +#define WM8995_WSEQ_DATA_START61_SHIFT 0 /* WSEQ_DATA_START61 - [3:0] */ +#define WM8995_WSEQ_DATA_START61_WIDTH 4 /* WSEQ_DATA_START61 - [3:0] */ + +/* + * R12535 (0x30F7) - Write Sequencer 247 + */ +#define WM8995_WSEQ_EOS61 0x0100 /* WSEQ_EOS61 */ +#define WM8995_WSEQ_EOS61_MASK 0x0100 /* WSEQ_EOS61 */ +#define WM8995_WSEQ_EOS61_SHIFT 8 /* WSEQ_EOS61 */ +#define WM8995_WSEQ_EOS61_WIDTH 1 /* WSEQ_EOS61 */ +#define WM8995_WSEQ_DELAY61_MASK 0x000F /* WSEQ_DELAY61 - [3:0] */ +#define WM8995_WSEQ_DELAY61_SHIFT 0 /* WSEQ_DELAY61 - [3:0] */ +#define WM8995_WSEQ_DELAY61_WIDTH 4 /* WSEQ_DELAY61 - [3:0] */ + +/* + * R12536 (0x30F8) - Write Sequencer 248 + */ +#define WM8995_WSEQ_ADDR62_MASK 0x3FFF /* WSEQ_ADDR62 - [13:0] */ +#define WM8995_WSEQ_ADDR62_SHIFT 0 /* WSEQ_ADDR62 - [13:0] */ +#define WM8995_WSEQ_ADDR62_WIDTH 14 /* WSEQ_ADDR62 - [13:0] */ + +/* + * R12537 (0x30F9) - Write Sequencer 249 + */ +#define WM8995_WSEQ_DATA62_MASK 0x00FF /* WSEQ_DATA62 - [7:0] */ +#define WM8995_WSEQ_DATA62_SHIFT 0 /* WSEQ_DATA62 - [7:0] */ +#define WM8995_WSEQ_DATA62_WIDTH 8 /* WSEQ_DATA62 - [7:0] */ + +/* + * R12538 (0x30FA) - Write Sequencer 250 + */ +#define WM8995_WSEQ_DATA_WIDTH62_MASK 0x0700 /* WSEQ_DATA_WIDTH62 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH62_SHIFT 8 /* WSEQ_DATA_WIDTH62 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH62_WIDTH 3 /* WSEQ_DATA_WIDTH62 - [10:8] */ +#define WM8995_WSEQ_DATA_START62_MASK 0x000F /* WSEQ_DATA_START62 - [3:0] */ +#define WM8995_WSEQ_DATA_START62_SHIFT 0 /* WSEQ_DATA_START62 - [3:0] */ +#define WM8995_WSEQ_DATA_START62_WIDTH 4 /* WSEQ_DATA_START62 - [3:0] */ + +/* + * R12539 (0x30FB) - Write Sequencer 251 + */ +#define WM8995_WSEQ_EOS62 0x0100 /* WSEQ_EOS62 */ +#define WM8995_WSEQ_EOS62_MASK 0x0100 /* WSEQ_EOS62 */ +#define WM8995_WSEQ_EOS62_SHIFT 8 /* WSEQ_EOS62 */ +#define WM8995_WSEQ_EOS62_WIDTH 1 /* WSEQ_EOS62 */ +#define WM8995_WSEQ_DELAY62_MASK 0x000F /* WSEQ_DELAY62 - [3:0] */ +#define WM8995_WSEQ_DELAY62_SHIFT 0 /* WSEQ_DELAY62 - [3:0] */ +#define WM8995_WSEQ_DELAY62_WIDTH 4 /* WSEQ_DELAY62 - [3:0] */ + +/* + * R12540 (0x30FC) - Write Sequencer 252 + */ +#define WM8995_WSEQ_ADDR63_MASK 0x3FFF /* WSEQ_ADDR63 - [13:0] */ +#define WM8995_WSEQ_ADDR63_SHIFT 0 /* WSEQ_ADDR63 - [13:0] */ +#define WM8995_WSEQ_ADDR63_WIDTH 14 /* WSEQ_ADDR63 - [13:0] */ + +/* + * R12541 (0x30FD) - Write Sequencer 253 + */ +#define WM8995_WSEQ_DATA63_MASK 0x00FF /* WSEQ_DATA63 - [7:0] */ +#define WM8995_WSEQ_DATA63_SHIFT 0 /* WSEQ_DATA63 - [7:0] */ +#define WM8995_WSEQ_DATA63_WIDTH 8 /* WSEQ_DATA63 - [7:0] */ + +/* + * R12542 (0x30FE) - Write Sequencer 254 + */ +#define WM8995_WSEQ_DATA_WIDTH63_MASK 0x0700 /* WSEQ_DATA_WIDTH63 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH63_SHIFT 8 /* WSEQ_DATA_WIDTH63 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH63_WIDTH 3 /* WSEQ_DATA_WIDTH63 - [10:8] */ +#define WM8995_WSEQ_DATA_START63_MASK 0x000F /* WSEQ_DATA_START63 - [3:0] */ +#define WM8995_WSEQ_DATA_START63_SHIFT 0 /* WSEQ_DATA_START63 - [3:0] */ +#define WM8995_WSEQ_DATA_START63_WIDTH 4 /* WSEQ_DATA_START63 - [3:0] */ + +/* + * R12543 (0x30FF) - Write Sequencer 255 + */ +#define WM8995_WSEQ_EOS63 0x0100 /* WSEQ_EOS63 */ +#define WM8995_WSEQ_EOS63_MASK 0x0100 /* WSEQ_EOS63 */ +#define WM8995_WSEQ_EOS63_SHIFT 8 /* WSEQ_EOS63 */ +#define WM8995_WSEQ_EOS63_WIDTH 1 /* WSEQ_EOS63 */ +#define WM8995_WSEQ_DELAY63_MASK 0x000F /* WSEQ_DELAY63 - [3:0] */ +#define WM8995_WSEQ_DELAY63_SHIFT 0 /* WSEQ_DELAY63 - [3:0] */ +#define WM8995_WSEQ_DELAY63_WIDTH 4 /* WSEQ_DELAY63 - [3:0] */ + +/* + * R12544 (0x3100) - Write Sequencer 256 + */ +#define WM8995_WSEQ_ADDR64_MASK 0x3FFF /* WSEQ_ADDR64 - [13:0] */ +#define WM8995_WSEQ_ADDR64_SHIFT 0 /* WSEQ_ADDR64 - [13:0] */ +#define WM8995_WSEQ_ADDR64_WIDTH 14 /* WSEQ_ADDR64 - [13:0] */ + +/* + * R12545 (0x3101) - Write Sequencer 257 + */ +#define WM8995_WSEQ_DATA64_MASK 0x00FF /* WSEQ_DATA64 - [7:0] */ +#define WM8995_WSEQ_DATA64_SHIFT 0 /* WSEQ_DATA64 - [7:0] */ +#define WM8995_WSEQ_DATA64_WIDTH 8 /* WSEQ_DATA64 - [7:0] */ + +/* + * R12546 (0x3102) - Write Sequencer 258 + */ +#define WM8995_WSEQ_DATA_WIDTH64_MASK 0x0700 /* WSEQ_DATA_WIDTH64 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH64_SHIFT 8 /* WSEQ_DATA_WIDTH64 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH64_WIDTH 3 /* WSEQ_DATA_WIDTH64 - [10:8] */ +#define WM8995_WSEQ_DATA_START64_MASK 0x000F /* WSEQ_DATA_START64 - [3:0] */ +#define WM8995_WSEQ_DATA_START64_SHIFT 0 /* WSEQ_DATA_START64 - [3:0] */ +#define WM8995_WSEQ_DATA_START64_WIDTH 4 /* WSEQ_DATA_START64 - [3:0] */ + +/* + * R12547 (0x3103) - Write Sequencer 259 + */ +#define WM8995_WSEQ_EOS64 0x0100 /* WSEQ_EOS64 */ +#define WM8995_WSEQ_EOS64_MASK 0x0100 /* WSEQ_EOS64 */ +#define WM8995_WSEQ_EOS64_SHIFT 8 /* WSEQ_EOS64 */ +#define WM8995_WSEQ_EOS64_WIDTH 1 /* WSEQ_EOS64 */ +#define WM8995_WSEQ_DELAY64_MASK 0x000F /* WSEQ_DELAY64 - [3:0] */ +#define WM8995_WSEQ_DELAY64_SHIFT 0 /* WSEQ_DELAY64 - [3:0] */ +#define WM8995_WSEQ_DELAY64_WIDTH 4 /* WSEQ_DELAY64 - [3:0] */ + +/* + * R12548 (0x3104) - Write Sequencer 260 + */ +#define WM8995_WSEQ_ADDR65_MASK 0x3FFF /* WSEQ_ADDR65 - [13:0] */ +#define WM8995_WSEQ_ADDR65_SHIFT 0 /* WSEQ_ADDR65 - [13:0] */ +#define WM8995_WSEQ_ADDR65_WIDTH 14 /* WSEQ_ADDR65 - [13:0] */ + +/* + * R12549 (0x3105) - Write Sequencer 261 + */ +#define WM8995_WSEQ_DATA65_MASK 0x00FF /* WSEQ_DATA65 - [7:0] */ +#define WM8995_WSEQ_DATA65_SHIFT 0 /* WSEQ_DATA65 - [7:0] */ +#define WM8995_WSEQ_DATA65_WIDTH 8 /* WSEQ_DATA65 - [7:0] */ + +/* + * R12550 (0x3106) - Write Sequencer 262 + */ +#define WM8995_WSEQ_DATA_WIDTH65_MASK 0x0700 /* WSEQ_DATA_WIDTH65 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH65_SHIFT 8 /* WSEQ_DATA_WIDTH65 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH65_WIDTH 3 /* WSEQ_DATA_WIDTH65 - [10:8] */ +#define WM8995_WSEQ_DATA_START65_MASK 0x000F /* WSEQ_DATA_START65 - [3:0] */ +#define WM8995_WSEQ_DATA_START65_SHIFT 0 /* WSEQ_DATA_START65 - [3:0] */ +#define WM8995_WSEQ_DATA_START65_WIDTH 4 /* WSEQ_DATA_START65 - [3:0] */ + +/* + * R12551 (0x3107) - Write Sequencer 263 + */ +#define WM8995_WSEQ_EOS65 0x0100 /* WSEQ_EOS65 */ +#define WM8995_WSEQ_EOS65_MASK 0x0100 /* WSEQ_EOS65 */ +#define WM8995_WSEQ_EOS65_SHIFT 8 /* WSEQ_EOS65 */ +#define WM8995_WSEQ_EOS65_WIDTH 1 /* WSEQ_EOS65 */ +#define WM8995_WSEQ_DELAY65_MASK 0x000F /* WSEQ_DELAY65 - [3:0] */ +#define WM8995_WSEQ_DELAY65_SHIFT 0 /* WSEQ_DELAY65 - [3:0] */ +#define WM8995_WSEQ_DELAY65_WIDTH 4 /* WSEQ_DELAY65 - [3:0] */ + +/* + * R12552 (0x3108) - Write Sequencer 264 + */ +#define WM8995_WSEQ_ADDR66_MASK 0x3FFF /* WSEQ_ADDR66 - [13:0] */ +#define WM8995_WSEQ_ADDR66_SHIFT 0 /* WSEQ_ADDR66 - [13:0] */ +#define WM8995_WSEQ_ADDR66_WIDTH 14 /* WSEQ_ADDR66 - [13:0] */ + +/* + * R12553 (0x3109) - Write Sequencer 265 + */ +#define WM8995_WSEQ_DATA66_MASK 0x00FF /* WSEQ_DATA66 - [7:0] */ +#define WM8995_WSEQ_DATA66_SHIFT 0 /* WSEQ_DATA66 - [7:0] */ +#define WM8995_WSEQ_DATA66_WIDTH 8 /* WSEQ_DATA66 - [7:0] */ + +/* + * R12554 (0x310A) - Write Sequencer 266 + */ +#define WM8995_WSEQ_DATA_WIDTH66_MASK 0x0700 /* WSEQ_DATA_WIDTH66 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH66_SHIFT 8 /* WSEQ_DATA_WIDTH66 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH66_WIDTH 3 /* WSEQ_DATA_WIDTH66 - [10:8] */ +#define WM8995_WSEQ_DATA_START66_MASK 0x000F /* WSEQ_DATA_START66 - [3:0] */ +#define WM8995_WSEQ_DATA_START66_SHIFT 0 /* WSEQ_DATA_START66 - [3:0] */ +#define WM8995_WSEQ_DATA_START66_WIDTH 4 /* WSEQ_DATA_START66 - [3:0] */ + +/* + * R12555 (0x310B) - Write Sequencer 267 + */ +#define WM8995_WSEQ_EOS66 0x0100 /* WSEQ_EOS66 */ +#define WM8995_WSEQ_EOS66_MASK 0x0100 /* WSEQ_EOS66 */ +#define WM8995_WSEQ_EOS66_SHIFT 8 /* WSEQ_EOS66 */ +#define WM8995_WSEQ_EOS66_WIDTH 1 /* WSEQ_EOS66 */ +#define WM8995_WSEQ_DELAY66_MASK 0x000F /* WSEQ_DELAY66 - [3:0] */ +#define WM8995_WSEQ_DELAY66_SHIFT 0 /* WSEQ_DELAY66 - [3:0] */ +#define WM8995_WSEQ_DELAY66_WIDTH 4 /* WSEQ_DELAY66 - [3:0] */ + +/* + * R12556 (0x310C) - Write Sequencer 268 + */ +#define WM8995_WSEQ_ADDR67_MASK 0x3FFF /* WSEQ_ADDR67 - [13:0] */ +#define WM8995_WSEQ_ADDR67_SHIFT 0 /* WSEQ_ADDR67 - [13:0] */ +#define WM8995_WSEQ_ADDR67_WIDTH 14 /* WSEQ_ADDR67 - [13:0] */ + +/* + * R12557 (0x310D) - Write Sequencer 269 + */ +#define WM8995_WSEQ_DATA67_MASK 0x00FF /* WSEQ_DATA67 - [7:0] */ +#define WM8995_WSEQ_DATA67_SHIFT 0 /* WSEQ_DATA67 - [7:0] */ +#define WM8995_WSEQ_DATA67_WIDTH 8 /* WSEQ_DATA67 - [7:0] */ + +/* + * R12558 (0x310E) - Write Sequencer 270 + */ +#define WM8995_WSEQ_DATA_WIDTH67_MASK 0x0700 /* WSEQ_DATA_WIDTH67 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH67_SHIFT 8 /* WSEQ_DATA_WIDTH67 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH67_WIDTH 3 /* WSEQ_DATA_WIDTH67 - [10:8] */ +#define WM8995_WSEQ_DATA_START67_MASK 0x000F /* WSEQ_DATA_START67 - [3:0] */ +#define WM8995_WSEQ_DATA_START67_SHIFT 0 /* WSEQ_DATA_START67 - [3:0] */ +#define WM8995_WSEQ_DATA_START67_WIDTH 4 /* WSEQ_DATA_START67 - [3:0] */ + +/* + * R12559 (0x310F) - Write Sequencer 271 + */ +#define WM8995_WSEQ_EOS67 0x0100 /* WSEQ_EOS67 */ +#define WM8995_WSEQ_EOS67_MASK 0x0100 /* WSEQ_EOS67 */ +#define WM8995_WSEQ_EOS67_SHIFT 8 /* WSEQ_EOS67 */ +#define WM8995_WSEQ_EOS67_WIDTH 1 /* WSEQ_EOS67 */ +#define WM8995_WSEQ_DELAY67_MASK 0x000F /* WSEQ_DELAY67 - [3:0] */ +#define WM8995_WSEQ_DELAY67_SHIFT 0 /* WSEQ_DELAY67 - [3:0] */ +#define WM8995_WSEQ_DELAY67_WIDTH 4 /* WSEQ_DELAY67 - [3:0] */ + +/* + * R12560 (0x3110) - Write Sequencer 272 + */ +#define WM8995_WSEQ_ADDR68_MASK 0x3FFF /* WSEQ_ADDR68 - [13:0] */ +#define WM8995_WSEQ_ADDR68_SHIFT 0 /* WSEQ_ADDR68 - [13:0] */ +#define WM8995_WSEQ_ADDR68_WIDTH 14 /* WSEQ_ADDR68 - [13:0] */ + +/* + * R12561 (0x3111) - Write Sequencer 273 + */ +#define WM8995_WSEQ_DATA68_MASK 0x00FF /* WSEQ_DATA68 - [7:0] */ +#define WM8995_WSEQ_DATA68_SHIFT 0 /* WSEQ_DATA68 - [7:0] */ +#define WM8995_WSEQ_DATA68_WIDTH 8 /* WSEQ_DATA68 - [7:0] */ + +/* + * R12562 (0x3112) - Write Sequencer 274 + */ +#define WM8995_WSEQ_DATA_WIDTH68_MASK 0x0700 /* WSEQ_DATA_WIDTH68 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH68_SHIFT 8 /* WSEQ_DATA_WIDTH68 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH68_WIDTH 3 /* WSEQ_DATA_WIDTH68 - [10:8] */ +#define WM8995_WSEQ_DATA_START68_MASK 0x000F /* WSEQ_DATA_START68 - [3:0] */ +#define WM8995_WSEQ_DATA_START68_SHIFT 0 /* WSEQ_DATA_START68 - [3:0] */ +#define WM8995_WSEQ_DATA_START68_WIDTH 4 /* WSEQ_DATA_START68 - [3:0] */ + +/* + * R12563 (0x3113) - Write Sequencer 275 + */ +#define WM8995_WSEQ_EOS68 0x0100 /* WSEQ_EOS68 */ +#define WM8995_WSEQ_EOS68_MASK 0x0100 /* WSEQ_EOS68 */ +#define WM8995_WSEQ_EOS68_SHIFT 8 /* WSEQ_EOS68 */ +#define WM8995_WSEQ_EOS68_WIDTH 1 /* WSEQ_EOS68 */ +#define WM8995_WSEQ_DELAY68_MASK 0x000F /* WSEQ_DELAY68 - [3:0] */ +#define WM8995_WSEQ_DELAY68_SHIFT 0 /* WSEQ_DELAY68 - [3:0] */ +#define WM8995_WSEQ_DELAY68_WIDTH 4 /* WSEQ_DELAY68 - [3:0] */ + +/* + * R12564 (0x3114) - Write Sequencer 276 + */ +#define WM8995_WSEQ_ADDR69_MASK 0x3FFF /* WSEQ_ADDR69 - [13:0] */ +#define WM8995_WSEQ_ADDR69_SHIFT 0 /* WSEQ_ADDR69 - [13:0] */ +#define WM8995_WSEQ_ADDR69_WIDTH 14 /* WSEQ_ADDR69 - [13:0] */ + +/* + * R12565 (0x3115) - Write Sequencer 277 + */ +#define WM8995_WSEQ_DATA69_MASK 0x00FF /* WSEQ_DATA69 - [7:0] */ +#define WM8995_WSEQ_DATA69_SHIFT 0 /* WSEQ_DATA69 - [7:0] */ +#define WM8995_WSEQ_DATA69_WIDTH 8 /* WSEQ_DATA69 - [7:0] */ + +/* + * R12566 (0x3116) - Write Sequencer 278 + */ +#define WM8995_WSEQ_DATA_WIDTH69_MASK 0x0700 /* WSEQ_DATA_WIDTH69 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH69_SHIFT 8 /* WSEQ_DATA_WIDTH69 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH69_WIDTH 3 /* WSEQ_DATA_WIDTH69 - [10:8] */ +#define WM8995_WSEQ_DATA_START69_MASK 0x000F /* WSEQ_DATA_START69 - [3:0] */ +#define WM8995_WSEQ_DATA_START69_SHIFT 0 /* WSEQ_DATA_START69 - [3:0] */ +#define WM8995_WSEQ_DATA_START69_WIDTH 4 /* WSEQ_DATA_START69 - [3:0] */ + +/* + * R12567 (0x3117) - Write Sequencer 279 + */ +#define WM8995_WSEQ_EOS69 0x0100 /* WSEQ_EOS69 */ +#define WM8995_WSEQ_EOS69_MASK 0x0100 /* WSEQ_EOS69 */ +#define WM8995_WSEQ_EOS69_SHIFT 8 /* WSEQ_EOS69 */ +#define WM8995_WSEQ_EOS69_WIDTH 1 /* WSEQ_EOS69 */ +#define WM8995_WSEQ_DELAY69_MASK 0x000F /* WSEQ_DELAY69 - [3:0] */ +#define WM8995_WSEQ_DELAY69_SHIFT 0 /* WSEQ_DELAY69 - [3:0] */ +#define WM8995_WSEQ_DELAY69_WIDTH 4 /* WSEQ_DELAY69 - [3:0] */ + +/* + * R12568 (0x3118) - Write Sequencer 280 + */ +#define WM8995_WSEQ_ADDR70_MASK 0x3FFF /* WSEQ_ADDR70 - [13:0] */ +#define WM8995_WSEQ_ADDR70_SHIFT 0 /* WSEQ_ADDR70 - [13:0] */ +#define WM8995_WSEQ_ADDR70_WIDTH 14 /* WSEQ_ADDR70 - [13:0] */ + +/* + * R12569 (0x3119) - Write Sequencer 281 + */ +#define WM8995_WSEQ_DATA70_MASK 0x00FF /* WSEQ_DATA70 - [7:0] */ +#define WM8995_WSEQ_DATA70_SHIFT 0 /* WSEQ_DATA70 - [7:0] */ +#define WM8995_WSEQ_DATA70_WIDTH 8 /* WSEQ_DATA70 - [7:0] */ + +/* + * R12570 (0x311A) - Write Sequencer 282 + */ +#define WM8995_WSEQ_DATA_WIDTH70_MASK 0x0700 /* WSEQ_DATA_WIDTH70 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH70_SHIFT 8 /* WSEQ_DATA_WIDTH70 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH70_WIDTH 3 /* WSEQ_DATA_WIDTH70 - [10:8] */ +#define WM8995_WSEQ_DATA_START70_MASK 0x000F /* WSEQ_DATA_START70 - [3:0] */ +#define WM8995_WSEQ_DATA_START70_SHIFT 0 /* WSEQ_DATA_START70 - [3:0] */ +#define WM8995_WSEQ_DATA_START70_WIDTH 4 /* WSEQ_DATA_START70 - [3:0] */ + +/* + * R12571 (0x311B) - Write Sequencer 283 + */ +#define WM8995_WSEQ_EOS70 0x0100 /* WSEQ_EOS70 */ +#define WM8995_WSEQ_EOS70_MASK 0x0100 /* WSEQ_EOS70 */ +#define WM8995_WSEQ_EOS70_SHIFT 8 /* WSEQ_EOS70 */ +#define WM8995_WSEQ_EOS70_WIDTH 1 /* WSEQ_EOS70 */ +#define WM8995_WSEQ_DELAY70_MASK 0x000F /* WSEQ_DELAY70 - [3:0] */ +#define WM8995_WSEQ_DELAY70_SHIFT 0 /* WSEQ_DELAY70 - [3:0] */ +#define WM8995_WSEQ_DELAY70_WIDTH 4 /* WSEQ_DELAY70 - [3:0] */ + +/* + * R12572 (0x311C) - Write Sequencer 284 + */ +#define WM8995_WSEQ_ADDR71_MASK 0x3FFF /* WSEQ_ADDR71 - [13:0] */ +#define WM8995_WSEQ_ADDR71_SHIFT 0 /* WSEQ_ADDR71 - [13:0] */ +#define WM8995_WSEQ_ADDR71_WIDTH 14 /* WSEQ_ADDR71 - [13:0] */ + +/* + * R12573 (0x311D) - Write Sequencer 285 + */ +#define WM8995_WSEQ_DATA71_MASK 0x00FF /* WSEQ_DATA71 - [7:0] */ +#define WM8995_WSEQ_DATA71_SHIFT 0 /* WSEQ_DATA71 - [7:0] */ +#define WM8995_WSEQ_DATA71_WIDTH 8 /* WSEQ_DATA71 - [7:0] */ + +/* + * R12574 (0x311E) - Write Sequencer 286 + */ +#define WM8995_WSEQ_DATA_WIDTH71_MASK 0x0700 /* WSEQ_DATA_WIDTH71 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH71_SHIFT 8 /* WSEQ_DATA_WIDTH71 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH71_WIDTH 3 /* WSEQ_DATA_WIDTH71 - [10:8] */ +#define WM8995_WSEQ_DATA_START71_MASK 0x000F /* WSEQ_DATA_START71 - [3:0] */ +#define WM8995_WSEQ_DATA_START71_SHIFT 0 /* WSEQ_DATA_START71 - [3:0] */ +#define WM8995_WSEQ_DATA_START71_WIDTH 4 /* WSEQ_DATA_START71 - [3:0] */ + +/* + * R12575 (0x311F) - Write Sequencer 287 + */ +#define WM8995_WSEQ_EOS71 0x0100 /* WSEQ_EOS71 */ +#define WM8995_WSEQ_EOS71_MASK 0x0100 /* WSEQ_EOS71 */ +#define WM8995_WSEQ_EOS71_SHIFT 8 /* WSEQ_EOS71 */ +#define WM8995_WSEQ_EOS71_WIDTH 1 /* WSEQ_EOS71 */ +#define WM8995_WSEQ_DELAY71_MASK 0x000F /* WSEQ_DELAY71 - [3:0] */ +#define WM8995_WSEQ_DELAY71_SHIFT 0 /* WSEQ_DELAY71 - [3:0] */ +#define WM8995_WSEQ_DELAY71_WIDTH 4 /* WSEQ_DELAY71 - [3:0] */ + +/* + * R12576 (0x3120) - Write Sequencer 288 + */ +#define WM8995_WSEQ_ADDR72_MASK 0x3FFF /* WSEQ_ADDR72 - [13:0] */ +#define WM8995_WSEQ_ADDR72_SHIFT 0 /* WSEQ_ADDR72 - [13:0] */ +#define WM8995_WSEQ_ADDR72_WIDTH 14 /* WSEQ_ADDR72 - [13:0] */ + +/* + * R12577 (0x3121) - Write Sequencer 289 + */ +#define WM8995_WSEQ_DATA72_MASK 0x00FF /* WSEQ_DATA72 - [7:0] */ +#define WM8995_WSEQ_DATA72_SHIFT 0 /* WSEQ_DATA72 - [7:0] */ +#define WM8995_WSEQ_DATA72_WIDTH 8 /* WSEQ_DATA72 - [7:0] */ + +/* + * R12578 (0x3122) - Write Sequencer 290 + */ +#define WM8995_WSEQ_DATA_WIDTH72_MASK 0x0700 /* WSEQ_DATA_WIDTH72 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH72_SHIFT 8 /* WSEQ_DATA_WIDTH72 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH72_WIDTH 3 /* WSEQ_DATA_WIDTH72 - [10:8] */ +#define WM8995_WSEQ_DATA_START72_MASK 0x000F /* WSEQ_DATA_START72 - [3:0] */ +#define WM8995_WSEQ_DATA_START72_SHIFT 0 /* WSEQ_DATA_START72 - [3:0] */ +#define WM8995_WSEQ_DATA_START72_WIDTH 4 /* WSEQ_DATA_START72 - [3:0] */ + +/* + * R12579 (0x3123) - Write Sequencer 291 + */ +#define WM8995_WSEQ_EOS72 0x0100 /* WSEQ_EOS72 */ +#define WM8995_WSEQ_EOS72_MASK 0x0100 /* WSEQ_EOS72 */ +#define WM8995_WSEQ_EOS72_SHIFT 8 /* WSEQ_EOS72 */ +#define WM8995_WSEQ_EOS72_WIDTH 1 /* WSEQ_EOS72 */ +#define WM8995_WSEQ_DELAY72_MASK 0x000F /* WSEQ_DELAY72 - [3:0] */ +#define WM8995_WSEQ_DELAY72_SHIFT 0 /* WSEQ_DELAY72 - [3:0] */ +#define WM8995_WSEQ_DELAY72_WIDTH 4 /* WSEQ_DELAY72 - [3:0] */ + +/* + * R12580 (0x3124) - Write Sequencer 292 + */ +#define WM8995_WSEQ_ADDR73_MASK 0x3FFF /* WSEQ_ADDR73 - [13:0] */ +#define WM8995_WSEQ_ADDR73_SHIFT 0 /* WSEQ_ADDR73 - [13:0] */ +#define WM8995_WSEQ_ADDR73_WIDTH 14 /* WSEQ_ADDR73 - [13:0] */ + +/* + * R12581 (0x3125) - Write Sequencer 293 + */ +#define WM8995_WSEQ_DATA73_MASK 0x00FF /* WSEQ_DATA73 - [7:0] */ +#define WM8995_WSEQ_DATA73_SHIFT 0 /* WSEQ_DATA73 - [7:0] */ +#define WM8995_WSEQ_DATA73_WIDTH 8 /* WSEQ_DATA73 - [7:0] */ + +/* + * R12582 (0x3126) - Write Sequencer 294 + */ +#define WM8995_WSEQ_DATA_WIDTH73_MASK 0x0700 /* WSEQ_DATA_WIDTH73 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH73_SHIFT 8 /* WSEQ_DATA_WIDTH73 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH73_WIDTH 3 /* WSEQ_DATA_WIDTH73 - [10:8] */ +#define WM8995_WSEQ_DATA_START73_MASK 0x000F /* WSEQ_DATA_START73 - [3:0] */ +#define WM8995_WSEQ_DATA_START73_SHIFT 0 /* WSEQ_DATA_START73 - [3:0] */ +#define WM8995_WSEQ_DATA_START73_WIDTH 4 /* WSEQ_DATA_START73 - [3:0] */ + +/* + * R12583 (0x3127) - Write Sequencer 295 + */ +#define WM8995_WSEQ_EOS73 0x0100 /* WSEQ_EOS73 */ +#define WM8995_WSEQ_EOS73_MASK 0x0100 /* WSEQ_EOS73 */ +#define WM8995_WSEQ_EOS73_SHIFT 8 /* WSEQ_EOS73 */ +#define WM8995_WSEQ_EOS73_WIDTH 1 /* WSEQ_EOS73 */ +#define WM8995_WSEQ_DELAY73_MASK 0x000F /* WSEQ_DELAY73 - [3:0] */ +#define WM8995_WSEQ_DELAY73_SHIFT 0 /* WSEQ_DELAY73 - [3:0] */ +#define WM8995_WSEQ_DELAY73_WIDTH 4 /* WSEQ_DELAY73 - [3:0] */ + +/* + * R12584 (0x3128) - Write Sequencer 296 + */ +#define WM8995_WSEQ_ADDR74_MASK 0x3FFF /* WSEQ_ADDR74 - [13:0] */ +#define WM8995_WSEQ_ADDR74_SHIFT 0 /* WSEQ_ADDR74 - [13:0] */ +#define WM8995_WSEQ_ADDR74_WIDTH 14 /* WSEQ_ADDR74 - [13:0] */ + +/* + * R12585 (0x3129) - Write Sequencer 297 + */ +#define WM8995_WSEQ_DATA74_MASK 0x00FF /* WSEQ_DATA74 - [7:0] */ +#define WM8995_WSEQ_DATA74_SHIFT 0 /* WSEQ_DATA74 - [7:0] */ +#define WM8995_WSEQ_DATA74_WIDTH 8 /* WSEQ_DATA74 - [7:0] */ + +/* + * R12586 (0x312A) - Write Sequencer 298 + */ +#define WM8995_WSEQ_DATA_WIDTH74_MASK 0x0700 /* WSEQ_DATA_WIDTH74 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH74_SHIFT 8 /* WSEQ_DATA_WIDTH74 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH74_WIDTH 3 /* WSEQ_DATA_WIDTH74 - [10:8] */ +#define WM8995_WSEQ_DATA_START74_MASK 0x000F /* WSEQ_DATA_START74 - [3:0] */ +#define WM8995_WSEQ_DATA_START74_SHIFT 0 /* WSEQ_DATA_START74 - [3:0] */ +#define WM8995_WSEQ_DATA_START74_WIDTH 4 /* WSEQ_DATA_START74 - [3:0] */ + +/* + * R12587 (0x312B) - Write Sequencer 299 + */ +#define WM8995_WSEQ_EOS74 0x0100 /* WSEQ_EOS74 */ +#define WM8995_WSEQ_EOS74_MASK 0x0100 /* WSEQ_EOS74 */ +#define WM8995_WSEQ_EOS74_SHIFT 8 /* WSEQ_EOS74 */ +#define WM8995_WSEQ_EOS74_WIDTH 1 /* WSEQ_EOS74 */ +#define WM8995_WSEQ_DELAY74_MASK 0x000F /* WSEQ_DELAY74 - [3:0] */ +#define WM8995_WSEQ_DELAY74_SHIFT 0 /* WSEQ_DELAY74 - [3:0] */ +#define WM8995_WSEQ_DELAY74_WIDTH 4 /* WSEQ_DELAY74 - [3:0] */ + +/* + * R12588 (0x312C) - Write Sequencer 300 + */ +#define WM8995_WSEQ_ADDR75_MASK 0x3FFF /* WSEQ_ADDR75 - [13:0] */ +#define WM8995_WSEQ_ADDR75_SHIFT 0 /* WSEQ_ADDR75 - [13:0] */ +#define WM8995_WSEQ_ADDR75_WIDTH 14 /* WSEQ_ADDR75 - [13:0] */ + +/* + * R12589 (0x312D) - Write Sequencer 301 + */ +#define WM8995_WSEQ_DATA75_MASK 0x00FF /* WSEQ_DATA75 - [7:0] */ +#define WM8995_WSEQ_DATA75_SHIFT 0 /* WSEQ_DATA75 - [7:0] */ +#define WM8995_WSEQ_DATA75_WIDTH 8 /* WSEQ_DATA75 - [7:0] */ + +/* + * R12590 (0x312E) - Write Sequencer 302 + */ +#define WM8995_WSEQ_DATA_WIDTH75_MASK 0x0700 /* WSEQ_DATA_WIDTH75 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH75_SHIFT 8 /* WSEQ_DATA_WIDTH75 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH75_WIDTH 3 /* WSEQ_DATA_WIDTH75 - [10:8] */ +#define WM8995_WSEQ_DATA_START75_MASK 0x000F /* WSEQ_DATA_START75 - [3:0] */ +#define WM8995_WSEQ_DATA_START75_SHIFT 0 /* WSEQ_DATA_START75 - [3:0] */ +#define WM8995_WSEQ_DATA_START75_WIDTH 4 /* WSEQ_DATA_START75 - [3:0] */ + +/* + * R12591 (0x312F) - Write Sequencer 303 + */ +#define WM8995_WSEQ_EOS75 0x0100 /* WSEQ_EOS75 */ +#define WM8995_WSEQ_EOS75_MASK 0x0100 /* WSEQ_EOS75 */ +#define WM8995_WSEQ_EOS75_SHIFT 8 /* WSEQ_EOS75 */ +#define WM8995_WSEQ_EOS75_WIDTH 1 /* WSEQ_EOS75 */ +#define WM8995_WSEQ_DELAY75_MASK 0x000F /* WSEQ_DELAY75 - [3:0] */ +#define WM8995_WSEQ_DELAY75_SHIFT 0 /* WSEQ_DELAY75 - [3:0] */ +#define WM8995_WSEQ_DELAY75_WIDTH 4 /* WSEQ_DELAY75 - [3:0] */ + +/* + * R12592 (0x3130) - Write Sequencer 304 + */ +#define WM8995_WSEQ_ADDR76_MASK 0x3FFF /* WSEQ_ADDR76 - [13:0] */ +#define WM8995_WSEQ_ADDR76_SHIFT 0 /* WSEQ_ADDR76 - [13:0] */ +#define WM8995_WSEQ_ADDR76_WIDTH 14 /* WSEQ_ADDR76 - [13:0] */ + +/* + * R12593 (0x3131) - Write Sequencer 305 + */ +#define WM8995_WSEQ_DATA76_MASK 0x00FF /* WSEQ_DATA76 - [7:0] */ +#define WM8995_WSEQ_DATA76_SHIFT 0 /* WSEQ_DATA76 - [7:0] */ +#define WM8995_WSEQ_DATA76_WIDTH 8 /* WSEQ_DATA76 - [7:0] */ + +/* + * R12594 (0x3132) - Write Sequencer 306 + */ +#define WM8995_WSEQ_DATA_WIDTH76_MASK 0x0700 /* WSEQ_DATA_WIDTH76 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH76_SHIFT 8 /* WSEQ_DATA_WIDTH76 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH76_WIDTH 3 /* WSEQ_DATA_WIDTH76 - [10:8] */ +#define WM8995_WSEQ_DATA_START76_MASK 0x000F /* WSEQ_DATA_START76 - [3:0] */ +#define WM8995_WSEQ_DATA_START76_SHIFT 0 /* WSEQ_DATA_START76 - [3:0] */ +#define WM8995_WSEQ_DATA_START76_WIDTH 4 /* WSEQ_DATA_START76 - [3:0] */ + +/* + * R12595 (0x3133) - Write Sequencer 307 + */ +#define WM8995_WSEQ_EOS76 0x0100 /* WSEQ_EOS76 */ +#define WM8995_WSEQ_EOS76_MASK 0x0100 /* WSEQ_EOS76 */ +#define WM8995_WSEQ_EOS76_SHIFT 8 /* WSEQ_EOS76 */ +#define WM8995_WSEQ_EOS76_WIDTH 1 /* WSEQ_EOS76 */ +#define WM8995_WSEQ_DELAY76_MASK 0x000F /* WSEQ_DELAY76 - [3:0] */ +#define WM8995_WSEQ_DELAY76_SHIFT 0 /* WSEQ_DELAY76 - [3:0] */ +#define WM8995_WSEQ_DELAY76_WIDTH 4 /* WSEQ_DELAY76 - [3:0] */ + +/* + * R12596 (0x3134) - Write Sequencer 308 + */ +#define WM8995_WSEQ_ADDR77_MASK 0x3FFF /* WSEQ_ADDR77 - [13:0] */ +#define WM8995_WSEQ_ADDR77_SHIFT 0 /* WSEQ_ADDR77 - [13:0] */ +#define WM8995_WSEQ_ADDR77_WIDTH 14 /* WSEQ_ADDR77 - [13:0] */ + +/* + * R12597 (0x3135) - Write Sequencer 309 + */ +#define WM8995_WSEQ_DATA77_MASK 0x00FF /* WSEQ_DATA77 - [7:0] */ +#define WM8995_WSEQ_DATA77_SHIFT 0 /* WSEQ_DATA77 - [7:0] */ +#define WM8995_WSEQ_DATA77_WIDTH 8 /* WSEQ_DATA77 - [7:0] */ + +/* + * R12598 (0x3136) - Write Sequencer 310 + */ +#define WM8995_WSEQ_DATA_WIDTH77_MASK 0x0700 /* WSEQ_DATA_WIDTH77 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH77_SHIFT 8 /* WSEQ_DATA_WIDTH77 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH77_WIDTH 3 /* WSEQ_DATA_WIDTH77 - [10:8] */ +#define WM8995_WSEQ_DATA_START77_MASK 0x000F /* WSEQ_DATA_START77 - [3:0] */ +#define WM8995_WSEQ_DATA_START77_SHIFT 0 /* WSEQ_DATA_START77 - [3:0] */ +#define WM8995_WSEQ_DATA_START77_WIDTH 4 /* WSEQ_DATA_START77 - [3:0] */ + +/* + * R12599 (0x3137) - Write Sequencer 311 + */ +#define WM8995_WSEQ_EOS77 0x0100 /* WSEQ_EOS77 */ +#define WM8995_WSEQ_EOS77_MASK 0x0100 /* WSEQ_EOS77 */ +#define WM8995_WSEQ_EOS77_SHIFT 8 /* WSEQ_EOS77 */ +#define WM8995_WSEQ_EOS77_WIDTH 1 /* WSEQ_EOS77 */ +#define WM8995_WSEQ_DELAY77_MASK 0x000F /* WSEQ_DELAY77 - [3:0] */ +#define WM8995_WSEQ_DELAY77_SHIFT 0 /* WSEQ_DELAY77 - [3:0] */ +#define WM8995_WSEQ_DELAY77_WIDTH 4 /* WSEQ_DELAY77 - [3:0] */ + +/* + * R12600 (0x3138) - Write Sequencer 312 + */ +#define WM8995_WSEQ_ADDR78_MASK 0x3FFF /* WSEQ_ADDR78 - [13:0] */ +#define WM8995_WSEQ_ADDR78_SHIFT 0 /* WSEQ_ADDR78 - [13:0] */ +#define WM8995_WSEQ_ADDR78_WIDTH 14 /* WSEQ_ADDR78 - [13:0] */ + +/* + * R12601 (0x3139) - Write Sequencer 313 + */ +#define WM8995_WSEQ_DATA78_MASK 0x00FF /* WSEQ_DATA78 - [7:0] */ +#define WM8995_WSEQ_DATA78_SHIFT 0 /* WSEQ_DATA78 - [7:0] */ +#define WM8995_WSEQ_DATA78_WIDTH 8 /* WSEQ_DATA78 - [7:0] */ + +/* + * R12602 (0x313A) - Write Sequencer 314 + */ +#define WM8995_WSEQ_DATA_WIDTH78_MASK 0x0700 /* WSEQ_DATA_WIDTH78 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH78_SHIFT 8 /* WSEQ_DATA_WIDTH78 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH78_WIDTH 3 /* WSEQ_DATA_WIDTH78 - [10:8] */ +#define WM8995_WSEQ_DATA_START78_MASK 0x000F /* WSEQ_DATA_START78 - [3:0] */ +#define WM8995_WSEQ_DATA_START78_SHIFT 0 /* WSEQ_DATA_START78 - [3:0] */ +#define WM8995_WSEQ_DATA_START78_WIDTH 4 /* WSEQ_DATA_START78 - [3:0] */ + +/* + * R12603 (0x313B) - Write Sequencer 315 + */ +#define WM8995_WSEQ_EOS78 0x0100 /* WSEQ_EOS78 */ +#define WM8995_WSEQ_EOS78_MASK 0x0100 /* WSEQ_EOS78 */ +#define WM8995_WSEQ_EOS78_SHIFT 8 /* WSEQ_EOS78 */ +#define WM8995_WSEQ_EOS78_WIDTH 1 /* WSEQ_EOS78 */ +#define WM8995_WSEQ_DELAY78_MASK 0x000F /* WSEQ_DELAY78 - [3:0] */ +#define WM8995_WSEQ_DELAY78_SHIFT 0 /* WSEQ_DELAY78 - [3:0] */ +#define WM8995_WSEQ_DELAY78_WIDTH 4 /* WSEQ_DELAY78 - [3:0] */ + +/* + * R12604 (0x313C) - Write Sequencer 316 + */ +#define WM8995_WSEQ_ADDR79_MASK 0x3FFF /* WSEQ_ADDR79 - [13:0] */ +#define WM8995_WSEQ_ADDR79_SHIFT 0 /* WSEQ_ADDR79 - [13:0] */ +#define WM8995_WSEQ_ADDR79_WIDTH 14 /* WSEQ_ADDR79 - [13:0] */ + +/* + * R12605 (0x313D) - Write Sequencer 317 + */ +#define WM8995_WSEQ_DATA79_MASK 0x00FF /* WSEQ_DATA79 - [7:0] */ +#define WM8995_WSEQ_DATA79_SHIFT 0 /* WSEQ_DATA79 - [7:0] */ +#define WM8995_WSEQ_DATA79_WIDTH 8 /* WSEQ_DATA79 - [7:0] */ + +/* + * R12606 (0x313E) - Write Sequencer 318 + */ +#define WM8995_WSEQ_DATA_WIDTH79_MASK 0x0700 /* WSEQ_DATA_WIDTH79 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH79_SHIFT 8 /* WSEQ_DATA_WIDTH79 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH79_WIDTH 3 /* WSEQ_DATA_WIDTH79 - [10:8] */ +#define WM8995_WSEQ_DATA_START79_MASK 0x000F /* WSEQ_DATA_START79 - [3:0] */ +#define WM8995_WSEQ_DATA_START79_SHIFT 0 /* WSEQ_DATA_START79 - [3:0] */ +#define WM8995_WSEQ_DATA_START79_WIDTH 4 /* WSEQ_DATA_START79 - [3:0] */ + +/* + * R12607 (0x313F) - Write Sequencer 319 + */ +#define WM8995_WSEQ_EOS79 0x0100 /* WSEQ_EOS79 */ +#define WM8995_WSEQ_EOS79_MASK 0x0100 /* WSEQ_EOS79 */ +#define WM8995_WSEQ_EOS79_SHIFT 8 /* WSEQ_EOS79 */ +#define WM8995_WSEQ_EOS79_WIDTH 1 /* WSEQ_EOS79 */ +#define WM8995_WSEQ_DELAY79_MASK 0x000F /* WSEQ_DELAY79 - [3:0] */ +#define WM8995_WSEQ_DELAY79_SHIFT 0 /* WSEQ_DELAY79 - [3:0] */ +#define WM8995_WSEQ_DELAY79_WIDTH 4 /* WSEQ_DELAY79 - [3:0] */ + +/* + * R12608 (0x3140) - Write Sequencer 320 + */ +#define WM8995_WSEQ_ADDR80_MASK 0x3FFF /* WSEQ_ADDR80 - [13:0] */ +#define WM8995_WSEQ_ADDR80_SHIFT 0 /* WSEQ_ADDR80 - [13:0] */ +#define WM8995_WSEQ_ADDR80_WIDTH 14 /* WSEQ_ADDR80 - [13:0] */ + +/* + * R12609 (0x3141) - Write Sequencer 321 + */ +#define WM8995_WSEQ_DATA80_MASK 0x00FF /* WSEQ_DATA80 - [7:0] */ +#define WM8995_WSEQ_DATA80_SHIFT 0 /* WSEQ_DATA80 - [7:0] */ +#define WM8995_WSEQ_DATA80_WIDTH 8 /* WSEQ_DATA80 - [7:0] */ + +/* + * R12610 (0x3142) - Write Sequencer 322 + */ +#define WM8995_WSEQ_DATA_WIDTH80_MASK 0x0700 /* WSEQ_DATA_WIDTH80 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH80_SHIFT 8 /* WSEQ_DATA_WIDTH80 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH80_WIDTH 3 /* WSEQ_DATA_WIDTH80 - [10:8] */ +#define WM8995_WSEQ_DATA_START80_MASK 0x000F /* WSEQ_DATA_START80 - [3:0] */ +#define WM8995_WSEQ_DATA_START80_SHIFT 0 /* WSEQ_DATA_START80 - [3:0] */ +#define WM8995_WSEQ_DATA_START80_WIDTH 4 /* WSEQ_DATA_START80 - [3:0] */ + +/* + * R12611 (0x3143) - Write Sequencer 323 + */ +#define WM8995_WSEQ_EOS80 0x0100 /* WSEQ_EOS80 */ +#define WM8995_WSEQ_EOS80_MASK 0x0100 /* WSEQ_EOS80 */ +#define WM8995_WSEQ_EOS80_SHIFT 8 /* WSEQ_EOS80 */ +#define WM8995_WSEQ_EOS80_WIDTH 1 /* WSEQ_EOS80 */ +#define WM8995_WSEQ_DELAY80_MASK 0x000F /* WSEQ_DELAY80 - [3:0] */ +#define WM8995_WSEQ_DELAY80_SHIFT 0 /* WSEQ_DELAY80 - [3:0] */ +#define WM8995_WSEQ_DELAY80_WIDTH 4 /* WSEQ_DELAY80 - [3:0] */ + +/* + * R12612 (0x3144) - Write Sequencer 324 + */ +#define WM8995_WSEQ_ADDR81_MASK 0x3FFF /* WSEQ_ADDR81 - [13:0] */ +#define WM8995_WSEQ_ADDR81_SHIFT 0 /* WSEQ_ADDR81 - [13:0] */ +#define WM8995_WSEQ_ADDR81_WIDTH 14 /* WSEQ_ADDR81 - [13:0] */ + +/* + * R12613 (0x3145) - Write Sequencer 325 + */ +#define WM8995_WSEQ_DATA81_MASK 0x00FF /* WSEQ_DATA81 - [7:0] */ +#define WM8995_WSEQ_DATA81_SHIFT 0 /* WSEQ_DATA81 - [7:0] */ +#define WM8995_WSEQ_DATA81_WIDTH 8 /* WSEQ_DATA81 - [7:0] */ + +/* + * R12614 (0x3146) - Write Sequencer 326 + */ +#define WM8995_WSEQ_DATA_WIDTH81_MASK 0x0700 /* WSEQ_DATA_WIDTH81 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH81_SHIFT 8 /* WSEQ_DATA_WIDTH81 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH81_WIDTH 3 /* WSEQ_DATA_WIDTH81 - [10:8] */ +#define WM8995_WSEQ_DATA_START81_MASK 0x000F /* WSEQ_DATA_START81 - [3:0] */ +#define WM8995_WSEQ_DATA_START81_SHIFT 0 /* WSEQ_DATA_START81 - [3:0] */ +#define WM8995_WSEQ_DATA_START81_WIDTH 4 /* WSEQ_DATA_START81 - [3:0] */ + +/* + * R12615 (0x3147) - Write Sequencer 327 + */ +#define WM8995_WSEQ_EOS81 0x0100 /* WSEQ_EOS81 */ +#define WM8995_WSEQ_EOS81_MASK 0x0100 /* WSEQ_EOS81 */ +#define WM8995_WSEQ_EOS81_SHIFT 8 /* WSEQ_EOS81 */ +#define WM8995_WSEQ_EOS81_WIDTH 1 /* WSEQ_EOS81 */ +#define WM8995_WSEQ_DELAY81_MASK 0x000F /* WSEQ_DELAY81 - [3:0] */ +#define WM8995_WSEQ_DELAY81_SHIFT 0 /* WSEQ_DELAY81 - [3:0] */ +#define WM8995_WSEQ_DELAY81_WIDTH 4 /* WSEQ_DELAY81 - [3:0] */ + +/* + * R12616 (0x3148) - Write Sequencer 328 + */ +#define WM8995_WSEQ_ADDR82_MASK 0x3FFF /* WSEQ_ADDR82 - [13:0] */ +#define WM8995_WSEQ_ADDR82_SHIFT 0 /* WSEQ_ADDR82 - [13:0] */ +#define WM8995_WSEQ_ADDR82_WIDTH 14 /* WSEQ_ADDR82 - [13:0] */ + +/* + * R12617 (0x3149) - Write Sequencer 329 + */ +#define WM8995_WSEQ_DATA82_MASK 0x00FF /* WSEQ_DATA82 - [7:0] */ +#define WM8995_WSEQ_DATA82_SHIFT 0 /* WSEQ_DATA82 - [7:0] */ +#define WM8995_WSEQ_DATA82_WIDTH 8 /* WSEQ_DATA82 - [7:0] */ + +/* + * R12618 (0x314A) - Write Sequencer 330 + */ +#define WM8995_WSEQ_DATA_WIDTH82_MASK 0x0700 /* WSEQ_DATA_WIDTH82 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH82_SHIFT 8 /* WSEQ_DATA_WIDTH82 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH82_WIDTH 3 /* WSEQ_DATA_WIDTH82 - [10:8] */ +#define WM8995_WSEQ_DATA_START82_MASK 0x000F /* WSEQ_DATA_START82 - [3:0] */ +#define WM8995_WSEQ_DATA_START82_SHIFT 0 /* WSEQ_DATA_START82 - [3:0] */ +#define WM8995_WSEQ_DATA_START82_WIDTH 4 /* WSEQ_DATA_START82 - [3:0] */ + +/* + * R12619 (0x314B) - Write Sequencer 331 + */ +#define WM8995_WSEQ_EOS82 0x0100 /* WSEQ_EOS82 */ +#define WM8995_WSEQ_EOS82_MASK 0x0100 /* WSEQ_EOS82 */ +#define WM8995_WSEQ_EOS82_SHIFT 8 /* WSEQ_EOS82 */ +#define WM8995_WSEQ_EOS82_WIDTH 1 /* WSEQ_EOS82 */ +#define WM8995_WSEQ_DELAY82_MASK 0x000F /* WSEQ_DELAY82 - [3:0] */ +#define WM8995_WSEQ_DELAY82_SHIFT 0 /* WSEQ_DELAY82 - [3:0] */ +#define WM8995_WSEQ_DELAY82_WIDTH 4 /* WSEQ_DELAY82 - [3:0] */ + +/* + * R12620 (0x314C) - Write Sequencer 332 + */ +#define WM8995_WSEQ_ADDR83_MASK 0x3FFF /* WSEQ_ADDR83 - [13:0] */ +#define WM8995_WSEQ_ADDR83_SHIFT 0 /* WSEQ_ADDR83 - [13:0] */ +#define WM8995_WSEQ_ADDR83_WIDTH 14 /* WSEQ_ADDR83 - [13:0] */ + +/* + * R12621 (0x314D) - Write Sequencer 333 + */ +#define WM8995_WSEQ_DATA83_MASK 0x00FF /* WSEQ_DATA83 - [7:0] */ +#define WM8995_WSEQ_DATA83_SHIFT 0 /* WSEQ_DATA83 - [7:0] */ +#define WM8995_WSEQ_DATA83_WIDTH 8 /* WSEQ_DATA83 - [7:0] */ + +/* + * R12622 (0x314E) - Write Sequencer 334 + */ +#define WM8995_WSEQ_DATA_WIDTH83_MASK 0x0700 /* WSEQ_DATA_WIDTH83 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH83_SHIFT 8 /* WSEQ_DATA_WIDTH83 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH83_WIDTH 3 /* WSEQ_DATA_WIDTH83 - [10:8] */ +#define WM8995_WSEQ_DATA_START83_MASK 0x000F /* WSEQ_DATA_START83 - [3:0] */ +#define WM8995_WSEQ_DATA_START83_SHIFT 0 /* WSEQ_DATA_START83 - [3:0] */ +#define WM8995_WSEQ_DATA_START83_WIDTH 4 /* WSEQ_DATA_START83 - [3:0] */ + +/* + * R12623 (0x314F) - Write Sequencer 335 + */ +#define WM8995_WSEQ_EOS83 0x0100 /* WSEQ_EOS83 */ +#define WM8995_WSEQ_EOS83_MASK 0x0100 /* WSEQ_EOS83 */ +#define WM8995_WSEQ_EOS83_SHIFT 8 /* WSEQ_EOS83 */ +#define WM8995_WSEQ_EOS83_WIDTH 1 /* WSEQ_EOS83 */ +#define WM8995_WSEQ_DELAY83_MASK 0x000F /* WSEQ_DELAY83 - [3:0] */ +#define WM8995_WSEQ_DELAY83_SHIFT 0 /* WSEQ_DELAY83 - [3:0] */ +#define WM8995_WSEQ_DELAY83_WIDTH 4 /* WSEQ_DELAY83 - [3:0] */ + +/* + * R12624 (0x3150) - Write Sequencer 336 + */ +#define WM8995_WSEQ_ADDR84_MASK 0x3FFF /* WSEQ_ADDR84 - [13:0] */ +#define WM8995_WSEQ_ADDR84_SHIFT 0 /* WSEQ_ADDR84 - [13:0] */ +#define WM8995_WSEQ_ADDR84_WIDTH 14 /* WSEQ_ADDR84 - [13:0] */ + +/* + * R12625 (0x3151) - Write Sequencer 337 + */ +#define WM8995_WSEQ_DATA84_MASK 0x00FF /* WSEQ_DATA84 - [7:0] */ +#define WM8995_WSEQ_DATA84_SHIFT 0 /* WSEQ_DATA84 - [7:0] */ +#define WM8995_WSEQ_DATA84_WIDTH 8 /* WSEQ_DATA84 - [7:0] */ + +/* + * R12626 (0x3152) - Write Sequencer 338 + */ +#define WM8995_WSEQ_DATA_WIDTH84_MASK 0x0700 /* WSEQ_DATA_WIDTH84 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH84_SHIFT 8 /* WSEQ_DATA_WIDTH84 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH84_WIDTH 3 /* WSEQ_DATA_WIDTH84 - [10:8] */ +#define WM8995_WSEQ_DATA_START84_MASK 0x000F /* WSEQ_DATA_START84 - [3:0] */ +#define WM8995_WSEQ_DATA_START84_SHIFT 0 /* WSEQ_DATA_START84 - [3:0] */ +#define WM8995_WSEQ_DATA_START84_WIDTH 4 /* WSEQ_DATA_START84 - [3:0] */ + +/* + * R12627 (0x3153) - Write Sequencer 339 + */ +#define WM8995_WSEQ_EOS84 0x0100 /* WSEQ_EOS84 */ +#define WM8995_WSEQ_EOS84_MASK 0x0100 /* WSEQ_EOS84 */ +#define WM8995_WSEQ_EOS84_SHIFT 8 /* WSEQ_EOS84 */ +#define WM8995_WSEQ_EOS84_WIDTH 1 /* WSEQ_EOS84 */ +#define WM8995_WSEQ_DELAY84_MASK 0x000F /* WSEQ_DELAY84 - [3:0] */ +#define WM8995_WSEQ_DELAY84_SHIFT 0 /* WSEQ_DELAY84 - [3:0] */ +#define WM8995_WSEQ_DELAY84_WIDTH 4 /* WSEQ_DELAY84 - [3:0] */ + +/* + * R12628 (0x3154) - Write Sequencer 340 + */ +#define WM8995_WSEQ_ADDR85_MASK 0x3FFF /* WSEQ_ADDR85 - [13:0] */ +#define WM8995_WSEQ_ADDR85_SHIFT 0 /* WSEQ_ADDR85 - [13:0] */ +#define WM8995_WSEQ_ADDR85_WIDTH 14 /* WSEQ_ADDR85 - [13:0] */ + +/* + * R12629 (0x3155) - Write Sequencer 341 + */ +#define WM8995_WSEQ_DATA85_MASK 0x00FF /* WSEQ_DATA85 - [7:0] */ +#define WM8995_WSEQ_DATA85_SHIFT 0 /* WSEQ_DATA85 - [7:0] */ +#define WM8995_WSEQ_DATA85_WIDTH 8 /* WSEQ_DATA85 - [7:0] */ + +/* + * R12630 (0x3156) - Write Sequencer 342 + */ +#define WM8995_WSEQ_DATA_WIDTH85_MASK 0x0700 /* WSEQ_DATA_WIDTH85 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH85_SHIFT 8 /* WSEQ_DATA_WIDTH85 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH85_WIDTH 3 /* WSEQ_DATA_WIDTH85 - [10:8] */ +#define WM8995_WSEQ_DATA_START85_MASK 0x000F /* WSEQ_DATA_START85 - [3:0] */ +#define WM8995_WSEQ_DATA_START85_SHIFT 0 /* WSEQ_DATA_START85 - [3:0] */ +#define WM8995_WSEQ_DATA_START85_WIDTH 4 /* WSEQ_DATA_START85 - [3:0] */ + +/* + * R12631 (0x3157) - Write Sequencer 343 + */ +#define WM8995_WSEQ_EOS85 0x0100 /* WSEQ_EOS85 */ +#define WM8995_WSEQ_EOS85_MASK 0x0100 /* WSEQ_EOS85 */ +#define WM8995_WSEQ_EOS85_SHIFT 8 /* WSEQ_EOS85 */ +#define WM8995_WSEQ_EOS85_WIDTH 1 /* WSEQ_EOS85 */ +#define WM8995_WSEQ_DELAY85_MASK 0x000F /* WSEQ_DELAY85 - [3:0] */ +#define WM8995_WSEQ_DELAY85_SHIFT 0 /* WSEQ_DELAY85 - [3:0] */ +#define WM8995_WSEQ_DELAY85_WIDTH 4 /* WSEQ_DELAY85 - [3:0] */ + +/* + * R12632 (0x3158) - Write Sequencer 344 + */ +#define WM8995_WSEQ_ADDR86_MASK 0x3FFF /* WSEQ_ADDR86 - [13:0] */ +#define WM8995_WSEQ_ADDR86_SHIFT 0 /* WSEQ_ADDR86 - [13:0] */ +#define WM8995_WSEQ_ADDR86_WIDTH 14 /* WSEQ_ADDR86 - [13:0] */ + +/* + * R12633 (0x3159) - Write Sequencer 345 + */ +#define WM8995_WSEQ_DATA86_MASK 0x00FF /* WSEQ_DATA86 - [7:0] */ +#define WM8995_WSEQ_DATA86_SHIFT 0 /* WSEQ_DATA86 - [7:0] */ +#define WM8995_WSEQ_DATA86_WIDTH 8 /* WSEQ_DATA86 - [7:0] */ + +/* + * R12634 (0x315A) - Write Sequencer 346 + */ +#define WM8995_WSEQ_DATA_WIDTH86_MASK 0x0700 /* WSEQ_DATA_WIDTH86 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH86_SHIFT 8 /* WSEQ_DATA_WIDTH86 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH86_WIDTH 3 /* WSEQ_DATA_WIDTH86 - [10:8] */ +#define WM8995_WSEQ_DATA_START86_MASK 0x000F /* WSEQ_DATA_START86 - [3:0] */ +#define WM8995_WSEQ_DATA_START86_SHIFT 0 /* WSEQ_DATA_START86 - [3:0] */ +#define WM8995_WSEQ_DATA_START86_WIDTH 4 /* WSEQ_DATA_START86 - [3:0] */ + +/* + * R12635 (0x315B) - Write Sequencer 347 + */ +#define WM8995_WSEQ_EOS86 0x0100 /* WSEQ_EOS86 */ +#define WM8995_WSEQ_EOS86_MASK 0x0100 /* WSEQ_EOS86 */ +#define WM8995_WSEQ_EOS86_SHIFT 8 /* WSEQ_EOS86 */ +#define WM8995_WSEQ_EOS86_WIDTH 1 /* WSEQ_EOS86 */ +#define WM8995_WSEQ_DELAY86_MASK 0x000F /* WSEQ_DELAY86 - [3:0] */ +#define WM8995_WSEQ_DELAY86_SHIFT 0 /* WSEQ_DELAY86 - [3:0] */ +#define WM8995_WSEQ_DELAY86_WIDTH 4 /* WSEQ_DELAY86 - [3:0] */ + +/* + * R12636 (0x315C) - Write Sequencer 348 + */ +#define WM8995_WSEQ_ADDR87_MASK 0x3FFF /* WSEQ_ADDR87 - [13:0] */ +#define WM8995_WSEQ_ADDR87_SHIFT 0 /* WSEQ_ADDR87 - [13:0] */ +#define WM8995_WSEQ_ADDR87_WIDTH 14 /* WSEQ_ADDR87 - [13:0] */ + +/* + * R12637 (0x315D) - Write Sequencer 349 + */ +#define WM8995_WSEQ_DATA87_MASK 0x00FF /* WSEQ_DATA87 - [7:0] */ +#define WM8995_WSEQ_DATA87_SHIFT 0 /* WSEQ_DATA87 - [7:0] */ +#define WM8995_WSEQ_DATA87_WIDTH 8 /* WSEQ_DATA87 - [7:0] */ + +/* + * R12638 (0x315E) - Write Sequencer 350 + */ +#define WM8995_WSEQ_DATA_WIDTH87_MASK 0x0700 /* WSEQ_DATA_WIDTH87 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH87_SHIFT 8 /* WSEQ_DATA_WIDTH87 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH87_WIDTH 3 /* WSEQ_DATA_WIDTH87 - [10:8] */ +#define WM8995_WSEQ_DATA_START87_MASK 0x000F /* WSEQ_DATA_START87 - [3:0] */ +#define WM8995_WSEQ_DATA_START87_SHIFT 0 /* WSEQ_DATA_START87 - [3:0] */ +#define WM8995_WSEQ_DATA_START87_WIDTH 4 /* WSEQ_DATA_START87 - [3:0] */ + +/* + * R12639 (0x315F) - Write Sequencer 351 + */ +#define WM8995_WSEQ_EOS87 0x0100 /* WSEQ_EOS87 */ +#define WM8995_WSEQ_EOS87_MASK 0x0100 /* WSEQ_EOS87 */ +#define WM8995_WSEQ_EOS87_SHIFT 8 /* WSEQ_EOS87 */ +#define WM8995_WSEQ_EOS87_WIDTH 1 /* WSEQ_EOS87 */ +#define WM8995_WSEQ_DELAY87_MASK 0x000F /* WSEQ_DELAY87 - [3:0] */ +#define WM8995_WSEQ_DELAY87_SHIFT 0 /* WSEQ_DELAY87 - [3:0] */ +#define WM8995_WSEQ_DELAY87_WIDTH 4 /* WSEQ_DELAY87 - [3:0] */ + +/* + * R12640 (0x3160) - Write Sequencer 352 + */ +#define WM8995_WSEQ_ADDR88_MASK 0x3FFF /* WSEQ_ADDR88 - [13:0] */ +#define WM8995_WSEQ_ADDR88_SHIFT 0 /* WSEQ_ADDR88 - [13:0] */ +#define WM8995_WSEQ_ADDR88_WIDTH 14 /* WSEQ_ADDR88 - [13:0] */ + +/* + * R12641 (0x3161) - Write Sequencer 353 + */ +#define WM8995_WSEQ_DATA88_MASK 0x00FF /* WSEQ_DATA88 - [7:0] */ +#define WM8995_WSEQ_DATA88_SHIFT 0 /* WSEQ_DATA88 - [7:0] */ +#define WM8995_WSEQ_DATA88_WIDTH 8 /* WSEQ_DATA88 - [7:0] */ + +/* + * R12642 (0x3162) - Write Sequencer 354 + */ +#define WM8995_WSEQ_DATA_WIDTH88_MASK 0x0700 /* WSEQ_DATA_WIDTH88 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH88_SHIFT 8 /* WSEQ_DATA_WIDTH88 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH88_WIDTH 3 /* WSEQ_DATA_WIDTH88 - [10:8] */ +#define WM8995_WSEQ_DATA_START88_MASK 0x000F /* WSEQ_DATA_START88 - [3:0] */ +#define WM8995_WSEQ_DATA_START88_SHIFT 0 /* WSEQ_DATA_START88 - [3:0] */ +#define WM8995_WSEQ_DATA_START88_WIDTH 4 /* WSEQ_DATA_START88 - [3:0] */ + +/* + * R12643 (0x3163) - Write Sequencer 355 + */ +#define WM8995_WSEQ_EOS88 0x0100 /* WSEQ_EOS88 */ +#define WM8995_WSEQ_EOS88_MASK 0x0100 /* WSEQ_EOS88 */ +#define WM8995_WSEQ_EOS88_SHIFT 8 /* WSEQ_EOS88 */ +#define WM8995_WSEQ_EOS88_WIDTH 1 /* WSEQ_EOS88 */ +#define WM8995_WSEQ_DELAY88_MASK 0x000F /* WSEQ_DELAY88 - [3:0] */ +#define WM8995_WSEQ_DELAY88_SHIFT 0 /* WSEQ_DELAY88 - [3:0] */ +#define WM8995_WSEQ_DELAY88_WIDTH 4 /* WSEQ_DELAY88 - [3:0] */ + +/* + * R12644 (0x3164) - Write Sequencer 356 + */ +#define WM8995_WSEQ_ADDR89_MASK 0x3FFF /* WSEQ_ADDR89 - [13:0] */ +#define WM8995_WSEQ_ADDR89_SHIFT 0 /* WSEQ_ADDR89 - [13:0] */ +#define WM8995_WSEQ_ADDR89_WIDTH 14 /* WSEQ_ADDR89 - [13:0] */ + +/* + * R12645 (0x3165) - Write Sequencer 357 + */ +#define WM8995_WSEQ_DATA89_MASK 0x00FF /* WSEQ_DATA89 - [7:0] */ +#define WM8995_WSEQ_DATA89_SHIFT 0 /* WSEQ_DATA89 - [7:0] */ +#define WM8995_WSEQ_DATA89_WIDTH 8 /* WSEQ_DATA89 - [7:0] */ + +/* + * R12646 (0x3166) - Write Sequencer 358 + */ +#define WM8995_WSEQ_DATA_WIDTH89_MASK 0x0700 /* WSEQ_DATA_WIDTH89 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH89_SHIFT 8 /* WSEQ_DATA_WIDTH89 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH89_WIDTH 3 /* WSEQ_DATA_WIDTH89 - [10:8] */ +#define WM8995_WSEQ_DATA_START89_MASK 0x000F /* WSEQ_DATA_START89 - [3:0] */ +#define WM8995_WSEQ_DATA_START89_SHIFT 0 /* WSEQ_DATA_START89 - [3:0] */ +#define WM8995_WSEQ_DATA_START89_WIDTH 4 /* WSEQ_DATA_START89 - [3:0] */ + +/* + * R12647 (0x3167) - Write Sequencer 359 + */ +#define WM8995_WSEQ_EOS89 0x0100 /* WSEQ_EOS89 */ +#define WM8995_WSEQ_EOS89_MASK 0x0100 /* WSEQ_EOS89 */ +#define WM8995_WSEQ_EOS89_SHIFT 8 /* WSEQ_EOS89 */ +#define WM8995_WSEQ_EOS89_WIDTH 1 /* WSEQ_EOS89 */ +#define WM8995_WSEQ_DELAY89_MASK 0x000F /* WSEQ_DELAY89 - [3:0] */ +#define WM8995_WSEQ_DELAY89_SHIFT 0 /* WSEQ_DELAY89 - [3:0] */ +#define WM8995_WSEQ_DELAY89_WIDTH 4 /* WSEQ_DELAY89 - [3:0] */ + +/* + * R12648 (0x3168) - Write Sequencer 360 + */ +#define WM8995_WSEQ_ADDR90_MASK 0x3FFF /* WSEQ_ADDR90 - [13:0] */ +#define WM8995_WSEQ_ADDR90_SHIFT 0 /* WSEQ_ADDR90 - [13:0] */ +#define WM8995_WSEQ_ADDR90_WIDTH 14 /* WSEQ_ADDR90 - [13:0] */ + +/* + * R12649 (0x3169) - Write Sequencer 361 + */ +#define WM8995_WSEQ_DATA90_MASK 0x00FF /* WSEQ_DATA90 - [7:0] */ +#define WM8995_WSEQ_DATA90_SHIFT 0 /* WSEQ_DATA90 - [7:0] */ +#define WM8995_WSEQ_DATA90_WIDTH 8 /* WSEQ_DATA90 - [7:0] */ + +/* + * R12650 (0x316A) - Write Sequencer 362 + */ +#define WM8995_WSEQ_DATA_WIDTH90_MASK 0x0700 /* WSEQ_DATA_WIDTH90 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH90_SHIFT 8 /* WSEQ_DATA_WIDTH90 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH90_WIDTH 3 /* WSEQ_DATA_WIDTH90 - [10:8] */ +#define WM8995_WSEQ_DATA_START90_MASK 0x000F /* WSEQ_DATA_START90 - [3:0] */ +#define WM8995_WSEQ_DATA_START90_SHIFT 0 /* WSEQ_DATA_START90 - [3:0] */ +#define WM8995_WSEQ_DATA_START90_WIDTH 4 /* WSEQ_DATA_START90 - [3:0] */ + +/* + * R12651 (0x316B) - Write Sequencer 363 + */ +#define WM8995_WSEQ_EOS90 0x0100 /* WSEQ_EOS90 */ +#define WM8995_WSEQ_EOS90_MASK 0x0100 /* WSEQ_EOS90 */ +#define WM8995_WSEQ_EOS90_SHIFT 8 /* WSEQ_EOS90 */ +#define WM8995_WSEQ_EOS90_WIDTH 1 /* WSEQ_EOS90 */ +#define WM8995_WSEQ_DELAY90_MASK 0x000F /* WSEQ_DELAY90 - [3:0] */ +#define WM8995_WSEQ_DELAY90_SHIFT 0 /* WSEQ_DELAY90 - [3:0] */ +#define WM8995_WSEQ_DELAY90_WIDTH 4 /* WSEQ_DELAY90 - [3:0] */ + +/* + * R12652 (0x316C) - Write Sequencer 364 + */ +#define WM8995_WSEQ_ADDR91_MASK 0x3FFF /* WSEQ_ADDR91 - [13:0] */ +#define WM8995_WSEQ_ADDR91_SHIFT 0 /* WSEQ_ADDR91 - [13:0] */ +#define WM8995_WSEQ_ADDR91_WIDTH 14 /* WSEQ_ADDR91 - [13:0] */ + +/* + * R12653 (0x316D) - Write Sequencer 365 + */ +#define WM8995_WSEQ_DATA91_MASK 0x00FF /* WSEQ_DATA91 - [7:0] */ +#define WM8995_WSEQ_DATA91_SHIFT 0 /* WSEQ_DATA91 - [7:0] */ +#define WM8995_WSEQ_DATA91_WIDTH 8 /* WSEQ_DATA91 - [7:0] */ + +/* + * R12654 (0x316E) - Write Sequencer 366 + */ +#define WM8995_WSEQ_DATA_WIDTH91_MASK 0x0700 /* WSEQ_DATA_WIDTH91 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH91_SHIFT 8 /* WSEQ_DATA_WIDTH91 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH91_WIDTH 3 /* WSEQ_DATA_WIDTH91 - [10:8] */ +#define WM8995_WSEQ_DATA_START91_MASK 0x000F /* WSEQ_DATA_START91 - [3:0] */ +#define WM8995_WSEQ_DATA_START91_SHIFT 0 /* WSEQ_DATA_START91 - [3:0] */ +#define WM8995_WSEQ_DATA_START91_WIDTH 4 /* WSEQ_DATA_START91 - [3:0] */ + +/* + * R12655 (0x316F) - Write Sequencer 367 + */ +#define WM8995_WSEQ_EOS91 0x0100 /* WSEQ_EOS91 */ +#define WM8995_WSEQ_EOS91_MASK 0x0100 /* WSEQ_EOS91 */ +#define WM8995_WSEQ_EOS91_SHIFT 8 /* WSEQ_EOS91 */ +#define WM8995_WSEQ_EOS91_WIDTH 1 /* WSEQ_EOS91 */ +#define WM8995_WSEQ_DELAY91_MASK 0x000F /* WSEQ_DELAY91 - [3:0] */ +#define WM8995_WSEQ_DELAY91_SHIFT 0 /* WSEQ_DELAY91 - [3:0] */ +#define WM8995_WSEQ_DELAY91_WIDTH 4 /* WSEQ_DELAY91 - [3:0] */ + +/* + * R12656 (0x3170) - Write Sequencer 368 + */ +#define WM8995_WSEQ_ADDR92_MASK 0x3FFF /* WSEQ_ADDR92 - [13:0] */ +#define WM8995_WSEQ_ADDR92_SHIFT 0 /* WSEQ_ADDR92 - [13:0] */ +#define WM8995_WSEQ_ADDR92_WIDTH 14 /* WSEQ_ADDR92 - [13:0] */ + +/* + * R12657 (0x3171) - Write Sequencer 369 + */ +#define WM8995_WSEQ_DATA92_MASK 0x00FF /* WSEQ_DATA92 - [7:0] */ +#define WM8995_WSEQ_DATA92_SHIFT 0 /* WSEQ_DATA92 - [7:0] */ +#define WM8995_WSEQ_DATA92_WIDTH 8 /* WSEQ_DATA92 - [7:0] */ + +/* + * R12658 (0x3172) - Write Sequencer 370 + */ +#define WM8995_WSEQ_DATA_WIDTH92_MASK 0x0700 /* WSEQ_DATA_WIDTH92 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH92_SHIFT 8 /* WSEQ_DATA_WIDTH92 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH92_WIDTH 3 /* WSEQ_DATA_WIDTH92 - [10:8] */ +#define WM8995_WSEQ_DATA_START92_MASK 0x000F /* WSEQ_DATA_START92 - [3:0] */ +#define WM8995_WSEQ_DATA_START92_SHIFT 0 /* WSEQ_DATA_START92 - [3:0] */ +#define WM8995_WSEQ_DATA_START92_WIDTH 4 /* WSEQ_DATA_START92 - [3:0] */ + +/* + * R12659 (0x3173) - Write Sequencer 371 + */ +#define WM8995_WSEQ_EOS92 0x0100 /* WSEQ_EOS92 */ +#define WM8995_WSEQ_EOS92_MASK 0x0100 /* WSEQ_EOS92 */ +#define WM8995_WSEQ_EOS92_SHIFT 8 /* WSEQ_EOS92 */ +#define WM8995_WSEQ_EOS92_WIDTH 1 /* WSEQ_EOS92 */ +#define WM8995_WSEQ_DELAY92_MASK 0x000F /* WSEQ_DELAY92 - [3:0] */ +#define WM8995_WSEQ_DELAY92_SHIFT 0 /* WSEQ_DELAY92 - [3:0] */ +#define WM8995_WSEQ_DELAY92_WIDTH 4 /* WSEQ_DELAY92 - [3:0] */ + +/* + * R12660 (0x3174) - Write Sequencer 372 + */ +#define WM8995_WSEQ_ADDR93_MASK 0x3FFF /* WSEQ_ADDR93 - [13:0] */ +#define WM8995_WSEQ_ADDR93_SHIFT 0 /* WSEQ_ADDR93 - [13:0] */ +#define WM8995_WSEQ_ADDR93_WIDTH 14 /* WSEQ_ADDR93 - [13:0] */ + +/* + * R12661 (0x3175) - Write Sequencer 373 + */ +#define WM8995_WSEQ_DATA93_MASK 0x00FF /* WSEQ_DATA93 - [7:0] */ +#define WM8995_WSEQ_DATA93_SHIFT 0 /* WSEQ_DATA93 - [7:0] */ +#define WM8995_WSEQ_DATA93_WIDTH 8 /* WSEQ_DATA93 - [7:0] */ + +/* + * R12662 (0x3176) - Write Sequencer 374 + */ +#define WM8995_WSEQ_DATA_WIDTH93_MASK 0x0700 /* WSEQ_DATA_WIDTH93 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH93_SHIFT 8 /* WSEQ_DATA_WIDTH93 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH93_WIDTH 3 /* WSEQ_DATA_WIDTH93 - [10:8] */ +#define WM8995_WSEQ_DATA_START93_MASK 0x000F /* WSEQ_DATA_START93 - [3:0] */ +#define WM8995_WSEQ_DATA_START93_SHIFT 0 /* WSEQ_DATA_START93 - [3:0] */ +#define WM8995_WSEQ_DATA_START93_WIDTH 4 /* WSEQ_DATA_START93 - [3:0] */ + +/* + * R12663 (0x3177) - Write Sequencer 375 + */ +#define WM8995_WSEQ_EOS93 0x0100 /* WSEQ_EOS93 */ +#define WM8995_WSEQ_EOS93_MASK 0x0100 /* WSEQ_EOS93 */ +#define WM8995_WSEQ_EOS93_SHIFT 8 /* WSEQ_EOS93 */ +#define WM8995_WSEQ_EOS93_WIDTH 1 /* WSEQ_EOS93 */ +#define WM8995_WSEQ_DELAY93_MASK 0x000F /* WSEQ_DELAY93 - [3:0] */ +#define WM8995_WSEQ_DELAY93_SHIFT 0 /* WSEQ_DELAY93 - [3:0] */ +#define WM8995_WSEQ_DELAY93_WIDTH 4 /* WSEQ_DELAY93 - [3:0] */ + +/* + * R12664 (0x3178) - Write Sequencer 376 + */ +#define WM8995_WSEQ_ADDR94_MASK 0x3FFF /* WSEQ_ADDR94 - [13:0] */ +#define WM8995_WSEQ_ADDR94_SHIFT 0 /* WSEQ_ADDR94 - [13:0] */ +#define WM8995_WSEQ_ADDR94_WIDTH 14 /* WSEQ_ADDR94 - [13:0] */ + +/* + * R12665 (0x3179) - Write Sequencer 377 + */ +#define WM8995_WSEQ_DATA94_MASK 0x00FF /* WSEQ_DATA94 - [7:0] */ +#define WM8995_WSEQ_DATA94_SHIFT 0 /* WSEQ_DATA94 - [7:0] */ +#define WM8995_WSEQ_DATA94_WIDTH 8 /* WSEQ_DATA94 - [7:0] */ + +/* + * R12666 (0x317A) - Write Sequencer 378 + */ +#define WM8995_WSEQ_DATA_WIDTH94_MASK 0x0700 /* WSEQ_DATA_WIDTH94 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH94_SHIFT 8 /* WSEQ_DATA_WIDTH94 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH94_WIDTH 3 /* WSEQ_DATA_WIDTH94 - [10:8] */ +#define WM8995_WSEQ_DATA_START94_MASK 0x000F /* WSEQ_DATA_START94 - [3:0] */ +#define WM8995_WSEQ_DATA_START94_SHIFT 0 /* WSEQ_DATA_START94 - [3:0] */ +#define WM8995_WSEQ_DATA_START94_WIDTH 4 /* WSEQ_DATA_START94 - [3:0] */ + +/* + * R12667 (0x317B) - Write Sequencer 379 + */ +#define WM8995_WSEQ_EOS94 0x0100 /* WSEQ_EOS94 */ +#define WM8995_WSEQ_EOS94_MASK 0x0100 /* WSEQ_EOS94 */ +#define WM8995_WSEQ_EOS94_SHIFT 8 /* WSEQ_EOS94 */ +#define WM8995_WSEQ_EOS94_WIDTH 1 /* WSEQ_EOS94 */ +#define WM8995_WSEQ_DELAY94_MASK 0x000F /* WSEQ_DELAY94 - [3:0] */ +#define WM8995_WSEQ_DELAY94_SHIFT 0 /* WSEQ_DELAY94 - [3:0] */ +#define WM8995_WSEQ_DELAY94_WIDTH 4 /* WSEQ_DELAY94 - [3:0] */ + +/* + * R12668 (0x317C) - Write Sequencer 380 + */ +#define WM8995_WSEQ_ADDR95_MASK 0x3FFF /* WSEQ_ADDR95 - [13:0] */ +#define WM8995_WSEQ_ADDR95_SHIFT 0 /* WSEQ_ADDR95 - [13:0] */ +#define WM8995_WSEQ_ADDR95_WIDTH 14 /* WSEQ_ADDR95 - [13:0] */ + +/* + * R12669 (0x317D) - Write Sequencer 381 + */ +#define WM8995_WSEQ_DATA95_MASK 0x00FF /* WSEQ_DATA95 - [7:0] */ +#define WM8995_WSEQ_DATA95_SHIFT 0 /* WSEQ_DATA95 - [7:0] */ +#define WM8995_WSEQ_DATA95_WIDTH 8 /* WSEQ_DATA95 - [7:0] */ + +/* + * R12670 (0x317E) - Write Sequencer 382 + */ +#define WM8995_WSEQ_DATA_WIDTH95_MASK 0x0700 /* WSEQ_DATA_WIDTH95 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH95_SHIFT 8 /* WSEQ_DATA_WIDTH95 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH95_WIDTH 3 /* WSEQ_DATA_WIDTH95 - [10:8] */ +#define WM8995_WSEQ_DATA_START95_MASK 0x000F /* WSEQ_DATA_START95 - [3:0] */ +#define WM8995_WSEQ_DATA_START95_SHIFT 0 /* WSEQ_DATA_START95 - [3:0] */ +#define WM8995_WSEQ_DATA_START95_WIDTH 4 /* WSEQ_DATA_START95 - [3:0] */ + +/* + * R12671 (0x317F) - Write Sequencer 383 + */ +#define WM8995_WSEQ_EOS95 0x0100 /* WSEQ_EOS95 */ +#define WM8995_WSEQ_EOS95_MASK 0x0100 /* WSEQ_EOS95 */ +#define WM8995_WSEQ_EOS95_SHIFT 8 /* WSEQ_EOS95 */ +#define WM8995_WSEQ_EOS95_WIDTH 1 /* WSEQ_EOS95 */ +#define WM8995_WSEQ_DELAY95_MASK 0x000F /* WSEQ_DELAY95 - [3:0] */ +#define WM8995_WSEQ_DELAY95_SHIFT 0 /* WSEQ_DELAY95 - [3:0] */ +#define WM8995_WSEQ_DELAY95_WIDTH 4 /* WSEQ_DELAY95 - [3:0] */ + +/* + * R12672 (0x3180) - Write Sequencer 384 + */ +#define WM8995_WSEQ_ADDR96_MASK 0x3FFF /* WSEQ_ADDR96 - [13:0] */ +#define WM8995_WSEQ_ADDR96_SHIFT 0 /* WSEQ_ADDR96 - [13:0] */ +#define WM8995_WSEQ_ADDR96_WIDTH 14 /* WSEQ_ADDR96 - [13:0] */ + +/* + * R12673 (0x3181) - Write Sequencer 385 + */ +#define WM8995_WSEQ_DATA96_MASK 0x00FF /* WSEQ_DATA96 - [7:0] */ +#define WM8995_WSEQ_DATA96_SHIFT 0 /* WSEQ_DATA96 - [7:0] */ +#define WM8995_WSEQ_DATA96_WIDTH 8 /* WSEQ_DATA96 - [7:0] */ + +/* + * R12674 (0x3182) - Write Sequencer 386 + */ +#define WM8995_WSEQ_DATA_WIDTH96_MASK 0x0700 /* WSEQ_DATA_WIDTH96 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH96_SHIFT 8 /* WSEQ_DATA_WIDTH96 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH96_WIDTH 3 /* WSEQ_DATA_WIDTH96 - [10:8] */ +#define WM8995_WSEQ_DATA_START96_MASK 0x000F /* WSEQ_DATA_START96 - [3:0] */ +#define WM8995_WSEQ_DATA_START96_SHIFT 0 /* WSEQ_DATA_START96 - [3:0] */ +#define WM8995_WSEQ_DATA_START96_WIDTH 4 /* WSEQ_DATA_START96 - [3:0] */ + +/* + * R12675 (0x3183) - Write Sequencer 387 + */ +#define WM8995_WSEQ_EOS96 0x0100 /* WSEQ_EOS96 */ +#define WM8995_WSEQ_EOS96_MASK 0x0100 /* WSEQ_EOS96 */ +#define WM8995_WSEQ_EOS96_SHIFT 8 /* WSEQ_EOS96 */ +#define WM8995_WSEQ_EOS96_WIDTH 1 /* WSEQ_EOS96 */ +#define WM8995_WSEQ_DELAY96_MASK 0x000F /* WSEQ_DELAY96 - [3:0] */ +#define WM8995_WSEQ_DELAY96_SHIFT 0 /* WSEQ_DELAY96 - [3:0] */ +#define WM8995_WSEQ_DELAY96_WIDTH 4 /* WSEQ_DELAY96 - [3:0] */ + +/* + * R12676 (0x3184) - Write Sequencer 388 + */ +#define WM8995_WSEQ_ADDR97_MASK 0x3FFF /* WSEQ_ADDR97 - [13:0] */ +#define WM8995_WSEQ_ADDR97_SHIFT 0 /* WSEQ_ADDR97 - [13:0] */ +#define WM8995_WSEQ_ADDR97_WIDTH 14 /* WSEQ_ADDR97 - [13:0] */ + +/* + * R12677 (0x3185) - Write Sequencer 389 + */ +#define WM8995_WSEQ_DATA97_MASK 0x00FF /* WSEQ_DATA97 - [7:0] */ +#define WM8995_WSEQ_DATA97_SHIFT 0 /* WSEQ_DATA97 - [7:0] */ +#define WM8995_WSEQ_DATA97_WIDTH 8 /* WSEQ_DATA97 - [7:0] */ + +/* + * R12678 (0x3186) - Write Sequencer 390 + */ +#define WM8995_WSEQ_DATA_WIDTH97_MASK 0x0700 /* WSEQ_DATA_WIDTH97 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH97_SHIFT 8 /* WSEQ_DATA_WIDTH97 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH97_WIDTH 3 /* WSEQ_DATA_WIDTH97 - [10:8] */ +#define WM8995_WSEQ_DATA_START97_MASK 0x000F /* WSEQ_DATA_START97 - [3:0] */ +#define WM8995_WSEQ_DATA_START97_SHIFT 0 /* WSEQ_DATA_START97 - [3:0] */ +#define WM8995_WSEQ_DATA_START97_WIDTH 4 /* WSEQ_DATA_START97 - [3:0] */ + +/* + * R12679 (0x3187) - Write Sequencer 391 + */ +#define WM8995_WSEQ_EOS97 0x0100 /* WSEQ_EOS97 */ +#define WM8995_WSEQ_EOS97_MASK 0x0100 /* WSEQ_EOS97 */ +#define WM8995_WSEQ_EOS97_SHIFT 8 /* WSEQ_EOS97 */ +#define WM8995_WSEQ_EOS97_WIDTH 1 /* WSEQ_EOS97 */ +#define WM8995_WSEQ_DELAY97_MASK 0x000F /* WSEQ_DELAY97 - [3:0] */ +#define WM8995_WSEQ_DELAY97_SHIFT 0 /* WSEQ_DELAY97 - [3:0] */ +#define WM8995_WSEQ_DELAY97_WIDTH 4 /* WSEQ_DELAY97 - [3:0] */ + +/* + * R12680 (0x3188) - Write Sequencer 392 + */ +#define WM8995_WSEQ_ADDR98_MASK 0x3FFF /* WSEQ_ADDR98 - [13:0] */ +#define WM8995_WSEQ_ADDR98_SHIFT 0 /* WSEQ_ADDR98 - [13:0] */ +#define WM8995_WSEQ_ADDR98_WIDTH 14 /* WSEQ_ADDR98 - [13:0] */ + +/* + * R12681 (0x3189) - Write Sequencer 393 + */ +#define WM8995_WSEQ_DATA98_MASK 0x00FF /* WSEQ_DATA98 - [7:0] */ +#define WM8995_WSEQ_DATA98_SHIFT 0 /* WSEQ_DATA98 - [7:0] */ +#define WM8995_WSEQ_DATA98_WIDTH 8 /* WSEQ_DATA98 - [7:0] */ + +/* + * R12682 (0x318A) - Write Sequencer 394 + */ +#define WM8995_WSEQ_DATA_WIDTH98_MASK 0x0700 /* WSEQ_DATA_WIDTH98 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH98_SHIFT 8 /* WSEQ_DATA_WIDTH98 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH98_WIDTH 3 /* WSEQ_DATA_WIDTH98 - [10:8] */ +#define WM8995_WSEQ_DATA_START98_MASK 0x000F /* WSEQ_DATA_START98 - [3:0] */ +#define WM8995_WSEQ_DATA_START98_SHIFT 0 /* WSEQ_DATA_START98 - [3:0] */ +#define WM8995_WSEQ_DATA_START98_WIDTH 4 /* WSEQ_DATA_START98 - [3:0] */ + +/* + * R12683 (0x318B) - Write Sequencer 395 + */ +#define WM8995_WSEQ_EOS98 0x0100 /* WSEQ_EOS98 */ +#define WM8995_WSEQ_EOS98_MASK 0x0100 /* WSEQ_EOS98 */ +#define WM8995_WSEQ_EOS98_SHIFT 8 /* WSEQ_EOS98 */ +#define WM8995_WSEQ_EOS98_WIDTH 1 /* WSEQ_EOS98 */ +#define WM8995_WSEQ_DELAY98_MASK 0x000F /* WSEQ_DELAY98 - [3:0] */ +#define WM8995_WSEQ_DELAY98_SHIFT 0 /* WSEQ_DELAY98 - [3:0] */ +#define WM8995_WSEQ_DELAY98_WIDTH 4 /* WSEQ_DELAY98 - [3:0] */ + +/* + * R12684 (0x318C) - Write Sequencer 396 + */ +#define WM8995_WSEQ_ADDR99_MASK 0x3FFF /* WSEQ_ADDR99 - [13:0] */ +#define WM8995_WSEQ_ADDR99_SHIFT 0 /* WSEQ_ADDR99 - [13:0] */ +#define WM8995_WSEQ_ADDR99_WIDTH 14 /* WSEQ_ADDR99 - [13:0] */ + +/* + * R12685 (0x318D) - Write Sequencer 397 + */ +#define WM8995_WSEQ_DATA99_MASK 0x00FF /* WSEQ_DATA99 - [7:0] */ +#define WM8995_WSEQ_DATA99_SHIFT 0 /* WSEQ_DATA99 - [7:0] */ +#define WM8995_WSEQ_DATA99_WIDTH 8 /* WSEQ_DATA99 - [7:0] */ + +/* + * R12686 (0x318E) - Write Sequencer 398 + */ +#define WM8995_WSEQ_DATA_WIDTH99_MASK 0x0700 /* WSEQ_DATA_WIDTH99 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH99_SHIFT 8 /* WSEQ_DATA_WIDTH99 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH99_WIDTH 3 /* WSEQ_DATA_WIDTH99 - [10:8] */ +#define WM8995_WSEQ_DATA_START99_MASK 0x000F /* WSEQ_DATA_START99 - [3:0] */ +#define WM8995_WSEQ_DATA_START99_SHIFT 0 /* WSEQ_DATA_START99 - [3:0] */ +#define WM8995_WSEQ_DATA_START99_WIDTH 4 /* WSEQ_DATA_START99 - [3:0] */ + +/* + * R12687 (0x318F) - Write Sequencer 399 + */ +#define WM8995_WSEQ_EOS99 0x0100 /* WSEQ_EOS99 */ +#define WM8995_WSEQ_EOS99_MASK 0x0100 /* WSEQ_EOS99 */ +#define WM8995_WSEQ_EOS99_SHIFT 8 /* WSEQ_EOS99 */ +#define WM8995_WSEQ_EOS99_WIDTH 1 /* WSEQ_EOS99 */ +#define WM8995_WSEQ_DELAY99_MASK 0x000F /* WSEQ_DELAY99 - [3:0] */ +#define WM8995_WSEQ_DELAY99_SHIFT 0 /* WSEQ_DELAY99 - [3:0] */ +#define WM8995_WSEQ_DELAY99_WIDTH 4 /* WSEQ_DELAY99 - [3:0] */ + +/* + * R12688 (0x3190) - Write Sequencer 400 + */ +#define WM8995_WSEQ_ADDR100_MASK 0x3FFF /* WSEQ_ADDR100 - [13:0] */ +#define WM8995_WSEQ_ADDR100_SHIFT 0 /* WSEQ_ADDR100 - [13:0] */ +#define WM8995_WSEQ_ADDR100_WIDTH 14 /* WSEQ_ADDR100 - [13:0] */ + +/* + * R12689 (0x3191) - Write Sequencer 401 + */ +#define WM8995_WSEQ_DATA100_MASK 0x00FF /* WSEQ_DATA100 - [7:0] */ +#define WM8995_WSEQ_DATA100_SHIFT 0 /* WSEQ_DATA100 - [7:0] */ +#define WM8995_WSEQ_DATA100_WIDTH 8 /* WSEQ_DATA100 - [7:0] */ + +/* + * R12690 (0x3192) - Write Sequencer 402 + */ +#define WM8995_WSEQ_DATA_WIDTH100_MASK 0x0700 /* WSEQ_DATA_WIDTH100 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH100_SHIFT 8 /* WSEQ_DATA_WIDTH100 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH100_WIDTH 3 /* WSEQ_DATA_WIDTH100 - [10:8] */ +#define WM8995_WSEQ_DATA_START100_MASK 0x000F /* WSEQ_DATA_START100 - [3:0] */ +#define WM8995_WSEQ_DATA_START100_SHIFT 0 /* WSEQ_DATA_START100 - [3:0] */ +#define WM8995_WSEQ_DATA_START100_WIDTH 4 /* WSEQ_DATA_START100 - [3:0] */ + +/* + * R12691 (0x3193) - Write Sequencer 403 + */ +#define WM8995_WSEQ_EOS100 0x0100 /* WSEQ_EOS100 */ +#define WM8995_WSEQ_EOS100_MASK 0x0100 /* WSEQ_EOS100 */ +#define WM8995_WSEQ_EOS100_SHIFT 8 /* WSEQ_EOS100 */ +#define WM8995_WSEQ_EOS100_WIDTH 1 /* WSEQ_EOS100 */ +#define WM8995_WSEQ_DELAY100_MASK 0x000F /* WSEQ_DELAY100 - [3:0] */ +#define WM8995_WSEQ_DELAY100_SHIFT 0 /* WSEQ_DELAY100 - [3:0] */ +#define WM8995_WSEQ_DELAY100_WIDTH 4 /* WSEQ_DELAY100 - [3:0] */ + +/* + * R12692 (0x3194) - Write Sequencer 404 + */ +#define WM8995_WSEQ_ADDR101_MASK 0x3FFF /* WSEQ_ADDR101 - [13:0] */ +#define WM8995_WSEQ_ADDR101_SHIFT 0 /* WSEQ_ADDR101 - [13:0] */ +#define WM8995_WSEQ_ADDR101_WIDTH 14 /* WSEQ_ADDR101 - [13:0] */ + +/* + * R12693 (0x3195) - Write Sequencer 405 + */ +#define WM8995_WSEQ_DATA101_MASK 0x00FF /* WSEQ_DATA101 - [7:0] */ +#define WM8995_WSEQ_DATA101_SHIFT 0 /* WSEQ_DATA101 - [7:0] */ +#define WM8995_WSEQ_DATA101_WIDTH 8 /* WSEQ_DATA101 - [7:0] */ + +/* + * R12694 (0x3196) - Write Sequencer 406 + */ +#define WM8995_WSEQ_DATA_WIDTH101_MASK 0x0700 /* WSEQ_DATA_WIDTH101 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH101_SHIFT 8 /* WSEQ_DATA_WIDTH101 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH101_WIDTH 3 /* WSEQ_DATA_WIDTH101 - [10:8] */ +#define WM8995_WSEQ_DATA_START101_MASK 0x000F /* WSEQ_DATA_START101 - [3:0] */ +#define WM8995_WSEQ_DATA_START101_SHIFT 0 /* WSEQ_DATA_START101 - [3:0] */ +#define WM8995_WSEQ_DATA_START101_WIDTH 4 /* WSEQ_DATA_START101 - [3:0] */ + +/* + * R12695 (0x3197) - Write Sequencer 407 + */ +#define WM8995_WSEQ_EOS101 0x0100 /* WSEQ_EOS101 */ +#define WM8995_WSEQ_EOS101_MASK 0x0100 /* WSEQ_EOS101 */ +#define WM8995_WSEQ_EOS101_SHIFT 8 /* WSEQ_EOS101 */ +#define WM8995_WSEQ_EOS101_WIDTH 1 /* WSEQ_EOS101 */ +#define WM8995_WSEQ_DELAY101_MASK 0x000F /* WSEQ_DELAY101 - [3:0] */ +#define WM8995_WSEQ_DELAY101_SHIFT 0 /* WSEQ_DELAY101 - [3:0] */ +#define WM8995_WSEQ_DELAY101_WIDTH 4 /* WSEQ_DELAY101 - [3:0] */ + +/* + * R12696 (0x3198) - Write Sequencer 408 + */ +#define WM8995_WSEQ_ADDR102_MASK 0x3FFF /* WSEQ_ADDR102 - [13:0] */ +#define WM8995_WSEQ_ADDR102_SHIFT 0 /* WSEQ_ADDR102 - [13:0] */ +#define WM8995_WSEQ_ADDR102_WIDTH 14 /* WSEQ_ADDR102 - [13:0] */ + +/* + * R12697 (0x3199) - Write Sequencer 409 + */ +#define WM8995_WSEQ_DATA102_MASK 0x00FF /* WSEQ_DATA102 - [7:0] */ +#define WM8995_WSEQ_DATA102_SHIFT 0 /* WSEQ_DATA102 - [7:0] */ +#define WM8995_WSEQ_DATA102_WIDTH 8 /* WSEQ_DATA102 - [7:0] */ + +/* + * R12698 (0x319A) - Write Sequencer 410 + */ +#define WM8995_WSEQ_DATA_WIDTH102_MASK 0x0700 /* WSEQ_DATA_WIDTH102 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH102_SHIFT 8 /* WSEQ_DATA_WIDTH102 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH102_WIDTH 3 /* WSEQ_DATA_WIDTH102 - [10:8] */ +#define WM8995_WSEQ_DATA_START102_MASK 0x000F /* WSEQ_DATA_START102 - [3:0] */ +#define WM8995_WSEQ_DATA_START102_SHIFT 0 /* WSEQ_DATA_START102 - [3:0] */ +#define WM8995_WSEQ_DATA_START102_WIDTH 4 /* WSEQ_DATA_START102 - [3:0] */ + +/* + * R12699 (0x319B) - Write Sequencer 411 + */ +#define WM8995_WSEQ_EOS102 0x0100 /* WSEQ_EOS102 */ +#define WM8995_WSEQ_EOS102_MASK 0x0100 /* WSEQ_EOS102 */ +#define WM8995_WSEQ_EOS102_SHIFT 8 /* WSEQ_EOS102 */ +#define WM8995_WSEQ_EOS102_WIDTH 1 /* WSEQ_EOS102 */ +#define WM8995_WSEQ_DELAY102_MASK 0x000F /* WSEQ_DELAY102 - [3:0] */ +#define WM8995_WSEQ_DELAY102_SHIFT 0 /* WSEQ_DELAY102 - [3:0] */ +#define WM8995_WSEQ_DELAY102_WIDTH 4 /* WSEQ_DELAY102 - [3:0] */ + +/* + * R12700 (0x319C) - Write Sequencer 412 + */ +#define WM8995_WSEQ_ADDR103_MASK 0x3FFF /* WSEQ_ADDR103 - [13:0] */ +#define WM8995_WSEQ_ADDR103_SHIFT 0 /* WSEQ_ADDR103 - [13:0] */ +#define WM8995_WSEQ_ADDR103_WIDTH 14 /* WSEQ_ADDR103 - [13:0] */ + +/* + * R12701 (0x319D) - Write Sequencer 413 + */ +#define WM8995_WSEQ_DATA103_MASK 0x00FF /* WSEQ_DATA103 - [7:0] */ +#define WM8995_WSEQ_DATA103_SHIFT 0 /* WSEQ_DATA103 - [7:0] */ +#define WM8995_WSEQ_DATA103_WIDTH 8 /* WSEQ_DATA103 - [7:0] */ + +/* + * R12702 (0x319E) - Write Sequencer 414 + */ +#define WM8995_WSEQ_DATA_WIDTH103_MASK 0x0700 /* WSEQ_DATA_WIDTH103 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH103_SHIFT 8 /* WSEQ_DATA_WIDTH103 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH103_WIDTH 3 /* WSEQ_DATA_WIDTH103 - [10:8] */ +#define WM8995_WSEQ_DATA_START103_MASK 0x000F /* WSEQ_DATA_START103 - [3:0] */ +#define WM8995_WSEQ_DATA_START103_SHIFT 0 /* WSEQ_DATA_START103 - [3:0] */ +#define WM8995_WSEQ_DATA_START103_WIDTH 4 /* WSEQ_DATA_START103 - [3:0] */ + +/* + * R12703 (0x319F) - Write Sequencer 415 + */ +#define WM8995_WSEQ_EOS103 0x0100 /* WSEQ_EOS103 */ +#define WM8995_WSEQ_EOS103_MASK 0x0100 /* WSEQ_EOS103 */ +#define WM8995_WSEQ_EOS103_SHIFT 8 /* WSEQ_EOS103 */ +#define WM8995_WSEQ_EOS103_WIDTH 1 /* WSEQ_EOS103 */ +#define WM8995_WSEQ_DELAY103_MASK 0x000F /* WSEQ_DELAY103 - [3:0] */ +#define WM8995_WSEQ_DELAY103_SHIFT 0 /* WSEQ_DELAY103 - [3:0] */ +#define WM8995_WSEQ_DELAY103_WIDTH 4 /* WSEQ_DELAY103 - [3:0] */ + +/* + * R12704 (0x31A0) - Write Sequencer 416 + */ +#define WM8995_WSEQ_ADDR104_MASK 0x3FFF /* WSEQ_ADDR104 - [13:0] */ +#define WM8995_WSEQ_ADDR104_SHIFT 0 /* WSEQ_ADDR104 - [13:0] */ +#define WM8995_WSEQ_ADDR104_WIDTH 14 /* WSEQ_ADDR104 - [13:0] */ + +/* + * R12705 (0x31A1) - Write Sequencer 417 + */ +#define WM8995_WSEQ_DATA104_MASK 0x00FF /* WSEQ_DATA104 - [7:0] */ +#define WM8995_WSEQ_DATA104_SHIFT 0 /* WSEQ_DATA104 - [7:0] */ +#define WM8995_WSEQ_DATA104_WIDTH 8 /* WSEQ_DATA104 - [7:0] */ + +/* + * R12706 (0x31A2) - Write Sequencer 418 + */ +#define WM8995_WSEQ_DATA_WIDTH104_MASK 0x0700 /* WSEQ_DATA_WIDTH104 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH104_SHIFT 8 /* WSEQ_DATA_WIDTH104 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH104_WIDTH 3 /* WSEQ_DATA_WIDTH104 - [10:8] */ +#define WM8995_WSEQ_DATA_START104_MASK 0x000F /* WSEQ_DATA_START104 - [3:0] */ +#define WM8995_WSEQ_DATA_START104_SHIFT 0 /* WSEQ_DATA_START104 - [3:0] */ +#define WM8995_WSEQ_DATA_START104_WIDTH 4 /* WSEQ_DATA_START104 - [3:0] */ + +/* + * R12707 (0x31A3) - Write Sequencer 419 + */ +#define WM8995_WSEQ_EOS104 0x0100 /* WSEQ_EOS104 */ +#define WM8995_WSEQ_EOS104_MASK 0x0100 /* WSEQ_EOS104 */ +#define WM8995_WSEQ_EOS104_SHIFT 8 /* WSEQ_EOS104 */ +#define WM8995_WSEQ_EOS104_WIDTH 1 /* WSEQ_EOS104 */ +#define WM8995_WSEQ_DELAY104_MASK 0x000F /* WSEQ_DELAY104 - [3:0] */ +#define WM8995_WSEQ_DELAY104_SHIFT 0 /* WSEQ_DELAY104 - [3:0] */ +#define WM8995_WSEQ_DELAY104_WIDTH 4 /* WSEQ_DELAY104 - [3:0] */ + +/* + * R12708 (0x31A4) - Write Sequencer 420 + */ +#define WM8995_WSEQ_ADDR105_MASK 0x3FFF /* WSEQ_ADDR105 - [13:0] */ +#define WM8995_WSEQ_ADDR105_SHIFT 0 /* WSEQ_ADDR105 - [13:0] */ +#define WM8995_WSEQ_ADDR105_WIDTH 14 /* WSEQ_ADDR105 - [13:0] */ + +/* + * R12709 (0x31A5) - Write Sequencer 421 + */ +#define WM8995_WSEQ_DATA105_MASK 0x00FF /* WSEQ_DATA105 - [7:0] */ +#define WM8995_WSEQ_DATA105_SHIFT 0 /* WSEQ_DATA105 - [7:0] */ +#define WM8995_WSEQ_DATA105_WIDTH 8 /* WSEQ_DATA105 - [7:0] */ + +/* + * R12710 (0x31A6) - Write Sequencer 422 + */ +#define WM8995_WSEQ_DATA_WIDTH105_MASK 0x0700 /* WSEQ_DATA_WIDTH105 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH105_SHIFT 8 /* WSEQ_DATA_WIDTH105 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH105_WIDTH 3 /* WSEQ_DATA_WIDTH105 - [10:8] */ +#define WM8995_WSEQ_DATA_START105_MASK 0x000F /* WSEQ_DATA_START105 - [3:0] */ +#define WM8995_WSEQ_DATA_START105_SHIFT 0 /* WSEQ_DATA_START105 - [3:0] */ +#define WM8995_WSEQ_DATA_START105_WIDTH 4 /* WSEQ_DATA_START105 - [3:0] */ + +/* + * R12711 (0x31A7) - Write Sequencer 423 + */ +#define WM8995_WSEQ_EOS105 0x0100 /* WSEQ_EOS105 */ +#define WM8995_WSEQ_EOS105_MASK 0x0100 /* WSEQ_EOS105 */ +#define WM8995_WSEQ_EOS105_SHIFT 8 /* WSEQ_EOS105 */ +#define WM8995_WSEQ_EOS105_WIDTH 1 /* WSEQ_EOS105 */ +#define WM8995_WSEQ_DELAY105_MASK 0x000F /* WSEQ_DELAY105 - [3:0] */ +#define WM8995_WSEQ_DELAY105_SHIFT 0 /* WSEQ_DELAY105 - [3:0] */ +#define WM8995_WSEQ_DELAY105_WIDTH 4 /* WSEQ_DELAY105 - [3:0] */ + +/* + * R12712 (0x31A8) - Write Sequencer 424 + */ +#define WM8995_WSEQ_ADDR106_MASK 0x3FFF /* WSEQ_ADDR106 - [13:0] */ +#define WM8995_WSEQ_ADDR106_SHIFT 0 /* WSEQ_ADDR106 - [13:0] */ +#define WM8995_WSEQ_ADDR106_WIDTH 14 /* WSEQ_ADDR106 - [13:0] */ + +/* + * R12713 (0x31A9) - Write Sequencer 425 + */ +#define WM8995_WSEQ_DATA106_MASK 0x00FF /* WSEQ_DATA106 - [7:0] */ +#define WM8995_WSEQ_DATA106_SHIFT 0 /* WSEQ_DATA106 - [7:0] */ +#define WM8995_WSEQ_DATA106_WIDTH 8 /* WSEQ_DATA106 - [7:0] */ + +/* + * R12714 (0x31AA) - Write Sequencer 426 + */ +#define WM8995_WSEQ_DATA_WIDTH106_MASK 0x0700 /* WSEQ_DATA_WIDTH106 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH106_SHIFT 8 /* WSEQ_DATA_WIDTH106 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH106_WIDTH 3 /* WSEQ_DATA_WIDTH106 - [10:8] */ +#define WM8995_WSEQ_DATA_START106_MASK 0x000F /* WSEQ_DATA_START106 - [3:0] */ +#define WM8995_WSEQ_DATA_START106_SHIFT 0 /* WSEQ_DATA_START106 - [3:0] */ +#define WM8995_WSEQ_DATA_START106_WIDTH 4 /* WSEQ_DATA_START106 - [3:0] */ + +/* + * R12715 (0x31AB) - Write Sequencer 427 + */ +#define WM8995_WSEQ_EOS106 0x0100 /* WSEQ_EOS106 */ +#define WM8995_WSEQ_EOS106_MASK 0x0100 /* WSEQ_EOS106 */ +#define WM8995_WSEQ_EOS106_SHIFT 8 /* WSEQ_EOS106 */ +#define WM8995_WSEQ_EOS106_WIDTH 1 /* WSEQ_EOS106 */ +#define WM8995_WSEQ_DELAY106_MASK 0x000F /* WSEQ_DELAY106 - [3:0] */ +#define WM8995_WSEQ_DELAY106_SHIFT 0 /* WSEQ_DELAY106 - [3:0] */ +#define WM8995_WSEQ_DELAY106_WIDTH 4 /* WSEQ_DELAY106 - [3:0] */ + +/* + * R12716 (0x31AC) - Write Sequencer 428 + */ +#define WM8995_WSEQ_ADDR107_MASK 0x3FFF /* WSEQ_ADDR107 - [13:0] */ +#define WM8995_WSEQ_ADDR107_SHIFT 0 /* WSEQ_ADDR107 - [13:0] */ +#define WM8995_WSEQ_ADDR107_WIDTH 14 /* WSEQ_ADDR107 - [13:0] */ + +/* + * R12717 (0x31AD) - Write Sequencer 429 + */ +#define WM8995_WSEQ_DATA107_MASK 0x00FF /* WSEQ_DATA107 - [7:0] */ +#define WM8995_WSEQ_DATA107_SHIFT 0 /* WSEQ_DATA107 - [7:0] */ +#define WM8995_WSEQ_DATA107_WIDTH 8 /* WSEQ_DATA107 - [7:0] */ + +/* + * R12718 (0x31AE) - Write Sequencer 430 + */ +#define WM8995_WSEQ_DATA_WIDTH107_MASK 0x0700 /* WSEQ_DATA_WIDTH107 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH107_SHIFT 8 /* WSEQ_DATA_WIDTH107 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH107_WIDTH 3 /* WSEQ_DATA_WIDTH107 - [10:8] */ +#define WM8995_WSEQ_DATA_START107_MASK 0x000F /* WSEQ_DATA_START107 - [3:0] */ +#define WM8995_WSEQ_DATA_START107_SHIFT 0 /* WSEQ_DATA_START107 - [3:0] */ +#define WM8995_WSEQ_DATA_START107_WIDTH 4 /* WSEQ_DATA_START107 - [3:0] */ + +/* + * R12719 (0x31AF) - Write Sequencer 431 + */ +#define WM8995_WSEQ_EOS107 0x0100 /* WSEQ_EOS107 */ +#define WM8995_WSEQ_EOS107_MASK 0x0100 /* WSEQ_EOS107 */ +#define WM8995_WSEQ_EOS107_SHIFT 8 /* WSEQ_EOS107 */ +#define WM8995_WSEQ_EOS107_WIDTH 1 /* WSEQ_EOS107 */ +#define WM8995_WSEQ_DELAY107_MASK 0x000F /* WSEQ_DELAY107 - [3:0] */ +#define WM8995_WSEQ_DELAY107_SHIFT 0 /* WSEQ_DELAY107 - [3:0] */ +#define WM8995_WSEQ_DELAY107_WIDTH 4 /* WSEQ_DELAY107 - [3:0] */ + +/* + * R12720 (0x31B0) - Write Sequencer 432 + */ +#define WM8995_WSEQ_ADDR108_MASK 0x3FFF /* WSEQ_ADDR108 - [13:0] */ +#define WM8995_WSEQ_ADDR108_SHIFT 0 /* WSEQ_ADDR108 - [13:0] */ +#define WM8995_WSEQ_ADDR108_WIDTH 14 /* WSEQ_ADDR108 - [13:0] */ + +/* + * R12721 (0x31B1) - Write Sequencer 433 + */ +#define WM8995_WSEQ_DATA108_MASK 0x00FF /* WSEQ_DATA108 - [7:0] */ +#define WM8995_WSEQ_DATA108_SHIFT 0 /* WSEQ_DATA108 - [7:0] */ +#define WM8995_WSEQ_DATA108_WIDTH 8 /* WSEQ_DATA108 - [7:0] */ + +/* + * R12722 (0x31B2) - Write Sequencer 434 + */ +#define WM8995_WSEQ_DATA_WIDTH108_MASK 0x0700 /* WSEQ_DATA_WIDTH108 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH108_SHIFT 8 /* WSEQ_DATA_WIDTH108 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH108_WIDTH 3 /* WSEQ_DATA_WIDTH108 - [10:8] */ +#define WM8995_WSEQ_DATA_START108_MASK 0x000F /* WSEQ_DATA_START108 - [3:0] */ +#define WM8995_WSEQ_DATA_START108_SHIFT 0 /* WSEQ_DATA_START108 - [3:0] */ +#define WM8995_WSEQ_DATA_START108_WIDTH 4 /* WSEQ_DATA_START108 - [3:0] */ + +/* + * R12723 (0x31B3) - Write Sequencer 435 + */ +#define WM8995_WSEQ_EOS108 0x0100 /* WSEQ_EOS108 */ +#define WM8995_WSEQ_EOS108_MASK 0x0100 /* WSEQ_EOS108 */ +#define WM8995_WSEQ_EOS108_SHIFT 8 /* WSEQ_EOS108 */ +#define WM8995_WSEQ_EOS108_WIDTH 1 /* WSEQ_EOS108 */ +#define WM8995_WSEQ_DELAY108_MASK 0x000F /* WSEQ_DELAY108 - [3:0] */ +#define WM8995_WSEQ_DELAY108_SHIFT 0 /* WSEQ_DELAY108 - [3:0] */ +#define WM8995_WSEQ_DELAY108_WIDTH 4 /* WSEQ_DELAY108 - [3:0] */ + +/* + * R12724 (0x31B4) - Write Sequencer 436 + */ +#define WM8995_WSEQ_ADDR109_MASK 0x3FFF /* WSEQ_ADDR109 - [13:0] */ +#define WM8995_WSEQ_ADDR109_SHIFT 0 /* WSEQ_ADDR109 - [13:0] */ +#define WM8995_WSEQ_ADDR109_WIDTH 14 /* WSEQ_ADDR109 - [13:0] */ + +/* + * R12725 (0x31B5) - Write Sequencer 437 + */ +#define WM8995_WSEQ_DATA109_MASK 0x00FF /* WSEQ_DATA109 - [7:0] */ +#define WM8995_WSEQ_DATA109_SHIFT 0 /* WSEQ_DATA109 - [7:0] */ +#define WM8995_WSEQ_DATA109_WIDTH 8 /* WSEQ_DATA109 - [7:0] */ + +/* + * R12726 (0x31B6) - Write Sequencer 438 + */ +#define WM8995_WSEQ_DATA_WIDTH109_MASK 0x0700 /* WSEQ_DATA_WIDTH109 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH109_SHIFT 8 /* WSEQ_DATA_WIDTH109 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH109_WIDTH 3 /* WSEQ_DATA_WIDTH109 - [10:8] */ +#define WM8995_WSEQ_DATA_START109_MASK 0x000F /* WSEQ_DATA_START109 - [3:0] */ +#define WM8995_WSEQ_DATA_START109_SHIFT 0 /* WSEQ_DATA_START109 - [3:0] */ +#define WM8995_WSEQ_DATA_START109_WIDTH 4 /* WSEQ_DATA_START109 - [3:0] */ + +/* + * R12727 (0x31B7) - Write Sequencer 439 + */ +#define WM8995_WSEQ_EOS109 0x0100 /* WSEQ_EOS109 */ +#define WM8995_WSEQ_EOS109_MASK 0x0100 /* WSEQ_EOS109 */ +#define WM8995_WSEQ_EOS109_SHIFT 8 /* WSEQ_EOS109 */ +#define WM8995_WSEQ_EOS109_WIDTH 1 /* WSEQ_EOS109 */ +#define WM8995_WSEQ_DELAY109_MASK 0x000F /* WSEQ_DELAY109 - [3:0] */ +#define WM8995_WSEQ_DELAY109_SHIFT 0 /* WSEQ_DELAY109 - [3:0] */ +#define WM8995_WSEQ_DELAY109_WIDTH 4 /* WSEQ_DELAY109 - [3:0] */ + +/* + * R12728 (0x31B8) - Write Sequencer 440 + */ +#define WM8995_WSEQ_ADDR110_MASK 0x3FFF /* WSEQ_ADDR110 - [13:0] */ +#define WM8995_WSEQ_ADDR110_SHIFT 0 /* WSEQ_ADDR110 - [13:0] */ +#define WM8995_WSEQ_ADDR110_WIDTH 14 /* WSEQ_ADDR110 - [13:0] */ + +/* + * R12729 (0x31B9) - Write Sequencer 441 + */ +#define WM8995_WSEQ_DATA110_MASK 0x00FF /* WSEQ_DATA110 - [7:0] */ +#define WM8995_WSEQ_DATA110_SHIFT 0 /* WSEQ_DATA110 - [7:0] */ +#define WM8995_WSEQ_DATA110_WIDTH 8 /* WSEQ_DATA110 - [7:0] */ + +/* + * R12730 (0x31BA) - Write Sequencer 442 + */ +#define WM8995_WSEQ_DATA_WIDTH110_MASK 0x0700 /* WSEQ_DATA_WIDTH110 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH110_SHIFT 8 /* WSEQ_DATA_WIDTH110 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH110_WIDTH 3 /* WSEQ_DATA_WIDTH110 - [10:8] */ +#define WM8995_WSEQ_DATA_START110_MASK 0x000F /* WSEQ_DATA_START110 - [3:0] */ +#define WM8995_WSEQ_DATA_START110_SHIFT 0 /* WSEQ_DATA_START110 - [3:0] */ +#define WM8995_WSEQ_DATA_START110_WIDTH 4 /* WSEQ_DATA_START110 - [3:0] */ + +/* + * R12731 (0x31BB) - Write Sequencer 443 + */ +#define WM8995_WSEQ_EOS110 0x0100 /* WSEQ_EOS110 */ +#define WM8995_WSEQ_EOS110_MASK 0x0100 /* WSEQ_EOS110 */ +#define WM8995_WSEQ_EOS110_SHIFT 8 /* WSEQ_EOS110 */ +#define WM8995_WSEQ_EOS110_WIDTH 1 /* WSEQ_EOS110 */ +#define WM8995_WSEQ_DELAY110_MASK 0x000F /* WSEQ_DELAY110 - [3:0] */ +#define WM8995_WSEQ_DELAY110_SHIFT 0 /* WSEQ_DELAY110 - [3:0] */ +#define WM8995_WSEQ_DELAY110_WIDTH 4 /* WSEQ_DELAY110 - [3:0] */ + +/* + * R12732 (0x31BC) - Write Sequencer 444 + */ +#define WM8995_WSEQ_ADDR111_MASK 0x3FFF /* WSEQ_ADDR111 - [13:0] */ +#define WM8995_WSEQ_ADDR111_SHIFT 0 /* WSEQ_ADDR111 - [13:0] */ +#define WM8995_WSEQ_ADDR111_WIDTH 14 /* WSEQ_ADDR111 - [13:0] */ + +/* + * R12733 (0x31BD) - Write Sequencer 445 + */ +#define WM8995_WSEQ_DATA111_MASK 0x00FF /* WSEQ_DATA111 - [7:0] */ +#define WM8995_WSEQ_DATA111_SHIFT 0 /* WSEQ_DATA111 - [7:0] */ +#define WM8995_WSEQ_DATA111_WIDTH 8 /* WSEQ_DATA111 - [7:0] */ + +/* + * R12734 (0x31BE) - Write Sequencer 446 + */ +#define WM8995_WSEQ_DATA_WIDTH111_MASK 0x0700 /* WSEQ_DATA_WIDTH111 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH111_SHIFT 8 /* WSEQ_DATA_WIDTH111 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH111_WIDTH 3 /* WSEQ_DATA_WIDTH111 - [10:8] */ +#define WM8995_WSEQ_DATA_START111_MASK 0x000F /* WSEQ_DATA_START111 - [3:0] */ +#define WM8995_WSEQ_DATA_START111_SHIFT 0 /* WSEQ_DATA_START111 - [3:0] */ +#define WM8995_WSEQ_DATA_START111_WIDTH 4 /* WSEQ_DATA_START111 - [3:0] */ + +/* + * R12735 (0x31BF) - Write Sequencer 447 + */ +#define WM8995_WSEQ_EOS111 0x0100 /* WSEQ_EOS111 */ +#define WM8995_WSEQ_EOS111_MASK 0x0100 /* WSEQ_EOS111 */ +#define WM8995_WSEQ_EOS111_SHIFT 8 /* WSEQ_EOS111 */ +#define WM8995_WSEQ_EOS111_WIDTH 1 /* WSEQ_EOS111 */ +#define WM8995_WSEQ_DELAY111_MASK 0x000F /* WSEQ_DELAY111 - [3:0] */ +#define WM8995_WSEQ_DELAY111_SHIFT 0 /* WSEQ_DELAY111 - [3:0] */ +#define WM8995_WSEQ_DELAY111_WIDTH 4 /* WSEQ_DELAY111 - [3:0] */ + +/* + * R12736 (0x31C0) - Write Sequencer 448 + */ +#define WM8995_WSEQ_ADDR112_MASK 0x3FFF /* WSEQ_ADDR112 - [13:0] */ +#define WM8995_WSEQ_ADDR112_SHIFT 0 /* WSEQ_ADDR112 - [13:0] */ +#define WM8995_WSEQ_ADDR112_WIDTH 14 /* WSEQ_ADDR112 - [13:0] */ + +/* + * R12737 (0x31C1) - Write Sequencer 449 + */ +#define WM8995_WSEQ_DATA112_MASK 0x00FF /* WSEQ_DATA112 - [7:0] */ +#define WM8995_WSEQ_DATA112_SHIFT 0 /* WSEQ_DATA112 - [7:0] */ +#define WM8995_WSEQ_DATA112_WIDTH 8 /* WSEQ_DATA112 - [7:0] */ + +/* + * R12738 (0x31C2) - Write Sequencer 450 + */ +#define WM8995_WSEQ_DATA_WIDTH112_MASK 0x0700 /* WSEQ_DATA_WIDTH112 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH112_SHIFT 8 /* WSEQ_DATA_WIDTH112 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH112_WIDTH 3 /* WSEQ_DATA_WIDTH112 - [10:8] */ +#define WM8995_WSEQ_DATA_START112_MASK 0x000F /* WSEQ_DATA_START112 - [3:0] */ +#define WM8995_WSEQ_DATA_START112_SHIFT 0 /* WSEQ_DATA_START112 - [3:0] */ +#define WM8995_WSEQ_DATA_START112_WIDTH 4 /* WSEQ_DATA_START112 - [3:0] */ + +/* + * R12739 (0x31C3) - Write Sequencer 451 + */ +#define WM8995_WSEQ_EOS112 0x0100 /* WSEQ_EOS112 */ +#define WM8995_WSEQ_EOS112_MASK 0x0100 /* WSEQ_EOS112 */ +#define WM8995_WSEQ_EOS112_SHIFT 8 /* WSEQ_EOS112 */ +#define WM8995_WSEQ_EOS112_WIDTH 1 /* WSEQ_EOS112 */ +#define WM8995_WSEQ_DELAY112_MASK 0x000F /* WSEQ_DELAY112 - [3:0] */ +#define WM8995_WSEQ_DELAY112_SHIFT 0 /* WSEQ_DELAY112 - [3:0] */ +#define WM8995_WSEQ_DELAY112_WIDTH 4 /* WSEQ_DELAY112 - [3:0] */ + +/* + * R12740 (0x31C4) - Write Sequencer 452 + */ +#define WM8995_WSEQ_ADDR113_MASK 0x3FFF /* WSEQ_ADDR113 - [13:0] */ +#define WM8995_WSEQ_ADDR113_SHIFT 0 /* WSEQ_ADDR113 - [13:0] */ +#define WM8995_WSEQ_ADDR113_WIDTH 14 /* WSEQ_ADDR113 - [13:0] */ + +/* + * R12741 (0x31C5) - Write Sequencer 453 + */ +#define WM8995_WSEQ_DATA113_MASK 0x00FF /* WSEQ_DATA113 - [7:0] */ +#define WM8995_WSEQ_DATA113_SHIFT 0 /* WSEQ_DATA113 - [7:0] */ +#define WM8995_WSEQ_DATA113_WIDTH 8 /* WSEQ_DATA113 - [7:0] */ + +/* + * R12742 (0x31C6) - Write Sequencer 454 + */ +#define WM8995_WSEQ_DATA_WIDTH113_MASK 0x0700 /* WSEQ_DATA_WIDTH113 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH113_SHIFT 8 /* WSEQ_DATA_WIDTH113 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH113_WIDTH 3 /* WSEQ_DATA_WIDTH113 - [10:8] */ +#define WM8995_WSEQ_DATA_START113_MASK 0x000F /* WSEQ_DATA_START113 - [3:0] */ +#define WM8995_WSEQ_DATA_START113_SHIFT 0 /* WSEQ_DATA_START113 - [3:0] */ +#define WM8995_WSEQ_DATA_START113_WIDTH 4 /* WSEQ_DATA_START113 - [3:0] */ + +/* + * R12743 (0x31C7) - Write Sequencer 455 + */ +#define WM8995_WSEQ_EOS113 0x0100 /* WSEQ_EOS113 */ +#define WM8995_WSEQ_EOS113_MASK 0x0100 /* WSEQ_EOS113 */ +#define WM8995_WSEQ_EOS113_SHIFT 8 /* WSEQ_EOS113 */ +#define WM8995_WSEQ_EOS113_WIDTH 1 /* WSEQ_EOS113 */ +#define WM8995_WSEQ_DELAY113_MASK 0x000F /* WSEQ_DELAY113 - [3:0] */ +#define WM8995_WSEQ_DELAY113_SHIFT 0 /* WSEQ_DELAY113 - [3:0] */ +#define WM8995_WSEQ_DELAY113_WIDTH 4 /* WSEQ_DELAY113 - [3:0] */ + +/* + * R12744 (0x31C8) - Write Sequencer 456 + */ +#define WM8995_WSEQ_ADDR114_MASK 0x3FFF /* WSEQ_ADDR114 - [13:0] */ +#define WM8995_WSEQ_ADDR114_SHIFT 0 /* WSEQ_ADDR114 - [13:0] */ +#define WM8995_WSEQ_ADDR114_WIDTH 14 /* WSEQ_ADDR114 - [13:0] */ + +/* + * R12745 (0x31C9) - Write Sequencer 457 + */ +#define WM8995_WSEQ_DATA114_MASK 0x00FF /* WSEQ_DATA114 - [7:0] */ +#define WM8995_WSEQ_DATA114_SHIFT 0 /* WSEQ_DATA114 - [7:0] */ +#define WM8995_WSEQ_DATA114_WIDTH 8 /* WSEQ_DATA114 - [7:0] */ + +/* + * R12746 (0x31CA) - Write Sequencer 458 + */ +#define WM8995_WSEQ_DATA_WIDTH114_MASK 0x0700 /* WSEQ_DATA_WIDTH114 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH114_SHIFT 8 /* WSEQ_DATA_WIDTH114 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH114_WIDTH 3 /* WSEQ_DATA_WIDTH114 - [10:8] */ +#define WM8995_WSEQ_DATA_START114_MASK 0x000F /* WSEQ_DATA_START114 - [3:0] */ +#define WM8995_WSEQ_DATA_START114_SHIFT 0 /* WSEQ_DATA_START114 - [3:0] */ +#define WM8995_WSEQ_DATA_START114_WIDTH 4 /* WSEQ_DATA_START114 - [3:0] */ + +/* + * R12747 (0x31CB) - Write Sequencer 459 + */ +#define WM8995_WSEQ_EOS114 0x0100 /* WSEQ_EOS114 */ +#define WM8995_WSEQ_EOS114_MASK 0x0100 /* WSEQ_EOS114 */ +#define WM8995_WSEQ_EOS114_SHIFT 8 /* WSEQ_EOS114 */ +#define WM8995_WSEQ_EOS114_WIDTH 1 /* WSEQ_EOS114 */ +#define WM8995_WSEQ_DELAY114_MASK 0x000F /* WSEQ_DELAY114 - [3:0] */ +#define WM8995_WSEQ_DELAY114_SHIFT 0 /* WSEQ_DELAY114 - [3:0] */ +#define WM8995_WSEQ_DELAY114_WIDTH 4 /* WSEQ_DELAY114 - [3:0] */ + +/* + * R12748 (0x31CC) - Write Sequencer 460 + */ +#define WM8995_WSEQ_ADDR115_MASK 0x3FFF /* WSEQ_ADDR115 - [13:0] */ +#define WM8995_WSEQ_ADDR115_SHIFT 0 /* WSEQ_ADDR115 - [13:0] */ +#define WM8995_WSEQ_ADDR115_WIDTH 14 /* WSEQ_ADDR115 - [13:0] */ + +/* + * R12749 (0x31CD) - Write Sequencer 461 + */ +#define WM8995_WSEQ_DATA115_MASK 0x00FF /* WSEQ_DATA115 - [7:0] */ +#define WM8995_WSEQ_DATA115_SHIFT 0 /* WSEQ_DATA115 - [7:0] */ +#define WM8995_WSEQ_DATA115_WIDTH 8 /* WSEQ_DATA115 - [7:0] */ + +/* + * R12750 (0x31CE) - Write Sequencer 462 + */ +#define WM8995_WSEQ_DATA_WIDTH115_MASK 0x0700 /* WSEQ_DATA_WIDTH115 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH115_SHIFT 8 /* WSEQ_DATA_WIDTH115 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH115_WIDTH 3 /* WSEQ_DATA_WIDTH115 - [10:8] */ +#define WM8995_WSEQ_DATA_START115_MASK 0x000F /* WSEQ_DATA_START115 - [3:0] */ +#define WM8995_WSEQ_DATA_START115_SHIFT 0 /* WSEQ_DATA_START115 - [3:0] */ +#define WM8995_WSEQ_DATA_START115_WIDTH 4 /* WSEQ_DATA_START115 - [3:0] */ + +/* + * R12751 (0x31CF) - Write Sequencer 463 + */ +#define WM8995_WSEQ_EOS115 0x0100 /* WSEQ_EOS115 */ +#define WM8995_WSEQ_EOS115_MASK 0x0100 /* WSEQ_EOS115 */ +#define WM8995_WSEQ_EOS115_SHIFT 8 /* WSEQ_EOS115 */ +#define WM8995_WSEQ_EOS115_WIDTH 1 /* WSEQ_EOS115 */ +#define WM8995_WSEQ_DELAY115_MASK 0x000F /* WSEQ_DELAY115 - [3:0] */ +#define WM8995_WSEQ_DELAY115_SHIFT 0 /* WSEQ_DELAY115 - [3:0] */ +#define WM8995_WSEQ_DELAY115_WIDTH 4 /* WSEQ_DELAY115 - [3:0] */ + +/* + * R12752 (0x31D0) - Write Sequencer 464 + */ +#define WM8995_WSEQ_ADDR116_MASK 0x3FFF /* WSEQ_ADDR116 - [13:0] */ +#define WM8995_WSEQ_ADDR116_SHIFT 0 /* WSEQ_ADDR116 - [13:0] */ +#define WM8995_WSEQ_ADDR116_WIDTH 14 /* WSEQ_ADDR116 - [13:0] */ + +/* + * R12753 (0x31D1) - Write Sequencer 465 + */ +#define WM8995_WSEQ_DATA116_MASK 0x00FF /* WSEQ_DATA116 - [7:0] */ +#define WM8995_WSEQ_DATA116_SHIFT 0 /* WSEQ_DATA116 - [7:0] */ +#define WM8995_WSEQ_DATA116_WIDTH 8 /* WSEQ_DATA116 - [7:0] */ + +/* + * R12754 (0x31D2) - Write Sequencer 466 + */ +#define WM8995_WSEQ_DATA_WIDTH116_MASK 0x0700 /* WSEQ_DATA_WIDTH116 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH116_SHIFT 8 /* WSEQ_DATA_WIDTH116 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH116_WIDTH 3 /* WSEQ_DATA_WIDTH116 - [10:8] */ +#define WM8995_WSEQ_DATA_START116_MASK 0x000F /* WSEQ_DATA_START116 - [3:0] */ +#define WM8995_WSEQ_DATA_START116_SHIFT 0 /* WSEQ_DATA_START116 - [3:0] */ +#define WM8995_WSEQ_DATA_START116_WIDTH 4 /* WSEQ_DATA_START116 - [3:0] */ + +/* + * R12755 (0x31D3) - Write Sequencer 467 + */ +#define WM8995_WSEQ_EOS116 0x0100 /* WSEQ_EOS116 */ +#define WM8995_WSEQ_EOS116_MASK 0x0100 /* WSEQ_EOS116 */ +#define WM8995_WSEQ_EOS116_SHIFT 8 /* WSEQ_EOS116 */ +#define WM8995_WSEQ_EOS116_WIDTH 1 /* WSEQ_EOS116 */ +#define WM8995_WSEQ_DELAY116_MASK 0x000F /* WSEQ_DELAY116 - [3:0] */ +#define WM8995_WSEQ_DELAY116_SHIFT 0 /* WSEQ_DELAY116 - [3:0] */ +#define WM8995_WSEQ_DELAY116_WIDTH 4 /* WSEQ_DELAY116 - [3:0] */ + +/* + * R12756 (0x31D4) - Write Sequencer 468 + */ +#define WM8995_WSEQ_ADDR117_MASK 0x3FFF /* WSEQ_ADDR117 - [13:0] */ +#define WM8995_WSEQ_ADDR117_SHIFT 0 /* WSEQ_ADDR117 - [13:0] */ +#define WM8995_WSEQ_ADDR117_WIDTH 14 /* WSEQ_ADDR117 - [13:0] */ + +/* + * R12757 (0x31D5) - Write Sequencer 469 + */ +#define WM8995_WSEQ_DATA117_MASK 0x00FF /* WSEQ_DATA117 - [7:0] */ +#define WM8995_WSEQ_DATA117_SHIFT 0 /* WSEQ_DATA117 - [7:0] */ +#define WM8995_WSEQ_DATA117_WIDTH 8 /* WSEQ_DATA117 - [7:0] */ + +/* + * R12758 (0x31D6) - Write Sequencer 470 + */ +#define WM8995_WSEQ_DATA_WIDTH117_MASK 0x0700 /* WSEQ_DATA_WIDTH117 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH117_SHIFT 8 /* WSEQ_DATA_WIDTH117 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH117_WIDTH 3 /* WSEQ_DATA_WIDTH117 - [10:8] */ +#define WM8995_WSEQ_DATA_START117_MASK 0x000F /* WSEQ_DATA_START117 - [3:0] */ +#define WM8995_WSEQ_DATA_START117_SHIFT 0 /* WSEQ_DATA_START117 - [3:0] */ +#define WM8995_WSEQ_DATA_START117_WIDTH 4 /* WSEQ_DATA_START117 - [3:0] */ + +/* + * R12759 (0x31D7) - Write Sequencer 471 + */ +#define WM8995_WSEQ_EOS117 0x0100 /* WSEQ_EOS117 */ +#define WM8995_WSEQ_EOS117_MASK 0x0100 /* WSEQ_EOS117 */ +#define WM8995_WSEQ_EOS117_SHIFT 8 /* WSEQ_EOS117 */ +#define WM8995_WSEQ_EOS117_WIDTH 1 /* WSEQ_EOS117 */ +#define WM8995_WSEQ_DELAY117_MASK 0x000F /* WSEQ_DELAY117 - [3:0] */ +#define WM8995_WSEQ_DELAY117_SHIFT 0 /* WSEQ_DELAY117 - [3:0] */ +#define WM8995_WSEQ_DELAY117_WIDTH 4 /* WSEQ_DELAY117 - [3:0] */ + +/* + * R12760 (0x31D8) - Write Sequencer 472 + */ +#define WM8995_WSEQ_ADDR118_MASK 0x3FFF /* WSEQ_ADDR118 - [13:0] */ +#define WM8995_WSEQ_ADDR118_SHIFT 0 /* WSEQ_ADDR118 - [13:0] */ +#define WM8995_WSEQ_ADDR118_WIDTH 14 /* WSEQ_ADDR118 - [13:0] */ + +/* + * R12761 (0x31D9) - Write Sequencer 473 + */ +#define WM8995_WSEQ_DATA118_MASK 0x00FF /* WSEQ_DATA118 - [7:0] */ +#define WM8995_WSEQ_DATA118_SHIFT 0 /* WSEQ_DATA118 - [7:0] */ +#define WM8995_WSEQ_DATA118_WIDTH 8 /* WSEQ_DATA118 - [7:0] */ + +/* + * R12762 (0x31DA) - Write Sequencer 474 + */ +#define WM8995_WSEQ_DATA_WIDTH118_MASK 0x0700 /* WSEQ_DATA_WIDTH118 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH118_SHIFT 8 /* WSEQ_DATA_WIDTH118 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH118_WIDTH 3 /* WSEQ_DATA_WIDTH118 - [10:8] */ +#define WM8995_WSEQ_DATA_START118_MASK 0x000F /* WSEQ_DATA_START118 - [3:0] */ +#define WM8995_WSEQ_DATA_START118_SHIFT 0 /* WSEQ_DATA_START118 - [3:0] */ +#define WM8995_WSEQ_DATA_START118_WIDTH 4 /* WSEQ_DATA_START118 - [3:0] */ + +/* + * R12763 (0x31DB) - Write Sequencer 475 + */ +#define WM8995_WSEQ_EOS118 0x0100 /* WSEQ_EOS118 */ +#define WM8995_WSEQ_EOS118_MASK 0x0100 /* WSEQ_EOS118 */ +#define WM8995_WSEQ_EOS118_SHIFT 8 /* WSEQ_EOS118 */ +#define WM8995_WSEQ_EOS118_WIDTH 1 /* WSEQ_EOS118 */ +#define WM8995_WSEQ_DELAY118_MASK 0x000F /* WSEQ_DELAY118 - [3:0] */ +#define WM8995_WSEQ_DELAY118_SHIFT 0 /* WSEQ_DELAY118 - [3:0] */ +#define WM8995_WSEQ_DELAY118_WIDTH 4 /* WSEQ_DELAY118 - [3:0] */ + +/* + * R12764 (0x31DC) - Write Sequencer 476 + */ +#define WM8995_WSEQ_ADDR119_MASK 0x3FFF /* WSEQ_ADDR119 - [13:0] */ +#define WM8995_WSEQ_ADDR119_SHIFT 0 /* WSEQ_ADDR119 - [13:0] */ +#define WM8995_WSEQ_ADDR119_WIDTH 14 /* WSEQ_ADDR119 - [13:0] */ + +/* + * R12765 (0x31DD) - Write Sequencer 477 + */ +#define WM8995_WSEQ_DATA119_MASK 0x00FF /* WSEQ_DATA119 - [7:0] */ +#define WM8995_WSEQ_DATA119_SHIFT 0 /* WSEQ_DATA119 - [7:0] */ +#define WM8995_WSEQ_DATA119_WIDTH 8 /* WSEQ_DATA119 - [7:0] */ + +/* + * R12766 (0x31DE) - Write Sequencer 478 + */ +#define WM8995_WSEQ_DATA_WIDTH119_MASK 0x0700 /* WSEQ_DATA_WIDTH119 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH119_SHIFT 8 /* WSEQ_DATA_WIDTH119 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH119_WIDTH 3 /* WSEQ_DATA_WIDTH119 - [10:8] */ +#define WM8995_WSEQ_DATA_START119_MASK 0x000F /* WSEQ_DATA_START119 - [3:0] */ +#define WM8995_WSEQ_DATA_START119_SHIFT 0 /* WSEQ_DATA_START119 - [3:0] */ +#define WM8995_WSEQ_DATA_START119_WIDTH 4 /* WSEQ_DATA_START119 - [3:0] */ + +/* + * R12767 (0x31DF) - Write Sequencer 479 + */ +#define WM8995_WSEQ_EOS119 0x0100 /* WSEQ_EOS119 */ +#define WM8995_WSEQ_EOS119_MASK 0x0100 /* WSEQ_EOS119 */ +#define WM8995_WSEQ_EOS119_SHIFT 8 /* WSEQ_EOS119 */ +#define WM8995_WSEQ_EOS119_WIDTH 1 /* WSEQ_EOS119 */ +#define WM8995_WSEQ_DELAY119_MASK 0x000F /* WSEQ_DELAY119 - [3:0] */ +#define WM8995_WSEQ_DELAY119_SHIFT 0 /* WSEQ_DELAY119 - [3:0] */ +#define WM8995_WSEQ_DELAY119_WIDTH 4 /* WSEQ_DELAY119 - [3:0] */ + +/* + * R12768 (0x31E0) - Write Sequencer 480 + */ +#define WM8995_WSEQ_ADDR120_MASK 0x3FFF /* WSEQ_ADDR120 - [13:0] */ +#define WM8995_WSEQ_ADDR120_SHIFT 0 /* WSEQ_ADDR120 - [13:0] */ +#define WM8995_WSEQ_ADDR120_WIDTH 14 /* WSEQ_ADDR120 - [13:0] */ + +/* + * R12769 (0x31E1) - Write Sequencer 481 + */ +#define WM8995_WSEQ_DATA120_MASK 0x00FF /* WSEQ_DATA120 - [7:0] */ +#define WM8995_WSEQ_DATA120_SHIFT 0 /* WSEQ_DATA120 - [7:0] */ +#define WM8995_WSEQ_DATA120_WIDTH 8 /* WSEQ_DATA120 - [7:0] */ + +/* + * R12770 (0x31E2) - Write Sequencer 482 + */ +#define WM8995_WSEQ_DATA_WIDTH120_MASK 0x0700 /* WSEQ_DATA_WIDTH120 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH120_SHIFT 8 /* WSEQ_DATA_WIDTH120 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH120_WIDTH 3 /* WSEQ_DATA_WIDTH120 - [10:8] */ +#define WM8995_WSEQ_DATA_START120_MASK 0x000F /* WSEQ_DATA_START120 - [3:0] */ +#define WM8995_WSEQ_DATA_START120_SHIFT 0 /* WSEQ_DATA_START120 - [3:0] */ +#define WM8995_WSEQ_DATA_START120_WIDTH 4 /* WSEQ_DATA_START120 - [3:0] */ + +/* + * R12771 (0x31E3) - Write Sequencer 483 + */ +#define WM8995_WSEQ_EOS120 0x0100 /* WSEQ_EOS120 */ +#define WM8995_WSEQ_EOS120_MASK 0x0100 /* WSEQ_EOS120 */ +#define WM8995_WSEQ_EOS120_SHIFT 8 /* WSEQ_EOS120 */ +#define WM8995_WSEQ_EOS120_WIDTH 1 /* WSEQ_EOS120 */ +#define WM8995_WSEQ_DELAY120_MASK 0x000F /* WSEQ_DELAY120 - [3:0] */ +#define WM8995_WSEQ_DELAY120_SHIFT 0 /* WSEQ_DELAY120 - [3:0] */ +#define WM8995_WSEQ_DELAY120_WIDTH 4 /* WSEQ_DELAY120 - [3:0] */ + +/* + * R12772 (0x31E4) - Write Sequencer 484 + */ +#define WM8995_WSEQ_ADDR121_MASK 0x3FFF /* WSEQ_ADDR121 - [13:0] */ +#define WM8995_WSEQ_ADDR121_SHIFT 0 /* WSEQ_ADDR121 - [13:0] */ +#define WM8995_WSEQ_ADDR121_WIDTH 14 /* WSEQ_ADDR121 - [13:0] */ + +/* + * R12773 (0x31E5) - Write Sequencer 485 + */ +#define WM8995_WSEQ_DATA121_MASK 0x00FF /* WSEQ_DATA121 - [7:0] */ +#define WM8995_WSEQ_DATA121_SHIFT 0 /* WSEQ_DATA121 - [7:0] */ +#define WM8995_WSEQ_DATA121_WIDTH 8 /* WSEQ_DATA121 - [7:0] */ + +/* + * R12774 (0x31E6) - Write Sequencer 486 + */ +#define WM8995_WSEQ_DATA_WIDTH121_MASK 0x0700 /* WSEQ_DATA_WIDTH121 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH121_SHIFT 8 /* WSEQ_DATA_WIDTH121 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH121_WIDTH 3 /* WSEQ_DATA_WIDTH121 - [10:8] */ +#define WM8995_WSEQ_DATA_START121_MASK 0x000F /* WSEQ_DATA_START121 - [3:0] */ +#define WM8995_WSEQ_DATA_START121_SHIFT 0 /* WSEQ_DATA_START121 - [3:0] */ +#define WM8995_WSEQ_DATA_START121_WIDTH 4 /* WSEQ_DATA_START121 - [3:0] */ + +/* + * R12775 (0x31E7) - Write Sequencer 487 + */ +#define WM8995_WSEQ_EOS121 0x0100 /* WSEQ_EOS121 */ +#define WM8995_WSEQ_EOS121_MASK 0x0100 /* WSEQ_EOS121 */ +#define WM8995_WSEQ_EOS121_SHIFT 8 /* WSEQ_EOS121 */ +#define WM8995_WSEQ_EOS121_WIDTH 1 /* WSEQ_EOS121 */ +#define WM8995_WSEQ_DELAY121_MASK 0x000F /* WSEQ_DELAY121 - [3:0] */ +#define WM8995_WSEQ_DELAY121_SHIFT 0 /* WSEQ_DELAY121 - [3:0] */ +#define WM8995_WSEQ_DELAY121_WIDTH 4 /* WSEQ_DELAY121 - [3:0] */ + +/* + * R12776 (0x31E8) - Write Sequencer 488 + */ +#define WM8995_WSEQ_ADDR122_MASK 0x3FFF /* WSEQ_ADDR122 - [13:0] */ +#define WM8995_WSEQ_ADDR122_SHIFT 0 /* WSEQ_ADDR122 - [13:0] */ +#define WM8995_WSEQ_ADDR122_WIDTH 14 /* WSEQ_ADDR122 - [13:0] */ + +/* + * R12777 (0x31E9) - Write Sequencer 489 + */ +#define WM8995_WSEQ_DATA122_MASK 0x00FF /* WSEQ_DATA122 - [7:0] */ +#define WM8995_WSEQ_DATA122_SHIFT 0 /* WSEQ_DATA122 - [7:0] */ +#define WM8995_WSEQ_DATA122_WIDTH 8 /* WSEQ_DATA122 - [7:0] */ + +/* + * R12778 (0x31EA) - Write Sequencer 490 + */ +#define WM8995_WSEQ_DATA_WIDTH122_MASK 0x0700 /* WSEQ_DATA_WIDTH122 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH122_SHIFT 8 /* WSEQ_DATA_WIDTH122 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH122_WIDTH 3 /* WSEQ_DATA_WIDTH122 - [10:8] */ +#define WM8995_WSEQ_DATA_START122_MASK 0x000F /* WSEQ_DATA_START122 - [3:0] */ +#define WM8995_WSEQ_DATA_START122_SHIFT 0 /* WSEQ_DATA_START122 - [3:0] */ +#define WM8995_WSEQ_DATA_START122_WIDTH 4 /* WSEQ_DATA_START122 - [3:0] */ + +/* + * R12779 (0x31EB) - Write Sequencer 491 + */ +#define WM8995_WSEQ_EOS122 0x0100 /* WSEQ_EOS122 */ +#define WM8995_WSEQ_EOS122_MASK 0x0100 /* WSEQ_EOS122 */ +#define WM8995_WSEQ_EOS122_SHIFT 8 /* WSEQ_EOS122 */ +#define WM8995_WSEQ_EOS122_WIDTH 1 /* WSEQ_EOS122 */ +#define WM8995_WSEQ_DELAY122_MASK 0x000F /* WSEQ_DELAY122 - [3:0] */ +#define WM8995_WSEQ_DELAY122_SHIFT 0 /* WSEQ_DELAY122 - [3:0] */ +#define WM8995_WSEQ_DELAY122_WIDTH 4 /* WSEQ_DELAY122 - [3:0] */ + +/* + * R12780 (0x31EC) - Write Sequencer 492 + */ +#define WM8995_WSEQ_ADDR123_MASK 0x3FFF /* WSEQ_ADDR123 - [13:0] */ +#define WM8995_WSEQ_ADDR123_SHIFT 0 /* WSEQ_ADDR123 - [13:0] */ +#define WM8995_WSEQ_ADDR123_WIDTH 14 /* WSEQ_ADDR123 - [13:0] */ + +/* + * R12781 (0x31ED) - Write Sequencer 493 + */ +#define WM8995_WSEQ_DATA123_MASK 0x00FF /* WSEQ_DATA123 - [7:0] */ +#define WM8995_WSEQ_DATA123_SHIFT 0 /* WSEQ_DATA123 - [7:0] */ +#define WM8995_WSEQ_DATA123_WIDTH 8 /* WSEQ_DATA123 - [7:0] */ + +/* + * R12782 (0x31EE) - Write Sequencer 494 + */ +#define WM8995_WSEQ_DATA_WIDTH123_MASK 0x0700 /* WSEQ_DATA_WIDTH123 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH123_SHIFT 8 /* WSEQ_DATA_WIDTH123 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH123_WIDTH 3 /* WSEQ_DATA_WIDTH123 - [10:8] */ +#define WM8995_WSEQ_DATA_START123_MASK 0x000F /* WSEQ_DATA_START123 - [3:0] */ +#define WM8995_WSEQ_DATA_START123_SHIFT 0 /* WSEQ_DATA_START123 - [3:0] */ +#define WM8995_WSEQ_DATA_START123_WIDTH 4 /* WSEQ_DATA_START123 - [3:0] */ + +/* + * R12783 (0x31EF) - Write Sequencer 495 + */ +#define WM8995_WSEQ_EOS123 0x0100 /* WSEQ_EOS123 */ +#define WM8995_WSEQ_EOS123_MASK 0x0100 /* WSEQ_EOS123 */ +#define WM8995_WSEQ_EOS123_SHIFT 8 /* WSEQ_EOS123 */ +#define WM8995_WSEQ_EOS123_WIDTH 1 /* WSEQ_EOS123 */ +#define WM8995_WSEQ_DELAY123_MASK 0x000F /* WSEQ_DELAY123 - [3:0] */ +#define WM8995_WSEQ_DELAY123_SHIFT 0 /* WSEQ_DELAY123 - [3:0] */ +#define WM8995_WSEQ_DELAY123_WIDTH 4 /* WSEQ_DELAY123 - [3:0] */ + +/* + * R12784 (0x31F0) - Write Sequencer 496 + */ +#define WM8995_WSEQ_ADDR124_MASK 0x3FFF /* WSEQ_ADDR124 - [13:0] */ +#define WM8995_WSEQ_ADDR124_SHIFT 0 /* WSEQ_ADDR124 - [13:0] */ +#define WM8995_WSEQ_ADDR124_WIDTH 14 /* WSEQ_ADDR124 - [13:0] */ + +/* + * R12785 (0x31F1) - Write Sequencer 497 + */ +#define WM8995_WSEQ_DATA124_MASK 0x00FF /* WSEQ_DATA124 - [7:0] */ +#define WM8995_WSEQ_DATA124_SHIFT 0 /* WSEQ_DATA124 - [7:0] */ +#define WM8995_WSEQ_DATA124_WIDTH 8 /* WSEQ_DATA124 - [7:0] */ + +/* + * R12786 (0x31F2) - Write Sequencer 498 + */ +#define WM8995_WSEQ_DATA_WIDTH124_MASK 0x0700 /* WSEQ_DATA_WIDTH124 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH124_SHIFT 8 /* WSEQ_DATA_WIDTH124 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH124_WIDTH 3 /* WSEQ_DATA_WIDTH124 - [10:8] */ +#define WM8995_WSEQ_DATA_START124_MASK 0x000F /* WSEQ_DATA_START124 - [3:0] */ +#define WM8995_WSEQ_DATA_START124_SHIFT 0 /* WSEQ_DATA_START124 - [3:0] */ +#define WM8995_WSEQ_DATA_START124_WIDTH 4 /* WSEQ_DATA_START124 - [3:0] */ + +/* + * R12787 (0x31F3) - Write Sequencer 499 + */ +#define WM8995_WSEQ_EOS124 0x0100 /* WSEQ_EOS124 */ +#define WM8995_WSEQ_EOS124_MASK 0x0100 /* WSEQ_EOS124 */ +#define WM8995_WSEQ_EOS124_SHIFT 8 /* WSEQ_EOS124 */ +#define WM8995_WSEQ_EOS124_WIDTH 1 /* WSEQ_EOS124 */ +#define WM8995_WSEQ_DELAY124_MASK 0x000F /* WSEQ_DELAY124 - [3:0] */ +#define WM8995_WSEQ_DELAY124_SHIFT 0 /* WSEQ_DELAY124 - [3:0] */ +#define WM8995_WSEQ_DELAY124_WIDTH 4 /* WSEQ_DELAY124 - [3:0] */ + +/* + * R12788 (0x31F4) - Write Sequencer 500 + */ +#define WM8995_WSEQ_ADDR125_MASK 0x3FFF /* WSEQ_ADDR125 - [13:0] */ +#define WM8995_WSEQ_ADDR125_SHIFT 0 /* WSEQ_ADDR125 - [13:0] */ +#define WM8995_WSEQ_ADDR125_WIDTH 14 /* WSEQ_ADDR125 - [13:0] */ + +/* + * R12789 (0x31F5) - Write Sequencer 501 + */ +#define WM8995_WSEQ_DATA125_MASK 0x00FF /* WSEQ_DATA125 - [7:0] */ +#define WM8995_WSEQ_DATA125_SHIFT 0 /* WSEQ_DATA125 - [7:0] */ +#define WM8995_WSEQ_DATA125_WIDTH 8 /* WSEQ_DATA125 - [7:0] */ + +/* + * R12790 (0x31F6) - Write Sequencer 502 + */ +#define WM8995_WSEQ_DATA_WIDTH125_MASK 0x0700 /* WSEQ_DATA_WIDTH125 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH125_SHIFT 8 /* WSEQ_DATA_WIDTH125 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH125_WIDTH 3 /* WSEQ_DATA_WIDTH125 - [10:8] */ +#define WM8995_WSEQ_DATA_START125_MASK 0x000F /* WSEQ_DATA_START125 - [3:0] */ +#define WM8995_WSEQ_DATA_START125_SHIFT 0 /* WSEQ_DATA_START125 - [3:0] */ +#define WM8995_WSEQ_DATA_START125_WIDTH 4 /* WSEQ_DATA_START125 - [3:0] */ + +/* + * R12791 (0x31F7) - Write Sequencer 503 + */ +#define WM8995_WSEQ_EOS125 0x0100 /* WSEQ_EOS125 */ +#define WM8995_WSEQ_EOS125_MASK 0x0100 /* WSEQ_EOS125 */ +#define WM8995_WSEQ_EOS125_SHIFT 8 /* WSEQ_EOS125 */ +#define WM8995_WSEQ_EOS125_WIDTH 1 /* WSEQ_EOS125 */ +#define WM8995_WSEQ_DELAY125_MASK 0x000F /* WSEQ_DELAY125 - [3:0] */ +#define WM8995_WSEQ_DELAY125_SHIFT 0 /* WSEQ_DELAY125 - [3:0] */ +#define WM8995_WSEQ_DELAY125_WIDTH 4 /* WSEQ_DELAY125 - [3:0] */ + +/* + * R12792 (0x31F8) - Write Sequencer 504 + */ +#define WM8995_WSEQ_ADDR126_MASK 0x3FFF /* WSEQ_ADDR126 - [13:0] */ +#define WM8995_WSEQ_ADDR126_SHIFT 0 /* WSEQ_ADDR126 - [13:0] */ +#define WM8995_WSEQ_ADDR126_WIDTH 14 /* WSEQ_ADDR126 - [13:0] */ + +/* + * R12793 (0x31F9) - Write Sequencer 505 + */ +#define WM8995_WSEQ_DATA126_MASK 0x00FF /* WSEQ_DATA126 - [7:0] */ +#define WM8995_WSEQ_DATA126_SHIFT 0 /* WSEQ_DATA126 - [7:0] */ +#define WM8995_WSEQ_DATA126_WIDTH 8 /* WSEQ_DATA126 - [7:0] */ + +/* + * R12794 (0x31FA) - Write Sequencer 506 + */ +#define WM8995_WSEQ_DATA_WIDTH126_MASK 0x0700 /* WSEQ_DATA_WIDTH126 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH126_SHIFT 8 /* WSEQ_DATA_WIDTH126 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH126_WIDTH 3 /* WSEQ_DATA_WIDTH126 - [10:8] */ +#define WM8995_WSEQ_DATA_START126_MASK 0x000F /* WSEQ_DATA_START126 - [3:0] */ +#define WM8995_WSEQ_DATA_START126_SHIFT 0 /* WSEQ_DATA_START126 - [3:0] */ +#define WM8995_WSEQ_DATA_START126_WIDTH 4 /* WSEQ_DATA_START126 - [3:0] */ + +/* + * R12795 (0x31FB) - Write Sequencer 507 + */ +#define WM8995_WSEQ_EOS126 0x0100 /* WSEQ_EOS126 */ +#define WM8995_WSEQ_EOS126_MASK 0x0100 /* WSEQ_EOS126 */ +#define WM8995_WSEQ_EOS126_SHIFT 8 /* WSEQ_EOS126 */ +#define WM8995_WSEQ_EOS126_WIDTH 1 /* WSEQ_EOS126 */ +#define WM8995_WSEQ_DELAY126_MASK 0x000F /* WSEQ_DELAY126 - [3:0] */ +#define WM8995_WSEQ_DELAY126_SHIFT 0 /* WSEQ_DELAY126 - [3:0] */ +#define WM8995_WSEQ_DELAY126_WIDTH 4 /* WSEQ_DELAY126 - [3:0] */ + +/* + * R12796 (0x31FC) - Write Sequencer 508 + */ +#define WM8995_WSEQ_ADDR127_MASK 0x3FFF /* WSEQ_ADDR127 - [13:0] */ +#define WM8995_WSEQ_ADDR127_SHIFT 0 /* WSEQ_ADDR127 - [13:0] */ +#define WM8995_WSEQ_ADDR127_WIDTH 14 /* WSEQ_ADDR127 - [13:0] */ + +/* + * R12797 (0x31FD) - Write Sequencer 509 + */ +#define WM8995_WSEQ_DATA127_MASK 0x00FF /* WSEQ_DATA127 - [7:0] */ +#define WM8995_WSEQ_DATA127_SHIFT 0 /* WSEQ_DATA127 - [7:0] */ +#define WM8995_WSEQ_DATA127_WIDTH 8 /* WSEQ_DATA127 - [7:0] */ + +/* + * R12798 (0x31FE) - Write Sequencer 510 + */ +#define WM8995_WSEQ_DATA_WIDTH127_MASK 0x0700 /* WSEQ_DATA_WIDTH127 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH127_SHIFT 8 /* WSEQ_DATA_WIDTH127 - [10:8] */ +#define WM8995_WSEQ_DATA_WIDTH127_WIDTH 3 /* WSEQ_DATA_WIDTH127 - [10:8] */ +#define WM8995_WSEQ_DATA_START127_MASK 0x000F /* WSEQ_DATA_START127 - [3:0] */ +#define WM8995_WSEQ_DATA_START127_SHIFT 0 /* WSEQ_DATA_START127 - [3:0] */ +#define WM8995_WSEQ_DATA_START127_WIDTH 4 /* WSEQ_DATA_START127 - [3:0] */ + +/* + * R12799 (0x31FF) - Write Sequencer 511 + */ +#define WM8995_WSEQ_EOS127 0x0100 /* WSEQ_EOS127 */ +#define WM8995_WSEQ_EOS127_MASK 0x0100 /* WSEQ_EOS127 */ +#define WM8995_WSEQ_EOS127_SHIFT 8 /* WSEQ_EOS127 */ +#define WM8995_WSEQ_EOS127_WIDTH 1 /* WSEQ_EOS127 */ +#define WM8995_WSEQ_DELAY127_MASK 0x000F /* WSEQ_DELAY127 - [3:0] */ +#define WM8995_WSEQ_DELAY127_SHIFT 0 /* WSEQ_DELAY127 - [3:0] */ +#define WM8995_WSEQ_DELAY127_WIDTH 4 /* WSEQ_DELAY127 - [3:0] */ + +#define WM8995_CLASS_W_SWITCH(xname, reg, shift, max, invert) \ +{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ + .info = snd_soc_info_volsw, \ + .get = snd_soc_dapm_get_volsw, .put = wm8995_put_class_w, \ + .private_value = SOC_SINGLE_VALUE(reg, shift, max, invert) \ +} + +struct wm8995_reg_access { + u16 read; + u16 write; + u16 vol; +}; + +/* Sources for AIF1/2 SYSCLK - use with set_dai_sysclk() */ +enum clk_src { + WM8995_SYSCLK_MCLK1 = 1, + WM8995_SYSCLK_MCLK2, + WM8995_SYSCLK_FLL1, + WM8995_SYSCLK_FLL2, + WM8995_SYSCLK_OPCLK +}; + +#define WM8995_FLL1 1 +#define WM8995_FLL2 2 + +#define WM8995_FLL_SRC_MCLK1 1 +#define WM8995_FLL_SRC_MCLK2 2 +#define WM8995_FLL_SRC_LRCLK 3 +#define WM8995_FLL_SRC_BCLK 4 + +#endif /* _WM8995_H */ -- cgit v1.2.2 From 1435b9402fe0fb27ac4ec5bb271112de2c4806c0 Mon Sep 17 00:00:00 2001 From: Mark Brown Date: Thu, 23 Dec 2010 01:56:20 +0000 Subject: ASoC: ifdef out trace points from modules for x86 No idea why this works on ARM but not x86. Signed-off-by: Mark Brown --- sound/soc/codecs/88pm860x-codec.c | 2 ++ sound/soc/codecs/wm8350.c | 4 ++++ sound/soc/codecs/wm8903.c | 2 ++ sound/soc/codecs/wm8962.c | 2 ++ 4 files changed, 10 insertions(+) (limited to 'sound/soc/codecs') diff --git a/sound/soc/codecs/88pm860x-codec.c b/sound/soc/codecs/88pm860x-codec.c index a34fb924e77b..3e798a12ee3d 100644 --- a/sound/soc/codecs/88pm860x-codec.c +++ b/sound/soc/codecs/88pm860x-codec.c @@ -1263,9 +1263,11 @@ static irqreturn_t pm860x_codec_handler(int irq, void *data) mask = pm860x->det.hs_shrt | pm860x->det.hook_det | pm860x->det.lo_shrt | pm860x->det.hp_det; +#ifndef CONFIG_SND_SOC_88PM860X if (status & (HEADSET_STATUS | MIC_STATUS | SHORT_HS1 | SHORT_HS2 | SHORT_LO1 | SHORT_LO2)) trace_snd_soc_jack_irq(dev_name(pm860x->codec->dev)); +#endif if ((pm860x->det.hp_det & SND_JACK_HEADPHONE) && (status & HEADSET_STATUS)) diff --git a/sound/soc/codecs/wm8350.c b/sound/soc/codecs/wm8350.c index 82d877df3fb0..db07137bf3b9 100644 --- a/sound/soc/codecs/wm8350.c +++ b/sound/soc/codecs/wm8350.c @@ -1379,12 +1379,16 @@ static irqreturn_t wm8350_hp_jack_handler(int irq, void *data) switch (irq - wm8350->irq_base) { case WM8350_IRQ_CODEC_JCK_DET_L: +#ifndef CONFIG_SND_SOC_WM8350_MODULE trace_snd_soc_jack_irq("WM8350 HPL"); +#endif jack = &priv->hpl; break; case WM8350_IRQ_CODEC_JCK_DET_R: +#ifndef CONFIG_SND_SOC_WM8350_MODULE trace_snd_soc_jack_irq("WM8350 HPR"); +#endif jack = &priv->hpr; break; diff --git a/sound/soc/codecs/wm8903.c b/sound/soc/codecs/wm8903.c index b32699bc1927..02de5ae42d63 100644 --- a/sound/soc/codecs/wm8903.c +++ b/sound/soc/codecs/wm8903.c @@ -1534,8 +1534,10 @@ static irqreturn_t wm8903_irq(int irq, void *data) mic_report = wm8903->mic_last_report; int_pol = snd_soc_read(codec, WM8903_INTERRUPT_POLARITY_1); +#ifndef CONFIG_SND_SOC_WM8903_MODULE if (int_val & (WM8903_MICSHRT_EINT | WM8903_MICDET_EINT)) trace_snd_soc_jack_irq(dev_name(codec->dev)); +#endif if (int_val & WM8903_MICSHRT_EINT) { dev_dbg(codec->dev, "Microphone short (pol=%x)\n", int_pol); diff --git a/sound/soc/codecs/wm8962.c b/sound/soc/codecs/wm8962.c index a24f83d604c9..b311b465c4d8 100644 --- a/sound/soc/codecs/wm8962.c +++ b/sound/soc/codecs/wm8962.c @@ -3354,7 +3354,9 @@ static irqreturn_t wm8962_irq(int irq, void *data) if (active & (WM8962_MICSCD_EINT | WM8962_MICD_EINT)) { dev_dbg(codec->dev, "Microphone event detected\n"); +#ifndef CONFIG_SOUND_SOC_WM862_MODULE trace_snd_soc_jack_irq(dev_name(codec->dev)); +#endif pm_wakeup_event(codec->dev, 300); -- cgit v1.2.2 From f769bdf2a7ee97c8e762fc133ff00aabe935867b Mon Sep 17 00:00:00 2001 From: "Olaya, Margarita" Date: Mon, 20 Dec 2010 10:39:20 -0600 Subject: ASoC: twl6040: Convert HF and HS drivers to use DAPM OUT_DRV widget Make the phoenix HS and HF drivers use the new DAPM driver widget in order to guarantee power ON/OFF order sequence. Signed-off-by: Margarita Olaya Cabrera Acked-by: Mark Brown Signed-off-by: Liam Girdwood --- sound/soc/codecs/twl6040.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'sound/soc/codecs') diff --git a/sound/soc/codecs/twl6040.c b/sound/soc/codecs/twl6040.c index 2f68f5949a63..4bbf1b15a493 100644 --- a/sound/soc/codecs/twl6040.c +++ b/sound/soc/codecs/twl6040.c @@ -1138,19 +1138,19 @@ static const struct snd_soc_dapm_widget twl6040_dapm_widgets[] = { SND_SOC_NOPM, 0, 0, &hsr_mux_controls), /* Analog playback drivers */ - SND_SOC_DAPM_PGA_E("Handsfree Left Driver", + SND_SOC_DAPM_OUT_DRV_E("Handsfree Left Driver", TWL6040_REG_HFLCTL, 4, 0, NULL, 0, pga_event, SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), - SND_SOC_DAPM_PGA_E("Handsfree Right Driver", + SND_SOC_DAPM_OUT_DRV_E("Handsfree Right Driver", TWL6040_REG_HFRCTL, 4, 0, NULL, 0, pga_event, SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), - SND_SOC_DAPM_PGA_E("Headset Left Driver", + SND_SOC_DAPM_OUT_DRV_E("Headset Left Driver", TWL6040_REG_HSLCTL, 2, 0, NULL, 0, pga_event, SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), - SND_SOC_DAPM_PGA_E("Headset Right Driver", + SND_SOC_DAPM_OUT_DRV_E("Headset Right Driver", TWL6040_REG_HSRCTL, 2, 0, NULL, 0, pga_event, SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), -- cgit v1.2.2 From 3591f4cd53a3835e6d59dd509337503c2c61173e Mon Sep 17 00:00:00 2001 From: Peter Ujfalusi Date: Wed, 22 Dec 2010 10:45:16 +0200 Subject: ASoC: tlv320dac33: Remove manual FIFO configuration The manual FIFO configuration was the first version to enable the use of the FIFO in the codec. It had served it's purpose as debugging aid, but the automatic FIFO configuration is much safer to use. The removal of the manual controls, and configuration makes it easier to add new features for the codec later, since the manual mode neded different ways to calculate, and protect against misconfiguration. Signed-off-by: Peter Ujfalusi Acked-by: Mark Brown Signed-off-by: Liam Girdwood --- sound/soc/codecs/tlv320dac33.c | 157 ++++++----------------------------------- 1 file changed, 20 insertions(+), 137 deletions(-) (limited to 'sound/soc/codecs') diff --git a/sound/soc/codecs/tlv320dac33.c b/sound/soc/codecs/tlv320dac33.c index 776ac80cc1a8..c574ae238973 100644 --- a/sound/soc/codecs/tlv320dac33.c +++ b/sound/soc/codecs/tlv320dac33.c @@ -46,8 +46,6 @@ * 6144 stereo */ #define DAC33_BUFFER_SIZE_SAMPLES 6144 -#define NSAMPLE_MAX 5700 - #define MODE7_LTHR 10 #define MODE7_UTHR (DAC33_BUFFER_SIZE_SAMPLES - 10) @@ -99,16 +97,10 @@ struct tlv320dac33_priv { unsigned int refclk; unsigned int alarm_threshold; /* set to be half of LATENCY_TIME_MS */ - unsigned int nsample_min; /* nsample should not be lower than - * this */ - unsigned int nsample_max; /* nsample should not be higher than - * this */ enum dac33_fifo_modes fifo_mode;/* FIFO mode selection */ unsigned int nsample; /* burst read amount from host */ int mode1_latency; /* latency caused by the i2c writes in * us */ - int auto_fifo_config; /* Configure the FIFO based on the - * period size */ u8 burst_bclkdiv; /* BCLK divider value in burst mode */ unsigned int burst_rate; /* Interface speed in Burst modes */ @@ -436,73 +428,6 @@ static int dac33_playback_event(struct snd_soc_dapm_widget *w, return 0; } -static int dac33_get_nsample(struct snd_kcontrol *kcontrol, - struct snd_ctl_elem_value *ucontrol) -{ - struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); - struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec); - - ucontrol->value.integer.value[0] = dac33->nsample; - - return 0; -} - -static int dac33_set_nsample(struct snd_kcontrol *kcontrol, - struct snd_ctl_elem_value *ucontrol) -{ - struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); - struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec); - int ret = 0; - - if (dac33->nsample == ucontrol->value.integer.value[0]) - return 0; - - if (ucontrol->value.integer.value[0] < dac33->nsample_min || - ucontrol->value.integer.value[0] > dac33->nsample_max) { - ret = -EINVAL; - } else { - dac33->nsample = ucontrol->value.integer.value[0]; - /* Re calculate the burst time */ - dac33->mode1_us_burst = SAMPLES_TO_US(dac33->burst_rate, - dac33->nsample); - } - - return ret; -} - -static int dac33_get_uthr(struct snd_kcontrol *kcontrol, - struct snd_ctl_elem_value *ucontrol) -{ - struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); - struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec); - - ucontrol->value.integer.value[0] = dac33->uthr; - - return 0; -} - -static int dac33_set_uthr(struct snd_kcontrol *kcontrol, - struct snd_ctl_elem_value *ucontrol) -{ - struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); - struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec); - int ret = 0; - - if (dac33->substream) - return -EBUSY; - - if (dac33->uthr == ucontrol->value.integer.value[0]) - return 0; - - if (ucontrol->value.integer.value[0] < (MODE7_LTHR + 10) || - ucontrol->value.integer.value[0] > MODE7_UTHR) - ret = -EINVAL; - else - dac33->uthr = ucontrol->value.integer.value[0]; - - return ret; -} - static int dac33_get_fifo_mode(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { @@ -587,13 +512,6 @@ static const struct snd_kcontrol_new dac33_mode_snd_controls[] = { dac33_get_fifo_mode, dac33_set_fifo_mode), }; -static const struct snd_kcontrol_new dac33_fifo_snd_controls[] = { - SOC_SINGLE_EXT("nSample", 0, 0, 5900, 0, - dac33_get_nsample, dac33_set_nsample), - SOC_SINGLE_EXT("UTHR", 0, 0, MODE7_UTHR, 0, - dac33_get_uthr, dac33_set_uthr), -}; - /* Analog bypass */ static const struct snd_kcontrol_new dac33_dapm_abypassl_control = SOC_DAPM_SINGLE("Switch", DAC33_LINEL_TO_LLO_VOL, 7, 1, 1); @@ -853,10 +771,6 @@ static void dac33_shutdown(struct snd_pcm_substream *substream, struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec); dac33->substream = NULL; - - /* Reset the nSample restrictions */ - dac33->nsample_min = 0; - dac33->nsample_max = NSAMPLE_MAX; } static int dac33_hw_params(struct snd_pcm_substream *substream, @@ -1112,39 +1026,19 @@ static void dac33_calculate_times(struct snd_pcm_substream *substream) nsample_limit = DAC33_BUFFER_SIZE_SAMPLES - dac33->alarm_threshold; - if (dac33->auto_fifo_config) { - if (period_size <= dac33->alarm_threshold) - /* - * Configure nSamaple to number of periods, - * which covers the latency requironment. - */ - dac33->nsample = period_size * - ((dac33->alarm_threshold / period_size) + - (dac33->alarm_threshold % period_size ? - 1 : 0)); - else if (period_size > nsample_limit) - dac33->nsample = nsample_limit; - else - dac33->nsample = period_size; - } else { - /* nSample time shall not be shorter than i2c latency */ - dac33->nsample_min = dac33->alarm_threshold; + if (period_size <= dac33->alarm_threshold) /* - * nSample should not be bigger than alsa buffer minus - * size of one period to avoid overruns + * Configure nSamaple to number of periods, + * which covers the latency requironment. */ - dac33->nsample_max = substream->runtime->buffer_size - - period_size; - - if (dac33->nsample_max > nsample_limit) - dac33->nsample_max = nsample_limit; - - /* Correct the nSample if it is outside of the ranges */ - if (dac33->nsample < dac33->nsample_min) - dac33->nsample = dac33->nsample_min; - if (dac33->nsample > dac33->nsample_max) - dac33->nsample = dac33->nsample_max; - } + dac33->nsample = period_size * + ((dac33->alarm_threshold / period_size) + + (dac33->alarm_threshold % period_size ? + 1 : 0)); + else if (period_size > nsample_limit) + dac33->nsample = nsample_limit; + else + dac33->nsample = period_size; dac33->mode1_us_burst = SAMPLES_TO_US(dac33->burst_rate, dac33->nsample); @@ -1152,16 +1046,13 @@ static void dac33_calculate_times(struct snd_pcm_substream *substream) dac33->t_stamp2 = 0; break; case DAC33_FIFO_MODE7: - if (dac33->auto_fifo_config) { - dac33->uthr = UTHR_FROM_PERIOD_SIZE( - period_size, - rate, - dac33->burst_rate) + 9; - if (dac33->uthr > MODE7_UTHR) - dac33->uthr = MODE7_UTHR; - if (dac33->uthr < (MODE7_LTHR + 10)) - dac33->uthr = (MODE7_LTHR + 10); - } + dac33->uthr = UTHR_FROM_PERIOD_SIZE(period_size, rate, + dac33->burst_rate) + 9; + if (dac33->uthr > MODE7_UTHR) + dac33->uthr = MODE7_UTHR; + if (dac33->uthr < (MODE7_LTHR + 10)) + dac33->uthr = (MODE7_LTHR + 10); + dac33->mode7_us_to_lthr = SAMPLES_TO_US(substream->runtime->rate, dac33->uthr - MODE7_LTHR + 1); @@ -1486,14 +1377,10 @@ static int dac33_soc_probe(struct snd_soc_codec *codec) snd_soc_add_controls(codec, dac33_snd_controls, ARRAY_SIZE(dac33_snd_controls)); /* Only add the FIFO controls, if we have valid IRQ number */ - if (dac33->irq >= 0) { + if (dac33->irq >= 0) snd_soc_add_controls(codec, dac33_mode_snd_controls, ARRAY_SIZE(dac33_mode_snd_controls)); - /* FIFO usage controls only, if autoio config is not selected */ - if (!dac33->auto_fifo_config) - snd_soc_add_controls(codec, dac33_fifo_snd_controls, - ARRAY_SIZE(dac33_fifo_snd_controls)); - } + dac33_add_widgets(codec); err_power: @@ -1593,14 +1480,10 @@ static int __devinit dac33_i2c_probe(struct i2c_client *client, /* Pre calculate the burst rate */ dac33->burst_rate = BURST_BASEFREQ_HZ / dac33->burst_bclkdiv / 32; dac33->keep_bclk = pdata->keep_bclk; - dac33->auto_fifo_config = pdata->auto_fifo_config; dac33->mode1_latency = pdata->mode1_latency; if (!dac33->mode1_latency) dac33->mode1_latency = 10000; /* 10ms */ dac33->irq = client->irq; - dac33->nsample = NSAMPLE_MAX; - dac33->nsample_max = NSAMPLE_MAX; - dac33->uthr = MODE7_UTHR; /* Disable FIFO use by default */ dac33->fifo_mode = DAC33_FIFO_BYPASS; -- cgit v1.2.2 From 549675ed658761b9a84cb579795c9ec1da227fea Mon Sep 17 00:00:00 2001 From: Peter Ujfalusi Date: Wed, 22 Dec 2010 10:45:17 +0200 Subject: ASoC: tlv320dac33: Some cleanup for 32/24 bit support Change the structure of FIFO handling in order to pave the way for adding 32/24 bit audio support. Signed-off-by: Peter Ujfalusi Acked-by: Mark Brown Signed-off-by: Liam Girdwood --- sound/soc/codecs/tlv320dac33.c | 47 ++++++++++++++++++++++++------------------ 1 file changed, 27 insertions(+), 20 deletions(-) (limited to 'sound/soc/codecs') diff --git a/sound/soc/codecs/tlv320dac33.c b/sound/soc/codecs/tlv320dac33.c index c574ae238973..05a4e9fade47 100644 --- a/sound/soc/codecs/tlv320dac33.c +++ b/sound/soc/codecs/tlv320dac33.c @@ -42,12 +42,15 @@ #include #include "tlv320dac33.h" -#define DAC33_BUFFER_SIZE_BYTES 24576 /* bytes, 12288 16 bit words, - * 6144 stereo */ -#define DAC33_BUFFER_SIZE_SAMPLES 6144 - -#define MODE7_LTHR 10 -#define MODE7_UTHR (DAC33_BUFFER_SIZE_SAMPLES - 10) +/* + * The internal FIFO is 24576 bytes long + * It can be configured to hold 16bit or 24bit samples + * In 16bit configuration the FIFO can hold 6144 stereo samples + * In 24bit configuration the FIFO can hold 4096 stereo samples + */ +#define DAC33_FIFO_SIZE_16BIT 6144 +#define DAC33_FIFO_SIZE_24BIT 4096 +#define DAC33_MODE7_MARGIN 10 /* Safety margin for FIFO in Mode7 */ #define BURST_BASEFREQ_HZ 49152000 @@ -98,6 +101,7 @@ struct tlv320dac33_priv { unsigned int alarm_threshold; /* set to be half of LATENCY_TIME_MS */ enum dac33_fifo_modes fifo_mode;/* FIFO mode selection */ + unsigned int fifo_size; /* Size of the FIFO in samples */ unsigned int nsample; /* burst read amount from host */ int mode1_latency; /* latency caused by the i2c writes in * us */ @@ -650,7 +654,7 @@ static inline void dac33_prefill_handler(struct tlv320dac33_priv *dac33) spin_unlock_irq(&dac33->lock); dac33_write16(codec, DAC33_PREFILL_MSB, - DAC33_THRREG(MODE7_LTHR)); + DAC33_THRREG(DAC33_MODE7_MARGIN)); /* Enable Upper Threshold IRQ */ dac33_write(codec, DAC33_FIFO_IRQ_MASK, DAC33_MUT); @@ -773,12 +777,15 @@ static void dac33_shutdown(struct snd_pcm_substream *substream, dac33->substream = NULL; } +#define CALC_BURST_RATE(bclkdiv, bclk_per_sample) \ + (BURST_BASEFREQ_HZ / bclkdiv / bclk_per_sample) static int dac33_hw_params(struct snd_pcm_substream *substream, struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) { struct snd_soc_pcm_runtime *rtd = substream->private_data; struct snd_soc_codec *codec = rtd->codec; + struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec); /* Check parameters for validity */ switch (params_rate(params)) { @@ -793,6 +800,8 @@ static int dac33_hw_params(struct snd_pcm_substream *substream, switch (params_format(params)) { case SNDRV_PCM_FORMAT_S16_LE: + dac33->fifo_size = DAC33_FIFO_SIZE_16BIT; + dac33->burst_rate = CALC_BURST_RATE(dac33->burst_bclkdiv, 32); break; default: dev_err(codec->dev, "unsupported format %d\n", @@ -994,7 +1003,8 @@ static int dac33_prepare_chip(struct snd_pcm_substream *substream) * at the bottom, and also at the top of the FIFO */ dac33_write16(codec, DAC33_UTHR_MSB, DAC33_THRREG(dac33->uthr)); - dac33_write16(codec, DAC33_LTHR_MSB, DAC33_THRREG(MODE7_LTHR)); + dac33_write16(codec, DAC33_LTHR_MSB, + DAC33_THRREG(DAC33_MODE7_MARGIN)); break; default: break; @@ -1023,8 +1033,7 @@ static void dac33_calculate_times(struct snd_pcm_substream *substream) /* Number of samples under i2c latency */ dac33->alarm_threshold = US_TO_SAMPLES(rate, dac33->mode1_latency); - nsample_limit = DAC33_BUFFER_SIZE_SAMPLES - - dac33->alarm_threshold; + nsample_limit = dac33->fifo_size - dac33->alarm_threshold; if (period_size <= dac33->alarm_threshold) /* @@ -1048,14 +1057,14 @@ static void dac33_calculate_times(struct snd_pcm_substream *substream) case DAC33_FIFO_MODE7: dac33->uthr = UTHR_FROM_PERIOD_SIZE(period_size, rate, dac33->burst_rate) + 9; - if (dac33->uthr > MODE7_UTHR) - dac33->uthr = MODE7_UTHR; - if (dac33->uthr < (MODE7_LTHR + 10)) - dac33->uthr = (MODE7_LTHR + 10); + if (dac33->uthr > (dac33->fifo_size - DAC33_MODE7_MARGIN)) + dac33->uthr = dac33->fifo_size - DAC33_MODE7_MARGIN; + if (dac33->uthr < (DAC33_MODE7_MARGIN + 10)) + dac33->uthr = (DAC33_MODE7_MARGIN + 10); dac33->mode7_us_to_lthr = SAMPLES_TO_US(substream->runtime->rate, - dac33->uthr - MODE7_LTHR + 1); + dac33->uthr - DAC33_MODE7_MARGIN + 1); dac33->t_stamp1 = 0; break; default: @@ -1173,8 +1182,8 @@ static snd_pcm_sframes_t dac33_dai_delay( samples += (samples_in - samples_out); if (likely(samples > 0)) - delay = samples > DAC33_BUFFER_SIZE_SAMPLES ? - DAC33_BUFFER_SIZE_SAMPLES : samples; + delay = samples > dac33->fifo_size ? + dac33->fifo_size : samples; else delay = 0; } @@ -1226,7 +1235,7 @@ static snd_pcm_sframes_t dac33_dai_delay( samples_in = US_TO_SAMPLES( dac33->burst_rate, time_delta); - delay = MODE7_LTHR + samples_in - samples_out; + delay = DAC33_MODE7_MARGIN + samples_in - samples_out; if (unlikely(delay > uthr)) delay = uthr; @@ -1477,8 +1486,6 @@ static int __devinit dac33_i2c_probe(struct i2c_client *client, dac33->power_gpio = pdata->power_gpio; dac33->burst_bclkdiv = pdata->burst_bclkdiv; - /* Pre calculate the burst rate */ - dac33->burst_rate = BURST_BASEFREQ_HZ / dac33->burst_bclkdiv / 32; dac33->keep_bclk = pdata->keep_bclk; dac33->mode1_latency = pdata->mode1_latency; if (!dac33->mode1_latency) -- cgit v1.2.2 From 0d99d2b036974ed1160f9d10457b6054646fb7d6 Mon Sep 17 00:00:00 2001 From: Peter Ujfalusi Date: Wed, 22 Dec 2010 10:45:18 +0200 Subject: ASoC: tlv320dac33: Add 32/24 bit audio support Add support for 24 bit audio (with S32_LE msbits 24). The reason to limit the msbits to 24, is that the FIFO can be configured for 16 or 24 bit layout. It is unknown how the codec would downsample from 32 to 24 bit, if the interface is configured to receive 32 bit data. Signed-off-by: Peter Ujfalusi Acked-by: Mark Brown Signed-off-by: Liam Girdwood --- sound/soc/codecs/tlv320dac33.c | 16 ++++++++++++++-- 1 file changed, 14 insertions(+), 2 deletions(-) (limited to 'sound/soc/codecs') diff --git a/sound/soc/codecs/tlv320dac33.c b/sound/soc/codecs/tlv320dac33.c index 05a4e9fade47..13d521cfe393 100644 --- a/sound/soc/codecs/tlv320dac33.c +++ b/sound/soc/codecs/tlv320dac33.c @@ -764,6 +764,8 @@ static int dac33_startup(struct snd_pcm_substream *substream, /* Stream started, save the substream pointer */ dac33->substream = substream; + snd_pcm_hw_constraint_msbits(substream->runtime, 0, 32, 24); + return 0; } @@ -803,6 +805,10 @@ static int dac33_hw_params(struct snd_pcm_substream *substream, dac33->fifo_size = DAC33_FIFO_SIZE_16BIT; dac33->burst_rate = CALC_BURST_RATE(dac33->burst_bclkdiv, 32); break; + case SNDRV_PCM_FORMAT_S32_LE: + dac33->fifo_size = DAC33_FIFO_SIZE_24BIT; + dac33->burst_rate = CALC_BURST_RATE(dac33->burst_bclkdiv, 64); + break; default: dev_err(codec->dev, "unsupported format %d\n", params_format(params)); @@ -856,6 +862,9 @@ static int dac33_prepare_chip(struct snd_pcm_substream *substream) aictrl_a |= (DAC33_NCYCL_16 | DAC33_WLEN_16); fifoctrl_a |= DAC33_WIDTH; break; + case SNDRV_PCM_FORMAT_S32_LE: + aictrl_a |= (DAC33_NCYCL_32 | DAC33_WLEN_24); + break; default: dev_err(codec->dev, "unsupported format %d\n", substream->runtime->format); @@ -990,7 +999,10 @@ static int dac33_prepare_chip(struct snd_pcm_substream *substream) dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_C, dac33->burst_bclkdiv); else - dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_C, 32); + if (substream->runtime->format == SNDRV_PCM_FORMAT_S16_LE) + dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_C, 32); + else + dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_C, 16); switch (dac33->fifo_mode) { case DAC33_FIFO_MODE1: @@ -1438,7 +1450,7 @@ static struct snd_soc_codec_driver soc_codec_dev_tlv320dac33 = { #define DAC33_RATES (SNDRV_PCM_RATE_44100 | \ SNDRV_PCM_RATE_48000) -#define DAC33_FORMATS SNDRV_PCM_FMTBIT_S16_LE +#define DAC33_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE) static struct snd_soc_dai_ops dac33_dai_ops = { .startup = dac33_startup, -- cgit v1.2.2 From 524d7692bcdbec9027bfdc001a8aeb6eb6837117 Mon Sep 17 00:00:00 2001 From: Mark Brown Date: Thu, 23 Dec 2010 11:17:24 +0000 Subject: ASoC: Remove incorrect WM8903 erratum workaround Due to a typographical error in the erratum workaround it was never functional so just remove it. Signed-off-by: Mark Brown Acked-by: Liam Girdwood --- sound/soc/codecs/wm8903.c | 20 ++++++-------------- sound/soc/codecs/wm8903.h | 19 ------------------- 2 files changed, 6 insertions(+), 33 deletions(-) (limited to 'sound/soc/codecs') diff --git a/sound/soc/codecs/wm8903.c b/sound/soc/codecs/wm8903.c index 02de5ae42d63..b9843f72c455 100644 --- a/sound/soc/codecs/wm8903.c +++ b/sound/soc/codecs/wm8903.c @@ -1014,7 +1014,7 @@ static int wm8903_add_widgets(struct snd_soc_codec *codec) static int wm8903_set_bias_level(struct snd_soc_codec *codec, enum snd_soc_bias_level level) { - u16 reg, reg2; + u16 reg; switch (level) { case SND_SOC_BIAS_ON: @@ -1038,23 +1038,15 @@ static int wm8903_set_bias_level(struct snd_soc_codec *codec, wm8903_run_sequence(codec, 0); wm8903_sync_reg_cache(codec, codec->reg_cache); - /* Enable low impedence charge pump output */ - reg = snd_soc_read(codec, - WM8903_CONTROL_INTERFACE_TEST_1); - snd_soc_write(codec, WM8903_CONTROL_INTERFACE_TEST_1, - reg | WM8903_TEST_KEY); - reg2 = snd_soc_read(codec, WM8903_CHARGE_PUMP_TEST_1); - snd_soc_write(codec, WM8903_CHARGE_PUMP_TEST_1, - reg2 | WM8903_CP_SW_KELVIN_MODE_MASK); - snd_soc_write(codec, WM8903_CONTROL_INTERFACE_TEST_1, - reg); - /* By default no bypass paths are enabled so * enable Class W support. */ dev_dbg(codec->dev, "Enabling Class W\n"); - snd_soc_write(codec, WM8903_CLASS_W_0, reg | - WM8903_CP_DYN_FREQ | WM8903_CP_DYN_V); + snd_soc_update_bits(codec, WM8903_CLASS_W_0, + WM8903_CP_DYN_FREQ | + WM8903_CP_DYN_V, + WM8903_CP_DYN_FREQ | + WM8903_CP_DYN_V); } reg = snd_soc_read(codec, WM8903_VMID_CONTROL_0); diff --git a/sound/soc/codecs/wm8903.h b/sound/soc/codecs/wm8903.h index e47b8c8be921..5f23d3ca45f8 100644 --- a/sound/soc/codecs/wm8903.h +++ b/sound/soc/codecs/wm8903.h @@ -94,8 +94,6 @@ extern int wm8903_mic_detect(struct snd_soc_codec *codec, #define WM8903_INTERRUPT_STATUS_1_MASK 0x7A #define WM8903_INTERRUPT_POLARITY_1 0x7B #define WM8903_INTERRUPT_CONTROL 0x7E -#define WM8903_CONTROL_INTERFACE_TEST_1 0x81 -#define WM8903_CHARGE_PUMP_TEST_1 0x95 #define WM8903_CLOCK_RATE_TEST_4 0xA4 #define WM8903_ANALOGUE_OUTPUT_BIAS_0 0xAC @@ -1202,23 +1200,6 @@ extern int wm8903_mic_detect(struct snd_soc_codec *codec, #define WM8903_IRQ_POL_WIDTH 1 /* IRQ_POL */ /* - * R129 (0x81) - Control Interface Test 1 - */ -#define WM8903_USER_KEY 0x0002 /* USER_KEY */ -#define WM8903_USER_KEY_MASK 0x0002 /* USER_KEY */ -#define WM8903_USER_KEY_SHIFT 1 /* USER_KEY */ -#define WM8903_USER_KEY_WIDTH 1 /* USER_KEY */ -#define WM8903_TEST_KEY 0x0001 /* TEST_KEY */ -#define WM8903_TEST_KEY_MASK 0x0001 /* TEST_KEY */ -#define WM8903_TEST_KEY_SHIFT 0 /* TEST_KEY */ -#define WM8903_TEST_KEY_WIDTH 1 /* TEST_KEY */ - -/* - * R149 (0x95) - Charge Pump Test 1 - */ -#define WM8903_CP_SW_KELVIN_MODE_MASK 0x0006 /* CP_SW_KELVIN_MODE - [2:1] */ -#define WM8903_CP_SW_KELVIN_MODE_SHIFT 1 /* CP_SW_KELVIN_MODE - [2:1] */ -#define WM8903_CP_SW_KELVIN_MODE_WIDTH 2 /* CP_SW_KELVIN_MODE - [2:1] */ /* * R164 (0xA4) - Clock Rate Test 4 -- cgit v1.2.2 From 617eecdb3d51624afca3be546b72fe80d8708370 Mon Sep 17 00:00:00 2001 From: Mark Brown Date: Thu, 23 Dec 2010 12:03:07 +0000 Subject: ASoC: Remove WM8995 write sequencer bitfield definitions They're very verbose and extremely repetitive so bulk up the kernel more than is ideal. If required we can readd with WRITE_SEQUENCER_n type definitions that cover the entire register bank in a few defines. Signed-off-by: Mark Brown Acked-by: Liam Girdwood --- sound/soc/codecs/wm8995.h | 4480 --------------------------------------------- 1 file changed, 4480 deletions(-) (limited to 'sound/soc/codecs') diff --git a/sound/soc/codecs/wm8995.h b/sound/soc/codecs/wm8995.h index 6409e5a6b574..5642121c4977 100644 --- a/sound/soc/codecs/wm8995.h +++ b/sound/soc/codecs/wm8995.h @@ -4236,4486 +4236,6 @@ #define WM8995_SPK2_MUTE_SEQ1_SHIFT 0 /* SPK2_MUTE_SEQ1 - [7:0] */ #define WM8995_SPK2_MUTE_SEQ1_WIDTH 8 /* SPK2_MUTE_SEQ1 - [7:0] */ -/* - * R12288 (0x3000) - Write Sequencer 0 - */ -#define WM8995_WSEQ_ADDR0_MASK 0x3FFF /* WSEQ_ADDR0 - [13:0] */ -#define WM8995_WSEQ_ADDR0_SHIFT 0 /* WSEQ_ADDR0 - [13:0] */ -#define WM8995_WSEQ_ADDR0_WIDTH 14 /* WSEQ_ADDR0 - [13:0] */ - -/* - * R12289 (0x3001) - Write Sequencer 1 - */ -#define WM8995_WSEQ_DATA0_MASK 0x00FF /* WSEQ_DATA0 - [7:0] */ -#define WM8995_WSEQ_DATA0_SHIFT 0 /* WSEQ_DATA0 - [7:0] */ -#define WM8995_WSEQ_DATA0_WIDTH 8 /* WSEQ_DATA0 - [7:0] */ - -/* - * R12290 (0x3002) - Write Sequencer 2 - */ -#define WM8995_WSEQ_DATA_WIDTH0_MASK 0x0700 /* WSEQ_DATA_WIDTH0 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH0_SHIFT 8 /* WSEQ_DATA_WIDTH0 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH0_WIDTH 3 /* WSEQ_DATA_WIDTH0 - [10:8] */ -#define WM8995_WSEQ_DATA_START0_MASK 0x000F /* WSEQ_DATA_START0 - [3:0] */ -#define WM8995_WSEQ_DATA_START0_SHIFT 0 /* WSEQ_DATA_START0 - [3:0] */ -#define WM8995_WSEQ_DATA_START0_WIDTH 4 /* WSEQ_DATA_START0 - [3:0] */ - -/* - * R12291 (0x3003) - Write Sequencer 3 - */ -#define WM8995_WSEQ_EOS0 0x0100 /* WSEQ_EOS0 */ -#define WM8995_WSEQ_EOS0_MASK 0x0100 /* WSEQ_EOS0 */ -#define WM8995_WSEQ_EOS0_SHIFT 8 /* WSEQ_EOS0 */ -#define WM8995_WSEQ_EOS0_WIDTH 1 /* WSEQ_EOS0 */ -#define WM8995_WSEQ_DELAY0_MASK 0x000F /* WSEQ_DELAY0 - [3:0] */ -#define WM8995_WSEQ_DELAY0_SHIFT 0 /* WSEQ_DELAY0 - [3:0] */ -#define WM8995_WSEQ_DELAY0_WIDTH 4 /* WSEQ_DELAY0 - [3:0] */ - -/* - * R12292 (0x3004) - Write Sequencer 4 - */ -#define WM8995_WSEQ_ADDR1_MASK 0x3FFF /* WSEQ_ADDR1 - [13:0] */ -#define WM8995_WSEQ_ADDR1_SHIFT 0 /* WSEQ_ADDR1 - [13:0] */ -#define WM8995_WSEQ_ADDR1_WIDTH 14 /* WSEQ_ADDR1 - [13:0] */ - -/* - * R12293 (0x3005) - Write Sequencer 5 - */ -#define WM8995_WSEQ_DATA1_MASK 0x00FF /* WSEQ_DATA1 - [7:0] */ -#define WM8995_WSEQ_DATA1_SHIFT 0 /* WSEQ_DATA1 - [7:0] */ -#define WM8995_WSEQ_DATA1_WIDTH 8 /* WSEQ_DATA1 - [7:0] */ - -/* - * R12294 (0x3006) - Write Sequencer 6 - */ -#define WM8995_WSEQ_DATA_WIDTH1_MASK 0x0700 /* WSEQ_DATA_WIDTH1 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH1_SHIFT 8 /* WSEQ_DATA_WIDTH1 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH1_WIDTH 3 /* WSEQ_DATA_WIDTH1 - [10:8] */ -#define WM8995_WSEQ_DATA_START1_MASK 0x000F /* WSEQ_DATA_START1 - [3:0] */ -#define WM8995_WSEQ_DATA_START1_SHIFT 0 /* WSEQ_DATA_START1 - [3:0] */ -#define WM8995_WSEQ_DATA_START1_WIDTH 4 /* WSEQ_DATA_START1 - [3:0] */ - -/* - * R12295 (0x3007) - Write Sequencer 7 - */ -#define WM8995_WSEQ_EOS1 0x0100 /* WSEQ_EOS1 */ -#define WM8995_WSEQ_EOS1_MASK 0x0100 /* WSEQ_EOS1 */ -#define WM8995_WSEQ_EOS1_SHIFT 8 /* WSEQ_EOS1 */ -#define WM8995_WSEQ_EOS1_WIDTH 1 /* WSEQ_EOS1 */ -#define WM8995_WSEQ_DELAY1_MASK 0x000F /* WSEQ_DELAY1 - [3:0] */ -#define WM8995_WSEQ_DELAY1_SHIFT 0 /* WSEQ_DELAY1 - [3:0] */ -#define WM8995_WSEQ_DELAY1_WIDTH 4 /* WSEQ_DELAY1 - [3:0] */ - -/* - * R12296 (0x3008) - Write Sequencer 8 - */ -#define WM8995_WSEQ_ADDR2_MASK 0x3FFF /* WSEQ_ADDR2 - [13:0] */ -#define WM8995_WSEQ_ADDR2_SHIFT 0 /* WSEQ_ADDR2 - [13:0] */ -#define WM8995_WSEQ_ADDR2_WIDTH 14 /* WSEQ_ADDR2 - [13:0] */ - -/* - * R12297 (0x3009) - Write Sequencer 9 - */ -#define WM8995_WSEQ_DATA2_MASK 0x00FF /* WSEQ_DATA2 - [7:0] */ -#define WM8995_WSEQ_DATA2_SHIFT 0 /* WSEQ_DATA2 - [7:0] */ -#define WM8995_WSEQ_DATA2_WIDTH 8 /* WSEQ_DATA2 - [7:0] */ - -/* - * R12298 (0x300A) - Write Sequencer 10 - */ -#define WM8995_WSEQ_DATA_WIDTH2_MASK 0x0700 /* WSEQ_DATA_WIDTH2 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH2_SHIFT 8 /* WSEQ_DATA_WIDTH2 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH2_WIDTH 3 /* WSEQ_DATA_WIDTH2 - [10:8] */ -#define WM8995_WSEQ_DATA_START2_MASK 0x000F /* WSEQ_DATA_START2 - [3:0] */ -#define WM8995_WSEQ_DATA_START2_SHIFT 0 /* WSEQ_DATA_START2 - [3:0] */ -#define WM8995_WSEQ_DATA_START2_WIDTH 4 /* WSEQ_DATA_START2 - [3:0] */ - -/* - * R12299 (0x300B) - Write Sequencer 11 - */ -#define WM8995_WSEQ_EOS2 0x0100 /* WSEQ_EOS2 */ -#define WM8995_WSEQ_EOS2_MASK 0x0100 /* WSEQ_EOS2 */ -#define WM8995_WSEQ_EOS2_SHIFT 8 /* WSEQ_EOS2 */ -#define WM8995_WSEQ_EOS2_WIDTH 1 /* WSEQ_EOS2 */ -#define WM8995_WSEQ_DELAY2_MASK 0x000F /* WSEQ_DELAY2 - [3:0] */ -#define WM8995_WSEQ_DELAY2_SHIFT 0 /* WSEQ_DELAY2 - [3:0] */ -#define WM8995_WSEQ_DELAY2_WIDTH 4 /* WSEQ_DELAY2 - [3:0] */ - -/* - * R12300 (0x300C) - Write Sequencer 12 - */ -#define WM8995_WSEQ_ADDR3_MASK 0x3FFF /* WSEQ_ADDR3 - [13:0] */ -#define WM8995_WSEQ_ADDR3_SHIFT 0 /* WSEQ_ADDR3 - [13:0] */ -#define WM8995_WSEQ_ADDR3_WIDTH 14 /* WSEQ_ADDR3 - [13:0] */ - -/* - * R12301 (0x300D) - Write Sequencer 13 - */ -#define WM8995_WSEQ_DATA3_MASK 0x00FF /* WSEQ_DATA3 - [7:0] */ -#define WM8995_WSEQ_DATA3_SHIFT 0 /* WSEQ_DATA3 - [7:0] */ -#define WM8995_WSEQ_DATA3_WIDTH 8 /* WSEQ_DATA3 - [7:0] */ - -/* - * R12302 (0x300E) - Write Sequencer 14 - */ -#define WM8995_WSEQ_DATA_WIDTH3_MASK 0x0700 /* WSEQ_DATA_WIDTH3 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH3_SHIFT 8 /* WSEQ_DATA_WIDTH3 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH3_WIDTH 3 /* WSEQ_DATA_WIDTH3 - [10:8] */ -#define WM8995_WSEQ_DATA_START3_MASK 0x000F /* WSEQ_DATA_START3 - [3:0] */ -#define WM8995_WSEQ_DATA_START3_SHIFT 0 /* WSEQ_DATA_START3 - [3:0] */ -#define WM8995_WSEQ_DATA_START3_WIDTH 4 /* WSEQ_DATA_START3 - [3:0] */ - -/* - * R12303 (0x300F) - Write Sequencer 15 - */ -#define WM8995_WSEQ_EOS3 0x0100 /* WSEQ_EOS3 */ -#define WM8995_WSEQ_EOS3_MASK 0x0100 /* WSEQ_EOS3 */ -#define WM8995_WSEQ_EOS3_SHIFT 8 /* WSEQ_EOS3 */ -#define WM8995_WSEQ_EOS3_WIDTH 1 /* WSEQ_EOS3 */ -#define WM8995_WSEQ_DELAY3_MASK 0x000F /* WSEQ_DELAY3 - [3:0] */ -#define WM8995_WSEQ_DELAY3_SHIFT 0 /* WSEQ_DELAY3 - [3:0] */ -#define WM8995_WSEQ_DELAY3_WIDTH 4 /* WSEQ_DELAY3 - [3:0] */ - -/* - * R12304 (0x3010) - Write Sequencer 16 - */ -#define WM8995_WSEQ_ADDR4_MASK 0x3FFF /* WSEQ_ADDR4 - [13:0] */ -#define WM8995_WSEQ_ADDR4_SHIFT 0 /* WSEQ_ADDR4 - [13:0] */ -#define WM8995_WSEQ_ADDR4_WIDTH 14 /* WSEQ_ADDR4 - [13:0] */ - -/* - * R12305 (0x3011) - Write Sequencer 17 - */ -#define WM8995_WSEQ_DATA4_MASK 0x00FF /* WSEQ_DATA4 - [7:0] */ -#define WM8995_WSEQ_DATA4_SHIFT 0 /* WSEQ_DATA4 - [7:0] */ -#define WM8995_WSEQ_DATA4_WIDTH 8 /* WSEQ_DATA4 - [7:0] */ - -/* - * R12306 (0x3012) - Write Sequencer 18 - */ -#define WM8995_WSEQ_DATA_WIDTH4_MASK 0x0700 /* WSEQ_DATA_WIDTH4 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH4_SHIFT 8 /* WSEQ_DATA_WIDTH4 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH4_WIDTH 3 /* WSEQ_DATA_WIDTH4 - [10:8] */ -#define WM8995_WSEQ_DATA_START4_MASK 0x000F /* WSEQ_DATA_START4 - [3:0] */ -#define WM8995_WSEQ_DATA_START4_SHIFT 0 /* WSEQ_DATA_START4 - [3:0] */ -#define WM8995_WSEQ_DATA_START4_WIDTH 4 /* WSEQ_DATA_START4 - [3:0] */ - -/* - * R12307 (0x3013) - Write Sequencer 19 - */ -#define WM8995_WSEQ_EOS4 0x0100 /* WSEQ_EOS4 */ -#define WM8995_WSEQ_EOS4_MASK 0x0100 /* WSEQ_EOS4 */ -#define WM8995_WSEQ_EOS4_SHIFT 8 /* WSEQ_EOS4 */ -#define WM8995_WSEQ_EOS4_WIDTH 1 /* WSEQ_EOS4 */ -#define WM8995_WSEQ_DELAY4_MASK 0x000F /* WSEQ_DELAY4 - [3:0] */ -#define WM8995_WSEQ_DELAY4_SHIFT 0 /* WSEQ_DELAY4 - [3:0] */ -#define WM8995_WSEQ_DELAY4_WIDTH 4 /* WSEQ_DELAY4 - [3:0] */ - -/* - * R12308 (0x3014) - Write Sequencer 20 - */ -#define WM8995_WSEQ_ADDR5_MASK 0x3FFF /* WSEQ_ADDR5 - [13:0] */ -#define WM8995_WSEQ_ADDR5_SHIFT 0 /* WSEQ_ADDR5 - [13:0] */ -#define WM8995_WSEQ_ADDR5_WIDTH 14 /* WSEQ_ADDR5 - [13:0] */ - -/* - * R12309 (0x3015) - Write Sequencer 21 - */ -#define WM8995_WSEQ_DATA5_MASK 0x00FF /* WSEQ_DATA5 - [7:0] */ -#define WM8995_WSEQ_DATA5_SHIFT 0 /* WSEQ_DATA5 - [7:0] */ -#define WM8995_WSEQ_DATA5_WIDTH 8 /* WSEQ_DATA5 - [7:0] */ - -/* - * R12310 (0x3016) - Write Sequencer 22 - */ -#define WM8995_WSEQ_DATA_WIDTH5_MASK 0x0700 /* WSEQ_DATA_WIDTH5 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH5_SHIFT 8 /* WSEQ_DATA_WIDTH5 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH5_WIDTH 3 /* WSEQ_DATA_WIDTH5 - [10:8] */ -#define WM8995_WSEQ_DATA_START5_MASK 0x000F /* WSEQ_DATA_START5 - [3:0] */ -#define WM8995_WSEQ_DATA_START5_SHIFT 0 /* WSEQ_DATA_START5 - [3:0] */ -#define WM8995_WSEQ_DATA_START5_WIDTH 4 /* WSEQ_DATA_START5 - [3:0] */ - -/* - * R12311 (0x3017) - Write Sequencer 23 - */ -#define WM8995_WSEQ_EOS5 0x0100 /* WSEQ_EOS5 */ -#define WM8995_WSEQ_EOS5_MASK 0x0100 /* WSEQ_EOS5 */ -#define WM8995_WSEQ_EOS5_SHIFT 8 /* WSEQ_EOS5 */ -#define WM8995_WSEQ_EOS5_WIDTH 1 /* WSEQ_EOS5 */ -#define WM8995_WSEQ_DELAY5_MASK 0x000F /* WSEQ_DELAY5 - [3:0] */ -#define WM8995_WSEQ_DELAY5_SHIFT 0 /* WSEQ_DELAY5 - [3:0] */ -#define WM8995_WSEQ_DELAY5_WIDTH 4 /* WSEQ_DELAY5 - [3:0] */ - -/* - * R12312 (0x3018) - Write Sequencer 24 - */ -#define WM8995_WSEQ_ADDR6_MASK 0x3FFF /* WSEQ_ADDR6 - [13:0] */ -#define WM8995_WSEQ_ADDR6_SHIFT 0 /* WSEQ_ADDR6 - [13:0] */ -#define WM8995_WSEQ_ADDR6_WIDTH 14 /* WSEQ_ADDR6 - [13:0] */ - -/* - * R12313 (0x3019) - Write Sequencer 25 - */ -#define WM8995_WSEQ_DATA6_MASK 0x00FF /* WSEQ_DATA6 - [7:0] */ -#define WM8995_WSEQ_DATA6_SHIFT 0 /* WSEQ_DATA6 - [7:0] */ -#define WM8995_WSEQ_DATA6_WIDTH 8 /* WSEQ_DATA6 - [7:0] */ - -/* - * R12314 (0x301A) - Write Sequencer 26 - */ -#define WM8995_WSEQ_DATA_WIDTH6_MASK 0x0700 /* WSEQ_DATA_WIDTH6 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH6_SHIFT 8 /* WSEQ_DATA_WIDTH6 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH6_WIDTH 3 /* WSEQ_DATA_WIDTH6 - [10:8] */ -#define WM8995_WSEQ_DATA_START6_MASK 0x000F /* WSEQ_DATA_START6 - [3:0] */ -#define WM8995_WSEQ_DATA_START6_SHIFT 0 /* WSEQ_DATA_START6 - [3:0] */ -#define WM8995_WSEQ_DATA_START6_WIDTH 4 /* WSEQ_DATA_START6 - [3:0] */ - -/* - * R12315 (0x301B) - Write Sequencer 27 - */ -#define WM8995_WSEQ_EOS6 0x0100 /* WSEQ_EOS6 */ -#define WM8995_WSEQ_EOS6_MASK 0x0100 /* WSEQ_EOS6 */ -#define WM8995_WSEQ_EOS6_SHIFT 8 /* WSEQ_EOS6 */ -#define WM8995_WSEQ_EOS6_WIDTH 1 /* WSEQ_EOS6 */ -#define WM8995_WSEQ_DELAY6_MASK 0x000F /* WSEQ_DELAY6 - [3:0] */ -#define WM8995_WSEQ_DELAY6_SHIFT 0 /* WSEQ_DELAY6 - [3:0] */ -#define WM8995_WSEQ_DELAY6_WIDTH 4 /* WSEQ_DELAY6 - [3:0] */ - -/* - * R12316 (0x301C) - Write Sequencer 28 - */ -#define WM8995_WSEQ_ADDR7_MASK 0x3FFF /* WSEQ_ADDR7 - [13:0] */ -#define WM8995_WSEQ_ADDR7_SHIFT 0 /* WSEQ_ADDR7 - [13:0] */ -#define WM8995_WSEQ_ADDR7_WIDTH 14 /* WSEQ_ADDR7 - [13:0] */ - -/* - * R12317 (0x301D) - Write Sequencer 29 - */ -#define WM8995_WSEQ_DATA7_MASK 0x00FF /* WSEQ_DATA7 - [7:0] */ -#define WM8995_WSEQ_DATA7_SHIFT 0 /* WSEQ_DATA7 - [7:0] */ -#define WM8995_WSEQ_DATA7_WIDTH 8 /* WSEQ_DATA7 - [7:0] */ - -/* - * R12318 (0x301E) - Write Sequencer 30 - */ -#define WM8995_WSEQ_DATA_WIDTH7_MASK 0x0700 /* WSEQ_DATA_WIDTH7 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH7_SHIFT 8 /* WSEQ_DATA_WIDTH7 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH7_WIDTH 3 /* WSEQ_DATA_WIDTH7 - [10:8] */ -#define WM8995_WSEQ_DATA_START7_MASK 0x000F /* WSEQ_DATA_START7 - [3:0] */ -#define WM8995_WSEQ_DATA_START7_SHIFT 0 /* WSEQ_DATA_START7 - [3:0] */ -#define WM8995_WSEQ_DATA_START7_WIDTH 4 /* WSEQ_DATA_START7 - [3:0] */ - -/* - * R12319 (0x301F) - Write Sequencer 31 - */ -#define WM8995_WSEQ_EOS7 0x0100 /* WSEQ_EOS7 */ -#define WM8995_WSEQ_EOS7_MASK 0x0100 /* WSEQ_EOS7 */ -#define WM8995_WSEQ_EOS7_SHIFT 8 /* WSEQ_EOS7 */ -#define WM8995_WSEQ_EOS7_WIDTH 1 /* WSEQ_EOS7 */ -#define WM8995_WSEQ_DELAY7_MASK 0x000F /* WSEQ_DELAY7 - [3:0] */ -#define WM8995_WSEQ_DELAY7_SHIFT 0 /* WSEQ_DELAY7 - [3:0] */ -#define WM8995_WSEQ_DELAY7_WIDTH 4 /* WSEQ_DELAY7 - [3:0] */ - -/* - * R12320 (0x3020) - Write Sequencer 32 - */ -#define WM8995_WSEQ_ADDR8_MASK 0x3FFF /* WSEQ_ADDR8 - [13:0] */ -#define WM8995_WSEQ_ADDR8_SHIFT 0 /* WSEQ_ADDR8 - [13:0] */ -#define WM8995_WSEQ_ADDR8_WIDTH 14 /* WSEQ_ADDR8 - [13:0] */ - -/* - * R12321 (0x3021) - Write Sequencer 33 - */ -#define WM8995_WSEQ_DATA8_MASK 0x00FF /* WSEQ_DATA8 - [7:0] */ -#define WM8995_WSEQ_DATA8_SHIFT 0 /* WSEQ_DATA8 - [7:0] */ -#define WM8995_WSEQ_DATA8_WIDTH 8 /* WSEQ_DATA8 - [7:0] */ - -/* - * R12322 (0x3022) - Write Sequencer 34 - */ -#define WM8995_WSEQ_DATA_WIDTH8_MASK 0x0700 /* WSEQ_DATA_WIDTH8 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH8_SHIFT 8 /* WSEQ_DATA_WIDTH8 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH8_WIDTH 3 /* WSEQ_DATA_WIDTH8 - [10:8] */ -#define WM8995_WSEQ_DATA_START8_MASK 0x000F /* WSEQ_DATA_START8 - [3:0] */ -#define WM8995_WSEQ_DATA_START8_SHIFT 0 /* WSEQ_DATA_START8 - [3:0] */ -#define WM8995_WSEQ_DATA_START8_WIDTH 4 /* WSEQ_DATA_START8 - [3:0] */ - -/* - * R12323 (0x3023) - Write Sequencer 35 - */ -#define WM8995_WSEQ_EOS8 0x0100 /* WSEQ_EOS8 */ -#define WM8995_WSEQ_EOS8_MASK 0x0100 /* WSEQ_EOS8 */ -#define WM8995_WSEQ_EOS8_SHIFT 8 /* WSEQ_EOS8 */ -#define WM8995_WSEQ_EOS8_WIDTH 1 /* WSEQ_EOS8 */ -#define WM8995_WSEQ_DELAY8_MASK 0x000F /* WSEQ_DELAY8 - [3:0] */ -#define WM8995_WSEQ_DELAY8_SHIFT 0 /* WSEQ_DELAY8 - [3:0] */ -#define WM8995_WSEQ_DELAY8_WIDTH 4 /* WSEQ_DELAY8 - [3:0] */ - -/* - * R12324 (0x3024) - Write Sequencer 36 - */ -#define WM8995_WSEQ_ADDR9_MASK 0x3FFF /* WSEQ_ADDR9 - [13:0] */ -#define WM8995_WSEQ_ADDR9_SHIFT 0 /* WSEQ_ADDR9 - [13:0] */ -#define WM8995_WSEQ_ADDR9_WIDTH 14 /* WSEQ_ADDR9 - [13:0] */ - -/* - * R12325 (0x3025) - Write Sequencer 37 - */ -#define WM8995_WSEQ_DATA9_MASK 0x00FF /* WSEQ_DATA9 - [7:0] */ -#define WM8995_WSEQ_DATA9_SHIFT 0 /* WSEQ_DATA9 - [7:0] */ -#define WM8995_WSEQ_DATA9_WIDTH 8 /* WSEQ_DATA9 - [7:0] */ - -/* - * R12326 (0x3026) - Write Sequencer 38 - */ -#define WM8995_WSEQ_DATA_WIDTH9_MASK 0x0700 /* WSEQ_DATA_WIDTH9 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH9_SHIFT 8 /* WSEQ_DATA_WIDTH9 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH9_WIDTH 3 /* WSEQ_DATA_WIDTH9 - [10:8] */ -#define WM8995_WSEQ_DATA_START9_MASK 0x000F /* WSEQ_DATA_START9 - [3:0] */ -#define WM8995_WSEQ_DATA_START9_SHIFT 0 /* WSEQ_DATA_START9 - [3:0] */ -#define WM8995_WSEQ_DATA_START9_WIDTH 4 /* WSEQ_DATA_START9 - [3:0] */ - -/* - * R12327 (0x3027) - Write Sequencer 39 - */ -#define WM8995_WSEQ_EOS9 0x0100 /* WSEQ_EOS9 */ -#define WM8995_WSEQ_EOS9_MASK 0x0100 /* WSEQ_EOS9 */ -#define WM8995_WSEQ_EOS9_SHIFT 8 /* WSEQ_EOS9 */ -#define WM8995_WSEQ_EOS9_WIDTH 1 /* WSEQ_EOS9 */ -#define WM8995_WSEQ_DELAY9_MASK 0x000F /* WSEQ_DELAY9 - [3:0] */ -#define WM8995_WSEQ_DELAY9_SHIFT 0 /* WSEQ_DELAY9 - [3:0] */ -#define WM8995_WSEQ_DELAY9_WIDTH 4 /* WSEQ_DELAY9 - [3:0] */ - -/* - * R12328 (0x3028) - Write Sequencer 40 - */ -#define WM8995_WSEQ_ADDR10_MASK 0x3FFF /* WSEQ_ADDR10 - [13:0] */ -#define WM8995_WSEQ_ADDR10_SHIFT 0 /* WSEQ_ADDR10 - [13:0] */ -#define WM8995_WSEQ_ADDR10_WIDTH 14 /* WSEQ_ADDR10 - [13:0] */ - -/* - * R12329 (0x3029) - Write Sequencer 41 - */ -#define WM8995_WSEQ_DATA10_MASK 0x00FF /* WSEQ_DATA10 - [7:0] */ -#define WM8995_WSEQ_DATA10_SHIFT 0 /* WSEQ_DATA10 - [7:0] */ -#define WM8995_WSEQ_DATA10_WIDTH 8 /* WSEQ_DATA10 - [7:0] */ - -/* - * R12330 (0x302A) - Write Sequencer 42 - */ -#define WM8995_WSEQ_DATA_WIDTH10_MASK 0x0700 /* WSEQ_DATA_WIDTH10 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH10_SHIFT 8 /* WSEQ_DATA_WIDTH10 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH10_WIDTH 3 /* WSEQ_DATA_WIDTH10 - [10:8] */ -#define WM8995_WSEQ_DATA_START10_MASK 0x000F /* WSEQ_DATA_START10 - [3:0] */ -#define WM8995_WSEQ_DATA_START10_SHIFT 0 /* WSEQ_DATA_START10 - [3:0] */ -#define WM8995_WSEQ_DATA_START10_WIDTH 4 /* WSEQ_DATA_START10 - [3:0] */ - -/* - * R12331 (0x302B) - Write Sequencer 43 - */ -#define WM8995_WSEQ_EOS10 0x0100 /* WSEQ_EOS10 */ -#define WM8995_WSEQ_EOS10_MASK 0x0100 /* WSEQ_EOS10 */ -#define WM8995_WSEQ_EOS10_SHIFT 8 /* WSEQ_EOS10 */ -#define WM8995_WSEQ_EOS10_WIDTH 1 /* WSEQ_EOS10 */ -#define WM8995_WSEQ_DELAY10_MASK 0x000F /* WSEQ_DELAY10 - [3:0] */ -#define WM8995_WSEQ_DELAY10_SHIFT 0 /* WSEQ_DELAY10 - [3:0] */ -#define WM8995_WSEQ_DELAY10_WIDTH 4 /* WSEQ_DELAY10 - [3:0] */ - -/* - * R12332 (0x302C) - Write Sequencer 44 - */ -#define WM8995_WSEQ_ADDR11_MASK 0x3FFF /* WSEQ_ADDR11 - [13:0] */ -#define WM8995_WSEQ_ADDR11_SHIFT 0 /* WSEQ_ADDR11 - [13:0] */ -#define WM8995_WSEQ_ADDR11_WIDTH 14 /* WSEQ_ADDR11 - [13:0] */ - -/* - * R12333 (0x302D) - Write Sequencer 45 - */ -#define WM8995_WSEQ_DATA11_MASK 0x00FF /* WSEQ_DATA11 - [7:0] */ -#define WM8995_WSEQ_DATA11_SHIFT 0 /* WSEQ_DATA11 - [7:0] */ -#define WM8995_WSEQ_DATA11_WIDTH 8 /* WSEQ_DATA11 - [7:0] */ - -/* - * R12334 (0x302E) - Write Sequencer 46 - */ -#define WM8995_WSEQ_DATA_WIDTH11_MASK 0x0700 /* WSEQ_DATA_WIDTH11 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH11_SHIFT 8 /* WSEQ_DATA_WIDTH11 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH11_WIDTH 3 /* WSEQ_DATA_WIDTH11 - [10:8] */ -#define WM8995_WSEQ_DATA_START11_MASK 0x000F /* WSEQ_DATA_START11 - [3:0] */ -#define WM8995_WSEQ_DATA_START11_SHIFT 0 /* WSEQ_DATA_START11 - [3:0] */ -#define WM8995_WSEQ_DATA_START11_WIDTH 4 /* WSEQ_DATA_START11 - [3:0] */ - -/* - * R12335 (0x302F) - Write Sequencer 47 - */ -#define WM8995_WSEQ_EOS11 0x0100 /* WSEQ_EOS11 */ -#define WM8995_WSEQ_EOS11_MASK 0x0100 /* WSEQ_EOS11 */ -#define WM8995_WSEQ_EOS11_SHIFT 8 /* WSEQ_EOS11 */ -#define WM8995_WSEQ_EOS11_WIDTH 1 /* WSEQ_EOS11 */ -#define WM8995_WSEQ_DELAY11_MASK 0x000F /* WSEQ_DELAY11 - [3:0] */ -#define WM8995_WSEQ_DELAY11_SHIFT 0 /* WSEQ_DELAY11 - [3:0] */ -#define WM8995_WSEQ_DELAY11_WIDTH 4 /* WSEQ_DELAY11 - [3:0] */ - -/* - * R12336 (0x3030) - Write Sequencer 48 - */ -#define WM8995_WSEQ_ADDR12_MASK 0x3FFF /* WSEQ_ADDR12 - [13:0] */ -#define WM8995_WSEQ_ADDR12_SHIFT 0 /* WSEQ_ADDR12 - [13:0] */ -#define WM8995_WSEQ_ADDR12_WIDTH 14 /* WSEQ_ADDR12 - [13:0] */ - -/* - * R12337 (0x3031) - Write Sequencer 49 - */ -#define WM8995_WSEQ_DATA12_MASK 0x00FF /* WSEQ_DATA12 - [7:0] */ -#define WM8995_WSEQ_DATA12_SHIFT 0 /* WSEQ_DATA12 - [7:0] */ -#define WM8995_WSEQ_DATA12_WIDTH 8 /* WSEQ_DATA12 - [7:0] */ - -/* - * R12338 (0x3032) - Write Sequencer 50 - */ -#define WM8995_WSEQ_DATA_WIDTH12_MASK 0x0700 /* WSEQ_DATA_WIDTH12 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH12_SHIFT 8 /* WSEQ_DATA_WIDTH12 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH12_WIDTH 3 /* WSEQ_DATA_WIDTH12 - [10:8] */ -#define WM8995_WSEQ_DATA_START12_MASK 0x000F /* WSEQ_DATA_START12 - [3:0] */ -#define WM8995_WSEQ_DATA_START12_SHIFT 0 /* WSEQ_DATA_START12 - [3:0] */ -#define WM8995_WSEQ_DATA_START12_WIDTH 4 /* WSEQ_DATA_START12 - [3:0] */ - -/* - * R12339 (0x3033) - Write Sequencer 51 - */ -#define WM8995_WSEQ_EOS12 0x0100 /* WSEQ_EOS12 */ -#define WM8995_WSEQ_EOS12_MASK 0x0100 /* WSEQ_EOS12 */ -#define WM8995_WSEQ_EOS12_SHIFT 8 /* WSEQ_EOS12 */ -#define WM8995_WSEQ_EOS12_WIDTH 1 /* WSEQ_EOS12 */ -#define WM8995_WSEQ_DELAY12_MASK 0x000F /* WSEQ_DELAY12 - [3:0] */ -#define WM8995_WSEQ_DELAY12_SHIFT 0 /* WSEQ_DELAY12 - [3:0] */ -#define WM8995_WSEQ_DELAY12_WIDTH 4 /* WSEQ_DELAY12 - [3:0] */ - -/* - * R12340 (0x3034) - Write Sequencer 52 - */ -#define WM8995_WSEQ_ADDR13_MASK 0x3FFF /* WSEQ_ADDR13 - [13:0] */ -#define WM8995_WSEQ_ADDR13_SHIFT 0 /* WSEQ_ADDR13 - [13:0] */ -#define WM8995_WSEQ_ADDR13_WIDTH 14 /* WSEQ_ADDR13 - [13:0] */ - -/* - * R12341 (0x3035) - Write Sequencer 53 - */ -#define WM8995_WSEQ_DATA13_MASK 0x00FF /* WSEQ_DATA13 - [7:0] */ -#define WM8995_WSEQ_DATA13_SHIFT 0 /* WSEQ_DATA13 - [7:0] */ -#define WM8995_WSEQ_DATA13_WIDTH 8 /* WSEQ_DATA13 - [7:0] */ - -/* - * R12342 (0x3036) - Write Sequencer 54 - */ -#define WM8995_WSEQ_DATA_WIDTH13_MASK 0x0700 /* WSEQ_DATA_WIDTH13 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH13_SHIFT 8 /* WSEQ_DATA_WIDTH13 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH13_WIDTH 3 /* WSEQ_DATA_WIDTH13 - [10:8] */ -#define WM8995_WSEQ_DATA_START13_MASK 0x000F /* WSEQ_DATA_START13 - [3:0] */ -#define WM8995_WSEQ_DATA_START13_SHIFT 0 /* WSEQ_DATA_START13 - [3:0] */ -#define WM8995_WSEQ_DATA_START13_WIDTH 4 /* WSEQ_DATA_START13 - [3:0] */ - -/* - * R12343 (0x3037) - Write Sequencer 55 - */ -#define WM8995_WSEQ_EOS13 0x0100 /* WSEQ_EOS13 */ -#define WM8995_WSEQ_EOS13_MASK 0x0100 /* WSEQ_EOS13 */ -#define WM8995_WSEQ_EOS13_SHIFT 8 /* WSEQ_EOS13 */ -#define WM8995_WSEQ_EOS13_WIDTH 1 /* WSEQ_EOS13 */ -#define WM8995_WSEQ_DELAY13_MASK 0x000F /* WSEQ_DELAY13 - [3:0] */ -#define WM8995_WSEQ_DELAY13_SHIFT 0 /* WSEQ_DELAY13 - [3:0] */ -#define WM8995_WSEQ_DELAY13_WIDTH 4 /* WSEQ_DELAY13 - [3:0] */ - -/* - * R12344 (0x3038) - Write Sequencer 56 - */ -#define WM8995_WSEQ_ADDR14_MASK 0x3FFF /* WSEQ_ADDR14 - [13:0] */ -#define WM8995_WSEQ_ADDR14_SHIFT 0 /* WSEQ_ADDR14 - [13:0] */ -#define WM8995_WSEQ_ADDR14_WIDTH 14 /* WSEQ_ADDR14 - [13:0] */ - -/* - * R12345 (0x3039) - Write Sequencer 57 - */ -#define WM8995_WSEQ_DATA14_MASK 0x00FF /* WSEQ_DATA14 - [7:0] */ -#define WM8995_WSEQ_DATA14_SHIFT 0 /* WSEQ_DATA14 - [7:0] */ -#define WM8995_WSEQ_DATA14_WIDTH 8 /* WSEQ_DATA14 - [7:0] */ - -/* - * R12346 (0x303A) - Write Sequencer 58 - */ -#define WM8995_WSEQ_DATA_WIDTH14_MASK 0x0700 /* WSEQ_DATA_WIDTH14 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH14_SHIFT 8 /* WSEQ_DATA_WIDTH14 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH14_WIDTH 3 /* WSEQ_DATA_WIDTH14 - [10:8] */ -#define WM8995_WSEQ_DATA_START14_MASK 0x000F /* WSEQ_DATA_START14 - [3:0] */ -#define WM8995_WSEQ_DATA_START14_SHIFT 0 /* WSEQ_DATA_START14 - [3:0] */ -#define WM8995_WSEQ_DATA_START14_WIDTH 4 /* WSEQ_DATA_START14 - [3:0] */ - -/* - * R12347 (0x303B) - Write Sequencer 59 - */ -#define WM8995_WSEQ_EOS14 0x0100 /* WSEQ_EOS14 */ -#define WM8995_WSEQ_EOS14_MASK 0x0100 /* WSEQ_EOS14 */ -#define WM8995_WSEQ_EOS14_SHIFT 8 /* WSEQ_EOS14 */ -#define WM8995_WSEQ_EOS14_WIDTH 1 /* WSEQ_EOS14 */ -#define WM8995_WSEQ_DELAY14_MASK 0x000F /* WSEQ_DELAY14 - [3:0] */ -#define WM8995_WSEQ_DELAY14_SHIFT 0 /* WSEQ_DELAY14 - [3:0] */ -#define WM8995_WSEQ_DELAY14_WIDTH 4 /* WSEQ_DELAY14 - [3:0] */ - -/* - * R12348 (0x303C) - Write Sequencer 60 - */ -#define WM8995_WSEQ_ADDR15_MASK 0x3FFF /* WSEQ_ADDR15 - [13:0] */ -#define WM8995_WSEQ_ADDR15_SHIFT 0 /* WSEQ_ADDR15 - [13:0] */ -#define WM8995_WSEQ_ADDR15_WIDTH 14 /* WSEQ_ADDR15 - [13:0] */ - -/* - * R12349 (0x303D) - Write Sequencer 61 - */ -#define WM8995_WSEQ_DATA15_MASK 0x00FF /* WSEQ_DATA15 - [7:0] */ -#define WM8995_WSEQ_DATA15_SHIFT 0 /* WSEQ_DATA15 - [7:0] */ -#define WM8995_WSEQ_DATA15_WIDTH 8 /* WSEQ_DATA15 - [7:0] */ - -/* - * R12350 (0x303E) - Write Sequencer 62 - */ -#define WM8995_WSEQ_DATA_WIDTH15_MASK 0x0700 /* WSEQ_DATA_WIDTH15 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH15_SHIFT 8 /* WSEQ_DATA_WIDTH15 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH15_WIDTH 3 /* WSEQ_DATA_WIDTH15 - [10:8] */ -#define WM8995_WSEQ_DATA_START15_MASK 0x000F /* WSEQ_DATA_START15 - [3:0] */ -#define WM8995_WSEQ_DATA_START15_SHIFT 0 /* WSEQ_DATA_START15 - [3:0] */ -#define WM8995_WSEQ_DATA_START15_WIDTH 4 /* WSEQ_DATA_START15 - [3:0] */ - -/* - * R12351 (0x303F) - Write Sequencer 63 - */ -#define WM8995_WSEQ_EOS15 0x0100 /* WSEQ_EOS15 */ -#define WM8995_WSEQ_EOS15_MASK 0x0100 /* WSEQ_EOS15 */ -#define WM8995_WSEQ_EOS15_SHIFT 8 /* WSEQ_EOS15 */ -#define WM8995_WSEQ_EOS15_WIDTH 1 /* WSEQ_EOS15 */ -#define WM8995_WSEQ_DELAY15_MASK 0x000F /* WSEQ_DELAY15 - [3:0] */ -#define WM8995_WSEQ_DELAY15_SHIFT 0 /* WSEQ_DELAY15 - [3:0] */ -#define WM8995_WSEQ_DELAY15_WIDTH 4 /* WSEQ_DELAY15 - [3:0] */ - -/* - * R12352 (0x3040) - Write Sequencer 64 - */ -#define WM8995_WSEQ_ADDR16_MASK 0x3FFF /* WSEQ_ADDR16 - [13:0] */ -#define WM8995_WSEQ_ADDR16_SHIFT 0 /* WSEQ_ADDR16 - [13:0] */ -#define WM8995_WSEQ_ADDR16_WIDTH 14 /* WSEQ_ADDR16 - [13:0] */ - -/* - * R12353 (0x3041) - Write Sequencer 65 - */ -#define WM8995_WSEQ_DATA16_MASK 0x00FF /* WSEQ_DATA16 - [7:0] */ -#define WM8995_WSEQ_DATA16_SHIFT 0 /* WSEQ_DATA16 - [7:0] */ -#define WM8995_WSEQ_DATA16_WIDTH 8 /* WSEQ_DATA16 - [7:0] */ - -/* - * R12354 (0x3042) - Write Sequencer 66 - */ -#define WM8995_WSEQ_DATA_WIDTH16_MASK 0x0700 /* WSEQ_DATA_WIDTH16 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH16_SHIFT 8 /* WSEQ_DATA_WIDTH16 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH16_WIDTH 3 /* WSEQ_DATA_WIDTH16 - [10:8] */ -#define WM8995_WSEQ_DATA_START16_MASK 0x000F /* WSEQ_DATA_START16 - [3:0] */ -#define WM8995_WSEQ_DATA_START16_SHIFT 0 /* WSEQ_DATA_START16 - [3:0] */ -#define WM8995_WSEQ_DATA_START16_WIDTH 4 /* WSEQ_DATA_START16 - [3:0] */ - -/* - * R12355 (0x3043) - Write Sequencer 67 - */ -#define WM8995_WSEQ_EOS16 0x0100 /* WSEQ_EOS16 */ -#define WM8995_WSEQ_EOS16_MASK 0x0100 /* WSEQ_EOS16 */ -#define WM8995_WSEQ_EOS16_SHIFT 8 /* WSEQ_EOS16 */ -#define WM8995_WSEQ_EOS16_WIDTH 1 /* WSEQ_EOS16 */ -#define WM8995_WSEQ_DELAY16_MASK 0x000F /* WSEQ_DELAY16 - [3:0] */ -#define WM8995_WSEQ_DELAY16_SHIFT 0 /* WSEQ_DELAY16 - [3:0] */ -#define WM8995_WSEQ_DELAY16_WIDTH 4 /* WSEQ_DELAY16 - [3:0] */ - -/* - * R12356 (0x3044) - Write Sequencer 68 - */ -#define WM8995_WSEQ_ADDR17_MASK 0x3FFF /* WSEQ_ADDR17 - [13:0] */ -#define WM8995_WSEQ_ADDR17_SHIFT 0 /* WSEQ_ADDR17 - [13:0] */ -#define WM8995_WSEQ_ADDR17_WIDTH 14 /* WSEQ_ADDR17 - [13:0] */ - -/* - * R12357 (0x3045) - Write Sequencer 69 - */ -#define WM8995_WSEQ_DATA17_MASK 0x00FF /* WSEQ_DATA17 - [7:0] */ -#define WM8995_WSEQ_DATA17_SHIFT 0 /* WSEQ_DATA17 - [7:0] */ -#define WM8995_WSEQ_DATA17_WIDTH 8 /* WSEQ_DATA17 - [7:0] */ - -/* - * R12358 (0x3046) - Write Sequencer 70 - */ -#define WM8995_WSEQ_DATA_WIDTH17_MASK 0x0700 /* WSEQ_DATA_WIDTH17 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH17_SHIFT 8 /* WSEQ_DATA_WIDTH17 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH17_WIDTH 3 /* WSEQ_DATA_WIDTH17 - [10:8] */ -#define WM8995_WSEQ_DATA_START17_MASK 0x000F /* WSEQ_DATA_START17 - [3:0] */ -#define WM8995_WSEQ_DATA_START17_SHIFT 0 /* WSEQ_DATA_START17 - [3:0] */ -#define WM8995_WSEQ_DATA_START17_WIDTH 4 /* WSEQ_DATA_START17 - [3:0] */ - -/* - * R12359 (0x3047) - Write Sequencer 71 - */ -#define WM8995_WSEQ_EOS17 0x0100 /* WSEQ_EOS17 */ -#define WM8995_WSEQ_EOS17_MASK 0x0100 /* WSEQ_EOS17 */ -#define WM8995_WSEQ_EOS17_SHIFT 8 /* WSEQ_EOS17 */ -#define WM8995_WSEQ_EOS17_WIDTH 1 /* WSEQ_EOS17 */ -#define WM8995_WSEQ_DELAY17_MASK 0x000F /* WSEQ_DELAY17 - [3:0] */ -#define WM8995_WSEQ_DELAY17_SHIFT 0 /* WSEQ_DELAY17 - [3:0] */ -#define WM8995_WSEQ_DELAY17_WIDTH 4 /* WSEQ_DELAY17 - [3:0] */ - -/* - * R12360 (0x3048) - Write Sequencer 72 - */ -#define WM8995_WSEQ_ADDR18_MASK 0x3FFF /* WSEQ_ADDR18 - [13:0] */ -#define WM8995_WSEQ_ADDR18_SHIFT 0 /* WSEQ_ADDR18 - [13:0] */ -#define WM8995_WSEQ_ADDR18_WIDTH 14 /* WSEQ_ADDR18 - [13:0] */ - -/* - * R12361 (0x3049) - Write Sequencer 73 - */ -#define WM8995_WSEQ_DATA18_MASK 0x00FF /* WSEQ_DATA18 - [7:0] */ -#define WM8995_WSEQ_DATA18_SHIFT 0 /* WSEQ_DATA18 - [7:0] */ -#define WM8995_WSEQ_DATA18_WIDTH 8 /* WSEQ_DATA18 - [7:0] */ - -/* - * R12362 (0x304A) - Write Sequencer 74 - */ -#define WM8995_WSEQ_DATA_WIDTH18_MASK 0x0700 /* WSEQ_DATA_WIDTH18 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH18_SHIFT 8 /* WSEQ_DATA_WIDTH18 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH18_WIDTH 3 /* WSEQ_DATA_WIDTH18 - [10:8] */ -#define WM8995_WSEQ_DATA_START18_MASK 0x000F /* WSEQ_DATA_START18 - [3:0] */ -#define WM8995_WSEQ_DATA_START18_SHIFT 0 /* WSEQ_DATA_START18 - [3:0] */ -#define WM8995_WSEQ_DATA_START18_WIDTH 4 /* WSEQ_DATA_START18 - [3:0] */ - -/* - * R12363 (0x304B) - Write Sequencer 75 - */ -#define WM8995_WSEQ_EOS18 0x0100 /* WSEQ_EOS18 */ -#define WM8995_WSEQ_EOS18_MASK 0x0100 /* WSEQ_EOS18 */ -#define WM8995_WSEQ_EOS18_SHIFT 8 /* WSEQ_EOS18 */ -#define WM8995_WSEQ_EOS18_WIDTH 1 /* WSEQ_EOS18 */ -#define WM8995_WSEQ_DELAY18_MASK 0x000F /* WSEQ_DELAY18 - [3:0] */ -#define WM8995_WSEQ_DELAY18_SHIFT 0 /* WSEQ_DELAY18 - [3:0] */ -#define WM8995_WSEQ_DELAY18_WIDTH 4 /* WSEQ_DELAY18 - [3:0] */ - -/* - * R12364 (0x304C) - Write Sequencer 76 - */ -#define WM8995_WSEQ_ADDR19_MASK 0x3FFF /* WSEQ_ADDR19 - [13:0] */ -#define WM8995_WSEQ_ADDR19_SHIFT 0 /* WSEQ_ADDR19 - [13:0] */ -#define WM8995_WSEQ_ADDR19_WIDTH 14 /* WSEQ_ADDR19 - [13:0] */ - -/* - * R12365 (0x304D) - Write Sequencer 77 - */ -#define WM8995_WSEQ_DATA19_MASK 0x00FF /* WSEQ_DATA19 - [7:0] */ -#define WM8995_WSEQ_DATA19_SHIFT 0 /* WSEQ_DATA19 - [7:0] */ -#define WM8995_WSEQ_DATA19_WIDTH 8 /* WSEQ_DATA19 - [7:0] */ - -/* - * R12366 (0x304E) - Write Sequencer 78 - */ -#define WM8995_WSEQ_DATA_WIDTH19_MASK 0x0700 /* WSEQ_DATA_WIDTH19 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH19_SHIFT 8 /* WSEQ_DATA_WIDTH19 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH19_WIDTH 3 /* WSEQ_DATA_WIDTH19 - [10:8] */ -#define WM8995_WSEQ_DATA_START19_MASK 0x000F /* WSEQ_DATA_START19 - [3:0] */ -#define WM8995_WSEQ_DATA_START19_SHIFT 0 /* WSEQ_DATA_START19 - [3:0] */ -#define WM8995_WSEQ_DATA_START19_WIDTH 4 /* WSEQ_DATA_START19 - [3:0] */ - -/* - * R12367 (0x304F) - Write Sequencer 79 - */ -#define WM8995_WSEQ_EOS19 0x0100 /* WSEQ_EOS19 */ -#define WM8995_WSEQ_EOS19_MASK 0x0100 /* WSEQ_EOS19 */ -#define WM8995_WSEQ_EOS19_SHIFT 8 /* WSEQ_EOS19 */ -#define WM8995_WSEQ_EOS19_WIDTH 1 /* WSEQ_EOS19 */ -#define WM8995_WSEQ_DELAY19_MASK 0x000F /* WSEQ_DELAY19 - [3:0] */ -#define WM8995_WSEQ_DELAY19_SHIFT 0 /* WSEQ_DELAY19 - [3:0] */ -#define WM8995_WSEQ_DELAY19_WIDTH 4 /* WSEQ_DELAY19 - [3:0] */ - -/* - * R12368 (0x3050) - Write Sequencer 80 - */ -#define WM8995_WSEQ_ADDR20_MASK 0x3FFF /* WSEQ_ADDR20 - [13:0] */ -#define WM8995_WSEQ_ADDR20_SHIFT 0 /* WSEQ_ADDR20 - [13:0] */ -#define WM8995_WSEQ_ADDR20_WIDTH 14 /* WSEQ_ADDR20 - [13:0] */ - -/* - * R12369 (0x3051) - Write Sequencer 81 - */ -#define WM8995_WSEQ_DATA20_MASK 0x00FF /* WSEQ_DATA20 - [7:0] */ -#define WM8995_WSEQ_DATA20_SHIFT 0 /* WSEQ_DATA20 - [7:0] */ -#define WM8995_WSEQ_DATA20_WIDTH 8 /* WSEQ_DATA20 - [7:0] */ - -/* - * R12370 (0x3052) - Write Sequencer 82 - */ -#define WM8995_WSEQ_DATA_WIDTH20_MASK 0x0700 /* WSEQ_DATA_WIDTH20 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH20_SHIFT 8 /* WSEQ_DATA_WIDTH20 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH20_WIDTH 3 /* WSEQ_DATA_WIDTH20 - [10:8] */ -#define WM8995_WSEQ_DATA_START20_MASK 0x000F /* WSEQ_DATA_START20 - [3:0] */ -#define WM8995_WSEQ_DATA_START20_SHIFT 0 /* WSEQ_DATA_START20 - [3:0] */ -#define WM8995_WSEQ_DATA_START20_WIDTH 4 /* WSEQ_DATA_START20 - [3:0] */ - -/* - * R12371 (0x3053) - Write Sequencer 83 - */ -#define WM8995_WSEQ_EOS20 0x0100 /* WSEQ_EOS20 */ -#define WM8995_WSEQ_EOS20_MASK 0x0100 /* WSEQ_EOS20 */ -#define WM8995_WSEQ_EOS20_SHIFT 8 /* WSEQ_EOS20 */ -#define WM8995_WSEQ_EOS20_WIDTH 1 /* WSEQ_EOS20 */ -#define WM8995_WSEQ_DELAY20_MASK 0x000F /* WSEQ_DELAY20 - [3:0] */ -#define WM8995_WSEQ_DELAY20_SHIFT 0 /* WSEQ_DELAY20 - [3:0] */ -#define WM8995_WSEQ_DELAY20_WIDTH 4 /* WSEQ_DELAY20 - [3:0] */ - -/* - * R12372 (0x3054) - Write Sequencer 84 - */ -#define WM8995_WSEQ_ADDR21_MASK 0x3FFF /* WSEQ_ADDR21 - [13:0] */ -#define WM8995_WSEQ_ADDR21_SHIFT 0 /* WSEQ_ADDR21 - [13:0] */ -#define WM8995_WSEQ_ADDR21_WIDTH 14 /* WSEQ_ADDR21 - [13:0] */ - -/* - * R12373 (0x3055) - Write Sequencer 85 - */ -#define WM8995_WSEQ_DATA21_MASK 0x00FF /* WSEQ_DATA21 - [7:0] */ -#define WM8995_WSEQ_DATA21_SHIFT 0 /* WSEQ_DATA21 - [7:0] */ -#define WM8995_WSEQ_DATA21_WIDTH 8 /* WSEQ_DATA21 - [7:0] */ - -/* - * R12374 (0x3056) - Write Sequencer 86 - */ -#define WM8995_WSEQ_DATA_WIDTH21_MASK 0x0700 /* WSEQ_DATA_WIDTH21 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH21_SHIFT 8 /* WSEQ_DATA_WIDTH21 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH21_WIDTH 3 /* WSEQ_DATA_WIDTH21 - [10:8] */ -#define WM8995_WSEQ_DATA_START21_MASK 0x000F /* WSEQ_DATA_START21 - [3:0] */ -#define WM8995_WSEQ_DATA_START21_SHIFT 0 /* WSEQ_DATA_START21 - [3:0] */ -#define WM8995_WSEQ_DATA_START21_WIDTH 4 /* WSEQ_DATA_START21 - [3:0] */ - -/* - * R12375 (0x3057) - Write Sequencer 87 - */ -#define WM8995_WSEQ_EOS21 0x0100 /* WSEQ_EOS21 */ -#define WM8995_WSEQ_EOS21_MASK 0x0100 /* WSEQ_EOS21 */ -#define WM8995_WSEQ_EOS21_SHIFT 8 /* WSEQ_EOS21 */ -#define WM8995_WSEQ_EOS21_WIDTH 1 /* WSEQ_EOS21 */ -#define WM8995_WSEQ_DELAY21_MASK 0x000F /* WSEQ_DELAY21 - [3:0] */ -#define WM8995_WSEQ_DELAY21_SHIFT 0 /* WSEQ_DELAY21 - [3:0] */ -#define WM8995_WSEQ_DELAY21_WIDTH 4 /* WSEQ_DELAY21 - [3:0] */ - -/* - * R12376 (0x3058) - Write Sequencer 88 - */ -#define WM8995_WSEQ_ADDR22_MASK 0x3FFF /* WSEQ_ADDR22 - [13:0] */ -#define WM8995_WSEQ_ADDR22_SHIFT 0 /* WSEQ_ADDR22 - [13:0] */ -#define WM8995_WSEQ_ADDR22_WIDTH 14 /* WSEQ_ADDR22 - [13:0] */ - -/* - * R12377 (0x3059) - Write Sequencer 89 - */ -#define WM8995_WSEQ_DATA22_MASK 0x00FF /* WSEQ_DATA22 - [7:0] */ -#define WM8995_WSEQ_DATA22_SHIFT 0 /* WSEQ_DATA22 - [7:0] */ -#define WM8995_WSEQ_DATA22_WIDTH 8 /* WSEQ_DATA22 - [7:0] */ - -/* - * R12378 (0x305A) - Write Sequencer 90 - */ -#define WM8995_WSEQ_DATA_WIDTH22_MASK 0x0700 /* WSEQ_DATA_WIDTH22 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH22_SHIFT 8 /* WSEQ_DATA_WIDTH22 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH22_WIDTH 3 /* WSEQ_DATA_WIDTH22 - [10:8] */ -#define WM8995_WSEQ_DATA_START22_MASK 0x000F /* WSEQ_DATA_START22 - [3:0] */ -#define WM8995_WSEQ_DATA_START22_SHIFT 0 /* WSEQ_DATA_START22 - [3:0] */ -#define WM8995_WSEQ_DATA_START22_WIDTH 4 /* WSEQ_DATA_START22 - [3:0] */ - -/* - * R12379 (0x305B) - Write Sequencer 91 - */ -#define WM8995_WSEQ_EOS22 0x0100 /* WSEQ_EOS22 */ -#define WM8995_WSEQ_EOS22_MASK 0x0100 /* WSEQ_EOS22 */ -#define WM8995_WSEQ_EOS22_SHIFT 8 /* WSEQ_EOS22 */ -#define WM8995_WSEQ_EOS22_WIDTH 1 /* WSEQ_EOS22 */ -#define WM8995_WSEQ_DELAY22_MASK 0x000F /* WSEQ_DELAY22 - [3:0] */ -#define WM8995_WSEQ_DELAY22_SHIFT 0 /* WSEQ_DELAY22 - [3:0] */ -#define WM8995_WSEQ_DELAY22_WIDTH 4 /* WSEQ_DELAY22 - [3:0] */ - -/* - * R12380 (0x305C) - Write Sequencer 92 - */ -#define WM8995_WSEQ_ADDR23_MASK 0x3FFF /* WSEQ_ADDR23 - [13:0] */ -#define WM8995_WSEQ_ADDR23_SHIFT 0 /* WSEQ_ADDR23 - [13:0] */ -#define WM8995_WSEQ_ADDR23_WIDTH 14 /* WSEQ_ADDR23 - [13:0] */ - -/* - * R12381 (0x305D) - Write Sequencer 93 - */ -#define WM8995_WSEQ_DATA23_MASK 0x00FF /* WSEQ_DATA23 - [7:0] */ -#define WM8995_WSEQ_DATA23_SHIFT 0 /* WSEQ_DATA23 - [7:0] */ -#define WM8995_WSEQ_DATA23_WIDTH 8 /* WSEQ_DATA23 - [7:0] */ - -/* - * R12382 (0x305E) - Write Sequencer 94 - */ -#define WM8995_WSEQ_DATA_WIDTH23_MASK 0x0700 /* WSEQ_DATA_WIDTH23 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH23_SHIFT 8 /* WSEQ_DATA_WIDTH23 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH23_WIDTH 3 /* WSEQ_DATA_WIDTH23 - [10:8] */ -#define WM8995_WSEQ_DATA_START23_MASK 0x000F /* WSEQ_DATA_START23 - [3:0] */ -#define WM8995_WSEQ_DATA_START23_SHIFT 0 /* WSEQ_DATA_START23 - [3:0] */ -#define WM8995_WSEQ_DATA_START23_WIDTH 4 /* WSEQ_DATA_START23 - [3:0] */ - -/* - * R12383 (0x305F) - Write Sequencer 95 - */ -#define WM8995_WSEQ_EOS23 0x0100 /* WSEQ_EOS23 */ -#define WM8995_WSEQ_EOS23_MASK 0x0100 /* WSEQ_EOS23 */ -#define WM8995_WSEQ_EOS23_SHIFT 8 /* WSEQ_EOS23 */ -#define WM8995_WSEQ_EOS23_WIDTH 1 /* WSEQ_EOS23 */ -#define WM8995_WSEQ_DELAY23_MASK 0x000F /* WSEQ_DELAY23 - [3:0] */ -#define WM8995_WSEQ_DELAY23_SHIFT 0 /* WSEQ_DELAY23 - [3:0] */ -#define WM8995_WSEQ_DELAY23_WIDTH 4 /* WSEQ_DELAY23 - [3:0] */ - -/* - * R12384 (0x3060) - Write Sequencer 96 - */ -#define WM8995_WSEQ_ADDR24_MASK 0x3FFF /* WSEQ_ADDR24 - [13:0] */ -#define WM8995_WSEQ_ADDR24_SHIFT 0 /* WSEQ_ADDR24 - [13:0] */ -#define WM8995_WSEQ_ADDR24_WIDTH 14 /* WSEQ_ADDR24 - [13:0] */ - -/* - * R12385 (0x3061) - Write Sequencer 97 - */ -#define WM8995_WSEQ_DATA24_MASK 0x00FF /* WSEQ_DATA24 - [7:0] */ -#define WM8995_WSEQ_DATA24_SHIFT 0 /* WSEQ_DATA24 - [7:0] */ -#define WM8995_WSEQ_DATA24_WIDTH 8 /* WSEQ_DATA24 - [7:0] */ - -/* - * R12386 (0x3062) - Write Sequencer 98 - */ -#define WM8995_WSEQ_DATA_WIDTH24_MASK 0x0700 /* WSEQ_DATA_WIDTH24 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH24_SHIFT 8 /* WSEQ_DATA_WIDTH24 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH24_WIDTH 3 /* WSEQ_DATA_WIDTH24 - [10:8] */ -#define WM8995_WSEQ_DATA_START24_MASK 0x000F /* WSEQ_DATA_START24 - [3:0] */ -#define WM8995_WSEQ_DATA_START24_SHIFT 0 /* WSEQ_DATA_START24 - [3:0] */ -#define WM8995_WSEQ_DATA_START24_WIDTH 4 /* WSEQ_DATA_START24 - [3:0] */ - -/* - * R12387 (0x3063) - Write Sequencer 99 - */ -#define WM8995_WSEQ_EOS24 0x0100 /* WSEQ_EOS24 */ -#define WM8995_WSEQ_EOS24_MASK 0x0100 /* WSEQ_EOS24 */ -#define WM8995_WSEQ_EOS24_SHIFT 8 /* WSEQ_EOS24 */ -#define WM8995_WSEQ_EOS24_WIDTH 1 /* WSEQ_EOS24 */ -#define WM8995_WSEQ_DELAY24_MASK 0x000F /* WSEQ_DELAY24 - [3:0] */ -#define WM8995_WSEQ_DELAY24_SHIFT 0 /* WSEQ_DELAY24 - [3:0] */ -#define WM8995_WSEQ_DELAY24_WIDTH 4 /* WSEQ_DELAY24 - [3:0] */ - -/* - * R12388 (0x3064) - Write Sequencer 100 - */ -#define WM8995_WSEQ_ADDR25_MASK 0x3FFF /* WSEQ_ADDR25 - [13:0] */ -#define WM8995_WSEQ_ADDR25_SHIFT 0 /* WSEQ_ADDR25 - [13:0] */ -#define WM8995_WSEQ_ADDR25_WIDTH 14 /* WSEQ_ADDR25 - [13:0] */ - -/* - * R12389 (0x3065) - Write Sequencer 101 - */ -#define WM8995_WSEQ_DATA25_MASK 0x00FF /* WSEQ_DATA25 - [7:0] */ -#define WM8995_WSEQ_DATA25_SHIFT 0 /* WSEQ_DATA25 - [7:0] */ -#define WM8995_WSEQ_DATA25_WIDTH 8 /* WSEQ_DATA25 - [7:0] */ - -/* - * R12390 (0x3066) - Write Sequencer 102 - */ -#define WM8995_WSEQ_DATA_WIDTH25_MASK 0x0700 /* WSEQ_DATA_WIDTH25 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH25_SHIFT 8 /* WSEQ_DATA_WIDTH25 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH25_WIDTH 3 /* WSEQ_DATA_WIDTH25 - [10:8] */ -#define WM8995_WSEQ_DATA_START25_MASK 0x000F /* WSEQ_DATA_START25 - [3:0] */ -#define WM8995_WSEQ_DATA_START25_SHIFT 0 /* WSEQ_DATA_START25 - [3:0] */ -#define WM8995_WSEQ_DATA_START25_WIDTH 4 /* WSEQ_DATA_START25 - [3:0] */ - -/* - * R12391 (0x3067) - Write Sequencer 103 - */ -#define WM8995_WSEQ_EOS25 0x0100 /* WSEQ_EOS25 */ -#define WM8995_WSEQ_EOS25_MASK 0x0100 /* WSEQ_EOS25 */ -#define WM8995_WSEQ_EOS25_SHIFT 8 /* WSEQ_EOS25 */ -#define WM8995_WSEQ_EOS25_WIDTH 1 /* WSEQ_EOS25 */ -#define WM8995_WSEQ_DELAY25_MASK 0x000F /* WSEQ_DELAY25 - [3:0] */ -#define WM8995_WSEQ_DELAY25_SHIFT 0 /* WSEQ_DELAY25 - [3:0] */ -#define WM8995_WSEQ_DELAY25_WIDTH 4 /* WSEQ_DELAY25 - [3:0] */ - -/* - * R12392 (0x3068) - Write Sequencer 104 - */ -#define WM8995_WSEQ_ADDR26_MASK 0x3FFF /* WSEQ_ADDR26 - [13:0] */ -#define WM8995_WSEQ_ADDR26_SHIFT 0 /* WSEQ_ADDR26 - [13:0] */ -#define WM8995_WSEQ_ADDR26_WIDTH 14 /* WSEQ_ADDR26 - [13:0] */ - -/* - * R12393 (0x3069) - Write Sequencer 105 - */ -#define WM8995_WSEQ_DATA26_MASK 0x00FF /* WSEQ_DATA26 - [7:0] */ -#define WM8995_WSEQ_DATA26_SHIFT 0 /* WSEQ_DATA26 - [7:0] */ -#define WM8995_WSEQ_DATA26_WIDTH 8 /* WSEQ_DATA26 - [7:0] */ - -/* - * R12394 (0x306A) - Write Sequencer 106 - */ -#define WM8995_WSEQ_DATA_WIDTH26_MASK 0x0700 /* WSEQ_DATA_WIDTH26 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH26_SHIFT 8 /* WSEQ_DATA_WIDTH26 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH26_WIDTH 3 /* WSEQ_DATA_WIDTH26 - [10:8] */ -#define WM8995_WSEQ_DATA_START26_MASK 0x000F /* WSEQ_DATA_START26 - [3:0] */ -#define WM8995_WSEQ_DATA_START26_SHIFT 0 /* WSEQ_DATA_START26 - [3:0] */ -#define WM8995_WSEQ_DATA_START26_WIDTH 4 /* WSEQ_DATA_START26 - [3:0] */ - -/* - * R12395 (0x306B) - Write Sequencer 107 - */ -#define WM8995_WSEQ_EOS26 0x0100 /* WSEQ_EOS26 */ -#define WM8995_WSEQ_EOS26_MASK 0x0100 /* WSEQ_EOS26 */ -#define WM8995_WSEQ_EOS26_SHIFT 8 /* WSEQ_EOS26 */ -#define WM8995_WSEQ_EOS26_WIDTH 1 /* WSEQ_EOS26 */ -#define WM8995_WSEQ_DELAY26_MASK 0x000F /* WSEQ_DELAY26 - [3:0] */ -#define WM8995_WSEQ_DELAY26_SHIFT 0 /* WSEQ_DELAY26 - [3:0] */ -#define WM8995_WSEQ_DELAY26_WIDTH 4 /* WSEQ_DELAY26 - [3:0] */ - -/* - * R12396 (0x306C) - Write Sequencer 108 - */ -#define WM8995_WSEQ_ADDR27_MASK 0x3FFF /* WSEQ_ADDR27 - [13:0] */ -#define WM8995_WSEQ_ADDR27_SHIFT 0 /* WSEQ_ADDR27 - [13:0] */ -#define WM8995_WSEQ_ADDR27_WIDTH 14 /* WSEQ_ADDR27 - [13:0] */ - -/* - * R12397 (0x306D) - Write Sequencer 109 - */ -#define WM8995_WSEQ_DATA27_MASK 0x00FF /* WSEQ_DATA27 - [7:0] */ -#define WM8995_WSEQ_DATA27_SHIFT 0 /* WSEQ_DATA27 - [7:0] */ -#define WM8995_WSEQ_DATA27_WIDTH 8 /* WSEQ_DATA27 - [7:0] */ - -/* - * R12398 (0x306E) - Write Sequencer 110 - */ -#define WM8995_WSEQ_DATA_WIDTH27_MASK 0x0700 /* WSEQ_DATA_WIDTH27 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH27_SHIFT 8 /* WSEQ_DATA_WIDTH27 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH27_WIDTH 3 /* WSEQ_DATA_WIDTH27 - [10:8] */ -#define WM8995_WSEQ_DATA_START27_MASK 0x000F /* WSEQ_DATA_START27 - [3:0] */ -#define WM8995_WSEQ_DATA_START27_SHIFT 0 /* WSEQ_DATA_START27 - [3:0] */ -#define WM8995_WSEQ_DATA_START27_WIDTH 4 /* WSEQ_DATA_START27 - [3:0] */ - -/* - * R12399 (0x306F) - Write Sequencer 111 - */ -#define WM8995_WSEQ_EOS27 0x0100 /* WSEQ_EOS27 */ -#define WM8995_WSEQ_EOS27_MASK 0x0100 /* WSEQ_EOS27 */ -#define WM8995_WSEQ_EOS27_SHIFT 8 /* WSEQ_EOS27 */ -#define WM8995_WSEQ_EOS27_WIDTH 1 /* WSEQ_EOS27 */ -#define WM8995_WSEQ_DELAY27_MASK 0x000F /* WSEQ_DELAY27 - [3:0] */ -#define WM8995_WSEQ_DELAY27_SHIFT 0 /* WSEQ_DELAY27 - [3:0] */ -#define WM8995_WSEQ_DELAY27_WIDTH 4 /* WSEQ_DELAY27 - [3:0] */ - -/* - * R12400 (0x3070) - Write Sequencer 112 - */ -#define WM8995_WSEQ_ADDR28_MASK 0x3FFF /* WSEQ_ADDR28 - [13:0] */ -#define WM8995_WSEQ_ADDR28_SHIFT 0 /* WSEQ_ADDR28 - [13:0] */ -#define WM8995_WSEQ_ADDR28_WIDTH 14 /* WSEQ_ADDR28 - [13:0] */ - -/* - * R12401 (0x3071) - Write Sequencer 113 - */ -#define WM8995_WSEQ_DATA28_MASK 0x00FF /* WSEQ_DATA28 - [7:0] */ -#define WM8995_WSEQ_DATA28_SHIFT 0 /* WSEQ_DATA28 - [7:0] */ -#define WM8995_WSEQ_DATA28_WIDTH 8 /* WSEQ_DATA28 - [7:0] */ - -/* - * R12402 (0x3072) - Write Sequencer 114 - */ -#define WM8995_WSEQ_DATA_WIDTH28_MASK 0x0700 /* WSEQ_DATA_WIDTH28 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH28_SHIFT 8 /* WSEQ_DATA_WIDTH28 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH28_WIDTH 3 /* WSEQ_DATA_WIDTH28 - [10:8] */ -#define WM8995_WSEQ_DATA_START28_MASK 0x000F /* WSEQ_DATA_START28 - [3:0] */ -#define WM8995_WSEQ_DATA_START28_SHIFT 0 /* WSEQ_DATA_START28 - [3:0] */ -#define WM8995_WSEQ_DATA_START28_WIDTH 4 /* WSEQ_DATA_START28 - [3:0] */ - -/* - * R12403 (0x3073) - Write Sequencer 115 - */ -#define WM8995_WSEQ_EOS28 0x0100 /* WSEQ_EOS28 */ -#define WM8995_WSEQ_EOS28_MASK 0x0100 /* WSEQ_EOS28 */ -#define WM8995_WSEQ_EOS28_SHIFT 8 /* WSEQ_EOS28 */ -#define WM8995_WSEQ_EOS28_WIDTH 1 /* WSEQ_EOS28 */ -#define WM8995_WSEQ_DELAY28_MASK 0x000F /* WSEQ_DELAY28 - [3:0] */ -#define WM8995_WSEQ_DELAY28_SHIFT 0 /* WSEQ_DELAY28 - [3:0] */ -#define WM8995_WSEQ_DELAY28_WIDTH 4 /* WSEQ_DELAY28 - [3:0] */ - -/* - * R12404 (0x3074) - Write Sequencer 116 - */ -#define WM8995_WSEQ_ADDR29_MASK 0x3FFF /* WSEQ_ADDR29 - [13:0] */ -#define WM8995_WSEQ_ADDR29_SHIFT 0 /* WSEQ_ADDR29 - [13:0] */ -#define WM8995_WSEQ_ADDR29_WIDTH 14 /* WSEQ_ADDR29 - [13:0] */ - -/* - * R12405 (0x3075) - Write Sequencer 117 - */ -#define WM8995_WSEQ_DATA29_MASK 0x00FF /* WSEQ_DATA29 - [7:0] */ -#define WM8995_WSEQ_DATA29_SHIFT 0 /* WSEQ_DATA29 - [7:0] */ -#define WM8995_WSEQ_DATA29_WIDTH 8 /* WSEQ_DATA29 - [7:0] */ - -/* - * R12406 (0x3076) - Write Sequencer 118 - */ -#define WM8995_WSEQ_DATA_WIDTH29_MASK 0x0700 /* WSEQ_DATA_WIDTH29 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH29_SHIFT 8 /* WSEQ_DATA_WIDTH29 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH29_WIDTH 3 /* WSEQ_DATA_WIDTH29 - [10:8] */ -#define WM8995_WSEQ_DATA_START29_MASK 0x000F /* WSEQ_DATA_START29 - [3:0] */ -#define WM8995_WSEQ_DATA_START29_SHIFT 0 /* WSEQ_DATA_START29 - [3:0] */ -#define WM8995_WSEQ_DATA_START29_WIDTH 4 /* WSEQ_DATA_START29 - [3:0] */ - -/* - * R12407 (0x3077) - Write Sequencer 119 - */ -#define WM8995_WSEQ_EOS29 0x0100 /* WSEQ_EOS29 */ -#define WM8995_WSEQ_EOS29_MASK 0x0100 /* WSEQ_EOS29 */ -#define WM8995_WSEQ_EOS29_SHIFT 8 /* WSEQ_EOS29 */ -#define WM8995_WSEQ_EOS29_WIDTH 1 /* WSEQ_EOS29 */ -#define WM8995_WSEQ_DELAY29_MASK 0x000F /* WSEQ_DELAY29 - [3:0] */ -#define WM8995_WSEQ_DELAY29_SHIFT 0 /* WSEQ_DELAY29 - [3:0] */ -#define WM8995_WSEQ_DELAY29_WIDTH 4 /* WSEQ_DELAY29 - [3:0] */ - -/* - * R12408 (0x3078) - Write Sequencer 120 - */ -#define WM8995_WSEQ_ADDR30_MASK 0x3FFF /* WSEQ_ADDR30 - [13:0] */ -#define WM8995_WSEQ_ADDR30_SHIFT 0 /* WSEQ_ADDR30 - [13:0] */ -#define WM8995_WSEQ_ADDR30_WIDTH 14 /* WSEQ_ADDR30 - [13:0] */ - -/* - * R12409 (0x3079) - Write Sequencer 121 - */ -#define WM8995_WSEQ_DATA30_MASK 0x00FF /* WSEQ_DATA30 - [7:0] */ -#define WM8995_WSEQ_DATA30_SHIFT 0 /* WSEQ_DATA30 - [7:0] */ -#define WM8995_WSEQ_DATA30_WIDTH 8 /* WSEQ_DATA30 - [7:0] */ - -/* - * R12410 (0x307A) - Write Sequencer 122 - */ -#define WM8995_WSEQ_DATA_WIDTH30_MASK 0x0700 /* WSEQ_DATA_WIDTH30 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH30_SHIFT 8 /* WSEQ_DATA_WIDTH30 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH30_WIDTH 3 /* WSEQ_DATA_WIDTH30 - [10:8] */ -#define WM8995_WSEQ_DATA_START30_MASK 0x000F /* WSEQ_DATA_START30 - [3:0] */ -#define WM8995_WSEQ_DATA_START30_SHIFT 0 /* WSEQ_DATA_START30 - [3:0] */ -#define WM8995_WSEQ_DATA_START30_WIDTH 4 /* WSEQ_DATA_START30 - [3:0] */ - -/* - * R12411 (0x307B) - Write Sequencer 123 - */ -#define WM8995_WSEQ_EOS30 0x0100 /* WSEQ_EOS30 */ -#define WM8995_WSEQ_EOS30_MASK 0x0100 /* WSEQ_EOS30 */ -#define WM8995_WSEQ_EOS30_SHIFT 8 /* WSEQ_EOS30 */ -#define WM8995_WSEQ_EOS30_WIDTH 1 /* WSEQ_EOS30 */ -#define WM8995_WSEQ_DELAY30_MASK 0x000F /* WSEQ_DELAY30 - [3:0] */ -#define WM8995_WSEQ_DELAY30_SHIFT 0 /* WSEQ_DELAY30 - [3:0] */ -#define WM8995_WSEQ_DELAY30_WIDTH 4 /* WSEQ_DELAY30 - [3:0] */ - -/* - * R12412 (0x307C) - Write Sequencer 124 - */ -#define WM8995_WSEQ_ADDR31_MASK 0x3FFF /* WSEQ_ADDR31 - [13:0] */ -#define WM8995_WSEQ_ADDR31_SHIFT 0 /* WSEQ_ADDR31 - [13:0] */ -#define WM8995_WSEQ_ADDR31_WIDTH 14 /* WSEQ_ADDR31 - [13:0] */ - -/* - * R12413 (0x307D) - Write Sequencer 125 - */ -#define WM8995_WSEQ_DATA31_MASK 0x00FF /* WSEQ_DATA31 - [7:0] */ -#define WM8995_WSEQ_DATA31_SHIFT 0 /* WSEQ_DATA31 - [7:0] */ -#define WM8995_WSEQ_DATA31_WIDTH 8 /* WSEQ_DATA31 - [7:0] */ - -/* - * R12414 (0x307E) - Write Sequencer 126 - */ -#define WM8995_WSEQ_DATA_WIDTH31_MASK 0x0700 /* WSEQ_DATA_WIDTH31 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH31_SHIFT 8 /* WSEQ_DATA_WIDTH31 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH31_WIDTH 3 /* WSEQ_DATA_WIDTH31 - [10:8] */ -#define WM8995_WSEQ_DATA_START31_MASK 0x000F /* WSEQ_DATA_START31 - [3:0] */ -#define WM8995_WSEQ_DATA_START31_SHIFT 0 /* WSEQ_DATA_START31 - [3:0] */ -#define WM8995_WSEQ_DATA_START31_WIDTH 4 /* WSEQ_DATA_START31 - [3:0] */ - -/* - * R12415 (0x307F) - Write Sequencer 127 - */ -#define WM8995_WSEQ_EOS31 0x0100 /* WSEQ_EOS31 */ -#define WM8995_WSEQ_EOS31_MASK 0x0100 /* WSEQ_EOS31 */ -#define WM8995_WSEQ_EOS31_SHIFT 8 /* WSEQ_EOS31 */ -#define WM8995_WSEQ_EOS31_WIDTH 1 /* WSEQ_EOS31 */ -#define WM8995_WSEQ_DELAY31_MASK 0x000F /* WSEQ_DELAY31 - [3:0] */ -#define WM8995_WSEQ_DELAY31_SHIFT 0 /* WSEQ_DELAY31 - [3:0] */ -#define WM8995_WSEQ_DELAY31_WIDTH 4 /* WSEQ_DELAY31 - [3:0] */ - -/* - * R12416 (0x3080) - Write Sequencer 128 - */ -#define WM8995_WSEQ_ADDR32_MASK 0x3FFF /* WSEQ_ADDR32 - [13:0] */ -#define WM8995_WSEQ_ADDR32_SHIFT 0 /* WSEQ_ADDR32 - [13:0] */ -#define WM8995_WSEQ_ADDR32_WIDTH 14 /* WSEQ_ADDR32 - [13:0] */ - -/* - * R12417 (0x3081) - Write Sequencer 129 - */ -#define WM8995_WSEQ_DATA32_MASK 0x00FF /* WSEQ_DATA32 - [7:0] */ -#define WM8995_WSEQ_DATA32_SHIFT 0 /* WSEQ_DATA32 - [7:0] */ -#define WM8995_WSEQ_DATA32_WIDTH 8 /* WSEQ_DATA32 - [7:0] */ - -/* - * R12418 (0x3082) - Write Sequencer 130 - */ -#define WM8995_WSEQ_DATA_WIDTH32_MASK 0x0700 /* WSEQ_DATA_WIDTH32 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH32_SHIFT 8 /* WSEQ_DATA_WIDTH32 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH32_WIDTH 3 /* WSEQ_DATA_WIDTH32 - [10:8] */ -#define WM8995_WSEQ_DATA_START32_MASK 0x000F /* WSEQ_DATA_START32 - [3:0] */ -#define WM8995_WSEQ_DATA_START32_SHIFT 0 /* WSEQ_DATA_START32 - [3:0] */ -#define WM8995_WSEQ_DATA_START32_WIDTH 4 /* WSEQ_DATA_START32 - [3:0] */ - -/* - * R12419 (0x3083) - Write Sequencer 131 - */ -#define WM8995_WSEQ_EOS32 0x0100 /* WSEQ_EOS32 */ -#define WM8995_WSEQ_EOS32_MASK 0x0100 /* WSEQ_EOS32 */ -#define WM8995_WSEQ_EOS32_SHIFT 8 /* WSEQ_EOS32 */ -#define WM8995_WSEQ_EOS32_WIDTH 1 /* WSEQ_EOS32 */ -#define WM8995_WSEQ_DELAY32_MASK 0x000F /* WSEQ_DELAY32 - [3:0] */ -#define WM8995_WSEQ_DELAY32_SHIFT 0 /* WSEQ_DELAY32 - [3:0] */ -#define WM8995_WSEQ_DELAY32_WIDTH 4 /* WSEQ_DELAY32 - [3:0] */ - -/* - * R12420 (0x3084) - Write Sequencer 132 - */ -#define WM8995_WSEQ_ADDR33_MASK 0x3FFF /* WSEQ_ADDR33 - [13:0] */ -#define WM8995_WSEQ_ADDR33_SHIFT 0 /* WSEQ_ADDR33 - [13:0] */ -#define WM8995_WSEQ_ADDR33_WIDTH 14 /* WSEQ_ADDR33 - [13:0] */ - -/* - * R12421 (0x3085) - Write Sequencer 133 - */ -#define WM8995_WSEQ_DATA33_MASK 0x00FF /* WSEQ_DATA33 - [7:0] */ -#define WM8995_WSEQ_DATA33_SHIFT 0 /* WSEQ_DATA33 - [7:0] */ -#define WM8995_WSEQ_DATA33_WIDTH 8 /* WSEQ_DATA33 - [7:0] */ - -/* - * R12422 (0x3086) - Write Sequencer 134 - */ -#define WM8995_WSEQ_DATA_WIDTH33_MASK 0x0700 /* WSEQ_DATA_WIDTH33 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH33_SHIFT 8 /* WSEQ_DATA_WIDTH33 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH33_WIDTH 3 /* WSEQ_DATA_WIDTH33 - [10:8] */ -#define WM8995_WSEQ_DATA_START33_MASK 0x000F /* WSEQ_DATA_START33 - [3:0] */ -#define WM8995_WSEQ_DATA_START33_SHIFT 0 /* WSEQ_DATA_START33 - [3:0] */ -#define WM8995_WSEQ_DATA_START33_WIDTH 4 /* WSEQ_DATA_START33 - [3:0] */ - -/* - * R12423 (0x3087) - Write Sequencer 135 - */ -#define WM8995_WSEQ_EOS33 0x0100 /* WSEQ_EOS33 */ -#define WM8995_WSEQ_EOS33_MASK 0x0100 /* WSEQ_EOS33 */ -#define WM8995_WSEQ_EOS33_SHIFT 8 /* WSEQ_EOS33 */ -#define WM8995_WSEQ_EOS33_WIDTH 1 /* WSEQ_EOS33 */ -#define WM8995_WSEQ_DELAY33_MASK 0x000F /* WSEQ_DELAY33 - [3:0] */ -#define WM8995_WSEQ_DELAY33_SHIFT 0 /* WSEQ_DELAY33 - [3:0] */ -#define WM8995_WSEQ_DELAY33_WIDTH 4 /* WSEQ_DELAY33 - [3:0] */ - -/* - * R12424 (0x3088) - Write Sequencer 136 - */ -#define WM8995_WSEQ_ADDR34_MASK 0x3FFF /* WSEQ_ADDR34 - [13:0] */ -#define WM8995_WSEQ_ADDR34_SHIFT 0 /* WSEQ_ADDR34 - [13:0] */ -#define WM8995_WSEQ_ADDR34_WIDTH 14 /* WSEQ_ADDR34 - [13:0] */ - -/* - * R12425 (0x3089) - Write Sequencer 137 - */ -#define WM8995_WSEQ_DATA34_MASK 0x00FF /* WSEQ_DATA34 - [7:0] */ -#define WM8995_WSEQ_DATA34_SHIFT 0 /* WSEQ_DATA34 - [7:0] */ -#define WM8995_WSEQ_DATA34_WIDTH 8 /* WSEQ_DATA34 - [7:0] */ - -/* - * R12426 (0x308A) - Write Sequencer 138 - */ -#define WM8995_WSEQ_DATA_WIDTH34_MASK 0x0700 /* WSEQ_DATA_WIDTH34 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH34_SHIFT 8 /* WSEQ_DATA_WIDTH34 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH34_WIDTH 3 /* WSEQ_DATA_WIDTH34 - [10:8] */ -#define WM8995_WSEQ_DATA_START34_MASK 0x000F /* WSEQ_DATA_START34 - [3:0] */ -#define WM8995_WSEQ_DATA_START34_SHIFT 0 /* WSEQ_DATA_START34 - [3:0] */ -#define WM8995_WSEQ_DATA_START34_WIDTH 4 /* WSEQ_DATA_START34 - [3:0] */ - -/* - * R12427 (0x308B) - Write Sequencer 139 - */ -#define WM8995_WSEQ_EOS34 0x0100 /* WSEQ_EOS34 */ -#define WM8995_WSEQ_EOS34_MASK 0x0100 /* WSEQ_EOS34 */ -#define WM8995_WSEQ_EOS34_SHIFT 8 /* WSEQ_EOS34 */ -#define WM8995_WSEQ_EOS34_WIDTH 1 /* WSEQ_EOS34 */ -#define WM8995_WSEQ_DELAY34_MASK 0x000F /* WSEQ_DELAY34 - [3:0] */ -#define WM8995_WSEQ_DELAY34_SHIFT 0 /* WSEQ_DELAY34 - [3:0] */ -#define WM8995_WSEQ_DELAY34_WIDTH 4 /* WSEQ_DELAY34 - [3:0] */ - -/* - * R12428 (0x308C) - Write Sequencer 140 - */ -#define WM8995_WSEQ_ADDR35_MASK 0x3FFF /* WSEQ_ADDR35 - [13:0] */ -#define WM8995_WSEQ_ADDR35_SHIFT 0 /* WSEQ_ADDR35 - [13:0] */ -#define WM8995_WSEQ_ADDR35_WIDTH 14 /* WSEQ_ADDR35 - [13:0] */ - -/* - * R12429 (0x308D) - Write Sequencer 141 - */ -#define WM8995_WSEQ_DATA35_MASK 0x00FF /* WSEQ_DATA35 - [7:0] */ -#define WM8995_WSEQ_DATA35_SHIFT 0 /* WSEQ_DATA35 - [7:0] */ -#define WM8995_WSEQ_DATA35_WIDTH 8 /* WSEQ_DATA35 - [7:0] */ - -/* - * R12430 (0x308E) - Write Sequencer 142 - */ -#define WM8995_WSEQ_DATA_WIDTH35_MASK 0x0700 /* WSEQ_DATA_WIDTH35 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH35_SHIFT 8 /* WSEQ_DATA_WIDTH35 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH35_WIDTH 3 /* WSEQ_DATA_WIDTH35 - [10:8] */ -#define WM8995_WSEQ_DATA_START35_MASK 0x000F /* WSEQ_DATA_START35 - [3:0] */ -#define WM8995_WSEQ_DATA_START35_SHIFT 0 /* WSEQ_DATA_START35 - [3:0] */ -#define WM8995_WSEQ_DATA_START35_WIDTH 4 /* WSEQ_DATA_START35 - [3:0] */ - -/* - * R12431 (0x308F) - Write Sequencer 143 - */ -#define WM8995_WSEQ_EOS35 0x0100 /* WSEQ_EOS35 */ -#define WM8995_WSEQ_EOS35_MASK 0x0100 /* WSEQ_EOS35 */ -#define WM8995_WSEQ_EOS35_SHIFT 8 /* WSEQ_EOS35 */ -#define WM8995_WSEQ_EOS35_WIDTH 1 /* WSEQ_EOS35 */ -#define WM8995_WSEQ_DELAY35_MASK 0x000F /* WSEQ_DELAY35 - [3:0] */ -#define WM8995_WSEQ_DELAY35_SHIFT 0 /* WSEQ_DELAY35 - [3:0] */ -#define WM8995_WSEQ_DELAY35_WIDTH 4 /* WSEQ_DELAY35 - [3:0] */ - -/* - * R12432 (0x3090) - Write Sequencer 144 - */ -#define WM8995_WSEQ_ADDR36_MASK 0x3FFF /* WSEQ_ADDR36 - [13:0] */ -#define WM8995_WSEQ_ADDR36_SHIFT 0 /* WSEQ_ADDR36 - [13:0] */ -#define WM8995_WSEQ_ADDR36_WIDTH 14 /* WSEQ_ADDR36 - [13:0] */ - -/* - * R12433 (0x3091) - Write Sequencer 145 - */ -#define WM8995_WSEQ_DATA36_MASK 0x00FF /* WSEQ_DATA36 - [7:0] */ -#define WM8995_WSEQ_DATA36_SHIFT 0 /* WSEQ_DATA36 - [7:0] */ -#define WM8995_WSEQ_DATA36_WIDTH 8 /* WSEQ_DATA36 - [7:0] */ - -/* - * R12434 (0x3092) - Write Sequencer 146 - */ -#define WM8995_WSEQ_DATA_WIDTH36_MASK 0x0700 /* WSEQ_DATA_WIDTH36 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH36_SHIFT 8 /* WSEQ_DATA_WIDTH36 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH36_WIDTH 3 /* WSEQ_DATA_WIDTH36 - [10:8] */ -#define WM8995_WSEQ_DATA_START36_MASK 0x000F /* WSEQ_DATA_START36 - [3:0] */ -#define WM8995_WSEQ_DATA_START36_SHIFT 0 /* WSEQ_DATA_START36 - [3:0] */ -#define WM8995_WSEQ_DATA_START36_WIDTH 4 /* WSEQ_DATA_START36 - [3:0] */ - -/* - * R12435 (0x3093) - Write Sequencer 147 - */ -#define WM8995_WSEQ_EOS36 0x0100 /* WSEQ_EOS36 */ -#define WM8995_WSEQ_EOS36_MASK 0x0100 /* WSEQ_EOS36 */ -#define WM8995_WSEQ_EOS36_SHIFT 8 /* WSEQ_EOS36 */ -#define WM8995_WSEQ_EOS36_WIDTH 1 /* WSEQ_EOS36 */ -#define WM8995_WSEQ_DELAY36_MASK 0x000F /* WSEQ_DELAY36 - [3:0] */ -#define WM8995_WSEQ_DELAY36_SHIFT 0 /* WSEQ_DELAY36 - [3:0] */ -#define WM8995_WSEQ_DELAY36_WIDTH 4 /* WSEQ_DELAY36 - [3:0] */ - -/* - * R12436 (0x3094) - Write Sequencer 148 - */ -#define WM8995_WSEQ_ADDR37_MASK 0x3FFF /* WSEQ_ADDR37 - [13:0] */ -#define WM8995_WSEQ_ADDR37_SHIFT 0 /* WSEQ_ADDR37 - [13:0] */ -#define WM8995_WSEQ_ADDR37_WIDTH 14 /* WSEQ_ADDR37 - [13:0] */ - -/* - * R12437 (0x3095) - Write Sequencer 149 - */ -#define WM8995_WSEQ_DATA37_MASK 0x00FF /* WSEQ_DATA37 - [7:0] */ -#define WM8995_WSEQ_DATA37_SHIFT 0 /* WSEQ_DATA37 - [7:0] */ -#define WM8995_WSEQ_DATA37_WIDTH 8 /* WSEQ_DATA37 - [7:0] */ - -/* - * R12438 (0x3096) - Write Sequencer 150 - */ -#define WM8995_WSEQ_DATA_WIDTH37_MASK 0x0700 /* WSEQ_DATA_WIDTH37 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH37_SHIFT 8 /* WSEQ_DATA_WIDTH37 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH37_WIDTH 3 /* WSEQ_DATA_WIDTH37 - [10:8] */ -#define WM8995_WSEQ_DATA_START37_MASK 0x000F /* WSEQ_DATA_START37 - [3:0] */ -#define WM8995_WSEQ_DATA_START37_SHIFT 0 /* WSEQ_DATA_START37 - [3:0] */ -#define WM8995_WSEQ_DATA_START37_WIDTH 4 /* WSEQ_DATA_START37 - [3:0] */ - -/* - * R12439 (0x3097) - Write Sequencer 151 - */ -#define WM8995_WSEQ_EOS37 0x0100 /* WSEQ_EOS37 */ -#define WM8995_WSEQ_EOS37_MASK 0x0100 /* WSEQ_EOS37 */ -#define WM8995_WSEQ_EOS37_SHIFT 8 /* WSEQ_EOS37 */ -#define WM8995_WSEQ_EOS37_WIDTH 1 /* WSEQ_EOS37 */ -#define WM8995_WSEQ_DELAY37_MASK 0x000F /* WSEQ_DELAY37 - [3:0] */ -#define WM8995_WSEQ_DELAY37_SHIFT 0 /* WSEQ_DELAY37 - [3:0] */ -#define WM8995_WSEQ_DELAY37_WIDTH 4 /* WSEQ_DELAY37 - [3:0] */ - -/* - * R12440 (0x3098) - Write Sequencer 152 - */ -#define WM8995_WSEQ_ADDR38_MASK 0x3FFF /* WSEQ_ADDR38 - [13:0] */ -#define WM8995_WSEQ_ADDR38_SHIFT 0 /* WSEQ_ADDR38 - [13:0] */ -#define WM8995_WSEQ_ADDR38_WIDTH 14 /* WSEQ_ADDR38 - [13:0] */ - -/* - * R12441 (0x3099) - Write Sequencer 153 - */ -#define WM8995_WSEQ_DATA38_MASK 0x00FF /* WSEQ_DATA38 - [7:0] */ -#define WM8995_WSEQ_DATA38_SHIFT 0 /* WSEQ_DATA38 - [7:0] */ -#define WM8995_WSEQ_DATA38_WIDTH 8 /* WSEQ_DATA38 - [7:0] */ - -/* - * R12442 (0x309A) - Write Sequencer 154 - */ -#define WM8995_WSEQ_DATA_WIDTH38_MASK 0x0700 /* WSEQ_DATA_WIDTH38 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH38_SHIFT 8 /* WSEQ_DATA_WIDTH38 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH38_WIDTH 3 /* WSEQ_DATA_WIDTH38 - [10:8] */ -#define WM8995_WSEQ_DATA_START38_MASK 0x000F /* WSEQ_DATA_START38 - [3:0] */ -#define WM8995_WSEQ_DATA_START38_SHIFT 0 /* WSEQ_DATA_START38 - [3:0] */ -#define WM8995_WSEQ_DATA_START38_WIDTH 4 /* WSEQ_DATA_START38 - [3:0] */ - -/* - * R12443 (0x309B) - Write Sequencer 155 - */ -#define WM8995_WSEQ_EOS38 0x0100 /* WSEQ_EOS38 */ -#define WM8995_WSEQ_EOS38_MASK 0x0100 /* WSEQ_EOS38 */ -#define WM8995_WSEQ_EOS38_SHIFT 8 /* WSEQ_EOS38 */ -#define WM8995_WSEQ_EOS38_WIDTH 1 /* WSEQ_EOS38 */ -#define WM8995_WSEQ_DELAY38_MASK 0x000F /* WSEQ_DELAY38 - [3:0] */ -#define WM8995_WSEQ_DELAY38_SHIFT 0 /* WSEQ_DELAY38 - [3:0] */ -#define WM8995_WSEQ_DELAY38_WIDTH 4 /* WSEQ_DELAY38 - [3:0] */ - -/* - * R12444 (0x309C) - Write Sequencer 156 - */ -#define WM8995_WSEQ_ADDR39_MASK 0x3FFF /* WSEQ_ADDR39 - [13:0] */ -#define WM8995_WSEQ_ADDR39_SHIFT 0 /* WSEQ_ADDR39 - [13:0] */ -#define WM8995_WSEQ_ADDR39_WIDTH 14 /* WSEQ_ADDR39 - [13:0] */ - -/* - * R12445 (0x309D) - Write Sequencer 157 - */ -#define WM8995_WSEQ_DATA39_MASK 0x00FF /* WSEQ_DATA39 - [7:0] */ -#define WM8995_WSEQ_DATA39_SHIFT 0 /* WSEQ_DATA39 - [7:0] */ -#define WM8995_WSEQ_DATA39_WIDTH 8 /* WSEQ_DATA39 - [7:0] */ - -/* - * R12446 (0x309E) - Write Sequencer 158 - */ -#define WM8995_WSEQ_DATA_WIDTH39_MASK 0x0700 /* WSEQ_DATA_WIDTH39 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH39_SHIFT 8 /* WSEQ_DATA_WIDTH39 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH39_WIDTH 3 /* WSEQ_DATA_WIDTH39 - [10:8] */ -#define WM8995_WSEQ_DATA_START39_MASK 0x000F /* WSEQ_DATA_START39 - [3:0] */ -#define WM8995_WSEQ_DATA_START39_SHIFT 0 /* WSEQ_DATA_START39 - [3:0] */ -#define WM8995_WSEQ_DATA_START39_WIDTH 4 /* WSEQ_DATA_START39 - [3:0] */ - -/* - * R12447 (0x309F) - Write Sequencer 159 - */ -#define WM8995_WSEQ_EOS39 0x0100 /* WSEQ_EOS39 */ -#define WM8995_WSEQ_EOS39_MASK 0x0100 /* WSEQ_EOS39 */ -#define WM8995_WSEQ_EOS39_SHIFT 8 /* WSEQ_EOS39 */ -#define WM8995_WSEQ_EOS39_WIDTH 1 /* WSEQ_EOS39 */ -#define WM8995_WSEQ_DELAY39_MASK 0x000F /* WSEQ_DELAY39 - [3:0] */ -#define WM8995_WSEQ_DELAY39_SHIFT 0 /* WSEQ_DELAY39 - [3:0] */ -#define WM8995_WSEQ_DELAY39_WIDTH 4 /* WSEQ_DELAY39 - [3:0] */ - -/* - * R12448 (0x30A0) - Write Sequencer 160 - */ -#define WM8995_WSEQ_ADDR40_MASK 0x3FFF /* WSEQ_ADDR40 - [13:0] */ -#define WM8995_WSEQ_ADDR40_SHIFT 0 /* WSEQ_ADDR40 - [13:0] */ -#define WM8995_WSEQ_ADDR40_WIDTH 14 /* WSEQ_ADDR40 - [13:0] */ - -/* - * R12449 (0x30A1) - Write Sequencer 161 - */ -#define WM8995_WSEQ_DATA40_MASK 0x00FF /* WSEQ_DATA40 - [7:0] */ -#define WM8995_WSEQ_DATA40_SHIFT 0 /* WSEQ_DATA40 - [7:0] */ -#define WM8995_WSEQ_DATA40_WIDTH 8 /* WSEQ_DATA40 - [7:0] */ - -/* - * R12450 (0x30A2) - Write Sequencer 162 - */ -#define WM8995_WSEQ_DATA_WIDTH40_MASK 0x0700 /* WSEQ_DATA_WIDTH40 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH40_SHIFT 8 /* WSEQ_DATA_WIDTH40 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH40_WIDTH 3 /* WSEQ_DATA_WIDTH40 - [10:8] */ -#define WM8995_WSEQ_DATA_START40_MASK 0x000F /* WSEQ_DATA_START40 - [3:0] */ -#define WM8995_WSEQ_DATA_START40_SHIFT 0 /* WSEQ_DATA_START40 - [3:0] */ -#define WM8995_WSEQ_DATA_START40_WIDTH 4 /* WSEQ_DATA_START40 - [3:0] */ - -/* - * R12451 (0x30A3) - Write Sequencer 163 - */ -#define WM8995_WSEQ_EOS40 0x0100 /* WSEQ_EOS40 */ -#define WM8995_WSEQ_EOS40_MASK 0x0100 /* WSEQ_EOS40 */ -#define WM8995_WSEQ_EOS40_SHIFT 8 /* WSEQ_EOS40 */ -#define WM8995_WSEQ_EOS40_WIDTH 1 /* WSEQ_EOS40 */ -#define WM8995_WSEQ_DELAY40_MASK 0x000F /* WSEQ_DELAY40 - [3:0] */ -#define WM8995_WSEQ_DELAY40_SHIFT 0 /* WSEQ_DELAY40 - [3:0] */ -#define WM8995_WSEQ_DELAY40_WIDTH 4 /* WSEQ_DELAY40 - [3:0] */ - -/* - * R12452 (0x30A4) - Write Sequencer 164 - */ -#define WM8995_WSEQ_ADDR41_MASK 0x3FFF /* WSEQ_ADDR41 - [13:0] */ -#define WM8995_WSEQ_ADDR41_SHIFT 0 /* WSEQ_ADDR41 - [13:0] */ -#define WM8995_WSEQ_ADDR41_WIDTH 14 /* WSEQ_ADDR41 - [13:0] */ - -/* - * R12453 (0x30A5) - Write Sequencer 165 - */ -#define WM8995_WSEQ_DATA41_MASK 0x00FF /* WSEQ_DATA41 - [7:0] */ -#define WM8995_WSEQ_DATA41_SHIFT 0 /* WSEQ_DATA41 - [7:0] */ -#define WM8995_WSEQ_DATA41_WIDTH 8 /* WSEQ_DATA41 - [7:0] */ - -/* - * R12454 (0x30A6) - Write Sequencer 166 - */ -#define WM8995_WSEQ_DATA_WIDTH41_MASK 0x0700 /* WSEQ_DATA_WIDTH41 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH41_SHIFT 8 /* WSEQ_DATA_WIDTH41 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH41_WIDTH 3 /* WSEQ_DATA_WIDTH41 - [10:8] */ -#define WM8995_WSEQ_DATA_START41_MASK 0x000F /* WSEQ_DATA_START41 - [3:0] */ -#define WM8995_WSEQ_DATA_START41_SHIFT 0 /* WSEQ_DATA_START41 - [3:0] */ -#define WM8995_WSEQ_DATA_START41_WIDTH 4 /* WSEQ_DATA_START41 - [3:0] */ - -/* - * R12455 (0x30A7) - Write Sequencer 167 - */ -#define WM8995_WSEQ_EOS41 0x0100 /* WSEQ_EOS41 */ -#define WM8995_WSEQ_EOS41_MASK 0x0100 /* WSEQ_EOS41 */ -#define WM8995_WSEQ_EOS41_SHIFT 8 /* WSEQ_EOS41 */ -#define WM8995_WSEQ_EOS41_WIDTH 1 /* WSEQ_EOS41 */ -#define WM8995_WSEQ_DELAY41_MASK 0x000F /* WSEQ_DELAY41 - [3:0] */ -#define WM8995_WSEQ_DELAY41_SHIFT 0 /* WSEQ_DELAY41 - [3:0] */ -#define WM8995_WSEQ_DELAY41_WIDTH 4 /* WSEQ_DELAY41 - [3:0] */ - -/* - * R12456 (0x30A8) - Write Sequencer 168 - */ -#define WM8995_WSEQ_ADDR42_MASK 0x3FFF /* WSEQ_ADDR42 - [13:0] */ -#define WM8995_WSEQ_ADDR42_SHIFT 0 /* WSEQ_ADDR42 - [13:0] */ -#define WM8995_WSEQ_ADDR42_WIDTH 14 /* WSEQ_ADDR42 - [13:0] */ - -/* - * R12457 (0x30A9) - Write Sequencer 169 - */ -#define WM8995_WSEQ_DATA42_MASK 0x00FF /* WSEQ_DATA42 - [7:0] */ -#define WM8995_WSEQ_DATA42_SHIFT 0 /* WSEQ_DATA42 - [7:0] */ -#define WM8995_WSEQ_DATA42_WIDTH 8 /* WSEQ_DATA42 - [7:0] */ - -/* - * R12458 (0x30AA) - Write Sequencer 170 - */ -#define WM8995_WSEQ_DATA_WIDTH42_MASK 0x0700 /* WSEQ_DATA_WIDTH42 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH42_SHIFT 8 /* WSEQ_DATA_WIDTH42 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH42_WIDTH 3 /* WSEQ_DATA_WIDTH42 - [10:8] */ -#define WM8995_WSEQ_DATA_START42_MASK 0x000F /* WSEQ_DATA_START42 - [3:0] */ -#define WM8995_WSEQ_DATA_START42_SHIFT 0 /* WSEQ_DATA_START42 - [3:0] */ -#define WM8995_WSEQ_DATA_START42_WIDTH 4 /* WSEQ_DATA_START42 - [3:0] */ - -/* - * R12459 (0x30AB) - Write Sequencer 171 - */ -#define WM8995_WSEQ_EOS42 0x0100 /* WSEQ_EOS42 */ -#define WM8995_WSEQ_EOS42_MASK 0x0100 /* WSEQ_EOS42 */ -#define WM8995_WSEQ_EOS42_SHIFT 8 /* WSEQ_EOS42 */ -#define WM8995_WSEQ_EOS42_WIDTH 1 /* WSEQ_EOS42 */ -#define WM8995_WSEQ_DELAY42_MASK 0x000F /* WSEQ_DELAY42 - [3:0] */ -#define WM8995_WSEQ_DELAY42_SHIFT 0 /* WSEQ_DELAY42 - [3:0] */ -#define WM8995_WSEQ_DELAY42_WIDTH 4 /* WSEQ_DELAY42 - [3:0] */ - -/* - * R12460 (0x30AC) - Write Sequencer 172 - */ -#define WM8995_WSEQ_ADDR43_MASK 0x3FFF /* WSEQ_ADDR43 - [13:0] */ -#define WM8995_WSEQ_ADDR43_SHIFT 0 /* WSEQ_ADDR43 - [13:0] */ -#define WM8995_WSEQ_ADDR43_WIDTH 14 /* WSEQ_ADDR43 - [13:0] */ - -/* - * R12461 (0x30AD) - Write Sequencer 173 - */ -#define WM8995_WSEQ_DATA43_MASK 0x00FF /* WSEQ_DATA43 - [7:0] */ -#define WM8995_WSEQ_DATA43_SHIFT 0 /* WSEQ_DATA43 - [7:0] */ -#define WM8995_WSEQ_DATA43_WIDTH 8 /* WSEQ_DATA43 - [7:0] */ - -/* - * R12462 (0x30AE) - Write Sequencer 174 - */ -#define WM8995_WSEQ_DATA_WIDTH43_MASK 0x0700 /* WSEQ_DATA_WIDTH43 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH43_SHIFT 8 /* WSEQ_DATA_WIDTH43 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH43_WIDTH 3 /* WSEQ_DATA_WIDTH43 - [10:8] */ -#define WM8995_WSEQ_DATA_START43_MASK 0x000F /* WSEQ_DATA_START43 - [3:0] */ -#define WM8995_WSEQ_DATA_START43_SHIFT 0 /* WSEQ_DATA_START43 - [3:0] */ -#define WM8995_WSEQ_DATA_START43_WIDTH 4 /* WSEQ_DATA_START43 - [3:0] */ - -/* - * R12463 (0x30AF) - Write Sequencer 175 - */ -#define WM8995_WSEQ_EOS43 0x0100 /* WSEQ_EOS43 */ -#define WM8995_WSEQ_EOS43_MASK 0x0100 /* WSEQ_EOS43 */ -#define WM8995_WSEQ_EOS43_SHIFT 8 /* WSEQ_EOS43 */ -#define WM8995_WSEQ_EOS43_WIDTH 1 /* WSEQ_EOS43 */ -#define WM8995_WSEQ_DELAY43_MASK 0x000F /* WSEQ_DELAY43 - [3:0] */ -#define WM8995_WSEQ_DELAY43_SHIFT 0 /* WSEQ_DELAY43 - [3:0] */ -#define WM8995_WSEQ_DELAY43_WIDTH 4 /* WSEQ_DELAY43 - [3:0] */ - -/* - * R12464 (0x30B0) - Write Sequencer 176 - */ -#define WM8995_WSEQ_ADDR44_MASK 0x3FFF /* WSEQ_ADDR44 - [13:0] */ -#define WM8995_WSEQ_ADDR44_SHIFT 0 /* WSEQ_ADDR44 - [13:0] */ -#define WM8995_WSEQ_ADDR44_WIDTH 14 /* WSEQ_ADDR44 - [13:0] */ - -/* - * R12465 (0x30B1) - Write Sequencer 177 - */ -#define WM8995_WSEQ_DATA44_MASK 0x00FF /* WSEQ_DATA44 - [7:0] */ -#define WM8995_WSEQ_DATA44_SHIFT 0 /* WSEQ_DATA44 - [7:0] */ -#define WM8995_WSEQ_DATA44_WIDTH 8 /* WSEQ_DATA44 - [7:0] */ - -/* - * R12466 (0x30B2) - Write Sequencer 178 - */ -#define WM8995_WSEQ_DATA_WIDTH44_MASK 0x0700 /* WSEQ_DATA_WIDTH44 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH44_SHIFT 8 /* WSEQ_DATA_WIDTH44 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH44_WIDTH 3 /* WSEQ_DATA_WIDTH44 - [10:8] */ -#define WM8995_WSEQ_DATA_START44_MASK 0x000F /* WSEQ_DATA_START44 - [3:0] */ -#define WM8995_WSEQ_DATA_START44_SHIFT 0 /* WSEQ_DATA_START44 - [3:0] */ -#define WM8995_WSEQ_DATA_START44_WIDTH 4 /* WSEQ_DATA_START44 - [3:0] */ - -/* - * R12467 (0x30B3) - Write Sequencer 179 - */ -#define WM8995_WSEQ_EOS44 0x0100 /* WSEQ_EOS44 */ -#define WM8995_WSEQ_EOS44_MASK 0x0100 /* WSEQ_EOS44 */ -#define WM8995_WSEQ_EOS44_SHIFT 8 /* WSEQ_EOS44 */ -#define WM8995_WSEQ_EOS44_WIDTH 1 /* WSEQ_EOS44 */ -#define WM8995_WSEQ_DELAY44_MASK 0x000F /* WSEQ_DELAY44 - [3:0] */ -#define WM8995_WSEQ_DELAY44_SHIFT 0 /* WSEQ_DELAY44 - [3:0] */ -#define WM8995_WSEQ_DELAY44_WIDTH 4 /* WSEQ_DELAY44 - [3:0] */ - -/* - * R12468 (0x30B4) - Write Sequencer 180 - */ -#define WM8995_WSEQ_ADDR45_MASK 0x3FFF /* WSEQ_ADDR45 - [13:0] */ -#define WM8995_WSEQ_ADDR45_SHIFT 0 /* WSEQ_ADDR45 - [13:0] */ -#define WM8995_WSEQ_ADDR45_WIDTH 14 /* WSEQ_ADDR45 - [13:0] */ - -/* - * R12469 (0x30B5) - Write Sequencer 181 - */ -#define WM8995_WSEQ_DATA45_MASK 0x00FF /* WSEQ_DATA45 - [7:0] */ -#define WM8995_WSEQ_DATA45_SHIFT 0 /* WSEQ_DATA45 - [7:0] */ -#define WM8995_WSEQ_DATA45_WIDTH 8 /* WSEQ_DATA45 - [7:0] */ - -/* - * R12470 (0x30B6) - Write Sequencer 182 - */ -#define WM8995_WSEQ_DATA_WIDTH45_MASK 0x0700 /* WSEQ_DATA_WIDTH45 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH45_SHIFT 8 /* WSEQ_DATA_WIDTH45 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH45_WIDTH 3 /* WSEQ_DATA_WIDTH45 - [10:8] */ -#define WM8995_WSEQ_DATA_START45_MASK 0x000F /* WSEQ_DATA_START45 - [3:0] */ -#define WM8995_WSEQ_DATA_START45_SHIFT 0 /* WSEQ_DATA_START45 - [3:0] */ -#define WM8995_WSEQ_DATA_START45_WIDTH 4 /* WSEQ_DATA_START45 - [3:0] */ - -/* - * R12471 (0x30B7) - Write Sequencer 183 - */ -#define WM8995_WSEQ_EOS45 0x0100 /* WSEQ_EOS45 */ -#define WM8995_WSEQ_EOS45_MASK 0x0100 /* WSEQ_EOS45 */ -#define WM8995_WSEQ_EOS45_SHIFT 8 /* WSEQ_EOS45 */ -#define WM8995_WSEQ_EOS45_WIDTH 1 /* WSEQ_EOS45 */ -#define WM8995_WSEQ_DELAY45_MASK 0x000F /* WSEQ_DELAY45 - [3:0] */ -#define WM8995_WSEQ_DELAY45_SHIFT 0 /* WSEQ_DELAY45 - [3:0] */ -#define WM8995_WSEQ_DELAY45_WIDTH 4 /* WSEQ_DELAY45 - [3:0] */ - -/* - * R12472 (0x30B8) - Write Sequencer 184 - */ -#define WM8995_WSEQ_ADDR46_MASK 0x3FFF /* WSEQ_ADDR46 - [13:0] */ -#define WM8995_WSEQ_ADDR46_SHIFT 0 /* WSEQ_ADDR46 - [13:0] */ -#define WM8995_WSEQ_ADDR46_WIDTH 14 /* WSEQ_ADDR46 - [13:0] */ - -/* - * R12473 (0x30B9) - Write Sequencer 185 - */ -#define WM8995_WSEQ_DATA46_MASK 0x00FF /* WSEQ_DATA46 - [7:0] */ -#define WM8995_WSEQ_DATA46_SHIFT 0 /* WSEQ_DATA46 - [7:0] */ -#define WM8995_WSEQ_DATA46_WIDTH 8 /* WSEQ_DATA46 - [7:0] */ - -/* - * R12474 (0x30BA) - Write Sequencer 186 - */ -#define WM8995_WSEQ_DATA_WIDTH46_MASK 0x0700 /* WSEQ_DATA_WIDTH46 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH46_SHIFT 8 /* WSEQ_DATA_WIDTH46 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH46_WIDTH 3 /* WSEQ_DATA_WIDTH46 - [10:8] */ -#define WM8995_WSEQ_DATA_START46_MASK 0x000F /* WSEQ_DATA_START46 - [3:0] */ -#define WM8995_WSEQ_DATA_START46_SHIFT 0 /* WSEQ_DATA_START46 - [3:0] */ -#define WM8995_WSEQ_DATA_START46_WIDTH 4 /* WSEQ_DATA_START46 - [3:0] */ - -/* - * R12475 (0x30BB) - Write Sequencer 187 - */ -#define WM8995_WSEQ_EOS46 0x0100 /* WSEQ_EOS46 */ -#define WM8995_WSEQ_EOS46_MASK 0x0100 /* WSEQ_EOS46 */ -#define WM8995_WSEQ_EOS46_SHIFT 8 /* WSEQ_EOS46 */ -#define WM8995_WSEQ_EOS46_WIDTH 1 /* WSEQ_EOS46 */ -#define WM8995_WSEQ_DELAY46_MASK 0x000F /* WSEQ_DELAY46 - [3:0] */ -#define WM8995_WSEQ_DELAY46_SHIFT 0 /* WSEQ_DELAY46 - [3:0] */ -#define WM8995_WSEQ_DELAY46_WIDTH 4 /* WSEQ_DELAY46 - [3:0] */ - -/* - * R12476 (0x30BC) - Write Sequencer 188 - */ -#define WM8995_WSEQ_ADDR47_MASK 0x3FFF /* WSEQ_ADDR47 - [13:0] */ -#define WM8995_WSEQ_ADDR47_SHIFT 0 /* WSEQ_ADDR47 - [13:0] */ -#define WM8995_WSEQ_ADDR47_WIDTH 14 /* WSEQ_ADDR47 - [13:0] */ - -/* - * R12477 (0x30BD) - Write Sequencer 189 - */ -#define WM8995_WSEQ_DATA47_MASK 0x00FF /* WSEQ_DATA47 - [7:0] */ -#define WM8995_WSEQ_DATA47_SHIFT 0 /* WSEQ_DATA47 - [7:0] */ -#define WM8995_WSEQ_DATA47_WIDTH 8 /* WSEQ_DATA47 - [7:0] */ - -/* - * R12478 (0x30BE) - Write Sequencer 190 - */ -#define WM8995_WSEQ_DATA_WIDTH47_MASK 0x0700 /* WSEQ_DATA_WIDTH47 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH47_SHIFT 8 /* WSEQ_DATA_WIDTH47 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH47_WIDTH 3 /* WSEQ_DATA_WIDTH47 - [10:8] */ -#define WM8995_WSEQ_DATA_START47_MASK 0x000F /* WSEQ_DATA_START47 - [3:0] */ -#define WM8995_WSEQ_DATA_START47_SHIFT 0 /* WSEQ_DATA_START47 - [3:0] */ -#define WM8995_WSEQ_DATA_START47_WIDTH 4 /* WSEQ_DATA_START47 - [3:0] */ - -/* - * R12479 (0x30BF) - Write Sequencer 191 - */ -#define WM8995_WSEQ_EOS47 0x0100 /* WSEQ_EOS47 */ -#define WM8995_WSEQ_EOS47_MASK 0x0100 /* WSEQ_EOS47 */ -#define WM8995_WSEQ_EOS47_SHIFT 8 /* WSEQ_EOS47 */ -#define WM8995_WSEQ_EOS47_WIDTH 1 /* WSEQ_EOS47 */ -#define WM8995_WSEQ_DELAY47_MASK 0x000F /* WSEQ_DELAY47 - [3:0] */ -#define WM8995_WSEQ_DELAY47_SHIFT 0 /* WSEQ_DELAY47 - [3:0] */ -#define WM8995_WSEQ_DELAY47_WIDTH 4 /* WSEQ_DELAY47 - [3:0] */ - -/* - * R12480 (0x30C0) - Write Sequencer 192 - */ -#define WM8995_WSEQ_ADDR48_MASK 0x3FFF /* WSEQ_ADDR48 - [13:0] */ -#define WM8995_WSEQ_ADDR48_SHIFT 0 /* WSEQ_ADDR48 - [13:0] */ -#define WM8995_WSEQ_ADDR48_WIDTH 14 /* WSEQ_ADDR48 - [13:0] */ - -/* - * R12481 (0x30C1) - Write Sequencer 193 - */ -#define WM8995_WSEQ_DATA48_MASK 0x00FF /* WSEQ_DATA48 - [7:0] */ -#define WM8995_WSEQ_DATA48_SHIFT 0 /* WSEQ_DATA48 - [7:0] */ -#define WM8995_WSEQ_DATA48_WIDTH 8 /* WSEQ_DATA48 - [7:0] */ - -/* - * R12482 (0x30C2) - Write Sequencer 194 - */ -#define WM8995_WSEQ_DATA_WIDTH48_MASK 0x0700 /* WSEQ_DATA_WIDTH48 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH48_SHIFT 8 /* WSEQ_DATA_WIDTH48 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH48_WIDTH 3 /* WSEQ_DATA_WIDTH48 - [10:8] */ -#define WM8995_WSEQ_DATA_START48_MASK 0x000F /* WSEQ_DATA_START48 - [3:0] */ -#define WM8995_WSEQ_DATA_START48_SHIFT 0 /* WSEQ_DATA_START48 - [3:0] */ -#define WM8995_WSEQ_DATA_START48_WIDTH 4 /* WSEQ_DATA_START48 - [3:0] */ - -/* - * R12483 (0x30C3) - Write Sequencer 195 - */ -#define WM8995_WSEQ_EOS48 0x0100 /* WSEQ_EOS48 */ -#define WM8995_WSEQ_EOS48_MASK 0x0100 /* WSEQ_EOS48 */ -#define WM8995_WSEQ_EOS48_SHIFT 8 /* WSEQ_EOS48 */ -#define WM8995_WSEQ_EOS48_WIDTH 1 /* WSEQ_EOS48 */ -#define WM8995_WSEQ_DELAY48_MASK 0x000F /* WSEQ_DELAY48 - [3:0] */ -#define WM8995_WSEQ_DELAY48_SHIFT 0 /* WSEQ_DELAY48 - [3:0] */ -#define WM8995_WSEQ_DELAY48_WIDTH 4 /* WSEQ_DELAY48 - [3:0] */ - -/* - * R12484 (0x30C4) - Write Sequencer 196 - */ -#define WM8995_WSEQ_ADDR49_MASK 0x3FFF /* WSEQ_ADDR49 - [13:0] */ -#define WM8995_WSEQ_ADDR49_SHIFT 0 /* WSEQ_ADDR49 - [13:0] */ -#define WM8995_WSEQ_ADDR49_WIDTH 14 /* WSEQ_ADDR49 - [13:0] */ - -/* - * R12485 (0x30C5) - Write Sequencer 197 - */ -#define WM8995_WSEQ_DATA49_MASK 0x00FF /* WSEQ_DATA49 - [7:0] */ -#define WM8995_WSEQ_DATA49_SHIFT 0 /* WSEQ_DATA49 - [7:0] */ -#define WM8995_WSEQ_DATA49_WIDTH 8 /* WSEQ_DATA49 - [7:0] */ - -/* - * R12486 (0x30C6) - Write Sequencer 198 - */ -#define WM8995_WSEQ_DATA_WIDTH49_MASK 0x0700 /* WSEQ_DATA_WIDTH49 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH49_SHIFT 8 /* WSEQ_DATA_WIDTH49 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH49_WIDTH 3 /* WSEQ_DATA_WIDTH49 - [10:8] */ -#define WM8995_WSEQ_DATA_START49_MASK 0x000F /* WSEQ_DATA_START49 - [3:0] */ -#define WM8995_WSEQ_DATA_START49_SHIFT 0 /* WSEQ_DATA_START49 - [3:0] */ -#define WM8995_WSEQ_DATA_START49_WIDTH 4 /* WSEQ_DATA_START49 - [3:0] */ - -/* - * R12487 (0x30C7) - Write Sequencer 199 - */ -#define WM8995_WSEQ_EOS49 0x0100 /* WSEQ_EOS49 */ -#define WM8995_WSEQ_EOS49_MASK 0x0100 /* WSEQ_EOS49 */ -#define WM8995_WSEQ_EOS49_SHIFT 8 /* WSEQ_EOS49 */ -#define WM8995_WSEQ_EOS49_WIDTH 1 /* WSEQ_EOS49 */ -#define WM8995_WSEQ_DELAY49_MASK 0x000F /* WSEQ_DELAY49 - [3:0] */ -#define WM8995_WSEQ_DELAY49_SHIFT 0 /* WSEQ_DELAY49 - [3:0] */ -#define WM8995_WSEQ_DELAY49_WIDTH 4 /* WSEQ_DELAY49 - [3:0] */ - -/* - * R12488 (0x30C8) - Write Sequencer 200 - */ -#define WM8995_WSEQ_ADDR50_MASK 0x3FFF /* WSEQ_ADDR50 - [13:0] */ -#define WM8995_WSEQ_ADDR50_SHIFT 0 /* WSEQ_ADDR50 - [13:0] */ -#define WM8995_WSEQ_ADDR50_WIDTH 14 /* WSEQ_ADDR50 - [13:0] */ - -/* - * R12489 (0x30C9) - Write Sequencer 201 - */ -#define WM8995_WSEQ_DATA50_MASK 0x00FF /* WSEQ_DATA50 - [7:0] */ -#define WM8995_WSEQ_DATA50_SHIFT 0 /* WSEQ_DATA50 - [7:0] */ -#define WM8995_WSEQ_DATA50_WIDTH 8 /* WSEQ_DATA50 - [7:0] */ - -/* - * R12490 (0x30CA) - Write Sequencer 202 - */ -#define WM8995_WSEQ_DATA_WIDTH50_MASK 0x0700 /* WSEQ_DATA_WIDTH50 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH50_SHIFT 8 /* WSEQ_DATA_WIDTH50 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH50_WIDTH 3 /* WSEQ_DATA_WIDTH50 - [10:8] */ -#define WM8995_WSEQ_DATA_START50_MASK 0x000F /* WSEQ_DATA_START50 - [3:0] */ -#define WM8995_WSEQ_DATA_START50_SHIFT 0 /* WSEQ_DATA_START50 - [3:0] */ -#define WM8995_WSEQ_DATA_START50_WIDTH 4 /* WSEQ_DATA_START50 - [3:0] */ - -/* - * R12491 (0x30CB) - Write Sequencer 203 - */ -#define WM8995_WSEQ_EOS50 0x0100 /* WSEQ_EOS50 */ -#define WM8995_WSEQ_EOS50_MASK 0x0100 /* WSEQ_EOS50 */ -#define WM8995_WSEQ_EOS50_SHIFT 8 /* WSEQ_EOS50 */ -#define WM8995_WSEQ_EOS50_WIDTH 1 /* WSEQ_EOS50 */ -#define WM8995_WSEQ_DELAY50_MASK 0x000F /* WSEQ_DELAY50 - [3:0] */ -#define WM8995_WSEQ_DELAY50_SHIFT 0 /* WSEQ_DELAY50 - [3:0] */ -#define WM8995_WSEQ_DELAY50_WIDTH 4 /* WSEQ_DELAY50 - [3:0] */ - -/* - * R12492 (0x30CC) - Write Sequencer 204 - */ -#define WM8995_WSEQ_ADDR51_MASK 0x3FFF /* WSEQ_ADDR51 - [13:0] */ -#define WM8995_WSEQ_ADDR51_SHIFT 0 /* WSEQ_ADDR51 - [13:0] */ -#define WM8995_WSEQ_ADDR51_WIDTH 14 /* WSEQ_ADDR51 - [13:0] */ - -/* - * R12493 (0x30CD) - Write Sequencer 205 - */ -#define WM8995_WSEQ_DATA51_MASK 0x00FF /* WSEQ_DATA51 - [7:0] */ -#define WM8995_WSEQ_DATA51_SHIFT 0 /* WSEQ_DATA51 - [7:0] */ -#define WM8995_WSEQ_DATA51_WIDTH 8 /* WSEQ_DATA51 - [7:0] */ - -/* - * R12494 (0x30CE) - Write Sequencer 206 - */ -#define WM8995_WSEQ_DATA_WIDTH51_MASK 0x0700 /* WSEQ_DATA_WIDTH51 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH51_SHIFT 8 /* WSEQ_DATA_WIDTH51 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH51_WIDTH 3 /* WSEQ_DATA_WIDTH51 - [10:8] */ -#define WM8995_WSEQ_DATA_START51_MASK 0x000F /* WSEQ_DATA_START51 - [3:0] */ -#define WM8995_WSEQ_DATA_START51_SHIFT 0 /* WSEQ_DATA_START51 - [3:0] */ -#define WM8995_WSEQ_DATA_START51_WIDTH 4 /* WSEQ_DATA_START51 - [3:0] */ - -/* - * R12495 (0x30CF) - Write Sequencer 207 - */ -#define WM8995_WSEQ_EOS51 0x0100 /* WSEQ_EOS51 */ -#define WM8995_WSEQ_EOS51_MASK 0x0100 /* WSEQ_EOS51 */ -#define WM8995_WSEQ_EOS51_SHIFT 8 /* WSEQ_EOS51 */ -#define WM8995_WSEQ_EOS51_WIDTH 1 /* WSEQ_EOS51 */ -#define WM8995_WSEQ_DELAY51_MASK 0x000F /* WSEQ_DELAY51 - [3:0] */ -#define WM8995_WSEQ_DELAY51_SHIFT 0 /* WSEQ_DELAY51 - [3:0] */ -#define WM8995_WSEQ_DELAY51_WIDTH 4 /* WSEQ_DELAY51 - [3:0] */ - -/* - * R12496 (0x30D0) - Write Sequencer 208 - */ -#define WM8995_WSEQ_ADDR52_MASK 0x3FFF /* WSEQ_ADDR52 - [13:0] */ -#define WM8995_WSEQ_ADDR52_SHIFT 0 /* WSEQ_ADDR52 - [13:0] */ -#define WM8995_WSEQ_ADDR52_WIDTH 14 /* WSEQ_ADDR52 - [13:0] */ - -/* - * R12497 (0x30D1) - Write Sequencer 209 - */ -#define WM8995_WSEQ_DATA52_MASK 0x00FF /* WSEQ_DATA52 - [7:0] */ -#define WM8995_WSEQ_DATA52_SHIFT 0 /* WSEQ_DATA52 - [7:0] */ -#define WM8995_WSEQ_DATA52_WIDTH 8 /* WSEQ_DATA52 - [7:0] */ - -/* - * R12498 (0x30D2) - Write Sequencer 210 - */ -#define WM8995_WSEQ_DATA_WIDTH52_MASK 0x0700 /* WSEQ_DATA_WIDTH52 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH52_SHIFT 8 /* WSEQ_DATA_WIDTH52 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH52_WIDTH 3 /* WSEQ_DATA_WIDTH52 - [10:8] */ -#define WM8995_WSEQ_DATA_START52_MASK 0x000F /* WSEQ_DATA_START52 - [3:0] */ -#define WM8995_WSEQ_DATA_START52_SHIFT 0 /* WSEQ_DATA_START52 - [3:0] */ -#define WM8995_WSEQ_DATA_START52_WIDTH 4 /* WSEQ_DATA_START52 - [3:0] */ - -/* - * R12499 (0x30D3) - Write Sequencer 211 - */ -#define WM8995_WSEQ_EOS52 0x0100 /* WSEQ_EOS52 */ -#define WM8995_WSEQ_EOS52_MASK 0x0100 /* WSEQ_EOS52 */ -#define WM8995_WSEQ_EOS52_SHIFT 8 /* WSEQ_EOS52 */ -#define WM8995_WSEQ_EOS52_WIDTH 1 /* WSEQ_EOS52 */ -#define WM8995_WSEQ_DELAY52_MASK 0x000F /* WSEQ_DELAY52 - [3:0] */ -#define WM8995_WSEQ_DELAY52_SHIFT 0 /* WSEQ_DELAY52 - [3:0] */ -#define WM8995_WSEQ_DELAY52_WIDTH 4 /* WSEQ_DELAY52 - [3:0] */ - -/* - * R12500 (0x30D4) - Write Sequencer 212 - */ -#define WM8995_WSEQ_ADDR53_MASK 0x3FFF /* WSEQ_ADDR53 - [13:0] */ -#define WM8995_WSEQ_ADDR53_SHIFT 0 /* WSEQ_ADDR53 - [13:0] */ -#define WM8995_WSEQ_ADDR53_WIDTH 14 /* WSEQ_ADDR53 - [13:0] */ - -/* - * R12501 (0x30D5) - Write Sequencer 213 - */ -#define WM8995_WSEQ_DATA53_MASK 0x00FF /* WSEQ_DATA53 - [7:0] */ -#define WM8995_WSEQ_DATA53_SHIFT 0 /* WSEQ_DATA53 - [7:0] */ -#define WM8995_WSEQ_DATA53_WIDTH 8 /* WSEQ_DATA53 - [7:0] */ - -/* - * R12502 (0x30D6) - Write Sequencer 214 - */ -#define WM8995_WSEQ_DATA_WIDTH53_MASK 0x0700 /* WSEQ_DATA_WIDTH53 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH53_SHIFT 8 /* WSEQ_DATA_WIDTH53 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH53_WIDTH 3 /* WSEQ_DATA_WIDTH53 - [10:8] */ -#define WM8995_WSEQ_DATA_START53_MASK 0x000F /* WSEQ_DATA_START53 - [3:0] */ -#define WM8995_WSEQ_DATA_START53_SHIFT 0 /* WSEQ_DATA_START53 - [3:0] */ -#define WM8995_WSEQ_DATA_START53_WIDTH 4 /* WSEQ_DATA_START53 - [3:0] */ - -/* - * R12503 (0x30D7) - Write Sequencer 215 - */ -#define WM8995_WSEQ_EOS53 0x0100 /* WSEQ_EOS53 */ -#define WM8995_WSEQ_EOS53_MASK 0x0100 /* WSEQ_EOS53 */ -#define WM8995_WSEQ_EOS53_SHIFT 8 /* WSEQ_EOS53 */ -#define WM8995_WSEQ_EOS53_WIDTH 1 /* WSEQ_EOS53 */ -#define WM8995_WSEQ_DELAY53_MASK 0x000F /* WSEQ_DELAY53 - [3:0] */ -#define WM8995_WSEQ_DELAY53_SHIFT 0 /* WSEQ_DELAY53 - [3:0] */ -#define WM8995_WSEQ_DELAY53_WIDTH 4 /* WSEQ_DELAY53 - [3:0] */ - -/* - * R12504 (0x30D8) - Write Sequencer 216 - */ -#define WM8995_WSEQ_ADDR54_MASK 0x3FFF /* WSEQ_ADDR54 - [13:0] */ -#define WM8995_WSEQ_ADDR54_SHIFT 0 /* WSEQ_ADDR54 - [13:0] */ -#define WM8995_WSEQ_ADDR54_WIDTH 14 /* WSEQ_ADDR54 - [13:0] */ - -/* - * R12505 (0x30D9) - Write Sequencer 217 - */ -#define WM8995_WSEQ_DATA54_MASK 0x00FF /* WSEQ_DATA54 - [7:0] */ -#define WM8995_WSEQ_DATA54_SHIFT 0 /* WSEQ_DATA54 - [7:0] */ -#define WM8995_WSEQ_DATA54_WIDTH 8 /* WSEQ_DATA54 - [7:0] */ - -/* - * R12506 (0x30DA) - Write Sequencer 218 - */ -#define WM8995_WSEQ_DATA_WIDTH54_MASK 0x0700 /* WSEQ_DATA_WIDTH54 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH54_SHIFT 8 /* WSEQ_DATA_WIDTH54 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH54_WIDTH 3 /* WSEQ_DATA_WIDTH54 - [10:8] */ -#define WM8995_WSEQ_DATA_START54_MASK 0x000F /* WSEQ_DATA_START54 - [3:0] */ -#define WM8995_WSEQ_DATA_START54_SHIFT 0 /* WSEQ_DATA_START54 - [3:0] */ -#define WM8995_WSEQ_DATA_START54_WIDTH 4 /* WSEQ_DATA_START54 - [3:0] */ - -/* - * R12507 (0x30DB) - Write Sequencer 219 - */ -#define WM8995_WSEQ_EOS54 0x0100 /* WSEQ_EOS54 */ -#define WM8995_WSEQ_EOS54_MASK 0x0100 /* WSEQ_EOS54 */ -#define WM8995_WSEQ_EOS54_SHIFT 8 /* WSEQ_EOS54 */ -#define WM8995_WSEQ_EOS54_WIDTH 1 /* WSEQ_EOS54 */ -#define WM8995_WSEQ_DELAY54_MASK 0x000F /* WSEQ_DELAY54 - [3:0] */ -#define WM8995_WSEQ_DELAY54_SHIFT 0 /* WSEQ_DELAY54 - [3:0] */ -#define WM8995_WSEQ_DELAY54_WIDTH 4 /* WSEQ_DELAY54 - [3:0] */ - -/* - * R12508 (0x30DC) - Write Sequencer 220 - */ -#define WM8995_WSEQ_ADDR55_MASK 0x3FFF /* WSEQ_ADDR55 - [13:0] */ -#define WM8995_WSEQ_ADDR55_SHIFT 0 /* WSEQ_ADDR55 - [13:0] */ -#define WM8995_WSEQ_ADDR55_WIDTH 14 /* WSEQ_ADDR55 - [13:0] */ - -/* - * R12509 (0x30DD) - Write Sequencer 221 - */ -#define WM8995_WSEQ_DATA55_MASK 0x00FF /* WSEQ_DATA55 - [7:0] */ -#define WM8995_WSEQ_DATA55_SHIFT 0 /* WSEQ_DATA55 - [7:0] */ -#define WM8995_WSEQ_DATA55_WIDTH 8 /* WSEQ_DATA55 - [7:0] */ - -/* - * R12510 (0x30DE) - Write Sequencer 222 - */ -#define WM8995_WSEQ_DATA_WIDTH55_MASK 0x0700 /* WSEQ_DATA_WIDTH55 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH55_SHIFT 8 /* WSEQ_DATA_WIDTH55 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH55_WIDTH 3 /* WSEQ_DATA_WIDTH55 - [10:8] */ -#define WM8995_WSEQ_DATA_START55_MASK 0x000F /* WSEQ_DATA_START55 - [3:0] */ -#define WM8995_WSEQ_DATA_START55_SHIFT 0 /* WSEQ_DATA_START55 - [3:0] */ -#define WM8995_WSEQ_DATA_START55_WIDTH 4 /* WSEQ_DATA_START55 - [3:0] */ - -/* - * R12511 (0x30DF) - Write Sequencer 223 - */ -#define WM8995_WSEQ_EOS55 0x0100 /* WSEQ_EOS55 */ -#define WM8995_WSEQ_EOS55_MASK 0x0100 /* WSEQ_EOS55 */ -#define WM8995_WSEQ_EOS55_SHIFT 8 /* WSEQ_EOS55 */ -#define WM8995_WSEQ_EOS55_WIDTH 1 /* WSEQ_EOS55 */ -#define WM8995_WSEQ_DELAY55_MASK 0x000F /* WSEQ_DELAY55 - [3:0] */ -#define WM8995_WSEQ_DELAY55_SHIFT 0 /* WSEQ_DELAY55 - [3:0] */ -#define WM8995_WSEQ_DELAY55_WIDTH 4 /* WSEQ_DELAY55 - [3:0] */ - -/* - * R12512 (0x30E0) - Write Sequencer 224 - */ -#define WM8995_WSEQ_ADDR56_MASK 0x3FFF /* WSEQ_ADDR56 - [13:0] */ -#define WM8995_WSEQ_ADDR56_SHIFT 0 /* WSEQ_ADDR56 - [13:0] */ -#define WM8995_WSEQ_ADDR56_WIDTH 14 /* WSEQ_ADDR56 - [13:0] */ - -/* - * R12513 (0x30E1) - Write Sequencer 225 - */ -#define WM8995_WSEQ_DATA56_MASK 0x00FF /* WSEQ_DATA56 - [7:0] */ -#define WM8995_WSEQ_DATA56_SHIFT 0 /* WSEQ_DATA56 - [7:0] */ -#define WM8995_WSEQ_DATA56_WIDTH 8 /* WSEQ_DATA56 - [7:0] */ - -/* - * R12514 (0x30E2) - Write Sequencer 226 - */ -#define WM8995_WSEQ_DATA_WIDTH56_MASK 0x0700 /* WSEQ_DATA_WIDTH56 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH56_SHIFT 8 /* WSEQ_DATA_WIDTH56 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH56_WIDTH 3 /* WSEQ_DATA_WIDTH56 - [10:8] */ -#define WM8995_WSEQ_DATA_START56_MASK 0x000F /* WSEQ_DATA_START56 - [3:0] */ -#define WM8995_WSEQ_DATA_START56_SHIFT 0 /* WSEQ_DATA_START56 - [3:0] */ -#define WM8995_WSEQ_DATA_START56_WIDTH 4 /* WSEQ_DATA_START56 - [3:0] */ - -/* - * R12515 (0x30E3) - Write Sequencer 227 - */ -#define WM8995_WSEQ_EOS56 0x0100 /* WSEQ_EOS56 */ -#define WM8995_WSEQ_EOS56_MASK 0x0100 /* WSEQ_EOS56 */ -#define WM8995_WSEQ_EOS56_SHIFT 8 /* WSEQ_EOS56 */ -#define WM8995_WSEQ_EOS56_WIDTH 1 /* WSEQ_EOS56 */ -#define WM8995_WSEQ_DELAY56_MASK 0x000F /* WSEQ_DELAY56 - [3:0] */ -#define WM8995_WSEQ_DELAY56_SHIFT 0 /* WSEQ_DELAY56 - [3:0] */ -#define WM8995_WSEQ_DELAY56_WIDTH 4 /* WSEQ_DELAY56 - [3:0] */ - -/* - * R12516 (0x30E4) - Write Sequencer 228 - */ -#define WM8995_WSEQ_ADDR57_MASK 0x3FFF /* WSEQ_ADDR57 - [13:0] */ -#define WM8995_WSEQ_ADDR57_SHIFT 0 /* WSEQ_ADDR57 - [13:0] */ -#define WM8995_WSEQ_ADDR57_WIDTH 14 /* WSEQ_ADDR57 - [13:0] */ - -/* - * R12517 (0x30E5) - Write Sequencer 229 - */ -#define WM8995_WSEQ_DATA57_MASK 0x00FF /* WSEQ_DATA57 - [7:0] */ -#define WM8995_WSEQ_DATA57_SHIFT 0 /* WSEQ_DATA57 - [7:0] */ -#define WM8995_WSEQ_DATA57_WIDTH 8 /* WSEQ_DATA57 - [7:0] */ - -/* - * R12518 (0x30E6) - Write Sequencer 230 - */ -#define WM8995_WSEQ_DATA_WIDTH57_MASK 0x0700 /* WSEQ_DATA_WIDTH57 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH57_SHIFT 8 /* WSEQ_DATA_WIDTH57 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH57_WIDTH 3 /* WSEQ_DATA_WIDTH57 - [10:8] */ -#define WM8995_WSEQ_DATA_START57_MASK 0x000F /* WSEQ_DATA_START57 - [3:0] */ -#define WM8995_WSEQ_DATA_START57_SHIFT 0 /* WSEQ_DATA_START57 - [3:0] */ -#define WM8995_WSEQ_DATA_START57_WIDTH 4 /* WSEQ_DATA_START57 - [3:0] */ - -/* - * R12519 (0x30E7) - Write Sequencer 231 - */ -#define WM8995_WSEQ_EOS57 0x0100 /* WSEQ_EOS57 */ -#define WM8995_WSEQ_EOS57_MASK 0x0100 /* WSEQ_EOS57 */ -#define WM8995_WSEQ_EOS57_SHIFT 8 /* WSEQ_EOS57 */ -#define WM8995_WSEQ_EOS57_WIDTH 1 /* WSEQ_EOS57 */ -#define WM8995_WSEQ_DELAY57_MASK 0x000F /* WSEQ_DELAY57 - [3:0] */ -#define WM8995_WSEQ_DELAY57_SHIFT 0 /* WSEQ_DELAY57 - [3:0] */ -#define WM8995_WSEQ_DELAY57_WIDTH 4 /* WSEQ_DELAY57 - [3:0] */ - -/* - * R12520 (0x30E8) - Write Sequencer 232 - */ -#define WM8995_WSEQ_ADDR58_MASK 0x3FFF /* WSEQ_ADDR58 - [13:0] */ -#define WM8995_WSEQ_ADDR58_SHIFT 0 /* WSEQ_ADDR58 - [13:0] */ -#define WM8995_WSEQ_ADDR58_WIDTH 14 /* WSEQ_ADDR58 - [13:0] */ - -/* - * R12521 (0x30E9) - Write Sequencer 233 - */ -#define WM8995_WSEQ_DATA58_MASK 0x00FF /* WSEQ_DATA58 - [7:0] */ -#define WM8995_WSEQ_DATA58_SHIFT 0 /* WSEQ_DATA58 - [7:0] */ -#define WM8995_WSEQ_DATA58_WIDTH 8 /* WSEQ_DATA58 - [7:0] */ - -/* - * R12522 (0x30EA) - Write Sequencer 234 - */ -#define WM8995_WSEQ_DATA_WIDTH58_MASK 0x0700 /* WSEQ_DATA_WIDTH58 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH58_SHIFT 8 /* WSEQ_DATA_WIDTH58 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH58_WIDTH 3 /* WSEQ_DATA_WIDTH58 - [10:8] */ -#define WM8995_WSEQ_DATA_START58_MASK 0x000F /* WSEQ_DATA_START58 - [3:0] */ -#define WM8995_WSEQ_DATA_START58_SHIFT 0 /* WSEQ_DATA_START58 - [3:0] */ -#define WM8995_WSEQ_DATA_START58_WIDTH 4 /* WSEQ_DATA_START58 - [3:0] */ - -/* - * R12523 (0x30EB) - Write Sequencer 235 - */ -#define WM8995_WSEQ_EOS58 0x0100 /* WSEQ_EOS58 */ -#define WM8995_WSEQ_EOS58_MASK 0x0100 /* WSEQ_EOS58 */ -#define WM8995_WSEQ_EOS58_SHIFT 8 /* WSEQ_EOS58 */ -#define WM8995_WSEQ_EOS58_WIDTH 1 /* WSEQ_EOS58 */ -#define WM8995_WSEQ_DELAY58_MASK 0x000F /* WSEQ_DELAY58 - [3:0] */ -#define WM8995_WSEQ_DELAY58_SHIFT 0 /* WSEQ_DELAY58 - [3:0] */ -#define WM8995_WSEQ_DELAY58_WIDTH 4 /* WSEQ_DELAY58 - [3:0] */ - -/* - * R12524 (0x30EC) - Write Sequencer 236 - */ -#define WM8995_WSEQ_ADDR59_MASK 0x3FFF /* WSEQ_ADDR59 - [13:0] */ -#define WM8995_WSEQ_ADDR59_SHIFT 0 /* WSEQ_ADDR59 - [13:0] */ -#define WM8995_WSEQ_ADDR59_WIDTH 14 /* WSEQ_ADDR59 - [13:0] */ - -/* - * R12525 (0x30ED) - Write Sequencer 237 - */ -#define WM8995_WSEQ_DATA59_MASK 0x00FF /* WSEQ_DATA59 - [7:0] */ -#define WM8995_WSEQ_DATA59_SHIFT 0 /* WSEQ_DATA59 - [7:0] */ -#define WM8995_WSEQ_DATA59_WIDTH 8 /* WSEQ_DATA59 - [7:0] */ - -/* - * R12526 (0x30EE) - Write Sequencer 238 - */ -#define WM8995_WSEQ_DATA_WIDTH59_MASK 0x0700 /* WSEQ_DATA_WIDTH59 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH59_SHIFT 8 /* WSEQ_DATA_WIDTH59 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH59_WIDTH 3 /* WSEQ_DATA_WIDTH59 - [10:8] */ -#define WM8995_WSEQ_DATA_START59_MASK 0x000F /* WSEQ_DATA_START59 - [3:0] */ -#define WM8995_WSEQ_DATA_START59_SHIFT 0 /* WSEQ_DATA_START59 - [3:0] */ -#define WM8995_WSEQ_DATA_START59_WIDTH 4 /* WSEQ_DATA_START59 - [3:0] */ - -/* - * R12527 (0x30EF) - Write Sequencer 239 - */ -#define WM8995_WSEQ_EOS59 0x0100 /* WSEQ_EOS59 */ -#define WM8995_WSEQ_EOS59_MASK 0x0100 /* WSEQ_EOS59 */ -#define WM8995_WSEQ_EOS59_SHIFT 8 /* WSEQ_EOS59 */ -#define WM8995_WSEQ_EOS59_WIDTH 1 /* WSEQ_EOS59 */ -#define WM8995_WSEQ_DELAY59_MASK 0x000F /* WSEQ_DELAY59 - [3:0] */ -#define WM8995_WSEQ_DELAY59_SHIFT 0 /* WSEQ_DELAY59 - [3:0] */ -#define WM8995_WSEQ_DELAY59_WIDTH 4 /* WSEQ_DELAY59 - [3:0] */ - -/* - * R12528 (0x30F0) - Write Sequencer 240 - */ -#define WM8995_WSEQ_ADDR60_MASK 0x3FFF /* WSEQ_ADDR60 - [13:0] */ -#define WM8995_WSEQ_ADDR60_SHIFT 0 /* WSEQ_ADDR60 - [13:0] */ -#define WM8995_WSEQ_ADDR60_WIDTH 14 /* WSEQ_ADDR60 - [13:0] */ - -/* - * R12529 (0x30F1) - Write Sequencer 241 - */ -#define WM8995_WSEQ_DATA60_MASK 0x00FF /* WSEQ_DATA60 - [7:0] */ -#define WM8995_WSEQ_DATA60_SHIFT 0 /* WSEQ_DATA60 - [7:0] */ -#define WM8995_WSEQ_DATA60_WIDTH 8 /* WSEQ_DATA60 - [7:0] */ - -/* - * R12530 (0x30F2) - Write Sequencer 242 - */ -#define WM8995_WSEQ_DATA_WIDTH60_MASK 0x0700 /* WSEQ_DATA_WIDTH60 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH60_SHIFT 8 /* WSEQ_DATA_WIDTH60 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH60_WIDTH 3 /* WSEQ_DATA_WIDTH60 - [10:8] */ -#define WM8995_WSEQ_DATA_START60_MASK 0x000F /* WSEQ_DATA_START60 - [3:0] */ -#define WM8995_WSEQ_DATA_START60_SHIFT 0 /* WSEQ_DATA_START60 - [3:0] */ -#define WM8995_WSEQ_DATA_START60_WIDTH 4 /* WSEQ_DATA_START60 - [3:0] */ - -/* - * R12531 (0x30F3) - Write Sequencer 243 - */ -#define WM8995_WSEQ_EOS60 0x0100 /* WSEQ_EOS60 */ -#define WM8995_WSEQ_EOS60_MASK 0x0100 /* WSEQ_EOS60 */ -#define WM8995_WSEQ_EOS60_SHIFT 8 /* WSEQ_EOS60 */ -#define WM8995_WSEQ_EOS60_WIDTH 1 /* WSEQ_EOS60 */ -#define WM8995_WSEQ_DELAY60_MASK 0x000F /* WSEQ_DELAY60 - [3:0] */ -#define WM8995_WSEQ_DELAY60_SHIFT 0 /* WSEQ_DELAY60 - [3:0] */ -#define WM8995_WSEQ_DELAY60_WIDTH 4 /* WSEQ_DELAY60 - [3:0] */ - -/* - * R12532 (0x30F4) - Write Sequencer 244 - */ -#define WM8995_WSEQ_ADDR61_MASK 0x3FFF /* WSEQ_ADDR61 - [13:0] */ -#define WM8995_WSEQ_ADDR61_SHIFT 0 /* WSEQ_ADDR61 - [13:0] */ -#define WM8995_WSEQ_ADDR61_WIDTH 14 /* WSEQ_ADDR61 - [13:0] */ - -/* - * R12533 (0x30F5) - Write Sequencer 245 - */ -#define WM8995_WSEQ_DATA61_MASK 0x00FF /* WSEQ_DATA61 - [7:0] */ -#define WM8995_WSEQ_DATA61_SHIFT 0 /* WSEQ_DATA61 - [7:0] */ -#define WM8995_WSEQ_DATA61_WIDTH 8 /* WSEQ_DATA61 - [7:0] */ - -/* - * R12534 (0x30F6) - Write Sequencer 246 - */ -#define WM8995_WSEQ_DATA_WIDTH61_MASK 0x0700 /* WSEQ_DATA_WIDTH61 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH61_SHIFT 8 /* WSEQ_DATA_WIDTH61 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH61_WIDTH 3 /* WSEQ_DATA_WIDTH61 - [10:8] */ -#define WM8995_WSEQ_DATA_START61_MASK 0x000F /* WSEQ_DATA_START61 - [3:0] */ -#define WM8995_WSEQ_DATA_START61_SHIFT 0 /* WSEQ_DATA_START61 - [3:0] */ -#define WM8995_WSEQ_DATA_START61_WIDTH 4 /* WSEQ_DATA_START61 - [3:0] */ - -/* - * R12535 (0x30F7) - Write Sequencer 247 - */ -#define WM8995_WSEQ_EOS61 0x0100 /* WSEQ_EOS61 */ -#define WM8995_WSEQ_EOS61_MASK 0x0100 /* WSEQ_EOS61 */ -#define WM8995_WSEQ_EOS61_SHIFT 8 /* WSEQ_EOS61 */ -#define WM8995_WSEQ_EOS61_WIDTH 1 /* WSEQ_EOS61 */ -#define WM8995_WSEQ_DELAY61_MASK 0x000F /* WSEQ_DELAY61 - [3:0] */ -#define WM8995_WSEQ_DELAY61_SHIFT 0 /* WSEQ_DELAY61 - [3:0] */ -#define WM8995_WSEQ_DELAY61_WIDTH 4 /* WSEQ_DELAY61 - [3:0] */ - -/* - * R12536 (0x30F8) - Write Sequencer 248 - */ -#define WM8995_WSEQ_ADDR62_MASK 0x3FFF /* WSEQ_ADDR62 - [13:0] */ -#define WM8995_WSEQ_ADDR62_SHIFT 0 /* WSEQ_ADDR62 - [13:0] */ -#define WM8995_WSEQ_ADDR62_WIDTH 14 /* WSEQ_ADDR62 - [13:0] */ - -/* - * R12537 (0x30F9) - Write Sequencer 249 - */ -#define WM8995_WSEQ_DATA62_MASK 0x00FF /* WSEQ_DATA62 - [7:0] */ -#define WM8995_WSEQ_DATA62_SHIFT 0 /* WSEQ_DATA62 - [7:0] */ -#define WM8995_WSEQ_DATA62_WIDTH 8 /* WSEQ_DATA62 - [7:0] */ - -/* - * R12538 (0x30FA) - Write Sequencer 250 - */ -#define WM8995_WSEQ_DATA_WIDTH62_MASK 0x0700 /* WSEQ_DATA_WIDTH62 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH62_SHIFT 8 /* WSEQ_DATA_WIDTH62 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH62_WIDTH 3 /* WSEQ_DATA_WIDTH62 - [10:8] */ -#define WM8995_WSEQ_DATA_START62_MASK 0x000F /* WSEQ_DATA_START62 - [3:0] */ -#define WM8995_WSEQ_DATA_START62_SHIFT 0 /* WSEQ_DATA_START62 - [3:0] */ -#define WM8995_WSEQ_DATA_START62_WIDTH 4 /* WSEQ_DATA_START62 - [3:0] */ - -/* - * R12539 (0x30FB) - Write Sequencer 251 - */ -#define WM8995_WSEQ_EOS62 0x0100 /* WSEQ_EOS62 */ -#define WM8995_WSEQ_EOS62_MASK 0x0100 /* WSEQ_EOS62 */ -#define WM8995_WSEQ_EOS62_SHIFT 8 /* WSEQ_EOS62 */ -#define WM8995_WSEQ_EOS62_WIDTH 1 /* WSEQ_EOS62 */ -#define WM8995_WSEQ_DELAY62_MASK 0x000F /* WSEQ_DELAY62 - [3:0] */ -#define WM8995_WSEQ_DELAY62_SHIFT 0 /* WSEQ_DELAY62 - [3:0] */ -#define WM8995_WSEQ_DELAY62_WIDTH 4 /* WSEQ_DELAY62 - [3:0] */ - -/* - * R12540 (0x30FC) - Write Sequencer 252 - */ -#define WM8995_WSEQ_ADDR63_MASK 0x3FFF /* WSEQ_ADDR63 - [13:0] */ -#define WM8995_WSEQ_ADDR63_SHIFT 0 /* WSEQ_ADDR63 - [13:0] */ -#define WM8995_WSEQ_ADDR63_WIDTH 14 /* WSEQ_ADDR63 - [13:0] */ - -/* - * R12541 (0x30FD) - Write Sequencer 253 - */ -#define WM8995_WSEQ_DATA63_MASK 0x00FF /* WSEQ_DATA63 - [7:0] */ -#define WM8995_WSEQ_DATA63_SHIFT 0 /* WSEQ_DATA63 - [7:0] */ -#define WM8995_WSEQ_DATA63_WIDTH 8 /* WSEQ_DATA63 - [7:0] */ - -/* - * R12542 (0x30FE) - Write Sequencer 254 - */ -#define WM8995_WSEQ_DATA_WIDTH63_MASK 0x0700 /* WSEQ_DATA_WIDTH63 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH63_SHIFT 8 /* WSEQ_DATA_WIDTH63 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH63_WIDTH 3 /* WSEQ_DATA_WIDTH63 - [10:8] */ -#define WM8995_WSEQ_DATA_START63_MASK 0x000F /* WSEQ_DATA_START63 - [3:0] */ -#define WM8995_WSEQ_DATA_START63_SHIFT 0 /* WSEQ_DATA_START63 - [3:0] */ -#define WM8995_WSEQ_DATA_START63_WIDTH 4 /* WSEQ_DATA_START63 - [3:0] */ - -/* - * R12543 (0x30FF) - Write Sequencer 255 - */ -#define WM8995_WSEQ_EOS63 0x0100 /* WSEQ_EOS63 */ -#define WM8995_WSEQ_EOS63_MASK 0x0100 /* WSEQ_EOS63 */ -#define WM8995_WSEQ_EOS63_SHIFT 8 /* WSEQ_EOS63 */ -#define WM8995_WSEQ_EOS63_WIDTH 1 /* WSEQ_EOS63 */ -#define WM8995_WSEQ_DELAY63_MASK 0x000F /* WSEQ_DELAY63 - [3:0] */ -#define WM8995_WSEQ_DELAY63_SHIFT 0 /* WSEQ_DELAY63 - [3:0] */ -#define WM8995_WSEQ_DELAY63_WIDTH 4 /* WSEQ_DELAY63 - [3:0] */ - -/* - * R12544 (0x3100) - Write Sequencer 256 - */ -#define WM8995_WSEQ_ADDR64_MASK 0x3FFF /* WSEQ_ADDR64 - [13:0] */ -#define WM8995_WSEQ_ADDR64_SHIFT 0 /* WSEQ_ADDR64 - [13:0] */ -#define WM8995_WSEQ_ADDR64_WIDTH 14 /* WSEQ_ADDR64 - [13:0] */ - -/* - * R12545 (0x3101) - Write Sequencer 257 - */ -#define WM8995_WSEQ_DATA64_MASK 0x00FF /* WSEQ_DATA64 - [7:0] */ -#define WM8995_WSEQ_DATA64_SHIFT 0 /* WSEQ_DATA64 - [7:0] */ -#define WM8995_WSEQ_DATA64_WIDTH 8 /* WSEQ_DATA64 - [7:0] */ - -/* - * R12546 (0x3102) - Write Sequencer 258 - */ -#define WM8995_WSEQ_DATA_WIDTH64_MASK 0x0700 /* WSEQ_DATA_WIDTH64 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH64_SHIFT 8 /* WSEQ_DATA_WIDTH64 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH64_WIDTH 3 /* WSEQ_DATA_WIDTH64 - [10:8] */ -#define WM8995_WSEQ_DATA_START64_MASK 0x000F /* WSEQ_DATA_START64 - [3:0] */ -#define WM8995_WSEQ_DATA_START64_SHIFT 0 /* WSEQ_DATA_START64 - [3:0] */ -#define WM8995_WSEQ_DATA_START64_WIDTH 4 /* WSEQ_DATA_START64 - [3:0] */ - -/* - * R12547 (0x3103) - Write Sequencer 259 - */ -#define WM8995_WSEQ_EOS64 0x0100 /* WSEQ_EOS64 */ -#define WM8995_WSEQ_EOS64_MASK 0x0100 /* WSEQ_EOS64 */ -#define WM8995_WSEQ_EOS64_SHIFT 8 /* WSEQ_EOS64 */ -#define WM8995_WSEQ_EOS64_WIDTH 1 /* WSEQ_EOS64 */ -#define WM8995_WSEQ_DELAY64_MASK 0x000F /* WSEQ_DELAY64 - [3:0] */ -#define WM8995_WSEQ_DELAY64_SHIFT 0 /* WSEQ_DELAY64 - [3:0] */ -#define WM8995_WSEQ_DELAY64_WIDTH 4 /* WSEQ_DELAY64 - [3:0] */ - -/* - * R12548 (0x3104) - Write Sequencer 260 - */ -#define WM8995_WSEQ_ADDR65_MASK 0x3FFF /* WSEQ_ADDR65 - [13:0] */ -#define WM8995_WSEQ_ADDR65_SHIFT 0 /* WSEQ_ADDR65 - [13:0] */ -#define WM8995_WSEQ_ADDR65_WIDTH 14 /* WSEQ_ADDR65 - [13:0] */ - -/* - * R12549 (0x3105) - Write Sequencer 261 - */ -#define WM8995_WSEQ_DATA65_MASK 0x00FF /* WSEQ_DATA65 - [7:0] */ -#define WM8995_WSEQ_DATA65_SHIFT 0 /* WSEQ_DATA65 - [7:0] */ -#define WM8995_WSEQ_DATA65_WIDTH 8 /* WSEQ_DATA65 - [7:0] */ - -/* - * R12550 (0x3106) - Write Sequencer 262 - */ -#define WM8995_WSEQ_DATA_WIDTH65_MASK 0x0700 /* WSEQ_DATA_WIDTH65 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH65_SHIFT 8 /* WSEQ_DATA_WIDTH65 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH65_WIDTH 3 /* WSEQ_DATA_WIDTH65 - [10:8] */ -#define WM8995_WSEQ_DATA_START65_MASK 0x000F /* WSEQ_DATA_START65 - [3:0] */ -#define WM8995_WSEQ_DATA_START65_SHIFT 0 /* WSEQ_DATA_START65 - [3:0] */ -#define WM8995_WSEQ_DATA_START65_WIDTH 4 /* WSEQ_DATA_START65 - [3:0] */ - -/* - * R12551 (0x3107) - Write Sequencer 263 - */ -#define WM8995_WSEQ_EOS65 0x0100 /* WSEQ_EOS65 */ -#define WM8995_WSEQ_EOS65_MASK 0x0100 /* WSEQ_EOS65 */ -#define WM8995_WSEQ_EOS65_SHIFT 8 /* WSEQ_EOS65 */ -#define WM8995_WSEQ_EOS65_WIDTH 1 /* WSEQ_EOS65 */ -#define WM8995_WSEQ_DELAY65_MASK 0x000F /* WSEQ_DELAY65 - [3:0] */ -#define WM8995_WSEQ_DELAY65_SHIFT 0 /* WSEQ_DELAY65 - [3:0] */ -#define WM8995_WSEQ_DELAY65_WIDTH 4 /* WSEQ_DELAY65 - [3:0] */ - -/* - * R12552 (0x3108) - Write Sequencer 264 - */ -#define WM8995_WSEQ_ADDR66_MASK 0x3FFF /* WSEQ_ADDR66 - [13:0] */ -#define WM8995_WSEQ_ADDR66_SHIFT 0 /* WSEQ_ADDR66 - [13:0] */ -#define WM8995_WSEQ_ADDR66_WIDTH 14 /* WSEQ_ADDR66 - [13:0] */ - -/* - * R12553 (0x3109) - Write Sequencer 265 - */ -#define WM8995_WSEQ_DATA66_MASK 0x00FF /* WSEQ_DATA66 - [7:0] */ -#define WM8995_WSEQ_DATA66_SHIFT 0 /* WSEQ_DATA66 - [7:0] */ -#define WM8995_WSEQ_DATA66_WIDTH 8 /* WSEQ_DATA66 - [7:0] */ - -/* - * R12554 (0x310A) - Write Sequencer 266 - */ -#define WM8995_WSEQ_DATA_WIDTH66_MASK 0x0700 /* WSEQ_DATA_WIDTH66 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH66_SHIFT 8 /* WSEQ_DATA_WIDTH66 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH66_WIDTH 3 /* WSEQ_DATA_WIDTH66 - [10:8] */ -#define WM8995_WSEQ_DATA_START66_MASK 0x000F /* WSEQ_DATA_START66 - [3:0] */ -#define WM8995_WSEQ_DATA_START66_SHIFT 0 /* WSEQ_DATA_START66 - [3:0] */ -#define WM8995_WSEQ_DATA_START66_WIDTH 4 /* WSEQ_DATA_START66 - [3:0] */ - -/* - * R12555 (0x310B) - Write Sequencer 267 - */ -#define WM8995_WSEQ_EOS66 0x0100 /* WSEQ_EOS66 */ -#define WM8995_WSEQ_EOS66_MASK 0x0100 /* WSEQ_EOS66 */ -#define WM8995_WSEQ_EOS66_SHIFT 8 /* WSEQ_EOS66 */ -#define WM8995_WSEQ_EOS66_WIDTH 1 /* WSEQ_EOS66 */ -#define WM8995_WSEQ_DELAY66_MASK 0x000F /* WSEQ_DELAY66 - [3:0] */ -#define WM8995_WSEQ_DELAY66_SHIFT 0 /* WSEQ_DELAY66 - [3:0] */ -#define WM8995_WSEQ_DELAY66_WIDTH 4 /* WSEQ_DELAY66 - [3:0] */ - -/* - * R12556 (0x310C) - Write Sequencer 268 - */ -#define WM8995_WSEQ_ADDR67_MASK 0x3FFF /* WSEQ_ADDR67 - [13:0] */ -#define WM8995_WSEQ_ADDR67_SHIFT 0 /* WSEQ_ADDR67 - [13:0] */ -#define WM8995_WSEQ_ADDR67_WIDTH 14 /* WSEQ_ADDR67 - [13:0] */ - -/* - * R12557 (0x310D) - Write Sequencer 269 - */ -#define WM8995_WSEQ_DATA67_MASK 0x00FF /* WSEQ_DATA67 - [7:0] */ -#define WM8995_WSEQ_DATA67_SHIFT 0 /* WSEQ_DATA67 - [7:0] */ -#define WM8995_WSEQ_DATA67_WIDTH 8 /* WSEQ_DATA67 - [7:0] */ - -/* - * R12558 (0x310E) - Write Sequencer 270 - */ -#define WM8995_WSEQ_DATA_WIDTH67_MASK 0x0700 /* WSEQ_DATA_WIDTH67 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH67_SHIFT 8 /* WSEQ_DATA_WIDTH67 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH67_WIDTH 3 /* WSEQ_DATA_WIDTH67 - [10:8] */ -#define WM8995_WSEQ_DATA_START67_MASK 0x000F /* WSEQ_DATA_START67 - [3:0] */ -#define WM8995_WSEQ_DATA_START67_SHIFT 0 /* WSEQ_DATA_START67 - [3:0] */ -#define WM8995_WSEQ_DATA_START67_WIDTH 4 /* WSEQ_DATA_START67 - [3:0] */ - -/* - * R12559 (0x310F) - Write Sequencer 271 - */ -#define WM8995_WSEQ_EOS67 0x0100 /* WSEQ_EOS67 */ -#define WM8995_WSEQ_EOS67_MASK 0x0100 /* WSEQ_EOS67 */ -#define WM8995_WSEQ_EOS67_SHIFT 8 /* WSEQ_EOS67 */ -#define WM8995_WSEQ_EOS67_WIDTH 1 /* WSEQ_EOS67 */ -#define WM8995_WSEQ_DELAY67_MASK 0x000F /* WSEQ_DELAY67 - [3:0] */ -#define WM8995_WSEQ_DELAY67_SHIFT 0 /* WSEQ_DELAY67 - [3:0] */ -#define WM8995_WSEQ_DELAY67_WIDTH 4 /* WSEQ_DELAY67 - [3:0] */ - -/* - * R12560 (0x3110) - Write Sequencer 272 - */ -#define WM8995_WSEQ_ADDR68_MASK 0x3FFF /* WSEQ_ADDR68 - [13:0] */ -#define WM8995_WSEQ_ADDR68_SHIFT 0 /* WSEQ_ADDR68 - [13:0] */ -#define WM8995_WSEQ_ADDR68_WIDTH 14 /* WSEQ_ADDR68 - [13:0] */ - -/* - * R12561 (0x3111) - Write Sequencer 273 - */ -#define WM8995_WSEQ_DATA68_MASK 0x00FF /* WSEQ_DATA68 - [7:0] */ -#define WM8995_WSEQ_DATA68_SHIFT 0 /* WSEQ_DATA68 - [7:0] */ -#define WM8995_WSEQ_DATA68_WIDTH 8 /* WSEQ_DATA68 - [7:0] */ - -/* - * R12562 (0x3112) - Write Sequencer 274 - */ -#define WM8995_WSEQ_DATA_WIDTH68_MASK 0x0700 /* WSEQ_DATA_WIDTH68 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH68_SHIFT 8 /* WSEQ_DATA_WIDTH68 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH68_WIDTH 3 /* WSEQ_DATA_WIDTH68 - [10:8] */ -#define WM8995_WSEQ_DATA_START68_MASK 0x000F /* WSEQ_DATA_START68 - [3:0] */ -#define WM8995_WSEQ_DATA_START68_SHIFT 0 /* WSEQ_DATA_START68 - [3:0] */ -#define WM8995_WSEQ_DATA_START68_WIDTH 4 /* WSEQ_DATA_START68 - [3:0] */ - -/* - * R12563 (0x3113) - Write Sequencer 275 - */ -#define WM8995_WSEQ_EOS68 0x0100 /* WSEQ_EOS68 */ -#define WM8995_WSEQ_EOS68_MASK 0x0100 /* WSEQ_EOS68 */ -#define WM8995_WSEQ_EOS68_SHIFT 8 /* WSEQ_EOS68 */ -#define WM8995_WSEQ_EOS68_WIDTH 1 /* WSEQ_EOS68 */ -#define WM8995_WSEQ_DELAY68_MASK 0x000F /* WSEQ_DELAY68 - [3:0] */ -#define WM8995_WSEQ_DELAY68_SHIFT 0 /* WSEQ_DELAY68 - [3:0] */ -#define WM8995_WSEQ_DELAY68_WIDTH 4 /* WSEQ_DELAY68 - [3:0] */ - -/* - * R12564 (0x3114) - Write Sequencer 276 - */ -#define WM8995_WSEQ_ADDR69_MASK 0x3FFF /* WSEQ_ADDR69 - [13:0] */ -#define WM8995_WSEQ_ADDR69_SHIFT 0 /* WSEQ_ADDR69 - [13:0] */ -#define WM8995_WSEQ_ADDR69_WIDTH 14 /* WSEQ_ADDR69 - [13:0] */ - -/* - * R12565 (0x3115) - Write Sequencer 277 - */ -#define WM8995_WSEQ_DATA69_MASK 0x00FF /* WSEQ_DATA69 - [7:0] */ -#define WM8995_WSEQ_DATA69_SHIFT 0 /* WSEQ_DATA69 - [7:0] */ -#define WM8995_WSEQ_DATA69_WIDTH 8 /* WSEQ_DATA69 - [7:0] */ - -/* - * R12566 (0x3116) - Write Sequencer 278 - */ -#define WM8995_WSEQ_DATA_WIDTH69_MASK 0x0700 /* WSEQ_DATA_WIDTH69 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH69_SHIFT 8 /* WSEQ_DATA_WIDTH69 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH69_WIDTH 3 /* WSEQ_DATA_WIDTH69 - [10:8] */ -#define WM8995_WSEQ_DATA_START69_MASK 0x000F /* WSEQ_DATA_START69 - [3:0] */ -#define WM8995_WSEQ_DATA_START69_SHIFT 0 /* WSEQ_DATA_START69 - [3:0] */ -#define WM8995_WSEQ_DATA_START69_WIDTH 4 /* WSEQ_DATA_START69 - [3:0] */ - -/* - * R12567 (0x3117) - Write Sequencer 279 - */ -#define WM8995_WSEQ_EOS69 0x0100 /* WSEQ_EOS69 */ -#define WM8995_WSEQ_EOS69_MASK 0x0100 /* WSEQ_EOS69 */ -#define WM8995_WSEQ_EOS69_SHIFT 8 /* WSEQ_EOS69 */ -#define WM8995_WSEQ_EOS69_WIDTH 1 /* WSEQ_EOS69 */ -#define WM8995_WSEQ_DELAY69_MASK 0x000F /* WSEQ_DELAY69 - [3:0] */ -#define WM8995_WSEQ_DELAY69_SHIFT 0 /* WSEQ_DELAY69 - [3:0] */ -#define WM8995_WSEQ_DELAY69_WIDTH 4 /* WSEQ_DELAY69 - [3:0] */ - -/* - * R12568 (0x3118) - Write Sequencer 280 - */ -#define WM8995_WSEQ_ADDR70_MASK 0x3FFF /* WSEQ_ADDR70 - [13:0] */ -#define WM8995_WSEQ_ADDR70_SHIFT 0 /* WSEQ_ADDR70 - [13:0] */ -#define WM8995_WSEQ_ADDR70_WIDTH 14 /* WSEQ_ADDR70 - [13:0] */ - -/* - * R12569 (0x3119) - Write Sequencer 281 - */ -#define WM8995_WSEQ_DATA70_MASK 0x00FF /* WSEQ_DATA70 - [7:0] */ -#define WM8995_WSEQ_DATA70_SHIFT 0 /* WSEQ_DATA70 - [7:0] */ -#define WM8995_WSEQ_DATA70_WIDTH 8 /* WSEQ_DATA70 - [7:0] */ - -/* - * R12570 (0x311A) - Write Sequencer 282 - */ -#define WM8995_WSEQ_DATA_WIDTH70_MASK 0x0700 /* WSEQ_DATA_WIDTH70 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH70_SHIFT 8 /* WSEQ_DATA_WIDTH70 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH70_WIDTH 3 /* WSEQ_DATA_WIDTH70 - [10:8] */ -#define WM8995_WSEQ_DATA_START70_MASK 0x000F /* WSEQ_DATA_START70 - [3:0] */ -#define WM8995_WSEQ_DATA_START70_SHIFT 0 /* WSEQ_DATA_START70 - [3:0] */ -#define WM8995_WSEQ_DATA_START70_WIDTH 4 /* WSEQ_DATA_START70 - [3:0] */ - -/* - * R12571 (0x311B) - Write Sequencer 283 - */ -#define WM8995_WSEQ_EOS70 0x0100 /* WSEQ_EOS70 */ -#define WM8995_WSEQ_EOS70_MASK 0x0100 /* WSEQ_EOS70 */ -#define WM8995_WSEQ_EOS70_SHIFT 8 /* WSEQ_EOS70 */ -#define WM8995_WSEQ_EOS70_WIDTH 1 /* WSEQ_EOS70 */ -#define WM8995_WSEQ_DELAY70_MASK 0x000F /* WSEQ_DELAY70 - [3:0] */ -#define WM8995_WSEQ_DELAY70_SHIFT 0 /* WSEQ_DELAY70 - [3:0] */ -#define WM8995_WSEQ_DELAY70_WIDTH 4 /* WSEQ_DELAY70 - [3:0] */ - -/* - * R12572 (0x311C) - Write Sequencer 284 - */ -#define WM8995_WSEQ_ADDR71_MASK 0x3FFF /* WSEQ_ADDR71 - [13:0] */ -#define WM8995_WSEQ_ADDR71_SHIFT 0 /* WSEQ_ADDR71 - [13:0] */ -#define WM8995_WSEQ_ADDR71_WIDTH 14 /* WSEQ_ADDR71 - [13:0] */ - -/* - * R12573 (0x311D) - Write Sequencer 285 - */ -#define WM8995_WSEQ_DATA71_MASK 0x00FF /* WSEQ_DATA71 - [7:0] */ -#define WM8995_WSEQ_DATA71_SHIFT 0 /* WSEQ_DATA71 - [7:0] */ -#define WM8995_WSEQ_DATA71_WIDTH 8 /* WSEQ_DATA71 - [7:0] */ - -/* - * R12574 (0x311E) - Write Sequencer 286 - */ -#define WM8995_WSEQ_DATA_WIDTH71_MASK 0x0700 /* WSEQ_DATA_WIDTH71 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH71_SHIFT 8 /* WSEQ_DATA_WIDTH71 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH71_WIDTH 3 /* WSEQ_DATA_WIDTH71 - [10:8] */ -#define WM8995_WSEQ_DATA_START71_MASK 0x000F /* WSEQ_DATA_START71 - [3:0] */ -#define WM8995_WSEQ_DATA_START71_SHIFT 0 /* WSEQ_DATA_START71 - [3:0] */ -#define WM8995_WSEQ_DATA_START71_WIDTH 4 /* WSEQ_DATA_START71 - [3:0] */ - -/* - * R12575 (0x311F) - Write Sequencer 287 - */ -#define WM8995_WSEQ_EOS71 0x0100 /* WSEQ_EOS71 */ -#define WM8995_WSEQ_EOS71_MASK 0x0100 /* WSEQ_EOS71 */ -#define WM8995_WSEQ_EOS71_SHIFT 8 /* WSEQ_EOS71 */ -#define WM8995_WSEQ_EOS71_WIDTH 1 /* WSEQ_EOS71 */ -#define WM8995_WSEQ_DELAY71_MASK 0x000F /* WSEQ_DELAY71 - [3:0] */ -#define WM8995_WSEQ_DELAY71_SHIFT 0 /* WSEQ_DELAY71 - [3:0] */ -#define WM8995_WSEQ_DELAY71_WIDTH 4 /* WSEQ_DELAY71 - [3:0] */ - -/* - * R12576 (0x3120) - Write Sequencer 288 - */ -#define WM8995_WSEQ_ADDR72_MASK 0x3FFF /* WSEQ_ADDR72 - [13:0] */ -#define WM8995_WSEQ_ADDR72_SHIFT 0 /* WSEQ_ADDR72 - [13:0] */ -#define WM8995_WSEQ_ADDR72_WIDTH 14 /* WSEQ_ADDR72 - [13:0] */ - -/* - * R12577 (0x3121) - Write Sequencer 289 - */ -#define WM8995_WSEQ_DATA72_MASK 0x00FF /* WSEQ_DATA72 - [7:0] */ -#define WM8995_WSEQ_DATA72_SHIFT 0 /* WSEQ_DATA72 - [7:0] */ -#define WM8995_WSEQ_DATA72_WIDTH 8 /* WSEQ_DATA72 - [7:0] */ - -/* - * R12578 (0x3122) - Write Sequencer 290 - */ -#define WM8995_WSEQ_DATA_WIDTH72_MASK 0x0700 /* WSEQ_DATA_WIDTH72 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH72_SHIFT 8 /* WSEQ_DATA_WIDTH72 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH72_WIDTH 3 /* WSEQ_DATA_WIDTH72 - [10:8] */ -#define WM8995_WSEQ_DATA_START72_MASK 0x000F /* WSEQ_DATA_START72 - [3:0] */ -#define WM8995_WSEQ_DATA_START72_SHIFT 0 /* WSEQ_DATA_START72 - [3:0] */ -#define WM8995_WSEQ_DATA_START72_WIDTH 4 /* WSEQ_DATA_START72 - [3:0] */ - -/* - * R12579 (0x3123) - Write Sequencer 291 - */ -#define WM8995_WSEQ_EOS72 0x0100 /* WSEQ_EOS72 */ -#define WM8995_WSEQ_EOS72_MASK 0x0100 /* WSEQ_EOS72 */ -#define WM8995_WSEQ_EOS72_SHIFT 8 /* WSEQ_EOS72 */ -#define WM8995_WSEQ_EOS72_WIDTH 1 /* WSEQ_EOS72 */ -#define WM8995_WSEQ_DELAY72_MASK 0x000F /* WSEQ_DELAY72 - [3:0] */ -#define WM8995_WSEQ_DELAY72_SHIFT 0 /* WSEQ_DELAY72 - [3:0] */ -#define WM8995_WSEQ_DELAY72_WIDTH 4 /* WSEQ_DELAY72 - [3:0] */ - -/* - * R12580 (0x3124) - Write Sequencer 292 - */ -#define WM8995_WSEQ_ADDR73_MASK 0x3FFF /* WSEQ_ADDR73 - [13:0] */ -#define WM8995_WSEQ_ADDR73_SHIFT 0 /* WSEQ_ADDR73 - [13:0] */ -#define WM8995_WSEQ_ADDR73_WIDTH 14 /* WSEQ_ADDR73 - [13:0] */ - -/* - * R12581 (0x3125) - Write Sequencer 293 - */ -#define WM8995_WSEQ_DATA73_MASK 0x00FF /* WSEQ_DATA73 - [7:0] */ -#define WM8995_WSEQ_DATA73_SHIFT 0 /* WSEQ_DATA73 - [7:0] */ -#define WM8995_WSEQ_DATA73_WIDTH 8 /* WSEQ_DATA73 - [7:0] */ - -/* - * R12582 (0x3126) - Write Sequencer 294 - */ -#define WM8995_WSEQ_DATA_WIDTH73_MASK 0x0700 /* WSEQ_DATA_WIDTH73 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH73_SHIFT 8 /* WSEQ_DATA_WIDTH73 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH73_WIDTH 3 /* WSEQ_DATA_WIDTH73 - [10:8] */ -#define WM8995_WSEQ_DATA_START73_MASK 0x000F /* WSEQ_DATA_START73 - [3:0] */ -#define WM8995_WSEQ_DATA_START73_SHIFT 0 /* WSEQ_DATA_START73 - [3:0] */ -#define WM8995_WSEQ_DATA_START73_WIDTH 4 /* WSEQ_DATA_START73 - [3:0] */ - -/* - * R12583 (0x3127) - Write Sequencer 295 - */ -#define WM8995_WSEQ_EOS73 0x0100 /* WSEQ_EOS73 */ -#define WM8995_WSEQ_EOS73_MASK 0x0100 /* WSEQ_EOS73 */ -#define WM8995_WSEQ_EOS73_SHIFT 8 /* WSEQ_EOS73 */ -#define WM8995_WSEQ_EOS73_WIDTH 1 /* WSEQ_EOS73 */ -#define WM8995_WSEQ_DELAY73_MASK 0x000F /* WSEQ_DELAY73 - [3:0] */ -#define WM8995_WSEQ_DELAY73_SHIFT 0 /* WSEQ_DELAY73 - [3:0] */ -#define WM8995_WSEQ_DELAY73_WIDTH 4 /* WSEQ_DELAY73 - [3:0] */ - -/* - * R12584 (0x3128) - Write Sequencer 296 - */ -#define WM8995_WSEQ_ADDR74_MASK 0x3FFF /* WSEQ_ADDR74 - [13:0] */ -#define WM8995_WSEQ_ADDR74_SHIFT 0 /* WSEQ_ADDR74 - [13:0] */ -#define WM8995_WSEQ_ADDR74_WIDTH 14 /* WSEQ_ADDR74 - [13:0] */ - -/* - * R12585 (0x3129) - Write Sequencer 297 - */ -#define WM8995_WSEQ_DATA74_MASK 0x00FF /* WSEQ_DATA74 - [7:0] */ -#define WM8995_WSEQ_DATA74_SHIFT 0 /* WSEQ_DATA74 - [7:0] */ -#define WM8995_WSEQ_DATA74_WIDTH 8 /* WSEQ_DATA74 - [7:0] */ - -/* - * R12586 (0x312A) - Write Sequencer 298 - */ -#define WM8995_WSEQ_DATA_WIDTH74_MASK 0x0700 /* WSEQ_DATA_WIDTH74 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH74_SHIFT 8 /* WSEQ_DATA_WIDTH74 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH74_WIDTH 3 /* WSEQ_DATA_WIDTH74 - [10:8] */ -#define WM8995_WSEQ_DATA_START74_MASK 0x000F /* WSEQ_DATA_START74 - [3:0] */ -#define WM8995_WSEQ_DATA_START74_SHIFT 0 /* WSEQ_DATA_START74 - [3:0] */ -#define WM8995_WSEQ_DATA_START74_WIDTH 4 /* WSEQ_DATA_START74 - [3:0] */ - -/* - * R12587 (0x312B) - Write Sequencer 299 - */ -#define WM8995_WSEQ_EOS74 0x0100 /* WSEQ_EOS74 */ -#define WM8995_WSEQ_EOS74_MASK 0x0100 /* WSEQ_EOS74 */ -#define WM8995_WSEQ_EOS74_SHIFT 8 /* WSEQ_EOS74 */ -#define WM8995_WSEQ_EOS74_WIDTH 1 /* WSEQ_EOS74 */ -#define WM8995_WSEQ_DELAY74_MASK 0x000F /* WSEQ_DELAY74 - [3:0] */ -#define WM8995_WSEQ_DELAY74_SHIFT 0 /* WSEQ_DELAY74 - [3:0] */ -#define WM8995_WSEQ_DELAY74_WIDTH 4 /* WSEQ_DELAY74 - [3:0] */ - -/* - * R12588 (0x312C) - Write Sequencer 300 - */ -#define WM8995_WSEQ_ADDR75_MASK 0x3FFF /* WSEQ_ADDR75 - [13:0] */ -#define WM8995_WSEQ_ADDR75_SHIFT 0 /* WSEQ_ADDR75 - [13:0] */ -#define WM8995_WSEQ_ADDR75_WIDTH 14 /* WSEQ_ADDR75 - [13:0] */ - -/* - * R12589 (0x312D) - Write Sequencer 301 - */ -#define WM8995_WSEQ_DATA75_MASK 0x00FF /* WSEQ_DATA75 - [7:0] */ -#define WM8995_WSEQ_DATA75_SHIFT 0 /* WSEQ_DATA75 - [7:0] */ -#define WM8995_WSEQ_DATA75_WIDTH 8 /* WSEQ_DATA75 - [7:0] */ - -/* - * R12590 (0x312E) - Write Sequencer 302 - */ -#define WM8995_WSEQ_DATA_WIDTH75_MASK 0x0700 /* WSEQ_DATA_WIDTH75 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH75_SHIFT 8 /* WSEQ_DATA_WIDTH75 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH75_WIDTH 3 /* WSEQ_DATA_WIDTH75 - [10:8] */ -#define WM8995_WSEQ_DATA_START75_MASK 0x000F /* WSEQ_DATA_START75 - [3:0] */ -#define WM8995_WSEQ_DATA_START75_SHIFT 0 /* WSEQ_DATA_START75 - [3:0] */ -#define WM8995_WSEQ_DATA_START75_WIDTH 4 /* WSEQ_DATA_START75 - [3:0] */ - -/* - * R12591 (0x312F) - Write Sequencer 303 - */ -#define WM8995_WSEQ_EOS75 0x0100 /* WSEQ_EOS75 */ -#define WM8995_WSEQ_EOS75_MASK 0x0100 /* WSEQ_EOS75 */ -#define WM8995_WSEQ_EOS75_SHIFT 8 /* WSEQ_EOS75 */ -#define WM8995_WSEQ_EOS75_WIDTH 1 /* WSEQ_EOS75 */ -#define WM8995_WSEQ_DELAY75_MASK 0x000F /* WSEQ_DELAY75 - [3:0] */ -#define WM8995_WSEQ_DELAY75_SHIFT 0 /* WSEQ_DELAY75 - [3:0] */ -#define WM8995_WSEQ_DELAY75_WIDTH 4 /* WSEQ_DELAY75 - [3:0] */ - -/* - * R12592 (0x3130) - Write Sequencer 304 - */ -#define WM8995_WSEQ_ADDR76_MASK 0x3FFF /* WSEQ_ADDR76 - [13:0] */ -#define WM8995_WSEQ_ADDR76_SHIFT 0 /* WSEQ_ADDR76 - [13:0] */ -#define WM8995_WSEQ_ADDR76_WIDTH 14 /* WSEQ_ADDR76 - [13:0] */ - -/* - * R12593 (0x3131) - Write Sequencer 305 - */ -#define WM8995_WSEQ_DATA76_MASK 0x00FF /* WSEQ_DATA76 - [7:0] */ -#define WM8995_WSEQ_DATA76_SHIFT 0 /* WSEQ_DATA76 - [7:0] */ -#define WM8995_WSEQ_DATA76_WIDTH 8 /* WSEQ_DATA76 - [7:0] */ - -/* - * R12594 (0x3132) - Write Sequencer 306 - */ -#define WM8995_WSEQ_DATA_WIDTH76_MASK 0x0700 /* WSEQ_DATA_WIDTH76 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH76_SHIFT 8 /* WSEQ_DATA_WIDTH76 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH76_WIDTH 3 /* WSEQ_DATA_WIDTH76 - [10:8] */ -#define WM8995_WSEQ_DATA_START76_MASK 0x000F /* WSEQ_DATA_START76 - [3:0] */ -#define WM8995_WSEQ_DATA_START76_SHIFT 0 /* WSEQ_DATA_START76 - [3:0] */ -#define WM8995_WSEQ_DATA_START76_WIDTH 4 /* WSEQ_DATA_START76 - [3:0] */ - -/* - * R12595 (0x3133) - Write Sequencer 307 - */ -#define WM8995_WSEQ_EOS76 0x0100 /* WSEQ_EOS76 */ -#define WM8995_WSEQ_EOS76_MASK 0x0100 /* WSEQ_EOS76 */ -#define WM8995_WSEQ_EOS76_SHIFT 8 /* WSEQ_EOS76 */ -#define WM8995_WSEQ_EOS76_WIDTH 1 /* WSEQ_EOS76 */ -#define WM8995_WSEQ_DELAY76_MASK 0x000F /* WSEQ_DELAY76 - [3:0] */ -#define WM8995_WSEQ_DELAY76_SHIFT 0 /* WSEQ_DELAY76 - [3:0] */ -#define WM8995_WSEQ_DELAY76_WIDTH 4 /* WSEQ_DELAY76 - [3:0] */ - -/* - * R12596 (0x3134) - Write Sequencer 308 - */ -#define WM8995_WSEQ_ADDR77_MASK 0x3FFF /* WSEQ_ADDR77 - [13:0] */ -#define WM8995_WSEQ_ADDR77_SHIFT 0 /* WSEQ_ADDR77 - [13:0] */ -#define WM8995_WSEQ_ADDR77_WIDTH 14 /* WSEQ_ADDR77 - [13:0] */ - -/* - * R12597 (0x3135) - Write Sequencer 309 - */ -#define WM8995_WSEQ_DATA77_MASK 0x00FF /* WSEQ_DATA77 - [7:0] */ -#define WM8995_WSEQ_DATA77_SHIFT 0 /* WSEQ_DATA77 - [7:0] */ -#define WM8995_WSEQ_DATA77_WIDTH 8 /* WSEQ_DATA77 - [7:0] */ - -/* - * R12598 (0x3136) - Write Sequencer 310 - */ -#define WM8995_WSEQ_DATA_WIDTH77_MASK 0x0700 /* WSEQ_DATA_WIDTH77 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH77_SHIFT 8 /* WSEQ_DATA_WIDTH77 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH77_WIDTH 3 /* WSEQ_DATA_WIDTH77 - [10:8] */ -#define WM8995_WSEQ_DATA_START77_MASK 0x000F /* WSEQ_DATA_START77 - [3:0] */ -#define WM8995_WSEQ_DATA_START77_SHIFT 0 /* WSEQ_DATA_START77 - [3:0] */ -#define WM8995_WSEQ_DATA_START77_WIDTH 4 /* WSEQ_DATA_START77 - [3:0] */ - -/* - * R12599 (0x3137) - Write Sequencer 311 - */ -#define WM8995_WSEQ_EOS77 0x0100 /* WSEQ_EOS77 */ -#define WM8995_WSEQ_EOS77_MASK 0x0100 /* WSEQ_EOS77 */ -#define WM8995_WSEQ_EOS77_SHIFT 8 /* WSEQ_EOS77 */ -#define WM8995_WSEQ_EOS77_WIDTH 1 /* WSEQ_EOS77 */ -#define WM8995_WSEQ_DELAY77_MASK 0x000F /* WSEQ_DELAY77 - [3:0] */ -#define WM8995_WSEQ_DELAY77_SHIFT 0 /* WSEQ_DELAY77 - [3:0] */ -#define WM8995_WSEQ_DELAY77_WIDTH 4 /* WSEQ_DELAY77 - [3:0] */ - -/* - * R12600 (0x3138) - Write Sequencer 312 - */ -#define WM8995_WSEQ_ADDR78_MASK 0x3FFF /* WSEQ_ADDR78 - [13:0] */ -#define WM8995_WSEQ_ADDR78_SHIFT 0 /* WSEQ_ADDR78 - [13:0] */ -#define WM8995_WSEQ_ADDR78_WIDTH 14 /* WSEQ_ADDR78 - [13:0] */ - -/* - * R12601 (0x3139) - Write Sequencer 313 - */ -#define WM8995_WSEQ_DATA78_MASK 0x00FF /* WSEQ_DATA78 - [7:0] */ -#define WM8995_WSEQ_DATA78_SHIFT 0 /* WSEQ_DATA78 - [7:0] */ -#define WM8995_WSEQ_DATA78_WIDTH 8 /* WSEQ_DATA78 - [7:0] */ - -/* - * R12602 (0x313A) - Write Sequencer 314 - */ -#define WM8995_WSEQ_DATA_WIDTH78_MASK 0x0700 /* WSEQ_DATA_WIDTH78 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH78_SHIFT 8 /* WSEQ_DATA_WIDTH78 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH78_WIDTH 3 /* WSEQ_DATA_WIDTH78 - [10:8] */ -#define WM8995_WSEQ_DATA_START78_MASK 0x000F /* WSEQ_DATA_START78 - [3:0] */ -#define WM8995_WSEQ_DATA_START78_SHIFT 0 /* WSEQ_DATA_START78 - [3:0] */ -#define WM8995_WSEQ_DATA_START78_WIDTH 4 /* WSEQ_DATA_START78 - [3:0] */ - -/* - * R12603 (0x313B) - Write Sequencer 315 - */ -#define WM8995_WSEQ_EOS78 0x0100 /* WSEQ_EOS78 */ -#define WM8995_WSEQ_EOS78_MASK 0x0100 /* WSEQ_EOS78 */ -#define WM8995_WSEQ_EOS78_SHIFT 8 /* WSEQ_EOS78 */ -#define WM8995_WSEQ_EOS78_WIDTH 1 /* WSEQ_EOS78 */ -#define WM8995_WSEQ_DELAY78_MASK 0x000F /* WSEQ_DELAY78 - [3:0] */ -#define WM8995_WSEQ_DELAY78_SHIFT 0 /* WSEQ_DELAY78 - [3:0] */ -#define WM8995_WSEQ_DELAY78_WIDTH 4 /* WSEQ_DELAY78 - [3:0] */ - -/* - * R12604 (0x313C) - Write Sequencer 316 - */ -#define WM8995_WSEQ_ADDR79_MASK 0x3FFF /* WSEQ_ADDR79 - [13:0] */ -#define WM8995_WSEQ_ADDR79_SHIFT 0 /* WSEQ_ADDR79 - [13:0] */ -#define WM8995_WSEQ_ADDR79_WIDTH 14 /* WSEQ_ADDR79 - [13:0] */ - -/* - * R12605 (0x313D) - Write Sequencer 317 - */ -#define WM8995_WSEQ_DATA79_MASK 0x00FF /* WSEQ_DATA79 - [7:0] */ -#define WM8995_WSEQ_DATA79_SHIFT 0 /* WSEQ_DATA79 - [7:0] */ -#define WM8995_WSEQ_DATA79_WIDTH 8 /* WSEQ_DATA79 - [7:0] */ - -/* - * R12606 (0x313E) - Write Sequencer 318 - */ -#define WM8995_WSEQ_DATA_WIDTH79_MASK 0x0700 /* WSEQ_DATA_WIDTH79 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH79_SHIFT 8 /* WSEQ_DATA_WIDTH79 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH79_WIDTH 3 /* WSEQ_DATA_WIDTH79 - [10:8] */ -#define WM8995_WSEQ_DATA_START79_MASK 0x000F /* WSEQ_DATA_START79 - [3:0] */ -#define WM8995_WSEQ_DATA_START79_SHIFT 0 /* WSEQ_DATA_START79 - [3:0] */ -#define WM8995_WSEQ_DATA_START79_WIDTH 4 /* WSEQ_DATA_START79 - [3:0] */ - -/* - * R12607 (0x313F) - Write Sequencer 319 - */ -#define WM8995_WSEQ_EOS79 0x0100 /* WSEQ_EOS79 */ -#define WM8995_WSEQ_EOS79_MASK 0x0100 /* WSEQ_EOS79 */ -#define WM8995_WSEQ_EOS79_SHIFT 8 /* WSEQ_EOS79 */ -#define WM8995_WSEQ_EOS79_WIDTH 1 /* WSEQ_EOS79 */ -#define WM8995_WSEQ_DELAY79_MASK 0x000F /* WSEQ_DELAY79 - [3:0] */ -#define WM8995_WSEQ_DELAY79_SHIFT 0 /* WSEQ_DELAY79 - [3:0] */ -#define WM8995_WSEQ_DELAY79_WIDTH 4 /* WSEQ_DELAY79 - [3:0] */ - -/* - * R12608 (0x3140) - Write Sequencer 320 - */ -#define WM8995_WSEQ_ADDR80_MASK 0x3FFF /* WSEQ_ADDR80 - [13:0] */ -#define WM8995_WSEQ_ADDR80_SHIFT 0 /* WSEQ_ADDR80 - [13:0] */ -#define WM8995_WSEQ_ADDR80_WIDTH 14 /* WSEQ_ADDR80 - [13:0] */ - -/* - * R12609 (0x3141) - Write Sequencer 321 - */ -#define WM8995_WSEQ_DATA80_MASK 0x00FF /* WSEQ_DATA80 - [7:0] */ -#define WM8995_WSEQ_DATA80_SHIFT 0 /* WSEQ_DATA80 - [7:0] */ -#define WM8995_WSEQ_DATA80_WIDTH 8 /* WSEQ_DATA80 - [7:0] */ - -/* - * R12610 (0x3142) - Write Sequencer 322 - */ -#define WM8995_WSEQ_DATA_WIDTH80_MASK 0x0700 /* WSEQ_DATA_WIDTH80 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH80_SHIFT 8 /* WSEQ_DATA_WIDTH80 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH80_WIDTH 3 /* WSEQ_DATA_WIDTH80 - [10:8] */ -#define WM8995_WSEQ_DATA_START80_MASK 0x000F /* WSEQ_DATA_START80 - [3:0] */ -#define WM8995_WSEQ_DATA_START80_SHIFT 0 /* WSEQ_DATA_START80 - [3:0] */ -#define WM8995_WSEQ_DATA_START80_WIDTH 4 /* WSEQ_DATA_START80 - [3:0] */ - -/* - * R12611 (0x3143) - Write Sequencer 323 - */ -#define WM8995_WSEQ_EOS80 0x0100 /* WSEQ_EOS80 */ -#define WM8995_WSEQ_EOS80_MASK 0x0100 /* WSEQ_EOS80 */ -#define WM8995_WSEQ_EOS80_SHIFT 8 /* WSEQ_EOS80 */ -#define WM8995_WSEQ_EOS80_WIDTH 1 /* WSEQ_EOS80 */ -#define WM8995_WSEQ_DELAY80_MASK 0x000F /* WSEQ_DELAY80 - [3:0] */ -#define WM8995_WSEQ_DELAY80_SHIFT 0 /* WSEQ_DELAY80 - [3:0] */ -#define WM8995_WSEQ_DELAY80_WIDTH 4 /* WSEQ_DELAY80 - [3:0] */ - -/* - * R12612 (0x3144) - Write Sequencer 324 - */ -#define WM8995_WSEQ_ADDR81_MASK 0x3FFF /* WSEQ_ADDR81 - [13:0] */ -#define WM8995_WSEQ_ADDR81_SHIFT 0 /* WSEQ_ADDR81 - [13:0] */ -#define WM8995_WSEQ_ADDR81_WIDTH 14 /* WSEQ_ADDR81 - [13:0] */ - -/* - * R12613 (0x3145) - Write Sequencer 325 - */ -#define WM8995_WSEQ_DATA81_MASK 0x00FF /* WSEQ_DATA81 - [7:0] */ -#define WM8995_WSEQ_DATA81_SHIFT 0 /* WSEQ_DATA81 - [7:0] */ -#define WM8995_WSEQ_DATA81_WIDTH 8 /* WSEQ_DATA81 - [7:0] */ - -/* - * R12614 (0x3146) - Write Sequencer 326 - */ -#define WM8995_WSEQ_DATA_WIDTH81_MASK 0x0700 /* WSEQ_DATA_WIDTH81 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH81_SHIFT 8 /* WSEQ_DATA_WIDTH81 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH81_WIDTH 3 /* WSEQ_DATA_WIDTH81 - [10:8] */ -#define WM8995_WSEQ_DATA_START81_MASK 0x000F /* WSEQ_DATA_START81 - [3:0] */ -#define WM8995_WSEQ_DATA_START81_SHIFT 0 /* WSEQ_DATA_START81 - [3:0] */ -#define WM8995_WSEQ_DATA_START81_WIDTH 4 /* WSEQ_DATA_START81 - [3:0] */ - -/* - * R12615 (0x3147) - Write Sequencer 327 - */ -#define WM8995_WSEQ_EOS81 0x0100 /* WSEQ_EOS81 */ -#define WM8995_WSEQ_EOS81_MASK 0x0100 /* WSEQ_EOS81 */ -#define WM8995_WSEQ_EOS81_SHIFT 8 /* WSEQ_EOS81 */ -#define WM8995_WSEQ_EOS81_WIDTH 1 /* WSEQ_EOS81 */ -#define WM8995_WSEQ_DELAY81_MASK 0x000F /* WSEQ_DELAY81 - [3:0] */ -#define WM8995_WSEQ_DELAY81_SHIFT 0 /* WSEQ_DELAY81 - [3:0] */ -#define WM8995_WSEQ_DELAY81_WIDTH 4 /* WSEQ_DELAY81 - [3:0] */ - -/* - * R12616 (0x3148) - Write Sequencer 328 - */ -#define WM8995_WSEQ_ADDR82_MASK 0x3FFF /* WSEQ_ADDR82 - [13:0] */ -#define WM8995_WSEQ_ADDR82_SHIFT 0 /* WSEQ_ADDR82 - [13:0] */ -#define WM8995_WSEQ_ADDR82_WIDTH 14 /* WSEQ_ADDR82 - [13:0] */ - -/* - * R12617 (0x3149) - Write Sequencer 329 - */ -#define WM8995_WSEQ_DATA82_MASK 0x00FF /* WSEQ_DATA82 - [7:0] */ -#define WM8995_WSEQ_DATA82_SHIFT 0 /* WSEQ_DATA82 - [7:0] */ -#define WM8995_WSEQ_DATA82_WIDTH 8 /* WSEQ_DATA82 - [7:0] */ - -/* - * R12618 (0x314A) - Write Sequencer 330 - */ -#define WM8995_WSEQ_DATA_WIDTH82_MASK 0x0700 /* WSEQ_DATA_WIDTH82 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH82_SHIFT 8 /* WSEQ_DATA_WIDTH82 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH82_WIDTH 3 /* WSEQ_DATA_WIDTH82 - [10:8] */ -#define WM8995_WSEQ_DATA_START82_MASK 0x000F /* WSEQ_DATA_START82 - [3:0] */ -#define WM8995_WSEQ_DATA_START82_SHIFT 0 /* WSEQ_DATA_START82 - [3:0] */ -#define WM8995_WSEQ_DATA_START82_WIDTH 4 /* WSEQ_DATA_START82 - [3:0] */ - -/* - * R12619 (0x314B) - Write Sequencer 331 - */ -#define WM8995_WSEQ_EOS82 0x0100 /* WSEQ_EOS82 */ -#define WM8995_WSEQ_EOS82_MASK 0x0100 /* WSEQ_EOS82 */ -#define WM8995_WSEQ_EOS82_SHIFT 8 /* WSEQ_EOS82 */ -#define WM8995_WSEQ_EOS82_WIDTH 1 /* WSEQ_EOS82 */ -#define WM8995_WSEQ_DELAY82_MASK 0x000F /* WSEQ_DELAY82 - [3:0] */ -#define WM8995_WSEQ_DELAY82_SHIFT 0 /* WSEQ_DELAY82 - [3:0] */ -#define WM8995_WSEQ_DELAY82_WIDTH 4 /* WSEQ_DELAY82 - [3:0] */ - -/* - * R12620 (0x314C) - Write Sequencer 332 - */ -#define WM8995_WSEQ_ADDR83_MASK 0x3FFF /* WSEQ_ADDR83 - [13:0] */ -#define WM8995_WSEQ_ADDR83_SHIFT 0 /* WSEQ_ADDR83 - [13:0] */ -#define WM8995_WSEQ_ADDR83_WIDTH 14 /* WSEQ_ADDR83 - [13:0] */ - -/* - * R12621 (0x314D) - Write Sequencer 333 - */ -#define WM8995_WSEQ_DATA83_MASK 0x00FF /* WSEQ_DATA83 - [7:0] */ -#define WM8995_WSEQ_DATA83_SHIFT 0 /* WSEQ_DATA83 - [7:0] */ -#define WM8995_WSEQ_DATA83_WIDTH 8 /* WSEQ_DATA83 - [7:0] */ - -/* - * R12622 (0x314E) - Write Sequencer 334 - */ -#define WM8995_WSEQ_DATA_WIDTH83_MASK 0x0700 /* WSEQ_DATA_WIDTH83 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH83_SHIFT 8 /* WSEQ_DATA_WIDTH83 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH83_WIDTH 3 /* WSEQ_DATA_WIDTH83 - [10:8] */ -#define WM8995_WSEQ_DATA_START83_MASK 0x000F /* WSEQ_DATA_START83 - [3:0] */ -#define WM8995_WSEQ_DATA_START83_SHIFT 0 /* WSEQ_DATA_START83 - [3:0] */ -#define WM8995_WSEQ_DATA_START83_WIDTH 4 /* WSEQ_DATA_START83 - [3:0] */ - -/* - * R12623 (0x314F) - Write Sequencer 335 - */ -#define WM8995_WSEQ_EOS83 0x0100 /* WSEQ_EOS83 */ -#define WM8995_WSEQ_EOS83_MASK 0x0100 /* WSEQ_EOS83 */ -#define WM8995_WSEQ_EOS83_SHIFT 8 /* WSEQ_EOS83 */ -#define WM8995_WSEQ_EOS83_WIDTH 1 /* WSEQ_EOS83 */ -#define WM8995_WSEQ_DELAY83_MASK 0x000F /* WSEQ_DELAY83 - [3:0] */ -#define WM8995_WSEQ_DELAY83_SHIFT 0 /* WSEQ_DELAY83 - [3:0] */ -#define WM8995_WSEQ_DELAY83_WIDTH 4 /* WSEQ_DELAY83 - [3:0] */ - -/* - * R12624 (0x3150) - Write Sequencer 336 - */ -#define WM8995_WSEQ_ADDR84_MASK 0x3FFF /* WSEQ_ADDR84 - [13:0] */ -#define WM8995_WSEQ_ADDR84_SHIFT 0 /* WSEQ_ADDR84 - [13:0] */ -#define WM8995_WSEQ_ADDR84_WIDTH 14 /* WSEQ_ADDR84 - [13:0] */ - -/* - * R12625 (0x3151) - Write Sequencer 337 - */ -#define WM8995_WSEQ_DATA84_MASK 0x00FF /* WSEQ_DATA84 - [7:0] */ -#define WM8995_WSEQ_DATA84_SHIFT 0 /* WSEQ_DATA84 - [7:0] */ -#define WM8995_WSEQ_DATA84_WIDTH 8 /* WSEQ_DATA84 - [7:0] */ - -/* - * R12626 (0x3152) - Write Sequencer 338 - */ -#define WM8995_WSEQ_DATA_WIDTH84_MASK 0x0700 /* WSEQ_DATA_WIDTH84 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH84_SHIFT 8 /* WSEQ_DATA_WIDTH84 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH84_WIDTH 3 /* WSEQ_DATA_WIDTH84 - [10:8] */ -#define WM8995_WSEQ_DATA_START84_MASK 0x000F /* WSEQ_DATA_START84 - [3:0] */ -#define WM8995_WSEQ_DATA_START84_SHIFT 0 /* WSEQ_DATA_START84 - [3:0] */ -#define WM8995_WSEQ_DATA_START84_WIDTH 4 /* WSEQ_DATA_START84 - [3:0] */ - -/* - * R12627 (0x3153) - Write Sequencer 339 - */ -#define WM8995_WSEQ_EOS84 0x0100 /* WSEQ_EOS84 */ -#define WM8995_WSEQ_EOS84_MASK 0x0100 /* WSEQ_EOS84 */ -#define WM8995_WSEQ_EOS84_SHIFT 8 /* WSEQ_EOS84 */ -#define WM8995_WSEQ_EOS84_WIDTH 1 /* WSEQ_EOS84 */ -#define WM8995_WSEQ_DELAY84_MASK 0x000F /* WSEQ_DELAY84 - [3:0] */ -#define WM8995_WSEQ_DELAY84_SHIFT 0 /* WSEQ_DELAY84 - [3:0] */ -#define WM8995_WSEQ_DELAY84_WIDTH 4 /* WSEQ_DELAY84 - [3:0] */ - -/* - * R12628 (0x3154) - Write Sequencer 340 - */ -#define WM8995_WSEQ_ADDR85_MASK 0x3FFF /* WSEQ_ADDR85 - [13:0] */ -#define WM8995_WSEQ_ADDR85_SHIFT 0 /* WSEQ_ADDR85 - [13:0] */ -#define WM8995_WSEQ_ADDR85_WIDTH 14 /* WSEQ_ADDR85 - [13:0] */ - -/* - * R12629 (0x3155) - Write Sequencer 341 - */ -#define WM8995_WSEQ_DATA85_MASK 0x00FF /* WSEQ_DATA85 - [7:0] */ -#define WM8995_WSEQ_DATA85_SHIFT 0 /* WSEQ_DATA85 - [7:0] */ -#define WM8995_WSEQ_DATA85_WIDTH 8 /* WSEQ_DATA85 - [7:0] */ - -/* - * R12630 (0x3156) - Write Sequencer 342 - */ -#define WM8995_WSEQ_DATA_WIDTH85_MASK 0x0700 /* WSEQ_DATA_WIDTH85 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH85_SHIFT 8 /* WSEQ_DATA_WIDTH85 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH85_WIDTH 3 /* WSEQ_DATA_WIDTH85 - [10:8] */ -#define WM8995_WSEQ_DATA_START85_MASK 0x000F /* WSEQ_DATA_START85 - [3:0] */ -#define WM8995_WSEQ_DATA_START85_SHIFT 0 /* WSEQ_DATA_START85 - [3:0] */ -#define WM8995_WSEQ_DATA_START85_WIDTH 4 /* WSEQ_DATA_START85 - [3:0] */ - -/* - * R12631 (0x3157) - Write Sequencer 343 - */ -#define WM8995_WSEQ_EOS85 0x0100 /* WSEQ_EOS85 */ -#define WM8995_WSEQ_EOS85_MASK 0x0100 /* WSEQ_EOS85 */ -#define WM8995_WSEQ_EOS85_SHIFT 8 /* WSEQ_EOS85 */ -#define WM8995_WSEQ_EOS85_WIDTH 1 /* WSEQ_EOS85 */ -#define WM8995_WSEQ_DELAY85_MASK 0x000F /* WSEQ_DELAY85 - [3:0] */ -#define WM8995_WSEQ_DELAY85_SHIFT 0 /* WSEQ_DELAY85 - [3:0] */ -#define WM8995_WSEQ_DELAY85_WIDTH 4 /* WSEQ_DELAY85 - [3:0] */ - -/* - * R12632 (0x3158) - Write Sequencer 344 - */ -#define WM8995_WSEQ_ADDR86_MASK 0x3FFF /* WSEQ_ADDR86 - [13:0] */ -#define WM8995_WSEQ_ADDR86_SHIFT 0 /* WSEQ_ADDR86 - [13:0] */ -#define WM8995_WSEQ_ADDR86_WIDTH 14 /* WSEQ_ADDR86 - [13:0] */ - -/* - * R12633 (0x3159) - Write Sequencer 345 - */ -#define WM8995_WSEQ_DATA86_MASK 0x00FF /* WSEQ_DATA86 - [7:0] */ -#define WM8995_WSEQ_DATA86_SHIFT 0 /* WSEQ_DATA86 - [7:0] */ -#define WM8995_WSEQ_DATA86_WIDTH 8 /* WSEQ_DATA86 - [7:0] */ - -/* - * R12634 (0x315A) - Write Sequencer 346 - */ -#define WM8995_WSEQ_DATA_WIDTH86_MASK 0x0700 /* WSEQ_DATA_WIDTH86 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH86_SHIFT 8 /* WSEQ_DATA_WIDTH86 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH86_WIDTH 3 /* WSEQ_DATA_WIDTH86 - [10:8] */ -#define WM8995_WSEQ_DATA_START86_MASK 0x000F /* WSEQ_DATA_START86 - [3:0] */ -#define WM8995_WSEQ_DATA_START86_SHIFT 0 /* WSEQ_DATA_START86 - [3:0] */ -#define WM8995_WSEQ_DATA_START86_WIDTH 4 /* WSEQ_DATA_START86 - [3:0] */ - -/* - * R12635 (0x315B) - Write Sequencer 347 - */ -#define WM8995_WSEQ_EOS86 0x0100 /* WSEQ_EOS86 */ -#define WM8995_WSEQ_EOS86_MASK 0x0100 /* WSEQ_EOS86 */ -#define WM8995_WSEQ_EOS86_SHIFT 8 /* WSEQ_EOS86 */ -#define WM8995_WSEQ_EOS86_WIDTH 1 /* WSEQ_EOS86 */ -#define WM8995_WSEQ_DELAY86_MASK 0x000F /* WSEQ_DELAY86 - [3:0] */ -#define WM8995_WSEQ_DELAY86_SHIFT 0 /* WSEQ_DELAY86 - [3:0] */ -#define WM8995_WSEQ_DELAY86_WIDTH 4 /* WSEQ_DELAY86 - [3:0] */ - -/* - * R12636 (0x315C) - Write Sequencer 348 - */ -#define WM8995_WSEQ_ADDR87_MASK 0x3FFF /* WSEQ_ADDR87 - [13:0] */ -#define WM8995_WSEQ_ADDR87_SHIFT 0 /* WSEQ_ADDR87 - [13:0] */ -#define WM8995_WSEQ_ADDR87_WIDTH 14 /* WSEQ_ADDR87 - [13:0] */ - -/* - * R12637 (0x315D) - Write Sequencer 349 - */ -#define WM8995_WSEQ_DATA87_MASK 0x00FF /* WSEQ_DATA87 - [7:0] */ -#define WM8995_WSEQ_DATA87_SHIFT 0 /* WSEQ_DATA87 - [7:0] */ -#define WM8995_WSEQ_DATA87_WIDTH 8 /* WSEQ_DATA87 - [7:0] */ - -/* - * R12638 (0x315E) - Write Sequencer 350 - */ -#define WM8995_WSEQ_DATA_WIDTH87_MASK 0x0700 /* WSEQ_DATA_WIDTH87 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH87_SHIFT 8 /* WSEQ_DATA_WIDTH87 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH87_WIDTH 3 /* WSEQ_DATA_WIDTH87 - [10:8] */ -#define WM8995_WSEQ_DATA_START87_MASK 0x000F /* WSEQ_DATA_START87 - [3:0] */ -#define WM8995_WSEQ_DATA_START87_SHIFT 0 /* WSEQ_DATA_START87 - [3:0] */ -#define WM8995_WSEQ_DATA_START87_WIDTH 4 /* WSEQ_DATA_START87 - [3:0] */ - -/* - * R12639 (0x315F) - Write Sequencer 351 - */ -#define WM8995_WSEQ_EOS87 0x0100 /* WSEQ_EOS87 */ -#define WM8995_WSEQ_EOS87_MASK 0x0100 /* WSEQ_EOS87 */ -#define WM8995_WSEQ_EOS87_SHIFT 8 /* WSEQ_EOS87 */ -#define WM8995_WSEQ_EOS87_WIDTH 1 /* WSEQ_EOS87 */ -#define WM8995_WSEQ_DELAY87_MASK 0x000F /* WSEQ_DELAY87 - [3:0] */ -#define WM8995_WSEQ_DELAY87_SHIFT 0 /* WSEQ_DELAY87 - [3:0] */ -#define WM8995_WSEQ_DELAY87_WIDTH 4 /* WSEQ_DELAY87 - [3:0] */ - -/* - * R12640 (0x3160) - Write Sequencer 352 - */ -#define WM8995_WSEQ_ADDR88_MASK 0x3FFF /* WSEQ_ADDR88 - [13:0] */ -#define WM8995_WSEQ_ADDR88_SHIFT 0 /* WSEQ_ADDR88 - [13:0] */ -#define WM8995_WSEQ_ADDR88_WIDTH 14 /* WSEQ_ADDR88 - [13:0] */ - -/* - * R12641 (0x3161) - Write Sequencer 353 - */ -#define WM8995_WSEQ_DATA88_MASK 0x00FF /* WSEQ_DATA88 - [7:0] */ -#define WM8995_WSEQ_DATA88_SHIFT 0 /* WSEQ_DATA88 - [7:0] */ -#define WM8995_WSEQ_DATA88_WIDTH 8 /* WSEQ_DATA88 - [7:0] */ - -/* - * R12642 (0x3162) - Write Sequencer 354 - */ -#define WM8995_WSEQ_DATA_WIDTH88_MASK 0x0700 /* WSEQ_DATA_WIDTH88 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH88_SHIFT 8 /* WSEQ_DATA_WIDTH88 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH88_WIDTH 3 /* WSEQ_DATA_WIDTH88 - [10:8] */ -#define WM8995_WSEQ_DATA_START88_MASK 0x000F /* WSEQ_DATA_START88 - [3:0] */ -#define WM8995_WSEQ_DATA_START88_SHIFT 0 /* WSEQ_DATA_START88 - [3:0] */ -#define WM8995_WSEQ_DATA_START88_WIDTH 4 /* WSEQ_DATA_START88 - [3:0] */ - -/* - * R12643 (0x3163) - Write Sequencer 355 - */ -#define WM8995_WSEQ_EOS88 0x0100 /* WSEQ_EOS88 */ -#define WM8995_WSEQ_EOS88_MASK 0x0100 /* WSEQ_EOS88 */ -#define WM8995_WSEQ_EOS88_SHIFT 8 /* WSEQ_EOS88 */ -#define WM8995_WSEQ_EOS88_WIDTH 1 /* WSEQ_EOS88 */ -#define WM8995_WSEQ_DELAY88_MASK 0x000F /* WSEQ_DELAY88 - [3:0] */ -#define WM8995_WSEQ_DELAY88_SHIFT 0 /* WSEQ_DELAY88 - [3:0] */ -#define WM8995_WSEQ_DELAY88_WIDTH 4 /* WSEQ_DELAY88 - [3:0] */ - -/* - * R12644 (0x3164) - Write Sequencer 356 - */ -#define WM8995_WSEQ_ADDR89_MASK 0x3FFF /* WSEQ_ADDR89 - [13:0] */ -#define WM8995_WSEQ_ADDR89_SHIFT 0 /* WSEQ_ADDR89 - [13:0] */ -#define WM8995_WSEQ_ADDR89_WIDTH 14 /* WSEQ_ADDR89 - [13:0] */ - -/* - * R12645 (0x3165) - Write Sequencer 357 - */ -#define WM8995_WSEQ_DATA89_MASK 0x00FF /* WSEQ_DATA89 - [7:0] */ -#define WM8995_WSEQ_DATA89_SHIFT 0 /* WSEQ_DATA89 - [7:0] */ -#define WM8995_WSEQ_DATA89_WIDTH 8 /* WSEQ_DATA89 - [7:0] */ - -/* - * R12646 (0x3166) - Write Sequencer 358 - */ -#define WM8995_WSEQ_DATA_WIDTH89_MASK 0x0700 /* WSEQ_DATA_WIDTH89 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH89_SHIFT 8 /* WSEQ_DATA_WIDTH89 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH89_WIDTH 3 /* WSEQ_DATA_WIDTH89 - [10:8] */ -#define WM8995_WSEQ_DATA_START89_MASK 0x000F /* WSEQ_DATA_START89 - [3:0] */ -#define WM8995_WSEQ_DATA_START89_SHIFT 0 /* WSEQ_DATA_START89 - [3:0] */ -#define WM8995_WSEQ_DATA_START89_WIDTH 4 /* WSEQ_DATA_START89 - [3:0] */ - -/* - * R12647 (0x3167) - Write Sequencer 359 - */ -#define WM8995_WSEQ_EOS89 0x0100 /* WSEQ_EOS89 */ -#define WM8995_WSEQ_EOS89_MASK 0x0100 /* WSEQ_EOS89 */ -#define WM8995_WSEQ_EOS89_SHIFT 8 /* WSEQ_EOS89 */ -#define WM8995_WSEQ_EOS89_WIDTH 1 /* WSEQ_EOS89 */ -#define WM8995_WSEQ_DELAY89_MASK 0x000F /* WSEQ_DELAY89 - [3:0] */ -#define WM8995_WSEQ_DELAY89_SHIFT 0 /* WSEQ_DELAY89 - [3:0] */ -#define WM8995_WSEQ_DELAY89_WIDTH 4 /* WSEQ_DELAY89 - [3:0] */ - -/* - * R12648 (0x3168) - Write Sequencer 360 - */ -#define WM8995_WSEQ_ADDR90_MASK 0x3FFF /* WSEQ_ADDR90 - [13:0] */ -#define WM8995_WSEQ_ADDR90_SHIFT 0 /* WSEQ_ADDR90 - [13:0] */ -#define WM8995_WSEQ_ADDR90_WIDTH 14 /* WSEQ_ADDR90 - [13:0] */ - -/* - * R12649 (0x3169) - Write Sequencer 361 - */ -#define WM8995_WSEQ_DATA90_MASK 0x00FF /* WSEQ_DATA90 - [7:0] */ -#define WM8995_WSEQ_DATA90_SHIFT 0 /* WSEQ_DATA90 - [7:0] */ -#define WM8995_WSEQ_DATA90_WIDTH 8 /* WSEQ_DATA90 - [7:0] */ - -/* - * R12650 (0x316A) - Write Sequencer 362 - */ -#define WM8995_WSEQ_DATA_WIDTH90_MASK 0x0700 /* WSEQ_DATA_WIDTH90 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH90_SHIFT 8 /* WSEQ_DATA_WIDTH90 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH90_WIDTH 3 /* WSEQ_DATA_WIDTH90 - [10:8] */ -#define WM8995_WSEQ_DATA_START90_MASK 0x000F /* WSEQ_DATA_START90 - [3:0] */ -#define WM8995_WSEQ_DATA_START90_SHIFT 0 /* WSEQ_DATA_START90 - [3:0] */ -#define WM8995_WSEQ_DATA_START90_WIDTH 4 /* WSEQ_DATA_START90 - [3:0] */ - -/* - * R12651 (0x316B) - Write Sequencer 363 - */ -#define WM8995_WSEQ_EOS90 0x0100 /* WSEQ_EOS90 */ -#define WM8995_WSEQ_EOS90_MASK 0x0100 /* WSEQ_EOS90 */ -#define WM8995_WSEQ_EOS90_SHIFT 8 /* WSEQ_EOS90 */ -#define WM8995_WSEQ_EOS90_WIDTH 1 /* WSEQ_EOS90 */ -#define WM8995_WSEQ_DELAY90_MASK 0x000F /* WSEQ_DELAY90 - [3:0] */ -#define WM8995_WSEQ_DELAY90_SHIFT 0 /* WSEQ_DELAY90 - [3:0] */ -#define WM8995_WSEQ_DELAY90_WIDTH 4 /* WSEQ_DELAY90 - [3:0] */ - -/* - * R12652 (0x316C) - Write Sequencer 364 - */ -#define WM8995_WSEQ_ADDR91_MASK 0x3FFF /* WSEQ_ADDR91 - [13:0] */ -#define WM8995_WSEQ_ADDR91_SHIFT 0 /* WSEQ_ADDR91 - [13:0] */ -#define WM8995_WSEQ_ADDR91_WIDTH 14 /* WSEQ_ADDR91 - [13:0] */ - -/* - * R12653 (0x316D) - Write Sequencer 365 - */ -#define WM8995_WSEQ_DATA91_MASK 0x00FF /* WSEQ_DATA91 - [7:0] */ -#define WM8995_WSEQ_DATA91_SHIFT 0 /* WSEQ_DATA91 - [7:0] */ -#define WM8995_WSEQ_DATA91_WIDTH 8 /* WSEQ_DATA91 - [7:0] */ - -/* - * R12654 (0x316E) - Write Sequencer 366 - */ -#define WM8995_WSEQ_DATA_WIDTH91_MASK 0x0700 /* WSEQ_DATA_WIDTH91 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH91_SHIFT 8 /* WSEQ_DATA_WIDTH91 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH91_WIDTH 3 /* WSEQ_DATA_WIDTH91 - [10:8] */ -#define WM8995_WSEQ_DATA_START91_MASK 0x000F /* WSEQ_DATA_START91 - [3:0] */ -#define WM8995_WSEQ_DATA_START91_SHIFT 0 /* WSEQ_DATA_START91 - [3:0] */ -#define WM8995_WSEQ_DATA_START91_WIDTH 4 /* WSEQ_DATA_START91 - [3:0] */ - -/* - * R12655 (0x316F) - Write Sequencer 367 - */ -#define WM8995_WSEQ_EOS91 0x0100 /* WSEQ_EOS91 */ -#define WM8995_WSEQ_EOS91_MASK 0x0100 /* WSEQ_EOS91 */ -#define WM8995_WSEQ_EOS91_SHIFT 8 /* WSEQ_EOS91 */ -#define WM8995_WSEQ_EOS91_WIDTH 1 /* WSEQ_EOS91 */ -#define WM8995_WSEQ_DELAY91_MASK 0x000F /* WSEQ_DELAY91 - [3:0] */ -#define WM8995_WSEQ_DELAY91_SHIFT 0 /* WSEQ_DELAY91 - [3:0] */ -#define WM8995_WSEQ_DELAY91_WIDTH 4 /* WSEQ_DELAY91 - [3:0] */ - -/* - * R12656 (0x3170) - Write Sequencer 368 - */ -#define WM8995_WSEQ_ADDR92_MASK 0x3FFF /* WSEQ_ADDR92 - [13:0] */ -#define WM8995_WSEQ_ADDR92_SHIFT 0 /* WSEQ_ADDR92 - [13:0] */ -#define WM8995_WSEQ_ADDR92_WIDTH 14 /* WSEQ_ADDR92 - [13:0] */ - -/* - * R12657 (0x3171) - Write Sequencer 369 - */ -#define WM8995_WSEQ_DATA92_MASK 0x00FF /* WSEQ_DATA92 - [7:0] */ -#define WM8995_WSEQ_DATA92_SHIFT 0 /* WSEQ_DATA92 - [7:0] */ -#define WM8995_WSEQ_DATA92_WIDTH 8 /* WSEQ_DATA92 - [7:0] */ - -/* - * R12658 (0x3172) - Write Sequencer 370 - */ -#define WM8995_WSEQ_DATA_WIDTH92_MASK 0x0700 /* WSEQ_DATA_WIDTH92 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH92_SHIFT 8 /* WSEQ_DATA_WIDTH92 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH92_WIDTH 3 /* WSEQ_DATA_WIDTH92 - [10:8] */ -#define WM8995_WSEQ_DATA_START92_MASK 0x000F /* WSEQ_DATA_START92 - [3:0] */ -#define WM8995_WSEQ_DATA_START92_SHIFT 0 /* WSEQ_DATA_START92 - [3:0] */ -#define WM8995_WSEQ_DATA_START92_WIDTH 4 /* WSEQ_DATA_START92 - [3:0] */ - -/* - * R12659 (0x3173) - Write Sequencer 371 - */ -#define WM8995_WSEQ_EOS92 0x0100 /* WSEQ_EOS92 */ -#define WM8995_WSEQ_EOS92_MASK 0x0100 /* WSEQ_EOS92 */ -#define WM8995_WSEQ_EOS92_SHIFT 8 /* WSEQ_EOS92 */ -#define WM8995_WSEQ_EOS92_WIDTH 1 /* WSEQ_EOS92 */ -#define WM8995_WSEQ_DELAY92_MASK 0x000F /* WSEQ_DELAY92 - [3:0] */ -#define WM8995_WSEQ_DELAY92_SHIFT 0 /* WSEQ_DELAY92 - [3:0] */ -#define WM8995_WSEQ_DELAY92_WIDTH 4 /* WSEQ_DELAY92 - [3:0] */ - -/* - * R12660 (0x3174) - Write Sequencer 372 - */ -#define WM8995_WSEQ_ADDR93_MASK 0x3FFF /* WSEQ_ADDR93 - [13:0] */ -#define WM8995_WSEQ_ADDR93_SHIFT 0 /* WSEQ_ADDR93 - [13:0] */ -#define WM8995_WSEQ_ADDR93_WIDTH 14 /* WSEQ_ADDR93 - [13:0] */ - -/* - * R12661 (0x3175) - Write Sequencer 373 - */ -#define WM8995_WSEQ_DATA93_MASK 0x00FF /* WSEQ_DATA93 - [7:0] */ -#define WM8995_WSEQ_DATA93_SHIFT 0 /* WSEQ_DATA93 - [7:0] */ -#define WM8995_WSEQ_DATA93_WIDTH 8 /* WSEQ_DATA93 - [7:0] */ - -/* - * R12662 (0x3176) - Write Sequencer 374 - */ -#define WM8995_WSEQ_DATA_WIDTH93_MASK 0x0700 /* WSEQ_DATA_WIDTH93 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH93_SHIFT 8 /* WSEQ_DATA_WIDTH93 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH93_WIDTH 3 /* WSEQ_DATA_WIDTH93 - [10:8] */ -#define WM8995_WSEQ_DATA_START93_MASK 0x000F /* WSEQ_DATA_START93 - [3:0] */ -#define WM8995_WSEQ_DATA_START93_SHIFT 0 /* WSEQ_DATA_START93 - [3:0] */ -#define WM8995_WSEQ_DATA_START93_WIDTH 4 /* WSEQ_DATA_START93 - [3:0] */ - -/* - * R12663 (0x3177) - Write Sequencer 375 - */ -#define WM8995_WSEQ_EOS93 0x0100 /* WSEQ_EOS93 */ -#define WM8995_WSEQ_EOS93_MASK 0x0100 /* WSEQ_EOS93 */ -#define WM8995_WSEQ_EOS93_SHIFT 8 /* WSEQ_EOS93 */ -#define WM8995_WSEQ_EOS93_WIDTH 1 /* WSEQ_EOS93 */ -#define WM8995_WSEQ_DELAY93_MASK 0x000F /* WSEQ_DELAY93 - [3:0] */ -#define WM8995_WSEQ_DELAY93_SHIFT 0 /* WSEQ_DELAY93 - [3:0] */ -#define WM8995_WSEQ_DELAY93_WIDTH 4 /* WSEQ_DELAY93 - [3:0] */ - -/* - * R12664 (0x3178) - Write Sequencer 376 - */ -#define WM8995_WSEQ_ADDR94_MASK 0x3FFF /* WSEQ_ADDR94 - [13:0] */ -#define WM8995_WSEQ_ADDR94_SHIFT 0 /* WSEQ_ADDR94 - [13:0] */ -#define WM8995_WSEQ_ADDR94_WIDTH 14 /* WSEQ_ADDR94 - [13:0] */ - -/* - * R12665 (0x3179) - Write Sequencer 377 - */ -#define WM8995_WSEQ_DATA94_MASK 0x00FF /* WSEQ_DATA94 - [7:0] */ -#define WM8995_WSEQ_DATA94_SHIFT 0 /* WSEQ_DATA94 - [7:0] */ -#define WM8995_WSEQ_DATA94_WIDTH 8 /* WSEQ_DATA94 - [7:0] */ - -/* - * R12666 (0x317A) - Write Sequencer 378 - */ -#define WM8995_WSEQ_DATA_WIDTH94_MASK 0x0700 /* WSEQ_DATA_WIDTH94 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH94_SHIFT 8 /* WSEQ_DATA_WIDTH94 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH94_WIDTH 3 /* WSEQ_DATA_WIDTH94 - [10:8] */ -#define WM8995_WSEQ_DATA_START94_MASK 0x000F /* WSEQ_DATA_START94 - [3:0] */ -#define WM8995_WSEQ_DATA_START94_SHIFT 0 /* WSEQ_DATA_START94 - [3:0] */ -#define WM8995_WSEQ_DATA_START94_WIDTH 4 /* WSEQ_DATA_START94 - [3:0] */ - -/* - * R12667 (0x317B) - Write Sequencer 379 - */ -#define WM8995_WSEQ_EOS94 0x0100 /* WSEQ_EOS94 */ -#define WM8995_WSEQ_EOS94_MASK 0x0100 /* WSEQ_EOS94 */ -#define WM8995_WSEQ_EOS94_SHIFT 8 /* WSEQ_EOS94 */ -#define WM8995_WSEQ_EOS94_WIDTH 1 /* WSEQ_EOS94 */ -#define WM8995_WSEQ_DELAY94_MASK 0x000F /* WSEQ_DELAY94 - [3:0] */ -#define WM8995_WSEQ_DELAY94_SHIFT 0 /* WSEQ_DELAY94 - [3:0] */ -#define WM8995_WSEQ_DELAY94_WIDTH 4 /* WSEQ_DELAY94 - [3:0] */ - -/* - * R12668 (0x317C) - Write Sequencer 380 - */ -#define WM8995_WSEQ_ADDR95_MASK 0x3FFF /* WSEQ_ADDR95 - [13:0] */ -#define WM8995_WSEQ_ADDR95_SHIFT 0 /* WSEQ_ADDR95 - [13:0] */ -#define WM8995_WSEQ_ADDR95_WIDTH 14 /* WSEQ_ADDR95 - [13:0] */ - -/* - * R12669 (0x317D) - Write Sequencer 381 - */ -#define WM8995_WSEQ_DATA95_MASK 0x00FF /* WSEQ_DATA95 - [7:0] */ -#define WM8995_WSEQ_DATA95_SHIFT 0 /* WSEQ_DATA95 - [7:0] */ -#define WM8995_WSEQ_DATA95_WIDTH 8 /* WSEQ_DATA95 - [7:0] */ - -/* - * R12670 (0x317E) - Write Sequencer 382 - */ -#define WM8995_WSEQ_DATA_WIDTH95_MASK 0x0700 /* WSEQ_DATA_WIDTH95 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH95_SHIFT 8 /* WSEQ_DATA_WIDTH95 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH95_WIDTH 3 /* WSEQ_DATA_WIDTH95 - [10:8] */ -#define WM8995_WSEQ_DATA_START95_MASK 0x000F /* WSEQ_DATA_START95 - [3:0] */ -#define WM8995_WSEQ_DATA_START95_SHIFT 0 /* WSEQ_DATA_START95 - [3:0] */ -#define WM8995_WSEQ_DATA_START95_WIDTH 4 /* WSEQ_DATA_START95 - [3:0] */ - -/* - * R12671 (0x317F) - Write Sequencer 383 - */ -#define WM8995_WSEQ_EOS95 0x0100 /* WSEQ_EOS95 */ -#define WM8995_WSEQ_EOS95_MASK 0x0100 /* WSEQ_EOS95 */ -#define WM8995_WSEQ_EOS95_SHIFT 8 /* WSEQ_EOS95 */ -#define WM8995_WSEQ_EOS95_WIDTH 1 /* WSEQ_EOS95 */ -#define WM8995_WSEQ_DELAY95_MASK 0x000F /* WSEQ_DELAY95 - [3:0] */ -#define WM8995_WSEQ_DELAY95_SHIFT 0 /* WSEQ_DELAY95 - [3:0] */ -#define WM8995_WSEQ_DELAY95_WIDTH 4 /* WSEQ_DELAY95 - [3:0] */ - -/* - * R12672 (0x3180) - Write Sequencer 384 - */ -#define WM8995_WSEQ_ADDR96_MASK 0x3FFF /* WSEQ_ADDR96 - [13:0] */ -#define WM8995_WSEQ_ADDR96_SHIFT 0 /* WSEQ_ADDR96 - [13:0] */ -#define WM8995_WSEQ_ADDR96_WIDTH 14 /* WSEQ_ADDR96 - [13:0] */ - -/* - * R12673 (0x3181) - Write Sequencer 385 - */ -#define WM8995_WSEQ_DATA96_MASK 0x00FF /* WSEQ_DATA96 - [7:0] */ -#define WM8995_WSEQ_DATA96_SHIFT 0 /* WSEQ_DATA96 - [7:0] */ -#define WM8995_WSEQ_DATA96_WIDTH 8 /* WSEQ_DATA96 - [7:0] */ - -/* - * R12674 (0x3182) - Write Sequencer 386 - */ -#define WM8995_WSEQ_DATA_WIDTH96_MASK 0x0700 /* WSEQ_DATA_WIDTH96 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH96_SHIFT 8 /* WSEQ_DATA_WIDTH96 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH96_WIDTH 3 /* WSEQ_DATA_WIDTH96 - [10:8] */ -#define WM8995_WSEQ_DATA_START96_MASK 0x000F /* WSEQ_DATA_START96 - [3:0] */ -#define WM8995_WSEQ_DATA_START96_SHIFT 0 /* WSEQ_DATA_START96 - [3:0] */ -#define WM8995_WSEQ_DATA_START96_WIDTH 4 /* WSEQ_DATA_START96 - [3:0] */ - -/* - * R12675 (0x3183) - Write Sequencer 387 - */ -#define WM8995_WSEQ_EOS96 0x0100 /* WSEQ_EOS96 */ -#define WM8995_WSEQ_EOS96_MASK 0x0100 /* WSEQ_EOS96 */ -#define WM8995_WSEQ_EOS96_SHIFT 8 /* WSEQ_EOS96 */ -#define WM8995_WSEQ_EOS96_WIDTH 1 /* WSEQ_EOS96 */ -#define WM8995_WSEQ_DELAY96_MASK 0x000F /* WSEQ_DELAY96 - [3:0] */ -#define WM8995_WSEQ_DELAY96_SHIFT 0 /* WSEQ_DELAY96 - [3:0] */ -#define WM8995_WSEQ_DELAY96_WIDTH 4 /* WSEQ_DELAY96 - [3:0] */ - -/* - * R12676 (0x3184) - Write Sequencer 388 - */ -#define WM8995_WSEQ_ADDR97_MASK 0x3FFF /* WSEQ_ADDR97 - [13:0] */ -#define WM8995_WSEQ_ADDR97_SHIFT 0 /* WSEQ_ADDR97 - [13:0] */ -#define WM8995_WSEQ_ADDR97_WIDTH 14 /* WSEQ_ADDR97 - [13:0] */ - -/* - * R12677 (0x3185) - Write Sequencer 389 - */ -#define WM8995_WSEQ_DATA97_MASK 0x00FF /* WSEQ_DATA97 - [7:0] */ -#define WM8995_WSEQ_DATA97_SHIFT 0 /* WSEQ_DATA97 - [7:0] */ -#define WM8995_WSEQ_DATA97_WIDTH 8 /* WSEQ_DATA97 - [7:0] */ - -/* - * R12678 (0x3186) - Write Sequencer 390 - */ -#define WM8995_WSEQ_DATA_WIDTH97_MASK 0x0700 /* WSEQ_DATA_WIDTH97 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH97_SHIFT 8 /* WSEQ_DATA_WIDTH97 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH97_WIDTH 3 /* WSEQ_DATA_WIDTH97 - [10:8] */ -#define WM8995_WSEQ_DATA_START97_MASK 0x000F /* WSEQ_DATA_START97 - [3:0] */ -#define WM8995_WSEQ_DATA_START97_SHIFT 0 /* WSEQ_DATA_START97 - [3:0] */ -#define WM8995_WSEQ_DATA_START97_WIDTH 4 /* WSEQ_DATA_START97 - [3:0] */ - -/* - * R12679 (0x3187) - Write Sequencer 391 - */ -#define WM8995_WSEQ_EOS97 0x0100 /* WSEQ_EOS97 */ -#define WM8995_WSEQ_EOS97_MASK 0x0100 /* WSEQ_EOS97 */ -#define WM8995_WSEQ_EOS97_SHIFT 8 /* WSEQ_EOS97 */ -#define WM8995_WSEQ_EOS97_WIDTH 1 /* WSEQ_EOS97 */ -#define WM8995_WSEQ_DELAY97_MASK 0x000F /* WSEQ_DELAY97 - [3:0] */ -#define WM8995_WSEQ_DELAY97_SHIFT 0 /* WSEQ_DELAY97 - [3:0] */ -#define WM8995_WSEQ_DELAY97_WIDTH 4 /* WSEQ_DELAY97 - [3:0] */ - -/* - * R12680 (0x3188) - Write Sequencer 392 - */ -#define WM8995_WSEQ_ADDR98_MASK 0x3FFF /* WSEQ_ADDR98 - [13:0] */ -#define WM8995_WSEQ_ADDR98_SHIFT 0 /* WSEQ_ADDR98 - [13:0] */ -#define WM8995_WSEQ_ADDR98_WIDTH 14 /* WSEQ_ADDR98 - [13:0] */ - -/* - * R12681 (0x3189) - Write Sequencer 393 - */ -#define WM8995_WSEQ_DATA98_MASK 0x00FF /* WSEQ_DATA98 - [7:0] */ -#define WM8995_WSEQ_DATA98_SHIFT 0 /* WSEQ_DATA98 - [7:0] */ -#define WM8995_WSEQ_DATA98_WIDTH 8 /* WSEQ_DATA98 - [7:0] */ - -/* - * R12682 (0x318A) - Write Sequencer 394 - */ -#define WM8995_WSEQ_DATA_WIDTH98_MASK 0x0700 /* WSEQ_DATA_WIDTH98 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH98_SHIFT 8 /* WSEQ_DATA_WIDTH98 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH98_WIDTH 3 /* WSEQ_DATA_WIDTH98 - [10:8] */ -#define WM8995_WSEQ_DATA_START98_MASK 0x000F /* WSEQ_DATA_START98 - [3:0] */ -#define WM8995_WSEQ_DATA_START98_SHIFT 0 /* WSEQ_DATA_START98 - [3:0] */ -#define WM8995_WSEQ_DATA_START98_WIDTH 4 /* WSEQ_DATA_START98 - [3:0] */ - -/* - * R12683 (0x318B) - Write Sequencer 395 - */ -#define WM8995_WSEQ_EOS98 0x0100 /* WSEQ_EOS98 */ -#define WM8995_WSEQ_EOS98_MASK 0x0100 /* WSEQ_EOS98 */ -#define WM8995_WSEQ_EOS98_SHIFT 8 /* WSEQ_EOS98 */ -#define WM8995_WSEQ_EOS98_WIDTH 1 /* WSEQ_EOS98 */ -#define WM8995_WSEQ_DELAY98_MASK 0x000F /* WSEQ_DELAY98 - [3:0] */ -#define WM8995_WSEQ_DELAY98_SHIFT 0 /* WSEQ_DELAY98 - [3:0] */ -#define WM8995_WSEQ_DELAY98_WIDTH 4 /* WSEQ_DELAY98 - [3:0] */ - -/* - * R12684 (0x318C) - Write Sequencer 396 - */ -#define WM8995_WSEQ_ADDR99_MASK 0x3FFF /* WSEQ_ADDR99 - [13:0] */ -#define WM8995_WSEQ_ADDR99_SHIFT 0 /* WSEQ_ADDR99 - [13:0] */ -#define WM8995_WSEQ_ADDR99_WIDTH 14 /* WSEQ_ADDR99 - [13:0] */ - -/* - * R12685 (0x318D) - Write Sequencer 397 - */ -#define WM8995_WSEQ_DATA99_MASK 0x00FF /* WSEQ_DATA99 - [7:0] */ -#define WM8995_WSEQ_DATA99_SHIFT 0 /* WSEQ_DATA99 - [7:0] */ -#define WM8995_WSEQ_DATA99_WIDTH 8 /* WSEQ_DATA99 - [7:0] */ - -/* - * R12686 (0x318E) - Write Sequencer 398 - */ -#define WM8995_WSEQ_DATA_WIDTH99_MASK 0x0700 /* WSEQ_DATA_WIDTH99 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH99_SHIFT 8 /* WSEQ_DATA_WIDTH99 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH99_WIDTH 3 /* WSEQ_DATA_WIDTH99 - [10:8] */ -#define WM8995_WSEQ_DATA_START99_MASK 0x000F /* WSEQ_DATA_START99 - [3:0] */ -#define WM8995_WSEQ_DATA_START99_SHIFT 0 /* WSEQ_DATA_START99 - [3:0] */ -#define WM8995_WSEQ_DATA_START99_WIDTH 4 /* WSEQ_DATA_START99 - [3:0] */ - -/* - * R12687 (0x318F) - Write Sequencer 399 - */ -#define WM8995_WSEQ_EOS99 0x0100 /* WSEQ_EOS99 */ -#define WM8995_WSEQ_EOS99_MASK 0x0100 /* WSEQ_EOS99 */ -#define WM8995_WSEQ_EOS99_SHIFT 8 /* WSEQ_EOS99 */ -#define WM8995_WSEQ_EOS99_WIDTH 1 /* WSEQ_EOS99 */ -#define WM8995_WSEQ_DELAY99_MASK 0x000F /* WSEQ_DELAY99 - [3:0] */ -#define WM8995_WSEQ_DELAY99_SHIFT 0 /* WSEQ_DELAY99 - [3:0] */ -#define WM8995_WSEQ_DELAY99_WIDTH 4 /* WSEQ_DELAY99 - [3:0] */ - -/* - * R12688 (0x3190) - Write Sequencer 400 - */ -#define WM8995_WSEQ_ADDR100_MASK 0x3FFF /* WSEQ_ADDR100 - [13:0] */ -#define WM8995_WSEQ_ADDR100_SHIFT 0 /* WSEQ_ADDR100 - [13:0] */ -#define WM8995_WSEQ_ADDR100_WIDTH 14 /* WSEQ_ADDR100 - [13:0] */ - -/* - * R12689 (0x3191) - Write Sequencer 401 - */ -#define WM8995_WSEQ_DATA100_MASK 0x00FF /* WSEQ_DATA100 - [7:0] */ -#define WM8995_WSEQ_DATA100_SHIFT 0 /* WSEQ_DATA100 - [7:0] */ -#define WM8995_WSEQ_DATA100_WIDTH 8 /* WSEQ_DATA100 - [7:0] */ - -/* - * R12690 (0x3192) - Write Sequencer 402 - */ -#define WM8995_WSEQ_DATA_WIDTH100_MASK 0x0700 /* WSEQ_DATA_WIDTH100 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH100_SHIFT 8 /* WSEQ_DATA_WIDTH100 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH100_WIDTH 3 /* WSEQ_DATA_WIDTH100 - [10:8] */ -#define WM8995_WSEQ_DATA_START100_MASK 0x000F /* WSEQ_DATA_START100 - [3:0] */ -#define WM8995_WSEQ_DATA_START100_SHIFT 0 /* WSEQ_DATA_START100 - [3:0] */ -#define WM8995_WSEQ_DATA_START100_WIDTH 4 /* WSEQ_DATA_START100 - [3:0] */ - -/* - * R12691 (0x3193) - Write Sequencer 403 - */ -#define WM8995_WSEQ_EOS100 0x0100 /* WSEQ_EOS100 */ -#define WM8995_WSEQ_EOS100_MASK 0x0100 /* WSEQ_EOS100 */ -#define WM8995_WSEQ_EOS100_SHIFT 8 /* WSEQ_EOS100 */ -#define WM8995_WSEQ_EOS100_WIDTH 1 /* WSEQ_EOS100 */ -#define WM8995_WSEQ_DELAY100_MASK 0x000F /* WSEQ_DELAY100 - [3:0] */ -#define WM8995_WSEQ_DELAY100_SHIFT 0 /* WSEQ_DELAY100 - [3:0] */ -#define WM8995_WSEQ_DELAY100_WIDTH 4 /* WSEQ_DELAY100 - [3:0] */ - -/* - * R12692 (0x3194) - Write Sequencer 404 - */ -#define WM8995_WSEQ_ADDR101_MASK 0x3FFF /* WSEQ_ADDR101 - [13:0] */ -#define WM8995_WSEQ_ADDR101_SHIFT 0 /* WSEQ_ADDR101 - [13:0] */ -#define WM8995_WSEQ_ADDR101_WIDTH 14 /* WSEQ_ADDR101 - [13:0] */ - -/* - * R12693 (0x3195) - Write Sequencer 405 - */ -#define WM8995_WSEQ_DATA101_MASK 0x00FF /* WSEQ_DATA101 - [7:0] */ -#define WM8995_WSEQ_DATA101_SHIFT 0 /* WSEQ_DATA101 - [7:0] */ -#define WM8995_WSEQ_DATA101_WIDTH 8 /* WSEQ_DATA101 - [7:0] */ - -/* - * R12694 (0x3196) - Write Sequencer 406 - */ -#define WM8995_WSEQ_DATA_WIDTH101_MASK 0x0700 /* WSEQ_DATA_WIDTH101 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH101_SHIFT 8 /* WSEQ_DATA_WIDTH101 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH101_WIDTH 3 /* WSEQ_DATA_WIDTH101 - [10:8] */ -#define WM8995_WSEQ_DATA_START101_MASK 0x000F /* WSEQ_DATA_START101 - [3:0] */ -#define WM8995_WSEQ_DATA_START101_SHIFT 0 /* WSEQ_DATA_START101 - [3:0] */ -#define WM8995_WSEQ_DATA_START101_WIDTH 4 /* WSEQ_DATA_START101 - [3:0] */ - -/* - * R12695 (0x3197) - Write Sequencer 407 - */ -#define WM8995_WSEQ_EOS101 0x0100 /* WSEQ_EOS101 */ -#define WM8995_WSEQ_EOS101_MASK 0x0100 /* WSEQ_EOS101 */ -#define WM8995_WSEQ_EOS101_SHIFT 8 /* WSEQ_EOS101 */ -#define WM8995_WSEQ_EOS101_WIDTH 1 /* WSEQ_EOS101 */ -#define WM8995_WSEQ_DELAY101_MASK 0x000F /* WSEQ_DELAY101 - [3:0] */ -#define WM8995_WSEQ_DELAY101_SHIFT 0 /* WSEQ_DELAY101 - [3:0] */ -#define WM8995_WSEQ_DELAY101_WIDTH 4 /* WSEQ_DELAY101 - [3:0] */ - -/* - * R12696 (0x3198) - Write Sequencer 408 - */ -#define WM8995_WSEQ_ADDR102_MASK 0x3FFF /* WSEQ_ADDR102 - [13:0] */ -#define WM8995_WSEQ_ADDR102_SHIFT 0 /* WSEQ_ADDR102 - [13:0] */ -#define WM8995_WSEQ_ADDR102_WIDTH 14 /* WSEQ_ADDR102 - [13:0] */ - -/* - * R12697 (0x3199) - Write Sequencer 409 - */ -#define WM8995_WSEQ_DATA102_MASK 0x00FF /* WSEQ_DATA102 - [7:0] */ -#define WM8995_WSEQ_DATA102_SHIFT 0 /* WSEQ_DATA102 - [7:0] */ -#define WM8995_WSEQ_DATA102_WIDTH 8 /* WSEQ_DATA102 - [7:0] */ - -/* - * R12698 (0x319A) - Write Sequencer 410 - */ -#define WM8995_WSEQ_DATA_WIDTH102_MASK 0x0700 /* WSEQ_DATA_WIDTH102 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH102_SHIFT 8 /* WSEQ_DATA_WIDTH102 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH102_WIDTH 3 /* WSEQ_DATA_WIDTH102 - [10:8] */ -#define WM8995_WSEQ_DATA_START102_MASK 0x000F /* WSEQ_DATA_START102 - [3:0] */ -#define WM8995_WSEQ_DATA_START102_SHIFT 0 /* WSEQ_DATA_START102 - [3:0] */ -#define WM8995_WSEQ_DATA_START102_WIDTH 4 /* WSEQ_DATA_START102 - [3:0] */ - -/* - * R12699 (0x319B) - Write Sequencer 411 - */ -#define WM8995_WSEQ_EOS102 0x0100 /* WSEQ_EOS102 */ -#define WM8995_WSEQ_EOS102_MASK 0x0100 /* WSEQ_EOS102 */ -#define WM8995_WSEQ_EOS102_SHIFT 8 /* WSEQ_EOS102 */ -#define WM8995_WSEQ_EOS102_WIDTH 1 /* WSEQ_EOS102 */ -#define WM8995_WSEQ_DELAY102_MASK 0x000F /* WSEQ_DELAY102 - [3:0] */ -#define WM8995_WSEQ_DELAY102_SHIFT 0 /* WSEQ_DELAY102 - [3:0] */ -#define WM8995_WSEQ_DELAY102_WIDTH 4 /* WSEQ_DELAY102 - [3:0] */ - -/* - * R12700 (0x319C) - Write Sequencer 412 - */ -#define WM8995_WSEQ_ADDR103_MASK 0x3FFF /* WSEQ_ADDR103 - [13:0] */ -#define WM8995_WSEQ_ADDR103_SHIFT 0 /* WSEQ_ADDR103 - [13:0] */ -#define WM8995_WSEQ_ADDR103_WIDTH 14 /* WSEQ_ADDR103 - [13:0] */ - -/* - * R12701 (0x319D) - Write Sequencer 413 - */ -#define WM8995_WSEQ_DATA103_MASK 0x00FF /* WSEQ_DATA103 - [7:0] */ -#define WM8995_WSEQ_DATA103_SHIFT 0 /* WSEQ_DATA103 - [7:0] */ -#define WM8995_WSEQ_DATA103_WIDTH 8 /* WSEQ_DATA103 - [7:0] */ - -/* - * R12702 (0x319E) - Write Sequencer 414 - */ -#define WM8995_WSEQ_DATA_WIDTH103_MASK 0x0700 /* WSEQ_DATA_WIDTH103 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH103_SHIFT 8 /* WSEQ_DATA_WIDTH103 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH103_WIDTH 3 /* WSEQ_DATA_WIDTH103 - [10:8] */ -#define WM8995_WSEQ_DATA_START103_MASK 0x000F /* WSEQ_DATA_START103 - [3:0] */ -#define WM8995_WSEQ_DATA_START103_SHIFT 0 /* WSEQ_DATA_START103 - [3:0] */ -#define WM8995_WSEQ_DATA_START103_WIDTH 4 /* WSEQ_DATA_START103 - [3:0] */ - -/* - * R12703 (0x319F) - Write Sequencer 415 - */ -#define WM8995_WSEQ_EOS103 0x0100 /* WSEQ_EOS103 */ -#define WM8995_WSEQ_EOS103_MASK 0x0100 /* WSEQ_EOS103 */ -#define WM8995_WSEQ_EOS103_SHIFT 8 /* WSEQ_EOS103 */ -#define WM8995_WSEQ_EOS103_WIDTH 1 /* WSEQ_EOS103 */ -#define WM8995_WSEQ_DELAY103_MASK 0x000F /* WSEQ_DELAY103 - [3:0] */ -#define WM8995_WSEQ_DELAY103_SHIFT 0 /* WSEQ_DELAY103 - [3:0] */ -#define WM8995_WSEQ_DELAY103_WIDTH 4 /* WSEQ_DELAY103 - [3:0] */ - -/* - * R12704 (0x31A0) - Write Sequencer 416 - */ -#define WM8995_WSEQ_ADDR104_MASK 0x3FFF /* WSEQ_ADDR104 - [13:0] */ -#define WM8995_WSEQ_ADDR104_SHIFT 0 /* WSEQ_ADDR104 - [13:0] */ -#define WM8995_WSEQ_ADDR104_WIDTH 14 /* WSEQ_ADDR104 - [13:0] */ - -/* - * R12705 (0x31A1) - Write Sequencer 417 - */ -#define WM8995_WSEQ_DATA104_MASK 0x00FF /* WSEQ_DATA104 - [7:0] */ -#define WM8995_WSEQ_DATA104_SHIFT 0 /* WSEQ_DATA104 - [7:0] */ -#define WM8995_WSEQ_DATA104_WIDTH 8 /* WSEQ_DATA104 - [7:0] */ - -/* - * R12706 (0x31A2) - Write Sequencer 418 - */ -#define WM8995_WSEQ_DATA_WIDTH104_MASK 0x0700 /* WSEQ_DATA_WIDTH104 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH104_SHIFT 8 /* WSEQ_DATA_WIDTH104 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH104_WIDTH 3 /* WSEQ_DATA_WIDTH104 - [10:8] */ -#define WM8995_WSEQ_DATA_START104_MASK 0x000F /* WSEQ_DATA_START104 - [3:0] */ -#define WM8995_WSEQ_DATA_START104_SHIFT 0 /* WSEQ_DATA_START104 - [3:0] */ -#define WM8995_WSEQ_DATA_START104_WIDTH 4 /* WSEQ_DATA_START104 - [3:0] */ - -/* - * R12707 (0x31A3) - Write Sequencer 419 - */ -#define WM8995_WSEQ_EOS104 0x0100 /* WSEQ_EOS104 */ -#define WM8995_WSEQ_EOS104_MASK 0x0100 /* WSEQ_EOS104 */ -#define WM8995_WSEQ_EOS104_SHIFT 8 /* WSEQ_EOS104 */ -#define WM8995_WSEQ_EOS104_WIDTH 1 /* WSEQ_EOS104 */ -#define WM8995_WSEQ_DELAY104_MASK 0x000F /* WSEQ_DELAY104 - [3:0] */ -#define WM8995_WSEQ_DELAY104_SHIFT 0 /* WSEQ_DELAY104 - [3:0] */ -#define WM8995_WSEQ_DELAY104_WIDTH 4 /* WSEQ_DELAY104 - [3:0] */ - -/* - * R12708 (0x31A4) - Write Sequencer 420 - */ -#define WM8995_WSEQ_ADDR105_MASK 0x3FFF /* WSEQ_ADDR105 - [13:0] */ -#define WM8995_WSEQ_ADDR105_SHIFT 0 /* WSEQ_ADDR105 - [13:0] */ -#define WM8995_WSEQ_ADDR105_WIDTH 14 /* WSEQ_ADDR105 - [13:0] */ - -/* - * R12709 (0x31A5) - Write Sequencer 421 - */ -#define WM8995_WSEQ_DATA105_MASK 0x00FF /* WSEQ_DATA105 - [7:0] */ -#define WM8995_WSEQ_DATA105_SHIFT 0 /* WSEQ_DATA105 - [7:0] */ -#define WM8995_WSEQ_DATA105_WIDTH 8 /* WSEQ_DATA105 - [7:0] */ - -/* - * R12710 (0x31A6) - Write Sequencer 422 - */ -#define WM8995_WSEQ_DATA_WIDTH105_MASK 0x0700 /* WSEQ_DATA_WIDTH105 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH105_SHIFT 8 /* WSEQ_DATA_WIDTH105 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH105_WIDTH 3 /* WSEQ_DATA_WIDTH105 - [10:8] */ -#define WM8995_WSEQ_DATA_START105_MASK 0x000F /* WSEQ_DATA_START105 - [3:0] */ -#define WM8995_WSEQ_DATA_START105_SHIFT 0 /* WSEQ_DATA_START105 - [3:0] */ -#define WM8995_WSEQ_DATA_START105_WIDTH 4 /* WSEQ_DATA_START105 - [3:0] */ - -/* - * R12711 (0x31A7) - Write Sequencer 423 - */ -#define WM8995_WSEQ_EOS105 0x0100 /* WSEQ_EOS105 */ -#define WM8995_WSEQ_EOS105_MASK 0x0100 /* WSEQ_EOS105 */ -#define WM8995_WSEQ_EOS105_SHIFT 8 /* WSEQ_EOS105 */ -#define WM8995_WSEQ_EOS105_WIDTH 1 /* WSEQ_EOS105 */ -#define WM8995_WSEQ_DELAY105_MASK 0x000F /* WSEQ_DELAY105 - [3:0] */ -#define WM8995_WSEQ_DELAY105_SHIFT 0 /* WSEQ_DELAY105 - [3:0] */ -#define WM8995_WSEQ_DELAY105_WIDTH 4 /* WSEQ_DELAY105 - [3:0] */ - -/* - * R12712 (0x31A8) - Write Sequencer 424 - */ -#define WM8995_WSEQ_ADDR106_MASK 0x3FFF /* WSEQ_ADDR106 - [13:0] */ -#define WM8995_WSEQ_ADDR106_SHIFT 0 /* WSEQ_ADDR106 - [13:0] */ -#define WM8995_WSEQ_ADDR106_WIDTH 14 /* WSEQ_ADDR106 - [13:0] */ - -/* - * R12713 (0x31A9) - Write Sequencer 425 - */ -#define WM8995_WSEQ_DATA106_MASK 0x00FF /* WSEQ_DATA106 - [7:0] */ -#define WM8995_WSEQ_DATA106_SHIFT 0 /* WSEQ_DATA106 - [7:0] */ -#define WM8995_WSEQ_DATA106_WIDTH 8 /* WSEQ_DATA106 - [7:0] */ - -/* - * R12714 (0x31AA) - Write Sequencer 426 - */ -#define WM8995_WSEQ_DATA_WIDTH106_MASK 0x0700 /* WSEQ_DATA_WIDTH106 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH106_SHIFT 8 /* WSEQ_DATA_WIDTH106 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH106_WIDTH 3 /* WSEQ_DATA_WIDTH106 - [10:8] */ -#define WM8995_WSEQ_DATA_START106_MASK 0x000F /* WSEQ_DATA_START106 - [3:0] */ -#define WM8995_WSEQ_DATA_START106_SHIFT 0 /* WSEQ_DATA_START106 - [3:0] */ -#define WM8995_WSEQ_DATA_START106_WIDTH 4 /* WSEQ_DATA_START106 - [3:0] */ - -/* - * R12715 (0x31AB) - Write Sequencer 427 - */ -#define WM8995_WSEQ_EOS106 0x0100 /* WSEQ_EOS106 */ -#define WM8995_WSEQ_EOS106_MASK 0x0100 /* WSEQ_EOS106 */ -#define WM8995_WSEQ_EOS106_SHIFT 8 /* WSEQ_EOS106 */ -#define WM8995_WSEQ_EOS106_WIDTH 1 /* WSEQ_EOS106 */ -#define WM8995_WSEQ_DELAY106_MASK 0x000F /* WSEQ_DELAY106 - [3:0] */ -#define WM8995_WSEQ_DELAY106_SHIFT 0 /* WSEQ_DELAY106 - [3:0] */ -#define WM8995_WSEQ_DELAY106_WIDTH 4 /* WSEQ_DELAY106 - [3:0] */ - -/* - * R12716 (0x31AC) - Write Sequencer 428 - */ -#define WM8995_WSEQ_ADDR107_MASK 0x3FFF /* WSEQ_ADDR107 - [13:0] */ -#define WM8995_WSEQ_ADDR107_SHIFT 0 /* WSEQ_ADDR107 - [13:0] */ -#define WM8995_WSEQ_ADDR107_WIDTH 14 /* WSEQ_ADDR107 - [13:0] */ - -/* - * R12717 (0x31AD) - Write Sequencer 429 - */ -#define WM8995_WSEQ_DATA107_MASK 0x00FF /* WSEQ_DATA107 - [7:0] */ -#define WM8995_WSEQ_DATA107_SHIFT 0 /* WSEQ_DATA107 - [7:0] */ -#define WM8995_WSEQ_DATA107_WIDTH 8 /* WSEQ_DATA107 - [7:0] */ - -/* - * R12718 (0x31AE) - Write Sequencer 430 - */ -#define WM8995_WSEQ_DATA_WIDTH107_MASK 0x0700 /* WSEQ_DATA_WIDTH107 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH107_SHIFT 8 /* WSEQ_DATA_WIDTH107 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH107_WIDTH 3 /* WSEQ_DATA_WIDTH107 - [10:8] */ -#define WM8995_WSEQ_DATA_START107_MASK 0x000F /* WSEQ_DATA_START107 - [3:0] */ -#define WM8995_WSEQ_DATA_START107_SHIFT 0 /* WSEQ_DATA_START107 - [3:0] */ -#define WM8995_WSEQ_DATA_START107_WIDTH 4 /* WSEQ_DATA_START107 - [3:0] */ - -/* - * R12719 (0x31AF) - Write Sequencer 431 - */ -#define WM8995_WSEQ_EOS107 0x0100 /* WSEQ_EOS107 */ -#define WM8995_WSEQ_EOS107_MASK 0x0100 /* WSEQ_EOS107 */ -#define WM8995_WSEQ_EOS107_SHIFT 8 /* WSEQ_EOS107 */ -#define WM8995_WSEQ_EOS107_WIDTH 1 /* WSEQ_EOS107 */ -#define WM8995_WSEQ_DELAY107_MASK 0x000F /* WSEQ_DELAY107 - [3:0] */ -#define WM8995_WSEQ_DELAY107_SHIFT 0 /* WSEQ_DELAY107 - [3:0] */ -#define WM8995_WSEQ_DELAY107_WIDTH 4 /* WSEQ_DELAY107 - [3:0] */ - -/* - * R12720 (0x31B0) - Write Sequencer 432 - */ -#define WM8995_WSEQ_ADDR108_MASK 0x3FFF /* WSEQ_ADDR108 - [13:0] */ -#define WM8995_WSEQ_ADDR108_SHIFT 0 /* WSEQ_ADDR108 - [13:0] */ -#define WM8995_WSEQ_ADDR108_WIDTH 14 /* WSEQ_ADDR108 - [13:0] */ - -/* - * R12721 (0x31B1) - Write Sequencer 433 - */ -#define WM8995_WSEQ_DATA108_MASK 0x00FF /* WSEQ_DATA108 - [7:0] */ -#define WM8995_WSEQ_DATA108_SHIFT 0 /* WSEQ_DATA108 - [7:0] */ -#define WM8995_WSEQ_DATA108_WIDTH 8 /* WSEQ_DATA108 - [7:0] */ - -/* - * R12722 (0x31B2) - Write Sequencer 434 - */ -#define WM8995_WSEQ_DATA_WIDTH108_MASK 0x0700 /* WSEQ_DATA_WIDTH108 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH108_SHIFT 8 /* WSEQ_DATA_WIDTH108 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH108_WIDTH 3 /* WSEQ_DATA_WIDTH108 - [10:8] */ -#define WM8995_WSEQ_DATA_START108_MASK 0x000F /* WSEQ_DATA_START108 - [3:0] */ -#define WM8995_WSEQ_DATA_START108_SHIFT 0 /* WSEQ_DATA_START108 - [3:0] */ -#define WM8995_WSEQ_DATA_START108_WIDTH 4 /* WSEQ_DATA_START108 - [3:0] */ - -/* - * R12723 (0x31B3) - Write Sequencer 435 - */ -#define WM8995_WSEQ_EOS108 0x0100 /* WSEQ_EOS108 */ -#define WM8995_WSEQ_EOS108_MASK 0x0100 /* WSEQ_EOS108 */ -#define WM8995_WSEQ_EOS108_SHIFT 8 /* WSEQ_EOS108 */ -#define WM8995_WSEQ_EOS108_WIDTH 1 /* WSEQ_EOS108 */ -#define WM8995_WSEQ_DELAY108_MASK 0x000F /* WSEQ_DELAY108 - [3:0] */ -#define WM8995_WSEQ_DELAY108_SHIFT 0 /* WSEQ_DELAY108 - [3:0] */ -#define WM8995_WSEQ_DELAY108_WIDTH 4 /* WSEQ_DELAY108 - [3:0] */ - -/* - * R12724 (0x31B4) - Write Sequencer 436 - */ -#define WM8995_WSEQ_ADDR109_MASK 0x3FFF /* WSEQ_ADDR109 - [13:0] */ -#define WM8995_WSEQ_ADDR109_SHIFT 0 /* WSEQ_ADDR109 - [13:0] */ -#define WM8995_WSEQ_ADDR109_WIDTH 14 /* WSEQ_ADDR109 - [13:0] */ - -/* - * R12725 (0x31B5) - Write Sequencer 437 - */ -#define WM8995_WSEQ_DATA109_MASK 0x00FF /* WSEQ_DATA109 - [7:0] */ -#define WM8995_WSEQ_DATA109_SHIFT 0 /* WSEQ_DATA109 - [7:0] */ -#define WM8995_WSEQ_DATA109_WIDTH 8 /* WSEQ_DATA109 - [7:0] */ - -/* - * R12726 (0x31B6) - Write Sequencer 438 - */ -#define WM8995_WSEQ_DATA_WIDTH109_MASK 0x0700 /* WSEQ_DATA_WIDTH109 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH109_SHIFT 8 /* WSEQ_DATA_WIDTH109 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH109_WIDTH 3 /* WSEQ_DATA_WIDTH109 - [10:8] */ -#define WM8995_WSEQ_DATA_START109_MASK 0x000F /* WSEQ_DATA_START109 - [3:0] */ -#define WM8995_WSEQ_DATA_START109_SHIFT 0 /* WSEQ_DATA_START109 - [3:0] */ -#define WM8995_WSEQ_DATA_START109_WIDTH 4 /* WSEQ_DATA_START109 - [3:0] */ - -/* - * R12727 (0x31B7) - Write Sequencer 439 - */ -#define WM8995_WSEQ_EOS109 0x0100 /* WSEQ_EOS109 */ -#define WM8995_WSEQ_EOS109_MASK 0x0100 /* WSEQ_EOS109 */ -#define WM8995_WSEQ_EOS109_SHIFT 8 /* WSEQ_EOS109 */ -#define WM8995_WSEQ_EOS109_WIDTH 1 /* WSEQ_EOS109 */ -#define WM8995_WSEQ_DELAY109_MASK 0x000F /* WSEQ_DELAY109 - [3:0] */ -#define WM8995_WSEQ_DELAY109_SHIFT 0 /* WSEQ_DELAY109 - [3:0] */ -#define WM8995_WSEQ_DELAY109_WIDTH 4 /* WSEQ_DELAY109 - [3:0] */ - -/* - * R12728 (0x31B8) - Write Sequencer 440 - */ -#define WM8995_WSEQ_ADDR110_MASK 0x3FFF /* WSEQ_ADDR110 - [13:0] */ -#define WM8995_WSEQ_ADDR110_SHIFT 0 /* WSEQ_ADDR110 - [13:0] */ -#define WM8995_WSEQ_ADDR110_WIDTH 14 /* WSEQ_ADDR110 - [13:0] */ - -/* - * R12729 (0x31B9) - Write Sequencer 441 - */ -#define WM8995_WSEQ_DATA110_MASK 0x00FF /* WSEQ_DATA110 - [7:0] */ -#define WM8995_WSEQ_DATA110_SHIFT 0 /* WSEQ_DATA110 - [7:0] */ -#define WM8995_WSEQ_DATA110_WIDTH 8 /* WSEQ_DATA110 - [7:0] */ - -/* - * R12730 (0x31BA) - Write Sequencer 442 - */ -#define WM8995_WSEQ_DATA_WIDTH110_MASK 0x0700 /* WSEQ_DATA_WIDTH110 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH110_SHIFT 8 /* WSEQ_DATA_WIDTH110 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH110_WIDTH 3 /* WSEQ_DATA_WIDTH110 - [10:8] */ -#define WM8995_WSEQ_DATA_START110_MASK 0x000F /* WSEQ_DATA_START110 - [3:0] */ -#define WM8995_WSEQ_DATA_START110_SHIFT 0 /* WSEQ_DATA_START110 - [3:0] */ -#define WM8995_WSEQ_DATA_START110_WIDTH 4 /* WSEQ_DATA_START110 - [3:0] */ - -/* - * R12731 (0x31BB) - Write Sequencer 443 - */ -#define WM8995_WSEQ_EOS110 0x0100 /* WSEQ_EOS110 */ -#define WM8995_WSEQ_EOS110_MASK 0x0100 /* WSEQ_EOS110 */ -#define WM8995_WSEQ_EOS110_SHIFT 8 /* WSEQ_EOS110 */ -#define WM8995_WSEQ_EOS110_WIDTH 1 /* WSEQ_EOS110 */ -#define WM8995_WSEQ_DELAY110_MASK 0x000F /* WSEQ_DELAY110 - [3:0] */ -#define WM8995_WSEQ_DELAY110_SHIFT 0 /* WSEQ_DELAY110 - [3:0] */ -#define WM8995_WSEQ_DELAY110_WIDTH 4 /* WSEQ_DELAY110 - [3:0] */ - -/* - * R12732 (0x31BC) - Write Sequencer 444 - */ -#define WM8995_WSEQ_ADDR111_MASK 0x3FFF /* WSEQ_ADDR111 - [13:0] */ -#define WM8995_WSEQ_ADDR111_SHIFT 0 /* WSEQ_ADDR111 - [13:0] */ -#define WM8995_WSEQ_ADDR111_WIDTH 14 /* WSEQ_ADDR111 - [13:0] */ - -/* - * R12733 (0x31BD) - Write Sequencer 445 - */ -#define WM8995_WSEQ_DATA111_MASK 0x00FF /* WSEQ_DATA111 - [7:0] */ -#define WM8995_WSEQ_DATA111_SHIFT 0 /* WSEQ_DATA111 - [7:0] */ -#define WM8995_WSEQ_DATA111_WIDTH 8 /* WSEQ_DATA111 - [7:0] */ - -/* - * R12734 (0x31BE) - Write Sequencer 446 - */ -#define WM8995_WSEQ_DATA_WIDTH111_MASK 0x0700 /* WSEQ_DATA_WIDTH111 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH111_SHIFT 8 /* WSEQ_DATA_WIDTH111 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH111_WIDTH 3 /* WSEQ_DATA_WIDTH111 - [10:8] */ -#define WM8995_WSEQ_DATA_START111_MASK 0x000F /* WSEQ_DATA_START111 - [3:0] */ -#define WM8995_WSEQ_DATA_START111_SHIFT 0 /* WSEQ_DATA_START111 - [3:0] */ -#define WM8995_WSEQ_DATA_START111_WIDTH 4 /* WSEQ_DATA_START111 - [3:0] */ - -/* - * R12735 (0x31BF) - Write Sequencer 447 - */ -#define WM8995_WSEQ_EOS111 0x0100 /* WSEQ_EOS111 */ -#define WM8995_WSEQ_EOS111_MASK 0x0100 /* WSEQ_EOS111 */ -#define WM8995_WSEQ_EOS111_SHIFT 8 /* WSEQ_EOS111 */ -#define WM8995_WSEQ_EOS111_WIDTH 1 /* WSEQ_EOS111 */ -#define WM8995_WSEQ_DELAY111_MASK 0x000F /* WSEQ_DELAY111 - [3:0] */ -#define WM8995_WSEQ_DELAY111_SHIFT 0 /* WSEQ_DELAY111 - [3:0] */ -#define WM8995_WSEQ_DELAY111_WIDTH 4 /* WSEQ_DELAY111 - [3:0] */ - -/* - * R12736 (0x31C0) - Write Sequencer 448 - */ -#define WM8995_WSEQ_ADDR112_MASK 0x3FFF /* WSEQ_ADDR112 - [13:0] */ -#define WM8995_WSEQ_ADDR112_SHIFT 0 /* WSEQ_ADDR112 - [13:0] */ -#define WM8995_WSEQ_ADDR112_WIDTH 14 /* WSEQ_ADDR112 - [13:0] */ - -/* - * R12737 (0x31C1) - Write Sequencer 449 - */ -#define WM8995_WSEQ_DATA112_MASK 0x00FF /* WSEQ_DATA112 - [7:0] */ -#define WM8995_WSEQ_DATA112_SHIFT 0 /* WSEQ_DATA112 - [7:0] */ -#define WM8995_WSEQ_DATA112_WIDTH 8 /* WSEQ_DATA112 - [7:0] */ - -/* - * R12738 (0x31C2) - Write Sequencer 450 - */ -#define WM8995_WSEQ_DATA_WIDTH112_MASK 0x0700 /* WSEQ_DATA_WIDTH112 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH112_SHIFT 8 /* WSEQ_DATA_WIDTH112 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH112_WIDTH 3 /* WSEQ_DATA_WIDTH112 - [10:8] */ -#define WM8995_WSEQ_DATA_START112_MASK 0x000F /* WSEQ_DATA_START112 - [3:0] */ -#define WM8995_WSEQ_DATA_START112_SHIFT 0 /* WSEQ_DATA_START112 - [3:0] */ -#define WM8995_WSEQ_DATA_START112_WIDTH 4 /* WSEQ_DATA_START112 - [3:0] */ - -/* - * R12739 (0x31C3) - Write Sequencer 451 - */ -#define WM8995_WSEQ_EOS112 0x0100 /* WSEQ_EOS112 */ -#define WM8995_WSEQ_EOS112_MASK 0x0100 /* WSEQ_EOS112 */ -#define WM8995_WSEQ_EOS112_SHIFT 8 /* WSEQ_EOS112 */ -#define WM8995_WSEQ_EOS112_WIDTH 1 /* WSEQ_EOS112 */ -#define WM8995_WSEQ_DELAY112_MASK 0x000F /* WSEQ_DELAY112 - [3:0] */ -#define WM8995_WSEQ_DELAY112_SHIFT 0 /* WSEQ_DELAY112 - [3:0] */ -#define WM8995_WSEQ_DELAY112_WIDTH 4 /* WSEQ_DELAY112 - [3:0] */ - -/* - * R12740 (0x31C4) - Write Sequencer 452 - */ -#define WM8995_WSEQ_ADDR113_MASK 0x3FFF /* WSEQ_ADDR113 - [13:0] */ -#define WM8995_WSEQ_ADDR113_SHIFT 0 /* WSEQ_ADDR113 - [13:0] */ -#define WM8995_WSEQ_ADDR113_WIDTH 14 /* WSEQ_ADDR113 - [13:0] */ - -/* - * R12741 (0x31C5) - Write Sequencer 453 - */ -#define WM8995_WSEQ_DATA113_MASK 0x00FF /* WSEQ_DATA113 - [7:0] */ -#define WM8995_WSEQ_DATA113_SHIFT 0 /* WSEQ_DATA113 - [7:0] */ -#define WM8995_WSEQ_DATA113_WIDTH 8 /* WSEQ_DATA113 - [7:0] */ - -/* - * R12742 (0x31C6) - Write Sequencer 454 - */ -#define WM8995_WSEQ_DATA_WIDTH113_MASK 0x0700 /* WSEQ_DATA_WIDTH113 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH113_SHIFT 8 /* WSEQ_DATA_WIDTH113 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH113_WIDTH 3 /* WSEQ_DATA_WIDTH113 - [10:8] */ -#define WM8995_WSEQ_DATA_START113_MASK 0x000F /* WSEQ_DATA_START113 - [3:0] */ -#define WM8995_WSEQ_DATA_START113_SHIFT 0 /* WSEQ_DATA_START113 - [3:0] */ -#define WM8995_WSEQ_DATA_START113_WIDTH 4 /* WSEQ_DATA_START113 - [3:0] */ - -/* - * R12743 (0x31C7) - Write Sequencer 455 - */ -#define WM8995_WSEQ_EOS113 0x0100 /* WSEQ_EOS113 */ -#define WM8995_WSEQ_EOS113_MASK 0x0100 /* WSEQ_EOS113 */ -#define WM8995_WSEQ_EOS113_SHIFT 8 /* WSEQ_EOS113 */ -#define WM8995_WSEQ_EOS113_WIDTH 1 /* WSEQ_EOS113 */ -#define WM8995_WSEQ_DELAY113_MASK 0x000F /* WSEQ_DELAY113 - [3:0] */ -#define WM8995_WSEQ_DELAY113_SHIFT 0 /* WSEQ_DELAY113 - [3:0] */ -#define WM8995_WSEQ_DELAY113_WIDTH 4 /* WSEQ_DELAY113 - [3:0] */ - -/* - * R12744 (0x31C8) - Write Sequencer 456 - */ -#define WM8995_WSEQ_ADDR114_MASK 0x3FFF /* WSEQ_ADDR114 - [13:0] */ -#define WM8995_WSEQ_ADDR114_SHIFT 0 /* WSEQ_ADDR114 - [13:0] */ -#define WM8995_WSEQ_ADDR114_WIDTH 14 /* WSEQ_ADDR114 - [13:0] */ - -/* - * R12745 (0x31C9) - Write Sequencer 457 - */ -#define WM8995_WSEQ_DATA114_MASK 0x00FF /* WSEQ_DATA114 - [7:0] */ -#define WM8995_WSEQ_DATA114_SHIFT 0 /* WSEQ_DATA114 - [7:0] */ -#define WM8995_WSEQ_DATA114_WIDTH 8 /* WSEQ_DATA114 - [7:0] */ - -/* - * R12746 (0x31CA) - Write Sequencer 458 - */ -#define WM8995_WSEQ_DATA_WIDTH114_MASK 0x0700 /* WSEQ_DATA_WIDTH114 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH114_SHIFT 8 /* WSEQ_DATA_WIDTH114 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH114_WIDTH 3 /* WSEQ_DATA_WIDTH114 - [10:8] */ -#define WM8995_WSEQ_DATA_START114_MASK 0x000F /* WSEQ_DATA_START114 - [3:0] */ -#define WM8995_WSEQ_DATA_START114_SHIFT 0 /* WSEQ_DATA_START114 - [3:0] */ -#define WM8995_WSEQ_DATA_START114_WIDTH 4 /* WSEQ_DATA_START114 - [3:0] */ - -/* - * R12747 (0x31CB) - Write Sequencer 459 - */ -#define WM8995_WSEQ_EOS114 0x0100 /* WSEQ_EOS114 */ -#define WM8995_WSEQ_EOS114_MASK 0x0100 /* WSEQ_EOS114 */ -#define WM8995_WSEQ_EOS114_SHIFT 8 /* WSEQ_EOS114 */ -#define WM8995_WSEQ_EOS114_WIDTH 1 /* WSEQ_EOS114 */ -#define WM8995_WSEQ_DELAY114_MASK 0x000F /* WSEQ_DELAY114 - [3:0] */ -#define WM8995_WSEQ_DELAY114_SHIFT 0 /* WSEQ_DELAY114 - [3:0] */ -#define WM8995_WSEQ_DELAY114_WIDTH 4 /* WSEQ_DELAY114 - [3:0] */ - -/* - * R12748 (0x31CC) - Write Sequencer 460 - */ -#define WM8995_WSEQ_ADDR115_MASK 0x3FFF /* WSEQ_ADDR115 - [13:0] */ -#define WM8995_WSEQ_ADDR115_SHIFT 0 /* WSEQ_ADDR115 - [13:0] */ -#define WM8995_WSEQ_ADDR115_WIDTH 14 /* WSEQ_ADDR115 - [13:0] */ - -/* - * R12749 (0x31CD) - Write Sequencer 461 - */ -#define WM8995_WSEQ_DATA115_MASK 0x00FF /* WSEQ_DATA115 - [7:0] */ -#define WM8995_WSEQ_DATA115_SHIFT 0 /* WSEQ_DATA115 - [7:0] */ -#define WM8995_WSEQ_DATA115_WIDTH 8 /* WSEQ_DATA115 - [7:0] */ - -/* - * R12750 (0x31CE) - Write Sequencer 462 - */ -#define WM8995_WSEQ_DATA_WIDTH115_MASK 0x0700 /* WSEQ_DATA_WIDTH115 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH115_SHIFT 8 /* WSEQ_DATA_WIDTH115 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH115_WIDTH 3 /* WSEQ_DATA_WIDTH115 - [10:8] */ -#define WM8995_WSEQ_DATA_START115_MASK 0x000F /* WSEQ_DATA_START115 - [3:0] */ -#define WM8995_WSEQ_DATA_START115_SHIFT 0 /* WSEQ_DATA_START115 - [3:0] */ -#define WM8995_WSEQ_DATA_START115_WIDTH 4 /* WSEQ_DATA_START115 - [3:0] */ - -/* - * R12751 (0x31CF) - Write Sequencer 463 - */ -#define WM8995_WSEQ_EOS115 0x0100 /* WSEQ_EOS115 */ -#define WM8995_WSEQ_EOS115_MASK 0x0100 /* WSEQ_EOS115 */ -#define WM8995_WSEQ_EOS115_SHIFT 8 /* WSEQ_EOS115 */ -#define WM8995_WSEQ_EOS115_WIDTH 1 /* WSEQ_EOS115 */ -#define WM8995_WSEQ_DELAY115_MASK 0x000F /* WSEQ_DELAY115 - [3:0] */ -#define WM8995_WSEQ_DELAY115_SHIFT 0 /* WSEQ_DELAY115 - [3:0] */ -#define WM8995_WSEQ_DELAY115_WIDTH 4 /* WSEQ_DELAY115 - [3:0] */ - -/* - * R12752 (0x31D0) - Write Sequencer 464 - */ -#define WM8995_WSEQ_ADDR116_MASK 0x3FFF /* WSEQ_ADDR116 - [13:0] */ -#define WM8995_WSEQ_ADDR116_SHIFT 0 /* WSEQ_ADDR116 - [13:0] */ -#define WM8995_WSEQ_ADDR116_WIDTH 14 /* WSEQ_ADDR116 - [13:0] */ - -/* - * R12753 (0x31D1) - Write Sequencer 465 - */ -#define WM8995_WSEQ_DATA116_MASK 0x00FF /* WSEQ_DATA116 - [7:0] */ -#define WM8995_WSEQ_DATA116_SHIFT 0 /* WSEQ_DATA116 - [7:0] */ -#define WM8995_WSEQ_DATA116_WIDTH 8 /* WSEQ_DATA116 - [7:0] */ - -/* - * R12754 (0x31D2) - Write Sequencer 466 - */ -#define WM8995_WSEQ_DATA_WIDTH116_MASK 0x0700 /* WSEQ_DATA_WIDTH116 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH116_SHIFT 8 /* WSEQ_DATA_WIDTH116 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH116_WIDTH 3 /* WSEQ_DATA_WIDTH116 - [10:8] */ -#define WM8995_WSEQ_DATA_START116_MASK 0x000F /* WSEQ_DATA_START116 - [3:0] */ -#define WM8995_WSEQ_DATA_START116_SHIFT 0 /* WSEQ_DATA_START116 - [3:0] */ -#define WM8995_WSEQ_DATA_START116_WIDTH 4 /* WSEQ_DATA_START116 - [3:0] */ - -/* - * R12755 (0x31D3) - Write Sequencer 467 - */ -#define WM8995_WSEQ_EOS116 0x0100 /* WSEQ_EOS116 */ -#define WM8995_WSEQ_EOS116_MASK 0x0100 /* WSEQ_EOS116 */ -#define WM8995_WSEQ_EOS116_SHIFT 8 /* WSEQ_EOS116 */ -#define WM8995_WSEQ_EOS116_WIDTH 1 /* WSEQ_EOS116 */ -#define WM8995_WSEQ_DELAY116_MASK 0x000F /* WSEQ_DELAY116 - [3:0] */ -#define WM8995_WSEQ_DELAY116_SHIFT 0 /* WSEQ_DELAY116 - [3:0] */ -#define WM8995_WSEQ_DELAY116_WIDTH 4 /* WSEQ_DELAY116 - [3:0] */ - -/* - * R12756 (0x31D4) - Write Sequencer 468 - */ -#define WM8995_WSEQ_ADDR117_MASK 0x3FFF /* WSEQ_ADDR117 - [13:0] */ -#define WM8995_WSEQ_ADDR117_SHIFT 0 /* WSEQ_ADDR117 - [13:0] */ -#define WM8995_WSEQ_ADDR117_WIDTH 14 /* WSEQ_ADDR117 - [13:0] */ - -/* - * R12757 (0x31D5) - Write Sequencer 469 - */ -#define WM8995_WSEQ_DATA117_MASK 0x00FF /* WSEQ_DATA117 - [7:0] */ -#define WM8995_WSEQ_DATA117_SHIFT 0 /* WSEQ_DATA117 - [7:0] */ -#define WM8995_WSEQ_DATA117_WIDTH 8 /* WSEQ_DATA117 - [7:0] */ - -/* - * R12758 (0x31D6) - Write Sequencer 470 - */ -#define WM8995_WSEQ_DATA_WIDTH117_MASK 0x0700 /* WSEQ_DATA_WIDTH117 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH117_SHIFT 8 /* WSEQ_DATA_WIDTH117 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH117_WIDTH 3 /* WSEQ_DATA_WIDTH117 - [10:8] */ -#define WM8995_WSEQ_DATA_START117_MASK 0x000F /* WSEQ_DATA_START117 - [3:0] */ -#define WM8995_WSEQ_DATA_START117_SHIFT 0 /* WSEQ_DATA_START117 - [3:0] */ -#define WM8995_WSEQ_DATA_START117_WIDTH 4 /* WSEQ_DATA_START117 - [3:0] */ - -/* - * R12759 (0x31D7) - Write Sequencer 471 - */ -#define WM8995_WSEQ_EOS117 0x0100 /* WSEQ_EOS117 */ -#define WM8995_WSEQ_EOS117_MASK 0x0100 /* WSEQ_EOS117 */ -#define WM8995_WSEQ_EOS117_SHIFT 8 /* WSEQ_EOS117 */ -#define WM8995_WSEQ_EOS117_WIDTH 1 /* WSEQ_EOS117 */ -#define WM8995_WSEQ_DELAY117_MASK 0x000F /* WSEQ_DELAY117 - [3:0] */ -#define WM8995_WSEQ_DELAY117_SHIFT 0 /* WSEQ_DELAY117 - [3:0] */ -#define WM8995_WSEQ_DELAY117_WIDTH 4 /* WSEQ_DELAY117 - [3:0] */ - -/* - * R12760 (0x31D8) - Write Sequencer 472 - */ -#define WM8995_WSEQ_ADDR118_MASK 0x3FFF /* WSEQ_ADDR118 - [13:0] */ -#define WM8995_WSEQ_ADDR118_SHIFT 0 /* WSEQ_ADDR118 - [13:0] */ -#define WM8995_WSEQ_ADDR118_WIDTH 14 /* WSEQ_ADDR118 - [13:0] */ - -/* - * R12761 (0x31D9) - Write Sequencer 473 - */ -#define WM8995_WSEQ_DATA118_MASK 0x00FF /* WSEQ_DATA118 - [7:0] */ -#define WM8995_WSEQ_DATA118_SHIFT 0 /* WSEQ_DATA118 - [7:0] */ -#define WM8995_WSEQ_DATA118_WIDTH 8 /* WSEQ_DATA118 - [7:0] */ - -/* - * R12762 (0x31DA) - Write Sequencer 474 - */ -#define WM8995_WSEQ_DATA_WIDTH118_MASK 0x0700 /* WSEQ_DATA_WIDTH118 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH118_SHIFT 8 /* WSEQ_DATA_WIDTH118 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH118_WIDTH 3 /* WSEQ_DATA_WIDTH118 - [10:8] */ -#define WM8995_WSEQ_DATA_START118_MASK 0x000F /* WSEQ_DATA_START118 - [3:0] */ -#define WM8995_WSEQ_DATA_START118_SHIFT 0 /* WSEQ_DATA_START118 - [3:0] */ -#define WM8995_WSEQ_DATA_START118_WIDTH 4 /* WSEQ_DATA_START118 - [3:0] */ - -/* - * R12763 (0x31DB) - Write Sequencer 475 - */ -#define WM8995_WSEQ_EOS118 0x0100 /* WSEQ_EOS118 */ -#define WM8995_WSEQ_EOS118_MASK 0x0100 /* WSEQ_EOS118 */ -#define WM8995_WSEQ_EOS118_SHIFT 8 /* WSEQ_EOS118 */ -#define WM8995_WSEQ_EOS118_WIDTH 1 /* WSEQ_EOS118 */ -#define WM8995_WSEQ_DELAY118_MASK 0x000F /* WSEQ_DELAY118 - [3:0] */ -#define WM8995_WSEQ_DELAY118_SHIFT 0 /* WSEQ_DELAY118 - [3:0] */ -#define WM8995_WSEQ_DELAY118_WIDTH 4 /* WSEQ_DELAY118 - [3:0] */ - -/* - * R12764 (0x31DC) - Write Sequencer 476 - */ -#define WM8995_WSEQ_ADDR119_MASK 0x3FFF /* WSEQ_ADDR119 - [13:0] */ -#define WM8995_WSEQ_ADDR119_SHIFT 0 /* WSEQ_ADDR119 - [13:0] */ -#define WM8995_WSEQ_ADDR119_WIDTH 14 /* WSEQ_ADDR119 - [13:0] */ - -/* - * R12765 (0x31DD) - Write Sequencer 477 - */ -#define WM8995_WSEQ_DATA119_MASK 0x00FF /* WSEQ_DATA119 - [7:0] */ -#define WM8995_WSEQ_DATA119_SHIFT 0 /* WSEQ_DATA119 - [7:0] */ -#define WM8995_WSEQ_DATA119_WIDTH 8 /* WSEQ_DATA119 - [7:0] */ - -/* - * R12766 (0x31DE) - Write Sequencer 478 - */ -#define WM8995_WSEQ_DATA_WIDTH119_MASK 0x0700 /* WSEQ_DATA_WIDTH119 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH119_SHIFT 8 /* WSEQ_DATA_WIDTH119 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH119_WIDTH 3 /* WSEQ_DATA_WIDTH119 - [10:8] */ -#define WM8995_WSEQ_DATA_START119_MASK 0x000F /* WSEQ_DATA_START119 - [3:0] */ -#define WM8995_WSEQ_DATA_START119_SHIFT 0 /* WSEQ_DATA_START119 - [3:0] */ -#define WM8995_WSEQ_DATA_START119_WIDTH 4 /* WSEQ_DATA_START119 - [3:0] */ - -/* - * R12767 (0x31DF) - Write Sequencer 479 - */ -#define WM8995_WSEQ_EOS119 0x0100 /* WSEQ_EOS119 */ -#define WM8995_WSEQ_EOS119_MASK 0x0100 /* WSEQ_EOS119 */ -#define WM8995_WSEQ_EOS119_SHIFT 8 /* WSEQ_EOS119 */ -#define WM8995_WSEQ_EOS119_WIDTH 1 /* WSEQ_EOS119 */ -#define WM8995_WSEQ_DELAY119_MASK 0x000F /* WSEQ_DELAY119 - [3:0] */ -#define WM8995_WSEQ_DELAY119_SHIFT 0 /* WSEQ_DELAY119 - [3:0] */ -#define WM8995_WSEQ_DELAY119_WIDTH 4 /* WSEQ_DELAY119 - [3:0] */ - -/* - * R12768 (0x31E0) - Write Sequencer 480 - */ -#define WM8995_WSEQ_ADDR120_MASK 0x3FFF /* WSEQ_ADDR120 - [13:0] */ -#define WM8995_WSEQ_ADDR120_SHIFT 0 /* WSEQ_ADDR120 - [13:0] */ -#define WM8995_WSEQ_ADDR120_WIDTH 14 /* WSEQ_ADDR120 - [13:0] */ - -/* - * R12769 (0x31E1) - Write Sequencer 481 - */ -#define WM8995_WSEQ_DATA120_MASK 0x00FF /* WSEQ_DATA120 - [7:0] */ -#define WM8995_WSEQ_DATA120_SHIFT 0 /* WSEQ_DATA120 - [7:0] */ -#define WM8995_WSEQ_DATA120_WIDTH 8 /* WSEQ_DATA120 - [7:0] */ - -/* - * R12770 (0x31E2) - Write Sequencer 482 - */ -#define WM8995_WSEQ_DATA_WIDTH120_MASK 0x0700 /* WSEQ_DATA_WIDTH120 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH120_SHIFT 8 /* WSEQ_DATA_WIDTH120 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH120_WIDTH 3 /* WSEQ_DATA_WIDTH120 - [10:8] */ -#define WM8995_WSEQ_DATA_START120_MASK 0x000F /* WSEQ_DATA_START120 - [3:0] */ -#define WM8995_WSEQ_DATA_START120_SHIFT 0 /* WSEQ_DATA_START120 - [3:0] */ -#define WM8995_WSEQ_DATA_START120_WIDTH 4 /* WSEQ_DATA_START120 - [3:0] */ - -/* - * R12771 (0x31E3) - Write Sequencer 483 - */ -#define WM8995_WSEQ_EOS120 0x0100 /* WSEQ_EOS120 */ -#define WM8995_WSEQ_EOS120_MASK 0x0100 /* WSEQ_EOS120 */ -#define WM8995_WSEQ_EOS120_SHIFT 8 /* WSEQ_EOS120 */ -#define WM8995_WSEQ_EOS120_WIDTH 1 /* WSEQ_EOS120 */ -#define WM8995_WSEQ_DELAY120_MASK 0x000F /* WSEQ_DELAY120 - [3:0] */ -#define WM8995_WSEQ_DELAY120_SHIFT 0 /* WSEQ_DELAY120 - [3:0] */ -#define WM8995_WSEQ_DELAY120_WIDTH 4 /* WSEQ_DELAY120 - [3:0] */ - -/* - * R12772 (0x31E4) - Write Sequencer 484 - */ -#define WM8995_WSEQ_ADDR121_MASK 0x3FFF /* WSEQ_ADDR121 - [13:0] */ -#define WM8995_WSEQ_ADDR121_SHIFT 0 /* WSEQ_ADDR121 - [13:0] */ -#define WM8995_WSEQ_ADDR121_WIDTH 14 /* WSEQ_ADDR121 - [13:0] */ - -/* - * R12773 (0x31E5) - Write Sequencer 485 - */ -#define WM8995_WSEQ_DATA121_MASK 0x00FF /* WSEQ_DATA121 - [7:0] */ -#define WM8995_WSEQ_DATA121_SHIFT 0 /* WSEQ_DATA121 - [7:0] */ -#define WM8995_WSEQ_DATA121_WIDTH 8 /* WSEQ_DATA121 - [7:0] */ - -/* - * R12774 (0x31E6) - Write Sequencer 486 - */ -#define WM8995_WSEQ_DATA_WIDTH121_MASK 0x0700 /* WSEQ_DATA_WIDTH121 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH121_SHIFT 8 /* WSEQ_DATA_WIDTH121 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH121_WIDTH 3 /* WSEQ_DATA_WIDTH121 - [10:8] */ -#define WM8995_WSEQ_DATA_START121_MASK 0x000F /* WSEQ_DATA_START121 - [3:0] */ -#define WM8995_WSEQ_DATA_START121_SHIFT 0 /* WSEQ_DATA_START121 - [3:0] */ -#define WM8995_WSEQ_DATA_START121_WIDTH 4 /* WSEQ_DATA_START121 - [3:0] */ - -/* - * R12775 (0x31E7) - Write Sequencer 487 - */ -#define WM8995_WSEQ_EOS121 0x0100 /* WSEQ_EOS121 */ -#define WM8995_WSEQ_EOS121_MASK 0x0100 /* WSEQ_EOS121 */ -#define WM8995_WSEQ_EOS121_SHIFT 8 /* WSEQ_EOS121 */ -#define WM8995_WSEQ_EOS121_WIDTH 1 /* WSEQ_EOS121 */ -#define WM8995_WSEQ_DELAY121_MASK 0x000F /* WSEQ_DELAY121 - [3:0] */ -#define WM8995_WSEQ_DELAY121_SHIFT 0 /* WSEQ_DELAY121 - [3:0] */ -#define WM8995_WSEQ_DELAY121_WIDTH 4 /* WSEQ_DELAY121 - [3:0] */ - -/* - * R12776 (0x31E8) - Write Sequencer 488 - */ -#define WM8995_WSEQ_ADDR122_MASK 0x3FFF /* WSEQ_ADDR122 - [13:0] */ -#define WM8995_WSEQ_ADDR122_SHIFT 0 /* WSEQ_ADDR122 - [13:0] */ -#define WM8995_WSEQ_ADDR122_WIDTH 14 /* WSEQ_ADDR122 - [13:0] */ - -/* - * R12777 (0x31E9) - Write Sequencer 489 - */ -#define WM8995_WSEQ_DATA122_MASK 0x00FF /* WSEQ_DATA122 - [7:0] */ -#define WM8995_WSEQ_DATA122_SHIFT 0 /* WSEQ_DATA122 - [7:0] */ -#define WM8995_WSEQ_DATA122_WIDTH 8 /* WSEQ_DATA122 - [7:0] */ - -/* - * R12778 (0x31EA) - Write Sequencer 490 - */ -#define WM8995_WSEQ_DATA_WIDTH122_MASK 0x0700 /* WSEQ_DATA_WIDTH122 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH122_SHIFT 8 /* WSEQ_DATA_WIDTH122 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH122_WIDTH 3 /* WSEQ_DATA_WIDTH122 - [10:8] */ -#define WM8995_WSEQ_DATA_START122_MASK 0x000F /* WSEQ_DATA_START122 - [3:0] */ -#define WM8995_WSEQ_DATA_START122_SHIFT 0 /* WSEQ_DATA_START122 - [3:0] */ -#define WM8995_WSEQ_DATA_START122_WIDTH 4 /* WSEQ_DATA_START122 - [3:0] */ - -/* - * R12779 (0x31EB) - Write Sequencer 491 - */ -#define WM8995_WSEQ_EOS122 0x0100 /* WSEQ_EOS122 */ -#define WM8995_WSEQ_EOS122_MASK 0x0100 /* WSEQ_EOS122 */ -#define WM8995_WSEQ_EOS122_SHIFT 8 /* WSEQ_EOS122 */ -#define WM8995_WSEQ_EOS122_WIDTH 1 /* WSEQ_EOS122 */ -#define WM8995_WSEQ_DELAY122_MASK 0x000F /* WSEQ_DELAY122 - [3:0] */ -#define WM8995_WSEQ_DELAY122_SHIFT 0 /* WSEQ_DELAY122 - [3:0] */ -#define WM8995_WSEQ_DELAY122_WIDTH 4 /* WSEQ_DELAY122 - [3:0] */ - -/* - * R12780 (0x31EC) - Write Sequencer 492 - */ -#define WM8995_WSEQ_ADDR123_MASK 0x3FFF /* WSEQ_ADDR123 - [13:0] */ -#define WM8995_WSEQ_ADDR123_SHIFT 0 /* WSEQ_ADDR123 - [13:0] */ -#define WM8995_WSEQ_ADDR123_WIDTH 14 /* WSEQ_ADDR123 - [13:0] */ - -/* - * R12781 (0x31ED) - Write Sequencer 493 - */ -#define WM8995_WSEQ_DATA123_MASK 0x00FF /* WSEQ_DATA123 - [7:0] */ -#define WM8995_WSEQ_DATA123_SHIFT 0 /* WSEQ_DATA123 - [7:0] */ -#define WM8995_WSEQ_DATA123_WIDTH 8 /* WSEQ_DATA123 - [7:0] */ - -/* - * R12782 (0x31EE) - Write Sequencer 494 - */ -#define WM8995_WSEQ_DATA_WIDTH123_MASK 0x0700 /* WSEQ_DATA_WIDTH123 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH123_SHIFT 8 /* WSEQ_DATA_WIDTH123 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH123_WIDTH 3 /* WSEQ_DATA_WIDTH123 - [10:8] */ -#define WM8995_WSEQ_DATA_START123_MASK 0x000F /* WSEQ_DATA_START123 - [3:0] */ -#define WM8995_WSEQ_DATA_START123_SHIFT 0 /* WSEQ_DATA_START123 - [3:0] */ -#define WM8995_WSEQ_DATA_START123_WIDTH 4 /* WSEQ_DATA_START123 - [3:0] */ - -/* - * R12783 (0x31EF) - Write Sequencer 495 - */ -#define WM8995_WSEQ_EOS123 0x0100 /* WSEQ_EOS123 */ -#define WM8995_WSEQ_EOS123_MASK 0x0100 /* WSEQ_EOS123 */ -#define WM8995_WSEQ_EOS123_SHIFT 8 /* WSEQ_EOS123 */ -#define WM8995_WSEQ_EOS123_WIDTH 1 /* WSEQ_EOS123 */ -#define WM8995_WSEQ_DELAY123_MASK 0x000F /* WSEQ_DELAY123 - [3:0] */ -#define WM8995_WSEQ_DELAY123_SHIFT 0 /* WSEQ_DELAY123 - [3:0] */ -#define WM8995_WSEQ_DELAY123_WIDTH 4 /* WSEQ_DELAY123 - [3:0] */ - -/* - * R12784 (0x31F0) - Write Sequencer 496 - */ -#define WM8995_WSEQ_ADDR124_MASK 0x3FFF /* WSEQ_ADDR124 - [13:0] */ -#define WM8995_WSEQ_ADDR124_SHIFT 0 /* WSEQ_ADDR124 - [13:0] */ -#define WM8995_WSEQ_ADDR124_WIDTH 14 /* WSEQ_ADDR124 - [13:0] */ - -/* - * R12785 (0x31F1) - Write Sequencer 497 - */ -#define WM8995_WSEQ_DATA124_MASK 0x00FF /* WSEQ_DATA124 - [7:0] */ -#define WM8995_WSEQ_DATA124_SHIFT 0 /* WSEQ_DATA124 - [7:0] */ -#define WM8995_WSEQ_DATA124_WIDTH 8 /* WSEQ_DATA124 - [7:0] */ - -/* - * R12786 (0x31F2) - Write Sequencer 498 - */ -#define WM8995_WSEQ_DATA_WIDTH124_MASK 0x0700 /* WSEQ_DATA_WIDTH124 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH124_SHIFT 8 /* WSEQ_DATA_WIDTH124 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH124_WIDTH 3 /* WSEQ_DATA_WIDTH124 - [10:8] */ -#define WM8995_WSEQ_DATA_START124_MASK 0x000F /* WSEQ_DATA_START124 - [3:0] */ -#define WM8995_WSEQ_DATA_START124_SHIFT 0 /* WSEQ_DATA_START124 - [3:0] */ -#define WM8995_WSEQ_DATA_START124_WIDTH 4 /* WSEQ_DATA_START124 - [3:0] */ - -/* - * R12787 (0x31F3) - Write Sequencer 499 - */ -#define WM8995_WSEQ_EOS124 0x0100 /* WSEQ_EOS124 */ -#define WM8995_WSEQ_EOS124_MASK 0x0100 /* WSEQ_EOS124 */ -#define WM8995_WSEQ_EOS124_SHIFT 8 /* WSEQ_EOS124 */ -#define WM8995_WSEQ_EOS124_WIDTH 1 /* WSEQ_EOS124 */ -#define WM8995_WSEQ_DELAY124_MASK 0x000F /* WSEQ_DELAY124 - [3:0] */ -#define WM8995_WSEQ_DELAY124_SHIFT 0 /* WSEQ_DELAY124 - [3:0] */ -#define WM8995_WSEQ_DELAY124_WIDTH 4 /* WSEQ_DELAY124 - [3:0] */ - -/* - * R12788 (0x31F4) - Write Sequencer 500 - */ -#define WM8995_WSEQ_ADDR125_MASK 0x3FFF /* WSEQ_ADDR125 - [13:0] */ -#define WM8995_WSEQ_ADDR125_SHIFT 0 /* WSEQ_ADDR125 - [13:0] */ -#define WM8995_WSEQ_ADDR125_WIDTH 14 /* WSEQ_ADDR125 - [13:0] */ - -/* - * R12789 (0x31F5) - Write Sequencer 501 - */ -#define WM8995_WSEQ_DATA125_MASK 0x00FF /* WSEQ_DATA125 - [7:0] */ -#define WM8995_WSEQ_DATA125_SHIFT 0 /* WSEQ_DATA125 - [7:0] */ -#define WM8995_WSEQ_DATA125_WIDTH 8 /* WSEQ_DATA125 - [7:0] */ - -/* - * R12790 (0x31F6) - Write Sequencer 502 - */ -#define WM8995_WSEQ_DATA_WIDTH125_MASK 0x0700 /* WSEQ_DATA_WIDTH125 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH125_SHIFT 8 /* WSEQ_DATA_WIDTH125 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH125_WIDTH 3 /* WSEQ_DATA_WIDTH125 - [10:8] */ -#define WM8995_WSEQ_DATA_START125_MASK 0x000F /* WSEQ_DATA_START125 - [3:0] */ -#define WM8995_WSEQ_DATA_START125_SHIFT 0 /* WSEQ_DATA_START125 - [3:0] */ -#define WM8995_WSEQ_DATA_START125_WIDTH 4 /* WSEQ_DATA_START125 - [3:0] */ - -/* - * R12791 (0x31F7) - Write Sequencer 503 - */ -#define WM8995_WSEQ_EOS125 0x0100 /* WSEQ_EOS125 */ -#define WM8995_WSEQ_EOS125_MASK 0x0100 /* WSEQ_EOS125 */ -#define WM8995_WSEQ_EOS125_SHIFT 8 /* WSEQ_EOS125 */ -#define WM8995_WSEQ_EOS125_WIDTH 1 /* WSEQ_EOS125 */ -#define WM8995_WSEQ_DELAY125_MASK 0x000F /* WSEQ_DELAY125 - [3:0] */ -#define WM8995_WSEQ_DELAY125_SHIFT 0 /* WSEQ_DELAY125 - [3:0] */ -#define WM8995_WSEQ_DELAY125_WIDTH 4 /* WSEQ_DELAY125 - [3:0] */ - -/* - * R12792 (0x31F8) - Write Sequencer 504 - */ -#define WM8995_WSEQ_ADDR126_MASK 0x3FFF /* WSEQ_ADDR126 - [13:0] */ -#define WM8995_WSEQ_ADDR126_SHIFT 0 /* WSEQ_ADDR126 - [13:0] */ -#define WM8995_WSEQ_ADDR126_WIDTH 14 /* WSEQ_ADDR126 - [13:0] */ - -/* - * R12793 (0x31F9) - Write Sequencer 505 - */ -#define WM8995_WSEQ_DATA126_MASK 0x00FF /* WSEQ_DATA126 - [7:0] */ -#define WM8995_WSEQ_DATA126_SHIFT 0 /* WSEQ_DATA126 - [7:0] */ -#define WM8995_WSEQ_DATA126_WIDTH 8 /* WSEQ_DATA126 - [7:0] */ - -/* - * R12794 (0x31FA) - Write Sequencer 506 - */ -#define WM8995_WSEQ_DATA_WIDTH126_MASK 0x0700 /* WSEQ_DATA_WIDTH126 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH126_SHIFT 8 /* WSEQ_DATA_WIDTH126 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH126_WIDTH 3 /* WSEQ_DATA_WIDTH126 - [10:8] */ -#define WM8995_WSEQ_DATA_START126_MASK 0x000F /* WSEQ_DATA_START126 - [3:0] */ -#define WM8995_WSEQ_DATA_START126_SHIFT 0 /* WSEQ_DATA_START126 - [3:0] */ -#define WM8995_WSEQ_DATA_START126_WIDTH 4 /* WSEQ_DATA_START126 - [3:0] */ - -/* - * R12795 (0x31FB) - Write Sequencer 507 - */ -#define WM8995_WSEQ_EOS126 0x0100 /* WSEQ_EOS126 */ -#define WM8995_WSEQ_EOS126_MASK 0x0100 /* WSEQ_EOS126 */ -#define WM8995_WSEQ_EOS126_SHIFT 8 /* WSEQ_EOS126 */ -#define WM8995_WSEQ_EOS126_WIDTH 1 /* WSEQ_EOS126 */ -#define WM8995_WSEQ_DELAY126_MASK 0x000F /* WSEQ_DELAY126 - [3:0] */ -#define WM8995_WSEQ_DELAY126_SHIFT 0 /* WSEQ_DELAY126 - [3:0] */ -#define WM8995_WSEQ_DELAY126_WIDTH 4 /* WSEQ_DELAY126 - [3:0] */ - -/* - * R12796 (0x31FC) - Write Sequencer 508 - */ -#define WM8995_WSEQ_ADDR127_MASK 0x3FFF /* WSEQ_ADDR127 - [13:0] */ -#define WM8995_WSEQ_ADDR127_SHIFT 0 /* WSEQ_ADDR127 - [13:0] */ -#define WM8995_WSEQ_ADDR127_WIDTH 14 /* WSEQ_ADDR127 - [13:0] */ - -/* - * R12797 (0x31FD) - Write Sequencer 509 - */ -#define WM8995_WSEQ_DATA127_MASK 0x00FF /* WSEQ_DATA127 - [7:0] */ -#define WM8995_WSEQ_DATA127_SHIFT 0 /* WSEQ_DATA127 - [7:0] */ -#define WM8995_WSEQ_DATA127_WIDTH 8 /* WSEQ_DATA127 - [7:0] */ - -/* - * R12798 (0x31FE) - Write Sequencer 510 - */ -#define WM8995_WSEQ_DATA_WIDTH127_MASK 0x0700 /* WSEQ_DATA_WIDTH127 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH127_SHIFT 8 /* WSEQ_DATA_WIDTH127 - [10:8] */ -#define WM8995_WSEQ_DATA_WIDTH127_WIDTH 3 /* WSEQ_DATA_WIDTH127 - [10:8] */ -#define WM8995_WSEQ_DATA_START127_MASK 0x000F /* WSEQ_DATA_START127 - [3:0] */ -#define WM8995_WSEQ_DATA_START127_SHIFT 0 /* WSEQ_DATA_START127 - [3:0] */ -#define WM8995_WSEQ_DATA_START127_WIDTH 4 /* WSEQ_DATA_START127 - [3:0] */ - -/* - * R12799 (0x31FF) - Write Sequencer 511 - */ -#define WM8995_WSEQ_EOS127 0x0100 /* WSEQ_EOS127 */ -#define WM8995_WSEQ_EOS127_MASK 0x0100 /* WSEQ_EOS127 */ -#define WM8995_WSEQ_EOS127_SHIFT 8 /* WSEQ_EOS127 */ -#define WM8995_WSEQ_EOS127_WIDTH 1 /* WSEQ_EOS127 */ -#define WM8995_WSEQ_DELAY127_MASK 0x000F /* WSEQ_DELAY127 - [3:0] */ -#define WM8995_WSEQ_DELAY127_SHIFT 0 /* WSEQ_DELAY127 - [3:0] */ -#define WM8995_WSEQ_DELAY127_WIDTH 4 /* WSEQ_DELAY127 - [3:0] */ - #define WM8995_CLASS_W_SWITCH(xname, reg, shift, max, invert) \ { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ .info = snd_soc_info_volsw, \ -- cgit v1.2.2 From 3f1c63261b7ff81bffd7d4ac6b933c9d0e4c4f94 Mon Sep 17 00:00:00 2001 From: Mark Brown Date: Mon, 27 Dec 2010 15:30:45 +0000 Subject: ASoC: Fix typo in x86 workaround Signed-off-by: Mark Brown --- sound/soc/codecs/wm8962.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'sound/soc/codecs') diff --git a/sound/soc/codecs/wm8962.c b/sound/soc/codecs/wm8962.c index b311b465c4d8..e2177144b714 100644 --- a/sound/soc/codecs/wm8962.c +++ b/sound/soc/codecs/wm8962.c @@ -3354,7 +3354,7 @@ static irqreturn_t wm8962_irq(int irq, void *data) if (active & (WM8962_MICSCD_EINT | WM8962_MICD_EINT)) { dev_dbg(codec->dev, "Microphone event detected\n"); -#ifndef CONFIG_SOUND_SOC_WM862_MODULE +#ifndef CONFIG_SOUND_SOC_WM8962_MODULE trace_snd_soc_jack_irq(dev_name(codec->dev)); #endif -- cgit v1.2.2 From 8b08c0fe95060bba87e98ae6308b90441698a878 Mon Sep 17 00:00:00 2001 From: Mark Brown Date: Fri, 24 Dec 2010 16:59:36 +0000 Subject: ASoC: Fix double comment start Signed-off-by: Mark Brown --- sound/soc/codecs/wm8903.h | 2 -- 1 file changed, 2 deletions(-) (limited to 'sound/soc/codecs') diff --git a/sound/soc/codecs/wm8903.h b/sound/soc/codecs/wm8903.h index 5f23d3ca45f8..e8490f3edd03 100644 --- a/sound/soc/codecs/wm8903.h +++ b/sound/soc/codecs/wm8903.h @@ -1199,8 +1199,6 @@ extern int wm8903_mic_detect(struct snd_soc_codec *codec, #define WM8903_IRQ_POL_SHIFT 0 /* IRQ_POL */ #define WM8903_IRQ_POL_WIDTH 1 /* IRQ_POL */ -/* - /* * R164 (0xA4) - Clock Rate Test 4 */ -- cgit v1.2.2 From 6dc47e97a064c4fc0e324fc4accc90415c1509b2 Mon Sep 17 00:00:00 2001 From: Mark Brown Date: Tue, 28 Dec 2010 02:14:25 +0000 Subject: ASoC: One more x86 typo fix Signed-off-by: Mark Brown --- sound/soc/codecs/wm8962.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'sound/soc/codecs') diff --git a/sound/soc/codecs/wm8962.c b/sound/soc/codecs/wm8962.c index e2177144b714..aa1192f6aa9c 100644 --- a/sound/soc/codecs/wm8962.c +++ b/sound/soc/codecs/wm8962.c @@ -3354,7 +3354,7 @@ static irqreturn_t wm8962_irq(int irq, void *data) if (active & (WM8962_MICSCD_EINT | WM8962_MICD_EINT)) { dev_dbg(codec->dev, "Microphone event detected\n"); -#ifndef CONFIG_SOUND_SOC_WM8962_MODULE +#ifndef CONFIG_SND_SOC_WM8962_MODULE trace_snd_soc_jack_irq(dev_name(codec->dev)); #endif -- cgit v1.2.2 From 839d271c509b6ce5c1da8a8e89fad73a1af0ddda Mon Sep 17 00:00:00 2001 From: Lars-Peter Clausen Date: Tue, 28 Dec 2010 21:37:55 +0100 Subject: ASoC: codecs: Remove unused reg_cache fields from device structs The multi-component patch(commit f0fba2ad1) moved the allocation of the register cache from the driver to the ASoC core. Most drivers where adjusted to this, but there are quite a few drivers left which now have an unused reg_cache field in their private device struct. This patch removes these unused fields. Signed-off-by: Lars-Peter Clausen Signed-off-by: Mark Brown --- sound/soc/codecs/88pm860x-codec.c | 1 - sound/soc/codecs/ad193x.c | 1 - sound/soc/codecs/ak4671.c | 1 - sound/soc/codecs/cs4270.c | 1 - sound/soc/codecs/cs42l51.c | 1 - sound/soc/codecs/cx20442.c | 1 - sound/soc/codecs/tlv320aic26.c | 4 +--- sound/soc/codecs/uda1380.c | 1 - sound/soc/codecs/wm8580.c | 1 - sound/soc/codecs/wm8711.c | 1 - sound/soc/codecs/wm8731.c | 1 - sound/soc/codecs/wm8750.c | 1 - sound/soc/codecs/wm8900.c | 1 - sound/soc/codecs/wm8903.c | 2 -- sound/soc/codecs/wm8940.c | 1 - sound/soc/codecs/wm8960.c | 1 - sound/soc/codecs/wm8961.c | 1 - sound/soc/codecs/wm8974.c | 1 - sound/soc/codecs/wm8978.c | 1 - sound/soc/codecs/wm8988.c | 1 - sound/soc/codecs/wm8993.c | 1 - sound/soc/codecs/wm9081.c | 1 - 22 files changed, 1 insertion(+), 25 deletions(-) (limited to 'sound/soc/codecs') diff --git a/sound/soc/codecs/88pm860x-codec.c b/sound/soc/codecs/88pm860x-codec.c index 3e798a12ee3d..5da8207a6961 100644 --- a/sound/soc/codecs/88pm860x-codec.c +++ b/sound/soc/codecs/88pm860x-codec.c @@ -146,7 +146,6 @@ struct pm860x_priv { int irq[4]; unsigned char name[4][MAX_NAME_LEN]; - unsigned char reg_cache[REG_CACHE_SIZE]; }; /* -9450dB to 0dB in 150dB steps ( mute instead of -9450dB) */ diff --git a/sound/soc/codecs/ad193x.c b/sound/soc/codecs/ad193x.c index a007bd7326fd..da46479bfcfa 100644 --- a/sound/soc/codecs/ad193x.c +++ b/sound/soc/codecs/ad193x.c @@ -23,7 +23,6 @@ /* codec private data */ struct ad193x_priv { - u8 reg_cache[AD193X_NUM_REGS]; enum snd_soc_control_type bus_type; void *control_data; int sysclk; diff --git a/sound/soc/codecs/ak4671.c b/sound/soc/codecs/ak4671.c index 4faf10553a30..2ec75abfa3e9 100644 --- a/sound/soc/codecs/ak4671.c +++ b/sound/soc/codecs/ak4671.c @@ -27,7 +27,6 @@ struct ak4671_priv { enum snd_soc_control_type control_type; void *control_data; - u8 reg_cache[AK4671_CACHEREGNUM]; }; /* ak4671 register cache & default register settings */ diff --git a/sound/soc/codecs/cs4270.c b/sound/soc/codecs/cs4270.c index 6d4bdc609ac8..3a582caa6ef9 100644 --- a/sound/soc/codecs/cs4270.c +++ b/sound/soc/codecs/cs4270.c @@ -114,7 +114,6 @@ static const char *supply_names[] = { struct cs4270_private { enum snd_soc_control_type control_type; void *control_data; - u8 reg_cache[CS4270_NUMREGS]; unsigned int mclk; /* Input frequency of the MCLK pin */ unsigned int mode; /* The mode (I2S or left-justified) */ unsigned int slave_mode; diff --git a/sound/soc/codecs/cs42l51.c b/sound/soc/codecs/cs42l51.c index d4e60dc45bf6..8fb7070108dd 100644 --- a/sound/soc/codecs/cs42l51.c +++ b/sound/soc/codecs/cs42l51.c @@ -46,7 +46,6 @@ struct cs42l51_private { unsigned int mclk; unsigned int audio_mode; /* The mode (I2S or left-justified) */ enum master_slave_mode func; - u8 reg_cache[CS42L51_NUMREGS]; }; #define CS42L51_FORMATS ( \ diff --git a/sound/soc/codecs/cx20442.c b/sound/soc/codecs/cx20442.c index a9521acad99c..03d1e860d229 100644 --- a/sound/soc/codecs/cx20442.c +++ b/sound/soc/codecs/cx20442.c @@ -26,7 +26,6 @@ struct cx20442_priv { enum snd_soc_control_type control_type; void *control_data; - u8 reg_cache[1]; }; #define CX20442_PM 0x0 diff --git a/sound/soc/codecs/tlv320aic26.c b/sound/soc/codecs/tlv320aic26.c index 68f0ae47f608..e2a7608d3944 100644 --- a/sound/soc/codecs/tlv320aic26.c +++ b/sound/soc/codecs/tlv320aic26.c @@ -30,7 +30,6 @@ MODULE_LICENSE("GPL"); struct aic26 { struct spi_device *spi; struct snd_soc_codec codec; - u16 reg_cache[AIC26_NUM_REGS]; /* shadow registers */ int master; int datfm; int mclk; @@ -354,7 +353,6 @@ static DEVICE_ATTR(keyclick, 0644, aic26_keyclick_show, aic26_keyclick_set); */ static int aic26_probe(struct snd_soc_codec *codec) { - struct aic26 *aic26 = snd_soc_codec_get_drvdata(codec); int ret, err, i, reg; dev_info(codec->dev, "Probing AIC26 SoC CODEC driver\n"); @@ -372,7 +370,7 @@ static int aic26_probe(struct snd_soc_codec *codec) aic26_reg_write(codec, AIC26_REG_AUDIO_CTRL3, reg); /* Fill register cache */ - for (i = 0; i < ARRAY_SIZE(aic26->reg_cache); i++) + for (i = 0; i < codec->driver->reg_cache_size; i++) aic26_reg_read(codec, i); /* Register the sysfs files for debugging */ diff --git a/sound/soc/codecs/uda1380.c b/sound/soc/codecs/uda1380.c index 800980e2e9ab..c5ca8cfea60f 100644 --- a/sound/soc/codecs/uda1380.c +++ b/sound/soc/codecs/uda1380.c @@ -35,7 +35,6 @@ /* codec private data */ struct uda1380_priv { struct snd_soc_codec *codec; - u16 reg_cache[UDA1380_CACHEREGNUM]; unsigned int dac_clk; struct work_struct work; void *control_data; diff --git a/sound/soc/codecs/wm8580.c b/sound/soc/codecs/wm8580.c index 0ebdecfd27a9..8f6b5ee6645b 100644 --- a/sound/soc/codecs/wm8580.c +++ b/sound/soc/codecs/wm8580.c @@ -190,7 +190,6 @@ static const char *wm8580_supply_names[WM8580_NUM_SUPPLIES] = { struct wm8580_priv { enum snd_soc_control_type control_type; struct regulator_bulk_data supplies[WM8580_NUM_SUPPLIES]; - u16 reg_cache[WM8580_MAX_REGISTER + 1]; struct pll_state a; struct pll_state b; int sysclk[2]; diff --git a/sound/soc/codecs/wm8711.c b/sound/soc/codecs/wm8711.c index fec37ebfdb34..97c30382d3ff 100644 --- a/sound/soc/codecs/wm8711.c +++ b/sound/soc/codecs/wm8711.c @@ -33,7 +33,6 @@ /* codec private data */ struct wm8711_priv { enum snd_soc_control_type bus_type; - u16 reg_cache[WM8711_CACHEREGNUM]; unsigned int sysclk; }; diff --git a/sound/soc/codecs/wm8731.c b/sound/soc/codecs/wm8731.c index 71122dc36826..0a67c31b2663 100644 --- a/sound/soc/codecs/wm8731.c +++ b/sound/soc/codecs/wm8731.c @@ -43,7 +43,6 @@ static const char *wm8731_supply_names[WM8731_NUM_SUPPLIES] = { struct wm8731_priv { enum snd_soc_control_type control_type; struct regulator_bulk_data supplies[WM8731_NUM_SUPPLIES]; - u16 reg_cache[WM8731_CACHEREGNUM]; unsigned int sysclk; int sysclk_type; int playback_fs; diff --git a/sound/soc/codecs/wm8750.c b/sound/soc/codecs/wm8750.c index 51280e96d721..38f38fddd190 100644 --- a/sound/soc/codecs/wm8750.c +++ b/sound/soc/codecs/wm8750.c @@ -52,7 +52,6 @@ static const u16 wm8750_reg[] = { struct wm8750_priv { unsigned int sysclk; enum snd_soc_control_type control_type; - u16 reg_cache[ARRAY_SIZE(wm8750_reg)]; }; #define wm8750_reset(c) snd_soc_write(c, WM8750_RESET, 0) diff --git a/sound/soc/codecs/wm8900.c b/sound/soc/codecs/wm8900.c index cfbaac1a0ead..cd0959926d12 100644 --- a/sound/soc/codecs/wm8900.c +++ b/sound/soc/codecs/wm8900.c @@ -139,7 +139,6 @@ struct wm8900_priv { enum snd_soc_control_type control_type; - u16 reg_cache[WM8900_MAXREG]; u32 fll_in; /* FLL input frequency */ u32 fll_out; /* FLL output frequency */ diff --git a/sound/soc/codecs/wm8903.c b/sound/soc/codecs/wm8903.c index b9843f72c455..987476a5895f 100644 --- a/sound/soc/codecs/wm8903.c +++ b/sound/soc/codecs/wm8903.c @@ -214,8 +214,6 @@ static u16 wm8903_reg_defaults[] = { struct wm8903_priv { - u16 reg_cache[ARRAY_SIZE(wm8903_reg_defaults)]; - int sysclk; int irq; diff --git a/sound/soc/codecs/wm8940.c b/sound/soc/codecs/wm8940.c index 381934fff4ec..fc7761fa8bd3 100644 --- a/sound/soc/codecs/wm8940.c +++ b/sound/soc/codecs/wm8940.c @@ -42,7 +42,6 @@ struct wm8940_priv { unsigned int sysclk; - u16 reg_cache[WM8940_CACHEREGNUM]; enum snd_soc_control_type control_type; void *control_data; }; diff --git a/sound/soc/codecs/wm8960.c b/sound/soc/codecs/wm8960.c index 054f5737319c..2bb856156eda 100644 --- a/sound/soc/codecs/wm8960.c +++ b/sound/soc/codecs/wm8960.c @@ -71,7 +71,6 @@ static const u16 wm8960_reg[WM8960_CACHEREGNUM] = { }; struct wm8960_priv { - u16 reg_cache[WM8960_CACHEREGNUM]; enum snd_soc_control_type control_type; void *control_data; int (*set_bias_level)(struct snd_soc_codec *, diff --git a/sound/soc/codecs/wm8961.c b/sound/soc/codecs/wm8961.c index 6b22ef200e20..55252e7d02c9 100644 --- a/sound/soc/codecs/wm8961.c +++ b/sound/soc/codecs/wm8961.c @@ -289,7 +289,6 @@ static u16 wm8961_reg_defaults[] = { struct wm8961_priv { enum snd_soc_control_type control_type; int sysclk; - u16 reg_cache[WM8961_MAX_REGISTER]; }; static int wm8961_volatile_register(unsigned int reg) diff --git a/sound/soc/codecs/wm8974.c b/sound/soc/codecs/wm8974.c index 5d286427532a..ca646a822444 100644 --- a/sound/soc/codecs/wm8974.c +++ b/sound/soc/codecs/wm8974.c @@ -51,7 +51,6 @@ static const u16 wm8974_reg[WM8974_CACHEREGNUM] = { struct wm8974_priv { enum snd_soc_control_type control_type; - u16 reg_cache[WM8974_CACHEREGNUM]; }; #define wm8974_reset(c) snd_soc_write(c, WM8974_RESET, 0) diff --git a/sound/soc/codecs/wm8978.c b/sound/soc/codecs/wm8978.c index a195af92b425..4bbc3442703f 100644 --- a/sound/soc/codecs/wm8978.c +++ b/sound/soc/codecs/wm8978.c @@ -59,7 +59,6 @@ struct wm8978_priv { unsigned int f_opclk; int mclk_idx; enum wm8978_sysclk_src sysclk; - u16 reg_cache[WM8978_CACHEREGNUM]; }; static const char *wm8978_companding[] = {"Off", "NC", "u-law", "A-law"}; diff --git a/sound/soc/codecs/wm8988.c b/sound/soc/codecs/wm8988.c index 65807b15a2cc..d7170f1381aa 100644 --- a/sound/soc/codecs/wm8988.c +++ b/sound/soc/codecs/wm8988.c @@ -53,7 +53,6 @@ struct wm8988_priv { unsigned int sysclk; enum snd_soc_control_type control_type; struct snd_pcm_hw_constraint_list *sysclk_constraints; - u16 reg_cache[WM8988_NUM_REG]; }; diff --git a/sound/soc/codecs/wm8993.c b/sound/soc/codecs/wm8993.c index 15f34a26debf..18c0d9ce7c32 100644 --- a/sound/soc/codecs/wm8993.c +++ b/sound/soc/codecs/wm8993.c @@ -225,7 +225,6 @@ static struct { struct wm8993_priv { struct wm_hubs_data hubs_data; - u16 reg_cache[WM8993_REGISTER_COUNT]; struct regulator_bulk_data supplies[WM8993_NUM_SUPPLIES]; struct wm8993_platform_data pdata; enum snd_soc_control_type control_type; diff --git a/sound/soc/codecs/wm9081.c b/sound/soc/codecs/wm9081.c index e5055b28c638..702db6937d4f 100644 --- a/sound/soc/codecs/wm9081.c +++ b/sound/soc/codecs/wm9081.c @@ -157,7 +157,6 @@ static struct { struct wm9081_priv { enum snd_soc_control_type control_type; void *control_data; - u16 reg_cache[WM9081_MAX_REGISTER + 1]; int sysclk_source; int mclk_rate; int sysclk_rate; -- cgit v1.2.2 From 7116f452c8e3e38f99ab3231a758eb366dacfe4a Mon Sep 17 00:00:00 2001 From: Mark Brown Date: Wed, 29 Dec 2010 13:05:21 +0000 Subject: ASoC: Yet more x86 tracepoint workarounds Signed-off-by: Mark Brown --- sound/soc/codecs/88pm860x-codec.c | 2 +- sound/soc/codecs/wm8350.c | 2 ++ sound/soc/codecs/wm8994.c | 4 ++++ 3 files changed, 7 insertions(+), 1 deletion(-) (limited to 'sound/soc/codecs') diff --git a/sound/soc/codecs/88pm860x-codec.c b/sound/soc/codecs/88pm860x-codec.c index 5da8207a6961..06b6981b8d6d 100644 --- a/sound/soc/codecs/88pm860x-codec.c +++ b/sound/soc/codecs/88pm860x-codec.c @@ -1262,7 +1262,7 @@ static irqreturn_t pm860x_codec_handler(int irq, void *data) mask = pm860x->det.hs_shrt | pm860x->det.hook_det | pm860x->det.lo_shrt | pm860x->det.hp_det; -#ifndef CONFIG_SND_SOC_88PM860X +#ifndef CONFIG_SND_SOC_88PM860X_MODULE if (status & (HEADSET_STATUS | MIC_STATUS | SHORT_HS1 | SHORT_HS2 | SHORT_LO1 | SHORT_LO2)) trace_snd_soc_jack_irq(dev_name(pm860x->codec->dev)); diff --git a/sound/soc/codecs/wm8350.c b/sound/soc/codecs/wm8350.c index db07137bf3b9..6d6dc9efe914 100644 --- a/sound/soc/codecs/wm8350.c +++ b/sound/soc/codecs/wm8350.c @@ -1463,7 +1463,9 @@ static irqreturn_t wm8350_mic_handler(int irq, void *data) u16 reg; int report = 0; +#ifndef CONFIG_SND_SOC_WM8350_MODULE trace_snd_soc_jack_irq("WM8350 mic"); +#endif reg = wm8350_reg_read(wm8350, WM8350_JACK_PIN_STATUS); if (reg & WM8350_JACK_MICSCD_LVL) diff --git a/sound/soc/codecs/wm8994.c b/sound/soc/codecs/wm8994.c index 067a532bed15..247a6a99feb8 100644 --- a/sound/soc/codecs/wm8994.c +++ b/sound/soc/codecs/wm8994.c @@ -2756,7 +2756,9 @@ static irqreturn_t wm8994_mic_irq(int irq, void *data) int reg; int report; +#ifndef CONFIG_SND_SOC_WM8994_MODULE trace_snd_soc_jack_irq(dev_name(codec->dev)); +#endif reg = snd_soc_read(codec, WM8994_INTERRUPT_RAW_STATUS_2); if (reg < 0) { @@ -2904,7 +2906,9 @@ static irqreturn_t wm8958_mic_irq(int irq, void *data) goto out; } +#ifndef CONFIG_SND_SOC_WM8994_MODULE trace_snd_soc_jack_irq(dev_name(codec->dev)); +#endif if (wm8994->jack_cb) wm8994->jack_cb(reg, wm8994->jack_cb_data); -- cgit v1.2.2 From 11b8fca53a84992c74f05a091102c32eb40f1a08 Mon Sep 17 00:00:00 2001 From: Timur Tabi Date: Mon, 10 Jan 2011 13:28:32 -0600 Subject: ASoC: cs4270: use the built-in register cache support Update the CS4270 driver to use ASoC's internal codec register cache feature. This change allows ASoC to perform the low-level I2C operations necessary to read the register cache. Support is also added for initializing the register cache with an array of known power-on default values. The CS4270 driver was handling the register cache itself, but somwhere along the conversion to multi-compaonent, this feature broke. Signed-off-by: Timur Tabi Acked-by: Liam Girdwood Signed-off-by: Mark Brown --- sound/soc/codecs/cs4270.c | 161 ++++++++++++++-------------------------------- 1 file changed, 48 insertions(+), 113 deletions(-) (limited to 'sound/soc/codecs') diff --git a/sound/soc/codecs/cs4270.c b/sound/soc/codecs/cs4270.c index 3a582caa6ef9..8b51245f2318 100644 --- a/sound/soc/codecs/cs4270.c +++ b/sound/soc/codecs/cs4270.c @@ -106,6 +106,21 @@ #define CS4270_MUTE_DAC_A 0x01 #define CS4270_MUTE_DAC_B 0x02 +/* Power-on default values for the registers + * + * This array contains the power-on default values of the registers, with the + * exception of the "CHIPID" register (01h). The lower four bits of that + * register contain the hardware revision, so it is treated as volatile. + * + * Also note that on the CS4270, the first readable register is 1, but ASoC + * assumes the first register is 0. Therfore, the array must have an entry for + * register 0, but we use cs4270_reg_is_readable() to tell ASoC that it can't + * be read. + */ +static const u8 cs4270_default_reg_cache[CS4270_LASTREG + 1] = { + 0x00, 0x00, 0x00, 0x30, 0x00, 0x60, 0x20, 0x00, 0x00 +}; + static const char *supply_names[] = { "va", "vd", "vlc" }; @@ -178,6 +193,20 @@ static struct cs4270_mode_ratios cs4270_mode_ratios[] = { /* The number of MCLK/LRCK ratios supported by the CS4270 */ #define NUM_MCLK_RATIOS ARRAY_SIZE(cs4270_mode_ratios) +static int cs4270_reg_is_readable(unsigned int reg) +{ + return (reg >= CS4270_FIRSTREG) && (reg <= CS4270_LASTREG); +} + +static int cs4270_reg_is_volatile(unsigned int reg) +{ + /* Unreadable registers are considered volatile */ + if ((reg < CS4270_FIRSTREG) || (reg > CS4270_LASTREG)) + return 1; + + return reg == CS4270_CHIPID; +} + /** * cs4270_set_dai_sysclk - determine the CS4270 samples rates. * @codec_dai: the codec DAI @@ -262,97 +291,6 @@ static int cs4270_set_dai_fmt(struct snd_soc_dai *codec_dai, return ret; } -/** - * cs4270_fill_cache - pre-fill the CS4270 register cache. - * @codec: the codec for this CS4270 - * - * This function fills in the CS4270 register cache by reading the register - * values from the hardware. - * - * This CS4270 registers are cached to avoid excessive I2C I/O operations. - * After the initial read to pre-fill the cache, the CS4270 never updates - * the register values, so we won't have a cache coherency problem. - * - * We use the auto-increment feature of the CS4270 to read all registers in - * one shot. - */ -static int cs4270_fill_cache(struct snd_soc_codec *codec) -{ - u8 *cache = codec->reg_cache; - struct i2c_client *i2c_client = codec->control_data; - s32 length; - - length = i2c_smbus_read_i2c_block_data(i2c_client, - CS4270_FIRSTREG | CS4270_I2C_INCR, CS4270_NUMREGS, cache); - - if (length != CS4270_NUMREGS) { - dev_err(codec->dev, "i2c read failure, addr=0x%x\n", - i2c_client->addr); - return -EIO; - } - - return 0; -} - -/** - * cs4270_read_reg_cache - read from the CS4270 register cache. - * @codec: the codec for this CS4270 - * @reg: the register to read - * - * This function returns the value for a given register. It reads only from - * the register cache, not the hardware itself. - * - * This CS4270 registers are cached to avoid excessive I2C I/O operations. - * After the initial read to pre-fill the cache, the CS4270 never updates - * the register values, so we won't have a cache coherency problem. - */ -static unsigned int cs4270_read_reg_cache(struct snd_soc_codec *codec, - unsigned int reg) -{ - u8 *cache = codec->reg_cache; - - if ((reg < CS4270_FIRSTREG) || (reg > CS4270_LASTREG)) - return -EIO; - - return cache[reg - CS4270_FIRSTREG]; -} - -/** - * cs4270_i2c_write - write to a CS4270 register via the I2C bus. - * @codec: the codec for this CS4270 - * @reg: the register to write - * @value: the value to write to the register - * - * This function writes the given value to the given CS4270 register, and - * also updates the register cache. - * - * Note that we don't use the hw_write function pointer of snd_soc_codec. - * That's because it's too clunky: the hw_write_t prototype does not match - * i2c_smbus_write_byte_data(), and it's just another layer of overhead. - */ -static int cs4270_i2c_write(struct snd_soc_codec *codec, unsigned int reg, - unsigned int value) -{ - u8 *cache = codec->reg_cache; - - if ((reg < CS4270_FIRSTREG) || (reg > CS4270_LASTREG)) - return -EIO; - - /* Only perform an I2C operation if the new value is different */ - if (cache[reg - CS4270_FIRSTREG] != value) { - struct i2c_client *client = codec->control_data; - if (i2c_smbus_write_byte_data(client, reg, value)) { - dev_err(codec->dev, "i2c write failed\n"); - return -EIO; - } - - /* We've written to the hardware, so update the cache */ - cache[reg - CS4270_FIRSTREG] = value; - } - - return 0; -} - /** * cs4270_hw_params - program the CS4270 with the given hardware parameters. * @substream: the audio stream @@ -550,15 +488,16 @@ static struct snd_soc_dai_driver cs4270_dai = { static int cs4270_probe(struct snd_soc_codec *codec) { struct cs4270_private *cs4270 = snd_soc_codec_get_drvdata(codec); - int i, ret, reg; + int i, ret; codec->control_data = cs4270->control_data; - /* The I2C interface is set up, so pre-fill our register cache */ - - ret = cs4270_fill_cache(codec); + /* Tell ASoC what kind of I/O to use to read the registers. ASoC will + * then do the I2C transactions itself. + */ + ret = snd_soc_codec_set_cache_io(codec, 8, 8, cs4270->control_type); if (ret < 0) { - dev_err(codec->dev, "failed to fill register cache\n"); + dev_err(codec->dev, "failed to set cache I/O (ret=%i)\n", ret); return ret; } @@ -567,10 +506,7 @@ static int cs4270_probe(struct snd_soc_codec *codec) * this feature disabled by default. An application (e.g. alsactl) can * re-enabled it by using the controls. */ - - reg = cs4270_read_reg_cache(codec, CS4270_MUTE); - reg &= ~CS4270_MUTE_AUTO; - ret = cs4270_i2c_write(codec, CS4270_MUTE, reg); + ret = snd_soc_update_bits(codec, CS4270_MUTE, CS4270_MUTE_AUTO, 0); if (ret < 0) { dev_err(codec->dev, "i2c write failed\n"); return ret; @@ -581,10 +517,8 @@ static int cs4270_probe(struct snd_soc_codec *codec) * playback has started. An application (e.g. alsactl) can * re-enabled it by using the controls. */ - - reg = cs4270_read_reg_cache(codec, CS4270_TRANS); - reg &= ~(CS4270_TRANS_SOFT | CS4270_TRANS_ZERO); - ret = cs4270_i2c_write(codec, CS4270_TRANS, reg); + ret = snd_soc_update_bits(codec, CS4270_TRANS, + CS4270_TRANS_SOFT | CS4270_TRANS_ZERO, 0); if (ret < 0) { dev_err(codec->dev, "i2c write failed\n"); return ret; @@ -707,15 +641,16 @@ static int cs4270_soc_resume(struct snd_soc_codec *codec) * Assign this variable to the codec_dev field of the machine driver's * snd_soc_device structure. */ -static struct snd_soc_codec_driver soc_codec_device_cs4270 = { - .probe = cs4270_probe, - .remove = cs4270_remove, - .suspend = cs4270_soc_suspend, - .resume = cs4270_soc_resume, - .read = cs4270_read_reg_cache, - .write = cs4270_i2c_write, - .reg_cache_size = CS4270_NUMREGS, - .reg_word_size = sizeof(u8), +static const struct snd_soc_codec_driver soc_codec_device_cs4270 = { + .probe = cs4270_probe, + .remove = cs4270_remove, + .suspend = cs4270_soc_suspend, + .resume = cs4270_soc_resume, + .volatile_register = cs4270_reg_is_volatile, + .readable_register = cs4270_reg_is_readable, + .reg_cache_size = CS4270_LASTREG + 1, + .reg_word_size = sizeof(u8), + .reg_cache_default = cs4270_default_reg_cache, }; /** -- cgit v1.2.2 From 03cfbdf9f7a1d392146718f67e50fa9ab2844f22 Mon Sep 17 00:00:00 2001 From: Takashi Iwai Date: Tue, 11 Jan 2011 17:58:26 +0100 Subject: ASoC: Fix section mismatch in wm8995.c __devinitconst can't be used for data referred in driver struct. Signed-off-by: Takashi Iwai --- sound/soc/codecs/wm8995.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'sound/soc/codecs') diff --git a/sound/soc/codecs/wm8995.c b/sound/soc/codecs/wm8995.c index 3d2110c1d81f..6045cbde492b 100644 --- a/sound/soc/codecs/wm8995.c +++ b/sound/soc/codecs/wm8995.c @@ -30,7 +30,7 @@ #include "wm8995.h" -static const u16 wm8995_reg_defs[WM8995_MAX_REGISTER + 1] __devinitconst = { +static const u16 wm8995_reg_defs[WM8995_MAX_REGISTER + 1] = { [0] = 0x8995, [5] = 0x0100, [16] = 0x000b, [17] = 0x000b, [24] = 0x02c0, [25] = 0x02c0, [26] = 0x02c0, [27] = 0x02c0, [28] = 0x000f, [32] = 0x0005, [33] = 0x0005, [40] = 0x0003, -- cgit v1.2.2 From a710770e05563fd5add9af686569ee9fa56bbd65 Mon Sep 17 00:00:00 2001 From: David Lambert Date: Thu, 6 Jan 2011 08:00:37 -0600 Subject: ASoC: DMIC codec: Adding a generic DMIC codec This codec is to be used by the DMIC driver to control the DMIC codec. This driver will be used on future implementations of the DMIC driver to support codec specific features. At this time, the codec driver just registers the codec DAI. Signed-off-by: David Lambert Acked-by: Mark Brown Signed-off-by: Liam Girdwood --- sound/soc/codecs/Kconfig | 3 ++ sound/soc/codecs/Makefile | 2 ++ sound/soc/codecs/dmic.c | 81 +++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 86 insertions(+) create mode 100644 sound/soc/codecs/dmic.c (limited to 'sound/soc/codecs') diff --git a/sound/soc/codecs/Kconfig b/sound/soc/codecs/Kconfig index 0f33db2be25a..f6c6d316ac67 100644 --- a/sound/soc/codecs/Kconfig +++ b/sound/soc/codecs/Kconfig @@ -166,6 +166,9 @@ config SND_SOC_L3 config SND_SOC_DA7210 tristate +config SND_SOC_DMIC + tristate + config SND_SOC_MAX98088 tristate diff --git a/sound/soc/codecs/Makefile b/sound/soc/codecs/Makefile index 10e5e099334a..9139cf95ff70 100644 --- a/sound/soc/codecs/Makefile +++ b/sound/soc/codecs/Makefile @@ -14,6 +14,7 @@ snd-soc-cs42l51-objs := cs42l51.o snd-soc-cs4270-objs := cs4270.o snd-soc-cx20442-objs := cx20442.o snd-soc-da7210-objs := da7210.o +snd-soc-dmic-objs := dmic.o snd-soc-l3-objs := l3.o snd-soc-max98088-objs := max98088.o snd-soc-pcm3008-objs := pcm3008.o @@ -91,6 +92,7 @@ obj-$(CONFIG_SND_SOC_CS42L51) += snd-soc-cs42l51.o obj-$(CONFIG_SND_SOC_CS4270) += snd-soc-cs4270.o obj-$(CONFIG_SND_SOC_CX20442) += snd-soc-cx20442.o obj-$(CONFIG_SND_SOC_DA7210) += snd-soc-da7210.o +obj-$(CONFIG_SND_SOC_DMIC) += snd-soc-dmic.o obj-$(CONFIG_SND_SOC_L3) += snd-soc-l3.o obj-$(CONFIG_SND_SOC_JZ4740_CODEC) += snd-soc-jz4740-codec.o obj-$(CONFIG_SND_SOC_MAX98088) += snd-soc-max98088.o diff --git a/sound/soc/codecs/dmic.c b/sound/soc/codecs/dmic.c new file mode 100644 index 000000000000..57e9dac88d38 --- /dev/null +++ b/sound/soc/codecs/dmic.c @@ -0,0 +1,81 @@ +/* + * dmic.c -- SoC audio for Generic Digital MICs + * + * Author: Liam Girdwood + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA + * 02110-1301 USA + * + */ + +#include +#include +#include +#include +#include +#include + +static struct snd_soc_dai_driver dmic_dai = { + .name = "dmic-hifi", + .capture = { + .stream_name = "Capture", + .channels_min = 1, + .channels_max = 8, + .rates = SNDRV_PCM_RATE_CONTINUOUS, + .formats = SNDRV_PCM_FMTBIT_S32_LE + | SNDRV_PCM_FMTBIT_S24_LE + | SNDRV_PCM_FMTBIT_S16_LE, + }, +}; + +static struct snd_soc_codec_driver soc_dmic = {}; + +static int __devinit dmic_dev_probe(struct platform_device *pdev) +{ + return snd_soc_register_codec(&pdev->dev, + &soc_dmic, &dmic_dai, 1); +} + +static int __devexit dmic_dev_remove(struct platform_device *pdev) +{ + snd_soc_unregister_codec(&pdev->dev); + return 0; +} + +MODULE_ALIAS("platform:dmic-codec"); + +static struct platform_driver dmic_driver = { + .driver = { + .name = "dmic-codec", + .owner = THIS_MODULE, + }, + .probe = dmic_dev_probe, + .remove = __devexit_p(dmic_dev_remove), +}; + +static int __init dmic_init(void) +{ + return platform_driver_register(&dmic_driver); +} +module_init(dmic_init); + +static void __exit dmic_exit(void) +{ + platform_driver_unregister(&dmic_driver); +} +module_exit(dmic_exit); + +MODULE_DESCRIPTION("Generic DMIC driver"); +MODULE_AUTHOR("Liam Girdwood "); +MODULE_LICENSE("GPL"); -- cgit v1.2.2 From 399b82e4930f5f97556c7fd84ea3ef312718adee Mon Sep 17 00:00:00 2001 From: Peter Ujfalusi Date: Mon, 10 Jan 2011 15:39:49 +0200 Subject: ASoC: tlv320dac33: Add DAPM selection for LOM invert The L/R LOM line can be invertined side of the corresponding DAC, or inverted from the corresponding LOP. Add control for user space to select the source of the LOM inversion. When only the analog bypass is enabled, and the LOM is inverted from DAC output, we need to power the corresponding DAC. Signed-off-by: Peter Ujfalusi Acked-by: Mark Brown Signed-off-by: Liam Girdwood --- sound/soc/codecs/tlv320dac33.c | 55 ++++++++++++++++++++++++++++++++++++++---- 1 file changed, 50 insertions(+), 5 deletions(-) (limited to 'sound/soc/codecs') diff --git a/sound/soc/codecs/tlv320dac33.c b/sound/soc/codecs/tlv320dac33.c index 13d521cfe393..71d7be8ac488 100644 --- a/sound/soc/codecs/tlv320dac33.c +++ b/sound/soc/codecs/tlv320dac33.c @@ -298,7 +298,6 @@ static void dac33_init_chip(struct snd_soc_codec *codec) if (unlikely(!dac33->chip_power)) return; - /* 44-46: DAC Control Registers */ /* A : DAC sample rate Fsref/1.5 */ dac33_write(codec, DAC33_DAC_CTRL_A, DAC33_DACRATE(0)); /* B : DAC src=normal, not muted */ @@ -321,6 +320,10 @@ static void dac33_init_chip(struct snd_soc_codec *codec) dac33_read_reg_cache(codec, DAC33_LINEL_TO_LLO_VOL)); dac33_write(codec, DAC33_LINER_TO_RLO_VOL, dac33_read_reg_cache(codec, DAC33_LINER_TO_RLO_VOL)); + + dac33_write(codec, DAC33_OUT_AMP_CTRL, + dac33_read_reg_cache(codec, DAC33_OUT_AMP_CTRL)); + } static inline int dac33_read_id(struct snd_soc_codec *codec) @@ -523,6 +526,25 @@ static const struct snd_kcontrol_new dac33_dapm_abypassl_control = static const struct snd_kcontrol_new dac33_dapm_abypassr_control = SOC_DAPM_SINGLE("Switch", DAC33_LINER_TO_RLO_VOL, 7, 1, 1); +/* LOP L/R invert selection */ +static const char *dac33_lr_lom_texts[] = {"DAC", "LOP"}; + +static const struct soc_enum dac33_left_lom_enum = + SOC_ENUM_SINGLE(DAC33_OUT_AMP_CTRL, 3, + ARRAY_SIZE(dac33_lr_lom_texts), + dac33_lr_lom_texts); + +static const struct snd_kcontrol_new dac33_dapm_left_lom_control = +SOC_DAPM_ENUM("Route", dac33_left_lom_enum); + +static const struct soc_enum dac33_right_lom_enum = + SOC_ENUM_SINGLE(DAC33_OUT_AMP_CTRL, 2, + ARRAY_SIZE(dac33_lr_lom_texts), + dac33_lr_lom_texts); + +static const struct snd_kcontrol_new dac33_dapm_right_lom_control = +SOC_DAPM_ENUM("Route", dac33_right_lom_enum); + static const struct snd_soc_dapm_widget dac33_dapm_widgets[] = { SND_SOC_DAPM_OUTPUT("LEFT_LO"), SND_SOC_DAPM_OUTPUT("RIGHT_LO"), @@ -539,6 +561,18 @@ static const struct snd_soc_dapm_widget dac33_dapm_widgets[] = { SND_SOC_DAPM_SWITCH("Analog Right Bypass", SND_SOC_NOPM, 0, 0, &dac33_dapm_abypassr_control), + SND_SOC_DAPM_MUX("Left LOM Inverted From", SND_SOC_NOPM, 0, 0, + &dac33_dapm_left_lom_control), + SND_SOC_DAPM_MUX("Right LOM Inverted From", SND_SOC_NOPM, 0, 0, + &dac33_dapm_right_lom_control), + /* + * For DAPM path, when only the anlog bypass path is enabled, and the + * LOP inverted from the corresponding DAC side. + * This is needed, so we can attach the DAC power supply in this case. + */ + SND_SOC_DAPM_PGA("Left Bypass PGA", SND_SOC_NOPM, 0, 0, NULL, 0), + SND_SOC_DAPM_PGA("Right Bypass PGA", SND_SOC_NOPM, 0, 0, NULL, 0), + SND_SOC_DAPM_REG(snd_soc_dapm_mixer, "Output Left Amplifier", DAC33_OUT_AMP_PWR_CTRL, 6, 3, 3, 0), SND_SOC_DAPM_REG(snd_soc_dapm_mixer, "Output Right Amplifier", @@ -561,11 +595,22 @@ static const struct snd_soc_dapm_route audio_map[] = { {"Output Left Amplifier", NULL, "DACL"}, {"Output Right Amplifier", NULL, "DACR"}, - {"Output Left Amplifier", NULL, "Analog Left Bypass"}, - {"Output Right Amplifier", NULL, "Analog Right Bypass"}, + {"Left Bypass PGA", NULL, "Analog Left Bypass"}, + {"Right Bypass PGA", NULL, "Analog Right Bypass"}, + + {"Left LOM Inverted From", "DAC", "Left Bypass PGA"}, + {"Right LOM Inverted From", "DAC", "Right Bypass PGA"}, + {"Left LOM Inverted From", "LOP", "Analog Left Bypass"}, + {"Right LOM Inverted From", "LOP", "Analog Right Bypass"}, + + {"Output Left Amplifier", NULL, "Left LOM Inverted From"}, + {"Output Right Amplifier", NULL, "Right LOM Inverted From"}, + + {"DACL", NULL, "Left DAC Power"}, + {"DACR", NULL, "Right DAC Power"}, - {"Output Left Amplifier", NULL, "Left DAC Power"}, - {"Output Right Amplifier", NULL, "Right DAC Power"}, + {"Left Bypass PGA", NULL, "Left DAC Power"}, + {"Right Bypass PGA", NULL, "Right DAC Power"}, /* output */ {"LEFT_LO", NULL, "Output Left Amplifier"}, -- cgit v1.2.2 From 559a8cd629f1b797732fd97afd58b41d8b6fb312 Mon Sep 17 00:00:00 2001 From: Peter Ujfalusi Date: Tue, 28 Dec 2010 11:16:19 +0200 Subject: ASoC: tpa6130a2: Fix compiler warning sound/soc/codecs/tpa6130a2.c: In function 'tpa6130a2_add_controls': sound/soc/codecs/tpa6130a2.c:342: warning: unused variable 'dapm' Introduced by commit 39646871a47fd8808c08de0ce7d7ca8393af2805 ("ASoC: tpa6130a2: Replace DAPM code with direct interface"). The DAPM code has been removed from the driver, but the dapm struct remained. Signed-off-by: Peter Ujfalusi Acked-by: Mark Brown Signed-off-by: Liam Girdwood --- sound/soc/codecs/tpa6130a2.c | 1 - 1 file changed, 1 deletion(-) (limited to 'sound/soc/codecs') diff --git a/sound/soc/codecs/tpa6130a2.c b/sound/soc/codecs/tpa6130a2.c index 0a99f313e218..1f1ac8110bef 100644 --- a/sound/soc/codecs/tpa6130a2.c +++ b/sound/soc/codecs/tpa6130a2.c @@ -339,7 +339,6 @@ EXPORT_SYMBOL_GPL(tpa6130a2_stereo_enable); int tpa6130a2_add_controls(struct snd_soc_codec *codec) { struct tpa6130a2_data *data; - struct snd_soc_dapm_context *dapm = &codec->dapm; if (tpa6130a2_client == NULL) return -ENODEV; -- cgit v1.2.2