From 86027ae78c9294bb450b76eec28cfb431a8fb3ee Mon Sep 17 00:00:00 2001 From: Jonas Andersson Date: Wed, 4 Mar 2009 08:24:26 +0100 Subject: ASoC: wm8510 pll settings When setting WM8510_MCLKDIV the pll was turned off. When setting pll frequency you got twice the expected freq, because the code calculated with postscaler of 8, but the hardware divide by 4. Signed-off-by: Jonas Andersson Signed-off-by: Mark Brown --- sound/soc/atmel/playpaq_wm8510.c | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) (limited to 'sound/soc/atmel/playpaq_wm8510.c') diff --git a/sound/soc/atmel/playpaq_wm8510.c b/sound/soc/atmel/playpaq_wm8510.c index 43dd8cee83c6..70657534e6b1 100644 --- a/sound/soc/atmel/playpaq_wm8510.c +++ b/sound/soc/atmel/playpaq_wm8510.c @@ -164,38 +164,38 @@ static int playpaq_wm8510_hw_params(struct snd_pcm_substream *substream, */ switch (params_rate(params)) { case 48000: - pll_out = 12288000; - mclk_div = WM8510_MCLKDIV_1; + pll_out = 24576000; + mclk_div = WM8510_MCLKDIV_2; bclk = WM8510_BCLKDIV_8; break; case 44100: - pll_out = 11289600; - mclk_div = WM8510_MCLKDIV_1; + pll_out = 22579200; + mclk_div = WM8510_MCLKDIV_2; bclk = WM8510_BCLKDIV_8; break; case 22050: - pll_out = 11289600; - mclk_div = WM8510_MCLKDIV_2; + pll_out = 22579200; + mclk_div = WM8510_MCLKDIV_4; bclk = WM8510_BCLKDIV_8; break; case 16000: - pll_out = 12288000; - mclk_div = WM8510_MCLKDIV_3; + pll_out = 24576000; + mclk_div = WM8510_MCLKDIV_6; bclk = WM8510_BCLKDIV_8; break; case 11025: - pll_out = 11289600; - mclk_div = WM8510_MCLKDIV_4; + pll_out = 22579200; + mclk_div = WM8510_MCLKDIV_8; bclk = WM8510_BCLKDIV_8; break; case 8000: - pll_out = 12288000; - mclk_div = WM8510_MCLKDIV_6; + pll_out = 24576000; + mclk_div = WM8510_MCLKDIV_12; bclk = WM8510_BCLKDIV_8; break; -- cgit v1.2.2