#ifndef __BNX2X_INIT_VALUES_H__
#define __BNX2X_INIT_VALUES_H__
/* This array contains the list of operations needed to initialize the chip.
*
* For each block in the chip there are three init stages:
* common - HW used by both ports,
* port1 and port2 - initialization for a specific Ethernet port.
* When a port is opened or closed, the management CPU tells the driver
* whether to init/disable common HW in addition to the port HW.
* This way the first port going up will first initializes the common HW,
* and the last port going down also resets the common HW
*
* For each init stage/block there is a list of actions needed in a format:
* {operation, register, data}
* where:
* OP_WR - write a value to the chip.
* OP_RD - read a register (usually a clear on read register).
* OP_SW - string write, write a section of consecutive addresses to the chip.
* OP_SI - copy a string using indirect writes.
* OP_ZR - clear a range of memory.
* OP_ZP - unzip and copy using DMAE.
* OP_WB - string copy using DMAE.
*
* The #defines mark the stages.
*
*/
static const struct raw_op init_ops[] = {
#define PRS_COMMON_START 0
{OP_WR, PRS_REG_INC_VALUE, 0xf},
{OP_WR, PRS_REG_EVENT_ID_1, 0x45},
{OP_WR, PRS_REG_EVENT_ID_2, 0x84},
{OP_WR, PRS_REG_EVENT_ID_3, 0x6},
{OP_WR, PRS_REG_NO_MATCH_EVENT_ID, 0x4},
{OP_WR, PRS_REG_CM_HDR_TYPE_0, 0x0},
{OP_WR, PRS_REG_CM_HDR_TYPE_1, 0x12170000},
{OP_WR, PRS_REG_CM_HDR_TYPE_2, 0x22170000},
{OP_WR, PRS_REG_CM_HDR_TYPE_3, 0x32170000},
{OP_ZR, PRS_REG_CM_HDR_TYPE_4, 0x5},
{OP_WR, PRS_REG_CM_HDR_LOOPBACK_TYPE_1, 0x12150000},
{OP_WR, PRS_REG_CM_HDR_LOOPBACK_TYPE_2, 0x22150000},
{OP_WR, PRS_REG_CM_HDR_LOOPBACK_TYPE_3, 0x32150000},
{OP_ZR, PRS_REG_CM_HDR_LOOPBACK_TYPE_4, 0x4},
{OP_WR, PRS_REG_CM_NO_MATCH_HDR, 0x2100000},
{OP_WR, PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_0, 0x100000},
{OP_WR, PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_1, 0x10100000},
{OP_WR, PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_2, 0x20100000},
{OP_WR, PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_3, 0x30100000},
{OP_ZR, PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_4, 0x4},
{OP_WR, PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_0, 0x100000},
{OP_WR, PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_1, 0x12140000},
{OP_WR, PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_2, 0x22140000},
{OP_WR, PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_3, 0x32140000},
{OP_ZR, PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_4, 0x4},
{OP_RD, PRS_REG_NUM_OF_PACKETS, 0x0},
{OP_RD, PRS_REG_NUM_OF_CFC_FLUSH_MESSAGES, 0x0},
{OP_RD, PRS_REG_NUM_OF_TRANSPARENT_FLUSH_MESSAGES, 0x0},
{OP_RD, PRS_REG_NUM_OF_DEAD_CYCLES, 0x0},
{OP_WR_E1H, PRS_REG_FCOE_TYPE, 0x8906},
{OP_WR, PRS_REG_FLUSH_REGIONS_TYPE_0, 0xff},
{OP_WR, PRS_REG_FLUSH_REGIONS_TYPE_1, 0xff},
{OP_WR, PRS_REG_FLUSH_REGIONS_TYPE_2, 0xff},
{OP_WR, PRS_REG_FLUSH_REGIONS_TYPE_3, 0xff},
{OP_WR, PRS_REG_FLUSH_REGIONS_TYPE_4, 0xff},
{OP_WR, PRS_REG_FLUSH_REGIONS_TYPE_5, 0xff},
{OP_WR, PRS_REG_FLUSH_REGIONS_TYPE_6, 0xff},
{OP_WR, PRS_REG_FLUSH_REGIONS_TYPE_7, 0xff},
{OP_WR, PRS_REG_PURE_REGIONS, 0x3e},
{OP_WR, PRS_REG_PACKET_REGIONS_TYPE_0, 0x0},
{OP_WR, PRS_REG_PACKET_REGIONS_TYPE_1, 0x3f},
