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/*
* Definitions for the new Marvell Yukon 2 driver.
*/
#ifndef _SKY2_H
#define _SKY2_H
#define ETH_JUMBO_MTU 9000 /* Maximum MTU supported */
/* PCI config registers */
enum {
PCI_DEV_REG1 = 0x40,
PCI_DEV_REG2 = 0x44,
PCI_DEV_STATUS = 0x7c,
PCI_DEV_REG3 = 0x80,
PCI_DEV_REG4 = 0x84,
PCI_DEV_REG5 = 0x88,
PCI_CFG_REG_0 = 0x90,
PCI_CFG_REG_1 = 0x94,
PSM_CONFIG_REG0 = 0x98,
PSM_CONFIG_REG1 = 0x9C,
PSM_CONFIG_REG2 = 0x160,
PSM_CONFIG_REG3 = 0x164,
PSM_CONFIG_REG4 = 0x168,
};
/* Yukon-2 */
enum pci_dev_reg_1 {
PCI_Y2_PIG_ENA = 1<<31, /* Enable Plug-in-Go (YUKON-2) */
PCI_Y2_DLL_DIS = 1<<30, /* Disable PCI DLL (YUKON-2) */
PCI_SW_PWR_ON_RST= 1<<30, /* SW Power on Reset (Yukon-EX) */
PCI_Y2_PHY2_COMA = 1<<29, /* Set PHY 2 to Coma Mode (YUKON-2) */
PCI_Y2_PHY1_COMA = 1<<28, /* Set PHY 1 to Coma Mode (YUKON-2) */
PCI_Y2_PHY2_POWD = 1<<27, /* Set PHY 2 to Power Down (YUKON-2) */
PCI_Y2_PHY1_POWD = 1<<26, /* Set PHY 1 to Power Down (YUKON-2) */
PCI_Y2_PME_LEGACY= 1<<15, /* PCI Express legacy power management mode */
PCI_PHY_LNK_TIM_MSK= 3L<<8,/* Bit 9.. 8: GPHY Link Trigger Timer */
PCI_ENA_L1_EVENT = 1<<7, /* Enable PEX L1 Event */
PCI_ENA_GPHY_LNK = 1<<6, /* Enable PEX L1 on GPHY Link down */
PCI_FORCE_PEX_L1 = 1<<5, /* Force to PEX L1 */
};
enum pci_dev_reg_2 {
PCI_VPD_WR_THR = 0xffL<<24, /* Bit 31..24: VPD Write Threshold */
PCI_DEV_SEL = 0x7fL<<17, /* Bit 23..17: EEPROM Device Select */
PCI_VPD_ROM_SZ = 7L<<14, /* Bit 16..14: VPD ROM Size */
PCI_PATCH_DIR = 0xfL<<8, /* Bit 11.. 8: Ext Patches dir 3..0 */
PCI_EXT_PATCHS = 0xfL<<4, /* Bit 7.. 4: Extended Patches 3..0 */
PCI_EN_DUMMY_RD = 1<<3, /* Enable Dummy Read */
PCI_REV_DESC = 1<<2, /* Reverse Desc. Bytes */
PCI_USEDATA64 = 1<<0, /* Use 64Bit Data bus ext */
};
/* PCI_OUR_REG_3 32 bit Our Register 3 (Yukon-ECU only) */
enum pci_dev_reg_3 {
P_CLK_ASF_REGS_DIS = 1<<18,/* Disable Clock ASF (Yukon-Ext.) */
P_CLK_COR_REGS_D0_DIS = 1<<17,/* Disable Clock Core Regs D0 */
P_CLK_MACSEC_DIS = 1<<17,/* Disable Clock MACSec (Yukon-Ext.) */
P_CLK_PCI_REGS_D0_DIS = 1<<16,/* Disable Clock PCI Regs D0 */
P_CLK_COR_YTB_ARB_DIS = 1<<15,/* Disable Clock YTB Arbiter */
P_CLK_MAC_LNK1_D3_DIS = 1<<14,/* Disable Clock MAC Link1 D3 */
P_CLK_COR_LNK1_D0_DIS = 1<<13,/* Disable Clock Core Link1 D0 */
P_CLK_MAC_LNK1_D0_DIS = 1<<12,/* Disable Clock MAC Link1 D0 */
P_CLK_COR_LNK1_D3_DIS = 1<<11,/* Disable Clock Core Link1 D3 */
P_CLK_PCI_MST_ARB_DIS = 1<<10,/* Disable Clock PCI Master Arb. */
P_CLK_COR_REGS_D3_DIS = 1<<9, /* Disable Clock Core Regs D3 */
P_CLK_PCI_REGS_D3_DIS = 1<<8, /* Disable Clock PCI Regs D3 */
P_CLK_REF_LNK1_GM_DIS = 1<<7, /* Disable Clock Ref. Link1 GMAC */
P_CLK_COR_LNK1_GM_DIS = 1<<6, /* Disable Clock Core Link1 GMAC */
P_CLK_PCI_COMMON_DIS = 1<<5, /* Disable Clock PCI Common */
P_CLK_COR_COMMON_DIS = 1<<4, /* Disable Clock Core Common */
P_CLK_PCI_LNK1_BMU_DIS = 1<<3, /* Disable Clock PCI Link1 BMU */
P_CLK_COR_LNK1_BMU_DIS = 1<<2, /* Disable Clock Core Link1 BMU */
P_CLK_PCI_LNK1_BIU_DIS = 1<<1, /* Disable Clock PCI Link1 BIU */
P_CLK_COR_LNK1_BIU_DIS = 1<<0, /* Disable Clock Core Link1 BIU */
PCIE_OUR3_WOL_D3_COLD_SET = P_CLK_ASF_REGS_DIS |
P_CLK_COR_REGS_D0_DIS |
P_CLK_COR_LNK1_D0_DIS |
P_CLK_MAC_LNK1_D0_DIS |
P_CLK_PCI_MST_ARB_DIS |
P_CLK_COR_COMMON_DIS |
P_CLK_COR_LNK1_BMU_DIS,
};
/* PCI_OUR_REG_4 32 bit Our Register 4 (Yukon-ECU only) */
enum pci_dev_reg_4 {
/* (Link Training & Status State Machine) */
P_PEX_LTSSM_STAT_MSK = 0x7fL<<25, /* Bit 31..25: PEX LTSSM Mask */
#define P_PEX_LTSSM_STAT(x) ((x << 25) & P_PEX_LTSSM_STAT_MSK)
P_PEX_LTSSM_L1_STAT = 0x34,
P_PEX_LTSSM_DET_STAT = 0x01,
P_TIMER_VALUE_MSK = 0xffL<<16, /* Bit 23..16: Timer Value Mask */
/* (Active State Power Management) */
P_FORCE_ASPM_REQUEST = 1<<15, /* Force ASPM Request (A1 only) */
P_ASPM_GPHY_LINK_DOWN = 1<<14, /* GPHY Link Down (A1 only) */
P_ASPM_INT_FIFO_EMPTY = 1<<13, /* Internal FIFO Empty (A1 only) */
P_ASPM_CLKRUN_REQUEST = 1<<12, /* CLKRUN Request (A1 only) */
P_ASPM_FORCE_CLKREQ_ENA = 1<<4, /* Force CLKREQ Enable (A1b only) */
P_ASPM_CLKREQ_PAD_CTL = 1<<3, /* CLKREQ PAD Control (A1 only) */
P_ASPM_A1_MODE_SELECT = 1<<2, /* A1 Mode Select (A1 only) */
P_CLK_GATE_PEX_UNIT_ENA = 1<<1, /* Enable Gate PEX Unit Clock */
P_CLK_GATE_ROOT_COR_ENA = 1<<0, /* Enable Gate Root Core Clock */
P_ASPM_CONTROL_MSK = P_FORCE_ASPM_REQUEST | P_ASPM_GPHY_LINK_DOWN
| P_ASPM_CLKRUN_REQUEST | P_ASPM_INT_FIFO_EMPTY,
};
/* PCI_OUR_REG_5 32 bit Our Register 5 (Yukon-ECU only) */
enum pci_dev_reg_5 {
/* Bit 31..27: for A3 & later */
P_CTL_DIV_CORE_CLK_ENA = 1<<31, /* Divide Core Clock Enable */
P_CTL_SRESET_VMAIN_AV = 1<<30, /* Soft Reset for Vmain_av De-Glitch */
P_CTL_BYPASS_VMAIN_AV = 1<<29, /* Bypass En. for Vmain_av De-Glitch */
P_CTL_TIM_VMAIN_AV_MSK = 3<<27, /* Bit 28..27: Timer Vmain_av Mask */
/* Bit 26..16: Release Clock on Event */
P_REL_PCIE_RST_DE_ASS = 1<<26, /* PCIe Reset De-Asserted */
P_REL_GPHY_REC_PACKET = 1<<25, /* GPHY Received Packet */
P_REL_INT_FIFO_N_EMPTY = 1<<24, /* Internal FIFO Not Empty */
P_REL_MAIN_PWR_AVAIL = 1<<23, /* Main Power Available */
P_REL_CLKRUN_REQ_REL = 1<<22, /* CLKRUN Request Release */
P_REL_PCIE_RESET_ASS = 1<<21, /* PCIe Reset Asserted */
P_REL_PME_ASSERTED = 1<<20, /* PME Asserted */
P_REL_PCIE_EXIT_L1_ST = 1<<19, /* PCIe Exit L1 State */
P_REL_LOADER_NOT_FIN = 1<<18, /* EPROM Loader Not Finished */
P_REL_PCIE_RX_EX_IDLE = 1<<17, /* PCIe Rx Exit Electrical Idle State */
P_REL_GPHY_LINK_UP = 1<<16, /* GPHY Link Up */
/* Bit 10.. 0: Mask for Gate Clock */
P_GAT_PCIE_RST_ASSERTED = 1<<10,/* PCIe Reset Asserted */
P_GAT_GPHY_N_REC_PACKET = 1<<9, /* GPHY Not Received Packet */
P_GAT_INT_FIFO_EMPTY = 1<<8, /* Internal FIFO Empty */
P_GAT_MAIN_PWR_N_AVAIL = 1<<7, /* Main Power Not Available */
P_GAT_CLKRUN_REQ_REL = 1<<6, /* CLKRUN Not Requested */
P_GAT_PCIE_RESET_ASS = 1<<5, /* PCIe Reset Asserted */
P_GAT_PME_DE_ASSERTED = 1<<4, /* PME De-Asserted */
P_GAT_PCIE_ENTER_L1_ST = 1<<3, /* PCIe Enter L1 State */
P_GAT_LOADER_FINISHED = 1<<2, /* EPROM Loader Finished */
P_GAT_PCIE_RX_EL_IDLE = 1<<1, /* PCIe Rx Electrical Idle State */
P_GAT_GPHY_LINK_DOWN = 1<<0, /* GPHY Link Down */
PCIE_OUR5_EVENT_CLK_D3_SET = P_REL_GPHY_REC_PACKET |
P_REL_INT_FIFO_N_EMPTY |
P_REL_PCIE_EXIT_L1_ST |
P_REL_PCIE_RX_EX_IDLE |
P_GAT_GPHY_N_REC_PACKET |
P_GAT_INT_FIFO_EMPTY |
P_GAT_PCIE_ENTER_L1_ST |
P_GAT_PCIE_RX_EL_IDLE,
};
/* PCI_CFG_REG_1 32 bit Config Register 1 (Yukon-Ext only) */
enum pci_cfg_reg1 {
P_CF1_DIS_REL_EVT_RST = 1<<24, /* Dis. Rel. Event during PCIE reset */
/* Bit 23..21: Release Clock on Event */
P_CF1_REL_LDR_NOT_FIN = 1<<23, /* EEPROM Loader Not Finished */
P_CF1_REL_VMAIN_AVLBL = 1<<22, /* Vmain available */
P_CF1_REL_PCIE_RESET = 1<<21, /* PCI-E reset */
/* Bit 20..18: Gate Clock on Event */
P_CF1_GAT_LDR_NOT_FIN = 1<<20, /* EEPROM Loader Finished */
P_CF1_GAT_PCIE_RX_IDLE = 1<<19, /* PCI-E Rx Electrical idle */
P_CF1_GAT_PCIE_RESET = 1<<18, /* PCI-E Reset */
P_CF1_PRST_PHY_CLKREQ = 1<<17, /* Enable PCI-E rst & PM2PHY gen. CLKREQ */
P_CF1_PCIE_RST_CLKREQ = 1<<16, /* Enable PCI-E rst generate CLKREQ */
P_CF1_ENA_CFG_LDR_DONE = 1<<8, /* Enable core level Config loader done */
P_CF1_ENA_TXBMU_RD_IDLE = 1<<1, /* Enable TX BMU Read IDLE for ASPM */
P_CF1_ENA_TXBMU_WR_IDLE = 1<<0, /* Enable TX BMU Write IDLE for ASPM */
PCIE_CFG1_EVENT_CLK_D3_SET = P_CF1_DIS_REL_EVT_RST |
P_CF1_REL_LDR_NOT_FIN |
P_CF1_REL_VMAIN_AVLBL |
P_CF1_REL_PCIE_RESET |
P_CF1_GAT_LDR_NOT_FIN |
P_CF1_GAT_PCIE_RESET |
P_CF1_PRST_PHY_CLKREQ |
P_CF1_ENA_CFG_LDR_DONE |
P_CF1_ENA_TXBMU_RD_IDLE |
P_CF1_ENA_TXBMU_WR_IDLE,
};
/* Yukon-Optima */
enum {
PSM_CONFIG_REG1_AC_PRESENT_STATUS = 1<<31, /* AC Present Status */
PSM_CONFIG_REG1_PTP_CLK_SEL = 1<<29, /* PTP Clock Select */
PSM_CONFIG_REG1_PTP_MODE = 1<<28, /* PTP Mode */
PSM_CONFIG_REG1_MUX_PHY_LINK = 1<<27, /* PHY Energy Detect Event */
PSM_CONFIG_REG1_EN_PIN63_AC_PRESENT = 1<<26, /* Enable LED_DUPLEX for ac_present */
PSM_CONFIG_REG1_EN_PCIE_TIMER = 1<<25, /* Enable PCIe Timer */
PSM_CONFIG_REG1_EN_SPU_TIMER = 1<<24, /* Enable SPU Timer */
PSM_CONFIG_REG1_POLARITY_AC_PRESENT = 1<<23, /* AC Present Polarity */
PSM_CONFIG_REG1_EN_AC_PRESENT = 1<<21, /* Enable AC Present */
PSM_CONFIG_REG1_EN_GPHY_INT_PSM = 1<<20, /* Enable GPHY INT for PSM */
PSM_CONFIG_REG1_DIS_PSM_TIMER = 1<<19, /* Disable PSM Timer */
};
/* Yukon-Supreme */
enum {
PSM_CONFIG_REG1_GPHY_ENERGY_STS = 1<<31, /* GPHY Energy Detect Status */
PSM_CONFIG_REG1_UART_MODE_MSK = 3<<29, /* UART_Mode */
PSM_CONFIG_REG1_CLK_RUN_ASF = 1<<28, /* Enable Clock Free Running for ASF Subsystem */
PSM_CONFIG_REG1_UART_CLK_DISABLE= 1<<27, /* Disable UART clock */
PSM_CONFIG_REG1_VAUX_ONE = 1<<26, /* Tie internal Vaux to 1'b1 */
PSM_CONFIG_REG1_UART_FC_RI_VAL = 1<<25, /* Default value for UART_RI_n */
PSM_CONFIG_REG1_UART_FC_DCD_VAL = 1<<24, /* Default value for UART_DCD_n */
PSM_CONFIG_REG1_UART_FC_DSR_VAL = 1<<23, /* Default value for UART_DSR_n */
PSM_CONFIG_REG1_UART_FC_CTS_VAL = 1<<22, /* Default value for UART_CTS_n */
PSM_CONFIG_REG1_LATCH_VAUX = 1<<21, /* Enable Latch current Vaux_avlbl */
PSM_CONFIG_REG1_FORCE_TESTMODE_INPUT= 1<<20, /* Force Testmode pin as input PAD */
PSM_CONFIG_REG1_UART_RST = 1<<19, /* UART_RST */
PSM_CONFIG_REG1_PSM_PCIE_L1_POL = 1<<18, /* PCIE L1 Event Polarity for PSM */
PSM_CONFIG_REG1_TIMER_STAT = 1<<17, /* PSM Timer Status */
PSM_CONFIG_REG1_GPHY_INT = 1<<16, /* GPHY INT Status */
PSM_CONFIG_REG1_FORCE_TESTMODE_ZERO= 1<<15, /* Force internal Testmode as 1'b0 */
PSM_CONFIG_REG1_EN_INT_ASPM_CLKREQ = 1<<14, /* ENABLE INT for CLKRUN on ASPM and CLKREQ */
PSM_CONFIG_REG1_EN_SND_TASK_ASPM_CLKREQ = 1<<13, /* ENABLE Snd_task for CLKRUN on ASPM and CLKREQ */
PSM_CONFIG_REG1_DIS_CLK_GATE_SND_TASK = 1<<12, /* Disable CLK_GATE control snd_task */
PSM_CONFIG_REG1_DIS_FF_CHIAN_SND_INTA = 1<<11, /* Disable flip-flop chain for sndmsg_inta */
PSM_CONFIG_REG1_DIS_LOADER = 1<<9, /* Disable Loader SM after PSM Goes back to IDLE */
PSM_CONFIG_REG1_DO_PWDN = 1<<8, /* Do Power Down, Start PSM Scheme */
PSM_CONFIG_REG1_DIS_PIG = 1<<7, /* Disable Plug-in-Go SM after PSM Goes back to IDLE */
PSM_CONFIG_REG1_DIS_PERST = 1<<6, /* Disable Internal PCIe Reset after PSM Goes back to IDLE */
PSM_CONFIG_REG1_EN_REG18_PD = 1<<5, /* Enable REG18 Power Down for PSM */
PSM_CONFIG_REG1_EN_PSM_LOAD = 1<<4, /* Disable EEPROM Loader after PSM Goes back to IDLE */
PSM_CONFIG_REG1_EN_PSM_HOT_RST = 1<<3, /* Enable PCIe Hot Reset for PSM */
PSM_CONFIG_REG1_EN_PSM_PERST = 1<<2, /* Enable PCIe Reset Event for PSM */
PSM_CONFIG_REG1_EN_PSM_PCIE_L1 = 1<<1, /* Enable PCIe L1 Event for PSM */
PSM_CONFIG_REG1_EN_PSM = 1<<0, /* Enable PSM Scheme */
};
/* PSM_CONFIG_REG4 0x0168 PSM Config Register 4 */
enum {
/* PHY Link Detect Timer */
PSM_CONFIG_REG4_TIMER_PHY_LINK_DETECT_MSK = 0xf<<4,
PSM_CONFIG_REG4_TIMER_PHY_LINK_DETECT_BASE = 4,
PSM_CONFIG_REG4_DEBUG_TIMER = 1<<1, /* Debug Timer */
PSM_CONFIG_REG4_RST_PHY_LINK_DETECT = 1<<0, /* Reset GPHY Link Detect */
};
#define PCI_STATUS_ERROR_BITS (PCI_STATUS_DETECTED_PARITY | \
PCI_STATUS_SIG_SYSTEM_ERROR | \
PCI_STATUS_REC_MASTER_ABORT | \
PCI_STATUS_REC_TARGET_ABORT | \
PCI_STATUS_PARITY)
enum csr_regs {
B0_RAP = 0x0000,
B0_CTST = 0x0004,
B0_POWER_CTRL = 0x0007,
B0_ISRC = 0x0008,
B0_IMSK = 0x000c,
B0_HWE_ISRC = 0x0010,
B0_HWE_IMSK = 0x0014,
/* Special ISR registers (Yukon-2 only) */
B0_Y2_SP_ISRC2 = 0x001c,
B0_Y2_SP_ISRC3 = 0x0020,
B0_Y2_SP_EISR = 0x0024,
B0_Y2_SP_LISR = 0x0028,
B0_Y2_SP_ICR = 0x002c,
B2_MAC_1 = 0x0100,
B2_MAC_2 = 0x0108,
B2_MAC_3 = 0x0110,
B2_CONN_TYP = 0x0118,
B2_PMD_TYP = 0x0119,
B2_MAC_CFG = 0x011a,
B2_CHIP_ID = 0x011b,
B2_E_0 = 0x011c,
B2_Y2_CLK_GATE = 0x011d,
B2_Y2_HW_RES = 0x011e,
B2_E_3 = 0x011f,
B2_Y2_CLK_CTRL = 0x0120,
B2_TI_INI = 0x0130,
B2_TI_VAL = 0x0134,
B2_TI_CTRL = 0x0138,
B2_TI_TEST = 0x0139,
B2_TST_CTRL1 = 0x0158,
B2_TST_CTRL2 = 0x0159,
B2_GP_IO = 0x015c,
B2_I2C_CTRL = 0x0160,
B2_I2C_DATA = 0x0164,
B2_I2C_IRQ = 0x0168,
B2_I2C_SW = 0x016c,
Y2_PEX_PHY_DATA = 0x0170,
Y2_PEX_PHY_ADDR = 0x0172,
B3_RAM_ADDR = 0x0180,
B3_RAM_DATA_LO = 0x0184,
B3_RAM_DATA_HI = 0x0188,
/* RAM Interface Registers */
/* Yukon-2: use RAM_BUFFER() to access the RAM buffer */
/*
* The HW-Spec. calls this registers Timeout Value 0..11. But this names are
* not usable in SW. Please notice these are NOT real timeouts, these are
* the number of qWords transferred continuously.
*/
#define RAM_BUFFER(port, reg) (reg | (port <<6))
B3_RI_WTO_R1 = 0x0190,
B3_RI_WTO_XA1 = 0x0191,
B3_RI_WTO_XS1 = 0x0192,
B3_RI_RTO_R1 = 0x0193,
B3_RI_RTO_XA1 = 0x0194,
B3_RI_RTO_XS1 = 0x0195,
B3_RI_WTO_R2 = 0x0196,
B3_RI_WTO_XA2 = 0x0197,
B3_RI_WTO_XS2 = 0x0198,
B3_RI_RTO_R2 = 0x0199,
B3_RI_RTO_XA2 = 0x019a,
B3_RI_RTO_XS2 = 0x019b,
B3_RI_TO_VAL = 0x019c,
B3_RI_CTRL = 0x01a0,
B3_RI_TEST = 0x01a2,
B3_MA_TOINI_RX1 = 0x01b0,
B3_MA_TOINI_RX2 = 0x01b1,
B3_MA_TOINI_TX1 = 0x01b2,
B3_MA_TOINI_TX2 = 0x01b3,
B3_MA_TOVAL_RX1 = 0x01b4,
B3_MA_TOVAL_RX2 = 0x01b5,
B3_MA_TOVAL_TX1 = 0x01b6,
B3_MA_TOVAL_TX2 = 0x01b7,
B3_MA_TO_CTRL = 0x01b8,
B3_MA_TO_TEST = 0x01ba,
B3_MA_RCINI_RX1 = 0x01c0,
B3_MA_RCINI_RX2 = 0x01c1,
B3_MA_RCINI_TX1 = 0x01c2,
B3_MA_RCINI_TX2 = 0x01c3,
B3_MA_RCVAL_RX1 = 0x01c4,
B3_MA_RCVAL_RX2 = 0x01c5,
B3_MA_RCVAL_TX1 = 0x01c6,
B3_MA_RCVAL_TX2 = 0x01c7,
B3_MA_RC_CTRL = 0x01c8,
B3_MA_RC_TEST = 0x01ca,
B3_PA_TOINI_RX1 = 0x01d0,
B3_PA_TOINI_RX2 = 0x01d4,
B3_PA_TOINI_TX1 = 0x01d8,
B3_PA_TOINI_TX2 = 0x01dc,
B3_PA_TOVAL_RX1 = 0x01e0,
B3_PA_TOVAL_RX2 = 0x01e4,
B3_PA_TOVAL_TX1 = 0x01e8,
B3_PA_TOVAL_TX2 = 0x01ec,
B3_PA_CTRL = 0x01f0,
B3_PA_TEST = 0x01f2,
Y2_CFG_SPC = 0x1c00, /* PCI config space region */
Y2_CFG_AER = 0x1d00, /* PCI Advanced Error Report region */
};
/* B0_CTST 24 bit Control/Status register */
enum {
Y2_VMAIN_AVAIL = 1<<17,/* VMAIN available (YUKON-2 only) */
Y2_VAUX_AVAIL = 1<<16,/* VAUX available (YUKON-2 only) */
Y2_HW_WOL_ON = 1<<15,/* HW WOL On (Yukon-EC Ultra A1 only) */
Y2_HW_WOL_OFF = 1<<14,/* HW WOL On (Yukon-EC Ultra A1 only) */
Y2_ASF_ENABLE = 1<<13,/* ASF Unit Enable (YUKON-2 only) */
Y2_ASF_DISABLE = 1<<12,/* ASF Unit Disable (YUKON-2 only) */
Y2_CLK_RUN_ENA = 1<<11,/* CLK_RUN Enable (YUKON-2 only) */
Y2_CLK_RUN_DIS = 1<<10,/* CLK_RUN Disable (YUKON-2 only) */
Y2_LED_STAT_ON = 1<<9, /* Status LED On (YUKON-2 only) */
Y2_LED_STAT_OFF = 1<<8, /* Status LED Off (YUKON-2 only) */
CS_ST_SW_IRQ = 1<<7, /* Set IRQ SW Request */
CS_CL_SW_IRQ = 1<<6, /* Clear IRQ SW Request */
CS_STOP_DONE = 1<<5, /* Stop Master is finished */
CS_STOP_MAST = 1<<4, /* Command Bit to stop the master */
CS_MRST_CLR = 1<<3, /* Clear Master reset */
CS_MRST_SET = 1<<2, /* Set Master reset */
CS_RST_CLR = 1<<1, /* Clear Software reset */
CS_RST_SET = 1, /* Set Software reset */
};
/* B0_POWER_CTRL 8 Bit Power Control reg (YUKON only) */
enum {
PC_VAUX_ENA = 1<<7, /* Switch VAUX Enable */
PC_VAUX_DIS = 1<<6, /* Switch VAUX Disable */
PC_VCC_ENA = 1<<5, /* Switch VCC Enable */
PC_VCC_DIS = 1<<4, /* Switch VCC Disable */
PC_VAUX_ON = 1<<3, /* Switch VAUX On */
PC_VAUX_OFF = 1<<2, /* Switch VAUX Off */
PC_VCC_ON = 1<<1, /* Switch VCC On */
PC_VCC_OFF = 1<<0, /* Switch VCC Off */
};
/* B2_IRQM_MSK 32 bit IRQ Moderation Mask */
/* B0_Y2_SP_ISRC2 32 bit Special Interrupt Source Reg 2 */
/* B0_Y2_SP_ISRC3 32 bit Special Interrupt Source Reg 3 */
/* B0_Y2_SP_EISR 32 bit Enter ISR Reg */
/* B0_Y2_SP_LISR 32 bit Leave ISR Reg */
enum {
Y2_IS_HW_ERR = 1<<31, /* Interrupt HW Error */
Y2_IS_STAT_BMU = 1<<30, /* Status BMU Interrupt */
Y2_IS_ASF = 1<<29, /* ASF subsystem Interrupt */
Y2_IS_POLL_CHK = 1<<27, /* Check IRQ from polling unit */
Y2_IS_TWSI_RDY = 1<<26, /* IRQ on end of TWSI Tx */
Y2_IS_IRQ_SW = 1<<25, /* SW forced IRQ */
Y2_IS_TIMINT = 1<<24, /* IRQ from Timer */
Y2_IS_IRQ_PHY2 = 1<<12, /* Interrupt from PHY 2 */
Y2_IS_IRQ_MAC2 = 1<<11, /* Interrupt from MAC 2 */
Y2_IS_CHK_RX2 = 1<<10, /* Descriptor error Rx 2 */
Y2_IS_CHK_TXS2 = 1<<9, /* Descriptor error TXS 2 */
Y2_IS_CHK_TXA2 = 1<<8, /* Descriptor error TXA 2 */
Y2_IS_PSM_ACK = 1<<7, /* PSM Acknowledge (Yukon-Optima only) */
Y2_IS_PTP_TIST = 1<<6, /* PTP Time Stamp (Yukon-Optima only) */
Y2_IS_PHY_QLNK = 1<<5, /* PHY Quick Link (Yukon-Optima only) */
Y2_IS_IRQ_PHY1 = 1<<4, /* Interrupt from PHY 1 */
Y2_IS_IRQ_MAC1 = 1<<3, /* Interrupt from MAC 1 */
Y2_IS_CHK_RX1 = 1<<2, /* Descriptor error Rx 1 */
Y2_IS_CHK_TXS1 = 1<<1, /* Descriptor error TXS 1 */
Y2_IS_CHK_TXA1 = 1<<0, /* Descriptor error TXA 1 */
Y2_IS_BASE = Y2_IS_HW_ERR | Y2_IS_STAT_BMU,
Y2_IS_PORT_1 = Y2_IS_IRQ_PHY1 | Y2_IS_IRQ_MAC1
| Y2_IS_CHK_TXA1 | Y2_IS_CHK_RX1,
Y2_IS_PORT_2 = Y2_IS_IRQ_PHY2 | Y2_IS_IRQ_MAC2
| Y2_IS_CHK_TXA2 | Y2_IS_CHK_RX2,
Y2_IS_ERROR = Y2_IS_HW_ERR |
Y2_IS_IRQ_MAC1 | Y2_IS_CHK_TXA1 | Y2_IS_CHK_RX1 |
Y2_IS_IRQ_MAC2 | Y2_IS_CHK_TXA2 | Y2_IS_CHK_RX2,
};
/* B2_IRQM_HWE_MSK 32 bit IRQ Moderation HW Error Mask */
enum {
IS_ERR_MSK = 0x00003fff,/* All Error bits */
IS_IRQ_TIST_OV = 1<<13, /* Time Stamp Timer Overflow (YUKON only) */
IS_IRQ_SENSOR = 1<<12, /* IRQ from Sensor (YUKON only) */
IS_IRQ_MST_ERR = 1<<11, /* IRQ master error detected */
IS_IRQ_STAT = 1<<10, /* IRQ status exception */
IS_NO_STAT_M1 = 1<<9, /* No Rx Status from MAC 1 */
IS_NO_STAT_M2 = 1<<8, /* No Rx Status from MAC 2 */
IS_NO_TIST_M1 = 1<<7, /* No Time Stamp from MAC 1 */
IS_NO_TIST_M2 = 1<<6, /* No Time Stamp from MAC 2 */
IS_RAM_RD_PAR = 1<<5, /* RAM Read Parity Error */
IS_RAM_WR_PAR = 1<<4, /* RAM Write Parity Error */
IS_M1_PAR_ERR = 1<<3, /* MAC 1 Parity Error */
IS_M2_PAR_ERR = 1<<2, /* MAC 2 Parity Error */
IS_R1_PAR_ERR = 1<<1, /* Queue R1 Parity Error */
IS_R2_PAR_ERR = 1<<0, /* Queue R2 Parity Error */
};
/* Hardware error interrupt mask for Yukon 2 */
enum {
Y2_IS_TIST_OV = 1<<29,/* Time Stamp Timer overflow interrupt */
Y2_IS_SENSOR = 1<<28, /* Sensor interrupt */
Y2_IS_MST_ERR = 1<<27, /* Master error interrupt */
Y2_IS_IRQ_STAT = 1<<26, /* Status exception interrupt */
Y2_IS_PCI_EXP = 1<<25, /* PCI-Express interrupt */
Y2_IS_PCI_NEXP = 1<<24, /* PCI-Express error similar to PCI error */
/* Link 2 */
Y2_IS_PAR_RD2 = 1<<13, /* Read RAM parity error interrupt */
Y2_IS_PAR_WR2 = 1<<12, /* Write RAM parity error interrupt */
Y2_IS_PAR_MAC2 = 1<<11, /* MAC hardware fault interrupt */
Y2_IS_PAR_RX2 = 1<<10, /* Parity Error Rx Queue 2 */
Y2_IS_TCP_TXS2 = 1<<9, /* TCP length mismatch sync Tx queue IRQ */
Y2_IS_TCP_TXA2 = 1<<8, /* TCP length mismatch async Tx queue IRQ */
/* Link 1 */
Y2_IS_PAR_RD1 = 1<<5, /* Read RAM parity error interrupt */
Y2_IS_PAR_WR1 = 1<<4, /* Write RAM parity error interrupt */
Y2_IS_PAR_MAC1 = 1<<3, /* MAC hardware fault interrupt */
Y2_IS_PAR_RX1 = 1<<2, /* Parity Error Rx Queue 1 */
Y2_IS_TCP_TXS1 = 1<<1, /* TCP length mismatch sync Tx queue IRQ */
Y2_IS_TCP_TXA1 = 1<<0, /* TCP length mismatch async Tx queue IRQ */
Y2_HWE_L1_MASK = Y2_IS_PAR_RD1 | Y2_IS_PAR_WR1 | Y2_IS_PAR_MAC1 |
Y2_IS_PAR_RX1 | Y2_IS_TCP_TXS1| Y2_IS_TCP_TXA1,
Y2_HWE_L2_MASK = Y2_IS_PAR_RD2 | Y2_IS_PAR_WR2 | Y2_IS_PAR_MAC2 |
Y2_IS_PAR_RX2 | Y2_IS_TCP_TXS2| Y2_IS_TCP_TXA2,
Y2_HWE_ALL_MASK = Y2_IS_TIST_OV | Y2_IS_MST_ERR | Y2_IS_IRQ_STAT |
Y2_HWE_L1_MASK | Y2_HWE_L2_MASK,
};
/* B28_DPT_CTRL 8 bit Descriptor Poll Timer Ctrl Reg */
enum {
DPT_START = 1<<1,
DPT_STOP = 1<<0,
};
/* B2_TST_CTRL1 8 bit Test Control Register 1 */
enum {
TST_FRC_DPERR_MR = 1<<7, /* force DATAPERR on MST RD */
TST_FRC_DPERR_MW = 1<<6, /* force DATAPERR on MST WR */
TST_FRC_DPERR_TR = 1<<5, /* force DATAPERR on TRG RD */
TST_FRC_DPERR_TW = 1<<4, /* force DATAPERR on TRG WR */
TST_FRC_APERR_M = 1<<3, /* force ADDRPERR on MST */
TST_FRC_APERR_T = 1<<2, /* force ADDRPERR on TRG */
TST_CFG_WRITE_ON = 1<<1, /* Enable Config Reg WR */
TST_CFG_WRITE_OFF= 1<<0, /* Disable Config Reg WR */
};
/* B2_GPIO */
enum {
GLB_GPIO_CLK_DEB_ENA = 1<<31, /* Clock Debug Enable */
GLB_GPIO_CLK_DBG_MSK = 0xf<<26, /* Clock Debug */
GLB_GPIO_INT_RST_D3_DIS = 1<<15, /* Disable Internal Reset After D3 to D0 */
GLB_GPIO_LED_PAD_SPEED_UP = 1<<14, /* LED PAD Speed Up */
GLB_GPIO_STAT_RACE_DIS = 1<<13, /* Status Race Disable */
GLB_GPIO_TEST_SEL_MSK = 3<<11, /* Testmode Select */
GLB_GPIO_TEST_SEL_BASE = 1<<11,
GLB_GPIO_RAND_ENA = 1<<10, /* Random Enable */
GLB_GPIO_RAND_BIT_1 = 1<<9, /* Random Bit 1 */
};
/* B2_MAC_CFG 8 bit MAC Configuration / Chip Revision */
enum {
CFG_CHIP_R_MSK = 0xf<<4, /* Bit 7.. 4: Chip Revision */
/* Bit 3.. 2: reserved */
CFG_DIS_M2_CLK = 1<<1, /* Disable Clock for 2nd MAC */
CFG_SNG_MAC = 1<<0, /* MAC Config: 0=2 MACs / 1=1 MAC*/
};
/* B2_CHIP_ID 8 bit Chip Identification Number */
enum {
CHIP_ID_YUKON_XL = 0xb3, /* YUKON-2 XL */
CHIP_ID_YUKON_EC_U = 0xb4, /* YUKON-2 EC Ultra */
CHIP_ID_YUKON_EX = 0xb5, /* YUKON-2 Extreme */
CHIP_ID_YUKON_EC = 0xb6, /* YUKON-2 EC */
CHIP_ID_YUKON_FE = 0xb7, /* YUKON-2 FE */
CHIP_ID_YUKON_FE_P = 0xb8, /* YUKON-2 FE+ */
CHIP_ID_YUKON_SUPR = 0xb9, /* YUKON-2 Supreme */
CHIP_ID_YUKON_UL_2 = 0xba, /* YUKON-2 Ultra 2 */
CHIP_ID_YUKON_OPT = 0xbc, /* YUKON-2 Optima */
};
enum yukon_ec_rev {
CHIP_REV_YU_EC_A1 = 0, /* Chip Rev. for Yukon-EC A1/A0 */
CHIP_REV_YU_EC_A2 = 1, /* Chip Rev. for Yukon-EC A2 */
CHIP_REV_YU_EC_A3 = 2, /* Chip Rev. for Yukon-EC A3 */
};
enum yukon_ec_u_rev {
CHIP_REV_YU_EC_U_A0 = 1,
CHIP_REV_YU_EC_U_A1 = 2,
CHIP_REV_YU_EC_U_B0 = 3,
};
enum yukon_fe_rev {
CHIP_REV_YU_FE_A1 = 1,
CHIP_REV_YU_FE_A2 = 2,
};
enum yukon_fe_p_rev {
CHIP_REV_YU_FE2_A0 = 0,
};
enum yukon_ex_rev {
CHIP_REV_YU_EX_A0 = 1,
CHIP_REV_YU_EX_B0 = 2,
};
enum yukon_supr_rev {
CHIP_REV_YU_SU_A0 = 0,
CHIP_REV_YU_SU_B0 = 1,
CHIP_REV_YU_SU_B1 = 3,
};
/* B2_Y2_CLK_GATE 8 bit Clock Gating (Yukon-2 only) */
enum {
Y2_STATUS_LNK2_INAC = 1<<7, /* Status Link 2 inactive (0 = active) */
Y2_CLK_GAT_LNK2_DIS = 1<<6, /* Disable clock gating Link 2 */
Y2_COR_CLK_LNK2_DIS = 1<<5, /* Disable Core clock Link 2 */
Y2_PCI_CLK_LNK2_DIS = 1<<4, /* Disable PCI clock Link 2 */
Y2_STATUS_LNK1_INAC = 1<<3, /* Status Link 1 inactive (0 = active) */
Y2_CLK_GAT_LNK1_DIS = 1<<2, /* Disable clock gating Link 1 */
Y2_COR_CLK_LNK1_DIS = 1<<1, /* Disable Core clock Link 1 */
Y2_PCI_CLK_LNK1_DIS = 1<<0, /* Disable PCI clock Link 1 */
};
/* B2_Y2_HW_RES 8 bit HW Resources (Yukon-2 only) */
enum {
CFG_LED_MODE_MSK = 7<<2, /* Bit 4.. 2: LED Mode Mask */
CFG_LINK_2_AVAIL = 1<<1, /* Link 2 available */
CFG_LINK_1_AVAIL = 1<<0, /* Link 1 available */
};
#define CFG_LED_MODE(x) (((x) & CFG_LED_MODE_MSK) >> 2)
#define CFG_DUAL_MAC_MSK (CFG_LINK_2_AVAIL | CFG_LINK_1_AVAIL)
/* B2_Y2_CLK_CTRL 32 bit Clock Frequency Control Register (Yukon-2/EC) */
enum {
Y2_CLK_DIV_VAL_MSK = 0xff<<16,/* Bit 23..16: Clock Divisor Value */
#define Y2_CLK_DIV_VAL(x) (((x)<<16) & Y2_CLK_DIV_VAL_MSK)
Y2_CLK_DIV_VAL2_MSK = 7<<21, /* Bit 23..21: Clock Divisor Value */
Y2_CLK_SELECT2_MSK = 0x1f<<16,/* Bit 20..16: Clock Select */
#define Y2_CLK_DIV_VAL_2(x) (((x)<<21) & Y2_CLK_DIV_VAL2_MSK)
#define Y2_CLK_SEL_VAL_2(x) (((x)<<16) & Y2_CLK_SELECT2_MSK)
Y2_CLK_DIV_ENA = 1<<1, /* Enable Core Clock Division */
Y2_CLK_DIV_DIS = 1<<0, /* Disable Core Clock Division */
};
/* B2_TI_CTRL 8 bit Timer control */
/* B2_IRQM_CTRL 8 bit IRQ Moderation Timer Control */
enum {
TIM_START = 1<<2, /* Start Timer */
TIM_STOP = 1<<1, /* Stop Timer */
TIM_CLR_IRQ = 1<<0, /* Clear Timer IRQ (!IRQM) */
};
/* B2_TI_TEST 8 Bit Timer Test */
/* B2_IRQM_TEST 8 bit IRQ Moderation Timer Test */
/* B28_DPT_TST 8 bit Descriptor Poll Timer Test Reg */
enum {
TIM_T_ON = 1<<2, /* Test mode on */
TIM_T_OFF = 1<<1, /* Test mode off */
TIM_T_STEP = 1<<0, /* Test step */
};
/* Y2_PEX_PHY_ADDR/DATA PEX PHY address and data reg (Yukon-2 only) */
enum {
PEX_RD_ACCESS = 1<<31, /* Access Mode Read = 1, Write = 0 */
PEX_DB_ACCESS = 1<<30, /* Access to debug register */
};
/* B3_RAM_ADDR 32 bit RAM Address, to read or write */
/* Bit 31..19: reserved */
#define RAM_ADR_RAN 0x0007ffffL /* Bit 18.. 0: RAM Address Range */
/* RAM Interface Registers */
/* B3_RI_CTRL 16 bit RAM Interface Control Register */
enum {
RI_CLR_RD_PERR = 1<<9, /* Clear IRQ RAM Read Parity Err */
RI_CLR_WR_PERR = 1<<8, /* Clear IRQ RAM Write Parity Err*/
RI_RST_CLR = 1<<1, /* Clear RAM Interface Reset */
RI_RST_SET = 1<<0, /* Set RAM Interface Reset */
};
#define SK_RI_TO_53 36 /* RAM interface timeout */
/* Port related registers FIFO, and Arbiter */
#define SK_REG(port,reg) (((port)<<7)+(reg))
/* Transmit Arbiter Registers MAC 1 and 2, use SK_REG() to access */
/* TXA_ITI_INI 32 bit Tx Arb Interval Timer Init Val */
/* TXA_ITI_VAL 32 bit Tx Arb Interval Timer Value */
/* TXA_LIM_INI 32 bit Tx Arb Limit Counter Init Val */
/* TXA_LIM_VAL 32 bit Tx Arb Limit Counter Value */
#define TXA_MAX_VAL 0x00ffffffUL /* Bit 23.. 0: Max TXA Timer/Cnt Val */
/* TXA_CTRL 8 bit Tx Arbiter Control Register */
enum {
TXA_ENA_FSYNC = 1<<7, /* Enable force of sync Tx queue */
TXA_DIS_FSYNC = 1<<6, /* Disable force of sync Tx queue */
TXA_ENA_ALLOC = 1<<5, /* Enable alloc of free bandwidth */
TXA_DIS_ALLOC = 1<<4, /* Disable alloc of free bandwidth */
TXA_START_RC = 1<<3, /* Start sync Rate Control */
TXA_STOP_RC = 1<<2, /* Stop sync Rate Control */
TXA_ENA_ARB = 1<<1, /* Enable Tx Arbiter */
TXA_DIS_ARB = 1<<0, /* Disable Tx Arbiter */
};
/*
* Bank 4 - 5
*/
/* Transmit Arbiter Registers MAC 1 and 2, use SK_REG() to access */
enum {
TXA_ITI_INI = 0x0200,/* 32 bit Tx Arb Interval Timer Init Val*/
TXA_ITI_VAL = 0x0204,/* 32 bit Tx Arb Interval Timer Value */
TXA_LIM_INI = 0x0208,/* 32 bit Tx Arb Limit Counter Init Val */
TXA_LIM_VAL = 0x020c,/* 32 bit Tx Arb Limit Counter Value */
TXA_CTRL = 0x0210,/* 8 bit Tx Arbiter Control Register */
TXA_TEST = 0x0211,/* 8 bit Tx Arbiter Test Register */
TXA_STAT = 0x0212,/* 8 bit Tx Arbiter Status Register */
};
enum {
B6_EXT_REG = 0x0300,/* External registers (GENESIS only) */
B7_CFG_SPC = 0x0380,/* copy of the Configuration register */
B8_RQ1_REGS = 0x0400,/* Receive Queue 1 */
B8_RQ2_REGS = 0x0480,/* Receive Queue 2 */
B8_TS1_REGS = 0x0600,/* Transmit sync queue 1 */
B8_TA1_REGS = 0x0680,/* Transmit async queue 1 */
B8_TS2_REGS = 0x0700,/* Transmit sync queue 2 */
B8_TA2_REGS = 0x0780,/* Transmit sync queue 2 */
B16_RAM_REGS = 0x0800,/* RAM Buffer Registers */
};
/* Queue Register Offsets, use Q_ADDR() to access */
enum {
B8_Q_REGS = 0x0400, /* base of Queue registers */
Q_D = 0x00, /* 8*32 bit Current Descriptor */
Q_VLAN = 0x20, /* 16 bit Current VLAN Tag */
Q_DONE = 0x24, /* 16 bit Done Index */
Q_AC_L = 0x28, /* 32 bit Current Address Counter Low dWord */
Q_AC_H = 0x2c, /* 32 bit Current Address Counter High dWord */
Q_BC = 0x30, /* 32 bit Current Byte Counter */
Q_CSR = 0x34, /* 32 bit BMU Control/Status Register */
Q_TEST = 0x38, /* 32 bit Test/Control Register */
/* Yukon-2 */
Q_WM = 0x40, /* 16 bit FIFO Watermark */
Q_AL = 0x42, /* 8 bit FIFO Alignment */
Q_RSP = 0x44, /* 16 bit FIFO Read Shadow Pointer */
Q_RSL = 0x46, /* 8 bit FIFO Read Shadow Level */
Q_RP = 0x48, /* 8 bit FIFO Read Pointer */
Q_RL = 0x4a, /* 8 bit FIFO Read Level */
Q_WP = 0x4c, /* 8 bit FIFO Write Pointer */
Q_WSP = 0x4d, /* 8 bit FIFO Write Shadow Pointer */
Q_WL = 0x4e, /* 8 bit FIFO Write Level */
Q_WSL = 0x4f, /* 8 bit FIFO Write Shadow Level */
};
#define Q_ADDR(reg, offs) (B8_Q_REGS + (reg) + (offs))
/* Q_TEST 32 bit Test Register */
enum {
/* Transmit */
F_TX_CHK_AUTO_OFF = 1<<31, /* Tx checksum auto calc off (Yukon EX) */
F_TX_CHK_AUTO_ON = 1<<30, /* Tx checksum auto calc off (Yukon EX) */
/* Receive */
F_M_RX_RAM_DIS = 1<<24, /* MAC Rx RAM Read Port disable */
/* Hardware testbits not used */
};
/* Queue Prefetch Unit Offsets, use Y2_QADDR() to address (Yukon-2 only)*/
enum {
Y2_B8_PREF_REGS = 0x0450,
PREF_UNIT_CTRL = 0x00, /* 32 bit Control register */
PREF_UNIT_LAST_IDX = 0x04, /* 16 bit Last Index */
PREF_UNIT_ADDR_LO = 0x08, /* 32 bit List start addr, low part */
PREF_UNIT_ADDR_HI = 0x0c, /* 32 bit List start addr, high part*/
PREF_UNIT_GET_IDX = 0x10, /* 16 bit Get Index */
PREF_UNIT_PUT_IDX = 0x14, /* 16 bit Put Index */
PREF_UNIT_FIFO_WP = 0x20, /* 8 bit FIFO write pointer */
PREF_UNIT_FIFO_RP = 0x24, /* 8 bit FIFO read pointer */
PREF_UNIT_FIFO_WM = 0x28, /* 8 bit FIFO watermark */
PREF_UNIT_FIFO_LEV = 0x2c, /* 8 bit FIFO level */
PREF_UNIT_MASK_IDX = 0x0fff,
};
#define Y2_QADDR(q,reg) (Y2_B8_PREF_REGS + (q) + (reg))
/* RAM Buffer Register Offsets */
enum {
RB_START = 0x00,/* 32 bit RAM Buffer Start Address */
RB_END = 0x04,/* 32 bit RAM Buffer End Address */
RB_WP = 0x08,/* 32 bit RAM Buffer Write Pointer */
RB_RP = 0x0c,/* 32 bit RAM Buffer Read Pointer */
RB_RX_UTPP = 0x10,/* 32 bit Rx Upper Threshold, Pause Packet */
RB_RX_LTPP = 0x14,/* 32 bit Rx Lower Threshold, Pause Packet */
RB_RX_UTHP = 0x18,/* 32 bit Rx Upper Threshold, High Prio */
RB_RX_LTHP = 0x1c,/* 32 bit Rx Lower Threshold, High Prio */
/* 0x10 - 0x1f: reserved at Tx RAM Buffer Registers */
RB_PC = 0x20,/* 32 bit RAM Buffer Packet Counter */
RB_LEV = 0x24,/* 32 bit RAM Buffer Level Register */
RB_CTRL = 0x28,/* 32 bit RAM Buffer Control Register */
RB_TST1 = 0x29,/* 8 bit RAM Buffer Test Register 1 */
RB_TST2 = 0x2a,/* 8 bit RAM Buffer Test Register 2 */
};
/* Receive and Transmit Queues */
enum {
Q_R1 = 0x0000, /* Receive Queue 1 */
Q_R2 = 0x0080, /* Receive Queue 2 */
Q_XS1 = 0x0200, /* Synchronous Transmit Queue 1 */
Q_XA1 = 0x0280, /* Asynchronous Transmit Queue 1 */
Q_XS2 = 0x0300, /* Synchronous Transmit Queue 2 */
Q_XA2 = 0x0380, /* Asynchronous Transmit Queue 2 */
};
/* Different PHY Types */
enum {
PHY_ADDR_MARV = 0,
};
#define RB_ADDR(offs, queue) ((u16) B16_RAM_REGS + (queue) + (offs))
enum {
LNK_SYNC_INI = 0x0c30,/* 32 bit Link Sync Cnt Init Value */
LNK_SYNC_VAL = 0x0c34,/* 32 bit Link Sync Cnt Current Value */
LNK_SYNC_CTRL = 0x0c38,/* 8 bit Link Sync Cnt Control Register */
LNK_SYNC_TST = 0x0c39,/* 8 bit Link Sync Cnt Test Register */
LNK_LED_REG = 0x0c3c,/* 8 bit Link LED Register */
/* Receive GMAC FIFO (YUKON and Yukon-2) */
RX_GMF_EA = 0x0c40,/* 32 bit Rx GMAC FIFO End Address */
RX_GMF_AF_THR = 0x0c44,/* 32 bit Rx GMAC FIFO Almost Full Thresh. */
RX_GMF_CTRL_T = 0x0c48,/* 32 bit Rx GMAC FIFO Control/Test */
RX_GMF_FL_MSK = 0x0c4c,/* 32 bit Rx GMAC FIFO Flush Mask */
RX_GMF_FL_THR = 0x0c50,/* 16 bit Rx GMAC FIFO Flush Threshold */
RX_GMF_FL_CTRL = 0x0c52,/* 16 bit Rx GMAC FIFO Flush Control */
RX_GMF_TR_THR = 0x0c54,/* 32 bit Rx Truncation Threshold (Yukon-2) */
RX_GMF_UP_THR = 0x0c58,/* 16 bit Rx Upper Pause Thr (Yukon-EC_U) */
RX_GMF_LP_THR = 0x0c5a,/* 16 bit Rx Lower Pause Thr (Yukon-EC_U) */
RX_GMF_VLAN = 0x0c5c,/* 32 bit Rx VLAN Type Register (Yukon-2) */
RX_GMF_WP = 0x0c60,/* 32 bit Rx GMAC FIFO Write Pointer */
RX_GMF_WLEV = 0x0c68,/* 32 bit Rx GMAC FIFO Write Level */
RX_GMF_RP = 0x0c70,/* 32 bit Rx GMAC FIFO Read Pointer */
RX_GMF_RLEV = 0x0c78,/* 32 bit Rx GMAC FIFO Read Level */
};
/* Q_BC 32 bit Current Byte Counter */
/* BMU Control Status Registers */
/* B0_R1_CSR 32 bit BMU Ctrl/Stat Rx Queue 1 */
/* B0_R2_CSR 32 bit BMU Ctrl/Stat Rx Queue 2 */
/* B0_XA1_CSR 32 bit BMU Ctrl/Stat Sync Tx Queue 1 */
/* B0_XS1_CSR 32 bit BMU Ctrl/Stat Async Tx Queue 1 */
/* B0_XA2_CSR 32 bit BMU Ctrl/Stat Sync Tx Queue 2 */
/* B0_XS2_CSR 32 bit BMU Ctrl/Stat Async Tx Queue 2 */
/* Q_CSR 32 bit BMU Control/Status Register */
/* Rx BMU Control / Status Registers (Yukon-2) */
enum {
BMU_IDLE = 1<<31, /* BMU Idle State */
BMU_RX_TCP_PKT = 1<<30, /* Rx TCP Packet (when RSS Hash enabled) */
BMU_RX_IP_PKT = 1<<29, /* Rx IP Packet (when RSS Hash enabled) */
BMU_ENA_RX_RSS_HASH = 1<<15, /* Enable Rx RSS Hash */
BMU_DIS_RX_RSS_HASH = 1<<14, /* Disable Rx RSS Hash */
BMU_ENA_RX_CHKSUM = 1<<13, /* Enable Rx TCP/IP Checksum Check */
BMU_DIS_RX_CHKSUM = 1<<12, /* Disable Rx TCP/IP Checksum Check */
BMU_CLR_IRQ_PAR = 1<<11, /* Clear IRQ on Parity errors (Rx) */
BMU_CLR_IRQ_TCP = 1<<11, /* Clear IRQ on TCP segment. error (Tx) */
BMU_CLR_IRQ_CHK = 1<<10, /* Clear IRQ Check */
BMU_STOP = 1<<9, /* Stop Rx/Tx Queue */
BMU_START = 1<<8, /* Start Rx/Tx Queue */
BMU_FIFO_OP_ON = 1<<7, /* FIFO Operational On */
BMU_FIFO_OP_OFF = 1<<6, /* FIFO Operational Off */
BMU_FIFO_ENA = 1<<5, /* Enable FIFO */
BMU_FIFO_RST = 1<<4, /* Reset FIFO */
BMU_OP_ON = 1<<3, /* BMU Operational On */
BMU_OP_OFF = 1<<2, /* BMU Operational Off */
BMU_RST_CLR = 1<<1, /* Clear BMU Reset (Enable) */
BMU_RST_SET = 1<<0, /* Set BMU Reset */
BMU_CLR_RESET = BMU_FIFO_RST | BMU_OP_OFF | BMU_RST_CLR,
BMU_OPER_INIT = BMU_CLR_IRQ_PAR | BMU_CLR_IRQ_CHK | BMU_START |
BMU_FIFO_ENA | BMU_OP_ON,
BMU_WM_DEFAULT = 0x600,
BMU_WM_PEX = 0x80,
};
/* Tx BMU Control / Status Registers (Yukon-2) */
/* Bit 31: same as for Rx */
enum {
BMU_TX_IPIDINCR_ON = 1<<13, /* Enable IP ID Increment */
BMU_TX_IPIDINCR_OFF = 1<<12, /* Disable IP ID Increment */
BMU_TX_CLR_IRQ_TCP = 1<<11, /* Clear IRQ on TCP segment length mismatch */
};
/* TBMU_TEST 0x06B8 Transmit BMU Test Register */
enum {
TBMU_TEST_BMU_TX_CHK_AUTO_OFF = 1<<31, /* BMU Tx Checksum Auto Calculation Disable */
TBMU_TEST_BMU_TX_CHK_AUTO_ON = 1<<30, /* BMU Tx Checksum Auto Calculation Enable */
TBMU_TEST_HOME_ADD_PAD_FIX1_EN = 1<<29, /* Home Address Paddiing FIX1 Enable */
TBMU_TEST_HOME_ADD_PAD_FIX1_DIS = 1<<28, /* Home Address Paddiing FIX1 Disable */
TBMU_TEST_ROUTING_ADD_FIX_EN = 1<<27, /* Routing Address Fix Enable */
TBMU_TEST_ROUTING_ADD_FIX_DIS = 1<<26, /* Routing Address Fix Disable */
TBMU_TEST_HOME_ADD_FIX_EN = 1<<25, /* Home address checksum fix enable */
TBMU_TEST_HOME_ADD_FIX_DIS = 1<<24, /* Home address checksum fix disable */
TBMU_TEST_TEST_RSPTR_ON = 1<<22, /* Testmode Shadow Read Ptr On */
TBMU_TEST_TEST_RSPTR_OFF = 1<<21, /* Testmode Shadow Read Ptr Off */
TBMU_TEST_TESTSTEP_RSPTR = 1<<20, /* Teststep Shadow Read Ptr */
TBMU_TEST_TEST_RPTR_ON = 1<<18, /* Testmode Read Ptr On */
TBMU_TEST_TEST_RPTR_OFF = 1<<17, /* Testmode Read Ptr Off */
TBMU_TEST_TESTSTEP_RPTR = 1<<16, /* Teststep Read Ptr */
TBMU_TEST_TEST_WSPTR_ON = 1<<14, /* Testmode Shadow Write Ptr On */
TBMU_TEST_TEST_WSPTR_OFF = 1<<13, /* Testmode Shadow Write Ptr Off */
TBMU_TEST_TESTSTEP_WSPTR = 1<<12, /* Teststep Shadow Write Ptr */
TBMU_TEST_TEST_WPTR_ON = 1<<10, /* Testmode Write Ptr On */
TBMU_TEST_TEST_WPTR_OFF = 1<<9, /* Testmode Write Ptr Off */
TBMU_TEST_TESTSTEP_WPTR = 1<<8, /* Teststep Write Ptr */
TBMU_TEST_TEST_REQ_NB_ON = 1<<6, /* Testmode Req Nbytes/Addr On */
TBMU_TEST_TEST_REQ_NB_OFF = 1<<5, /* Testmode Req Nbytes/Addr Off */
TBMU_TEST_TESTSTEP_REQ_NB = 1<<4, /* Teststep Req Nbytes/Addr */
TBMU_TEST_TEST_DONE_IDX_ON = 1<<2, /* Testmode Done Index On */
TBMU_TEST_TEST_DONE_IDX_OFF = 1<<1, /* Testmode Done Index Off */
TBMU_TEST_TESTSTEP_DONE_IDX = 1<<0, /* Teststep Done Index */
};
/* Queue Prefetch Unit Offsets, use Y2_QADDR() to address (Yukon-2 only)*/
/* PREF_UNIT_CTRL 32 bit Prefetch Control register */
enum {
PREF_UNIT_OP_ON = 1<<3, /* prefetch unit operational */
PREF_UNIT_OP_OFF = 1<<2, /* prefetch unit not operational */
PREF_UNIT_RST_CLR = 1<<1, /* Clear Prefetch Unit Reset */
PREF_UNIT_RST_SET = 1<<0, /* Set Prefetch Unit Reset */
};
/* RAM Buffer Register Offsets, use RB_ADDR(Queue, Offs) to access */
/* RB_START 32 bit RAM Buffer Start Address */
/* RB_END 32 bit RAM Buffer End Address */
/* RB_WP 32 bit RAM Buffer Write Pointer */
/* RB_RP 32 bit RAM Buffer Read Pointer */
/* RB_RX_UTPP 32 bit Rx Upper Threshold, Pause Pack */
/* RB_RX_LTPP 32 bit Rx Lower Threshold, Pause Pack */
/* RB_RX_UTHP 32 bit Rx Upper Threshold, High Prio */
/* RB_RX_LTHP 32 bit Rx Lower Threshold, High Prio */
/* RB_PC 32 bit RAM Buffer Packet Counter */
/* RB_LEV 32 bit RAM Buffer Level Register */
#define RB_MSK 0x0007ffff /* Bit 18.. 0: RAM Buffer Pointer Bits */
/* RB_TST2 8 bit RAM Buffer Test Register 2 */
/* RB_TST1 8 bit RAM Buffer Test Register 1 */
/* RB_CTRL 8 bit RAM Buffer Control Register */
enum {
RB_ENA_STFWD = 1<<5, /* Enable Store & Forward */
RB_DIS_STFWD = 1<<4, /* Disable Store & Forward */
RB_ENA_OP_MD = 1<<3, /* Enable Operation Mode */
RB_DIS_OP_MD = 1<<2, /* Disable Operation Mode */
RB_RST_CLR = 1<<1, /* Clear RAM Buf STM Reset */
RB_RST_SET = 1<<0, /* Set RAM Buf STM Reset */
};
/* Transmit GMAC FIFO (YUKON only) */
enum {
TX_GMF_EA = 0x0d40,/* 32 bit Tx GMAC FIFO End Address */
TX_GMF_AE_THR = 0x0d44,/* 32 bit Tx GMAC FIFO Almost Empty Thresh.*/
TX_GMF_CTRL_T = 0x0d48,/* 32 bit Tx GMAC FIFO Control/Test */
TX_GMF_WP = 0x0d60,/* 32 bit Tx GMAC FIFO Write Pointer */
TX_GMF_WSP = 0x0d64,/* 32 bit Tx GMAC FIFO Write Shadow Ptr. */
TX_GMF_WLEV = 0x0d68,/* 32 bit Tx GMAC FIFO Write Level */
TX_GMF_RP = 0x0d70,/* 32 bit Tx GMAC FIFO Read Pointer */
TX_GMF_RSTP = 0x0d74,/* 32 bit Tx GMAC FIFO Restart Pointer */
TX_GMF_RLEV = 0x0d78,/* 32 bit Tx GMAC FIFO Read Level */
/* Threshold values for Yukon-EC Ultra and Extreme */
ECU_AE_THR = 0x0070, /* Almost Empty Threshold */
ECU_TXFF_LEV = 0x01a0, /* Tx BMU FIFO Level */
ECU_JUMBO_WM = 0x0080, /* Jumbo Mode Watermark */
};
/* Descriptor Poll Timer Registers */
enum {
B28_DPT_INI = 0x0e00,/* 24 bit Descriptor Poll Timer Init Val */
B28_DPT_VAL = 0x0e04,/* 24 bit Descriptor Poll Timer Curr Val */
B28_DPT_CTRL = 0x0e08,/* 8 bit Descriptor Poll Timer Ctrl Reg */
B28_DPT_TST = 0x0e0a,/* 8 bit Descriptor Poll Timer Test Reg */
};
/* Time Stamp Timer Registers (YUKON only) */
enum {
GMAC_TI_ST_VAL = 0x0e14,/* 32 bit Time Stamp Timer Curr Val */
GMAC_TI_ST_CTRL = 0x0e18,/* 8 bit Time Stamp Timer Ctrl Reg */
GMAC_TI_ST_TST = 0x0e1a,/* 8 bit Time Stamp Timer Test Reg */
};
/* Polling Unit Registers (Yukon-2 only) */
enum {
POLL_CTRL = 0x0e20, /* 32 bit Polling Unit Control Reg */
POLL_LAST_IDX = 0x0e24,/* 16 bit Polling Unit List Last Index */
POLL_LIST_ADDR_LO= 0x0e28,/* 32 bit Poll. List Start Addr (low) */
POLL_LIST_ADDR_HI= 0x0e2c,/* 32 bit Poll. List Start Addr (high) */
};
enum {
SMB_CFG = 0x0e40, /* 32 bit SMBus Config Register */
SMB_CSR = 0x0e44, /* 32 bit SMBus Control/Status Register */
};
enum {
CPU_WDOG = 0x0e48, /* 32 bit Watchdog Register */
CPU_CNTR = 0x0e4C, /* 32 bit Counter Register */
CPU_TIM = 0x0e50,/* 32 bit Timer Compare Register */
CPU_AHB_ADDR = 0x0e54, /* 32 bit CPU AHB Debug Register */
CPU_AHB_WDATA = 0x0e58, /* 32 bit CPU AHB Debug Register */
CPU_AHB_RDATA = 0x0e5C, /* 32 bit CPU AHB Debug Register */
HCU_MAP_BASE = 0x0e60, /* 32 bit Reset Mapping Base */
CPU_AHB_CTRL = 0x0e64, /* 32 bit CPU AHB Debug Register */
HCU_CCSR = 0x0e68, /* 32 bit CPU Control and Status Register */
HCU_HCSR = 0x0e6C, /* 32 bit Host Control and Status Register */
};
/* ASF Subsystem Registers (Yukon-2 only) */
enum {
B28_Y2_SMB_CONFIG = 0x0e40,/* 32 bit ASF SMBus Config Register */
B28_Y2_SMB_CSD_REG = 0x0e44,/* 32 bit ASF SMB Control/Status/Data */
B28_Y2_ASF_IRQ_V_BASE=0x0e60,/* 32 bit ASF IRQ Vector Base */
B28_Y2_ASF_STAT_CMD= 0x0e68,/* 32 bit ASF Status and Command Reg */
B28_Y2_ASF_HOST_COM= 0x0e6c,/* 32 bit ASF Host Communication Reg */
B28_Y2_DATA_REG_1 = 0x0e70,/* 32 bit ASF/Host Data Register 1 */
B28_Y2_DATA_REG_2 = 0x0e74,/* 32 bit ASF/Host Data Register 2 */
B28_Y2_DATA_REG_3 = 0x0e78,/* 32 bit ASF/Host Data Register 3 */
B28_Y2_DATA_REG_4 = 0x0e7c,/* 32 bit ASF/Host Data Register 4 */
};
/* Status BMU Registers (Yukon-2 only)*/
enum {
STAT_CTRL = 0x0e80,/* 32 bit Status BMU Control Reg */
STAT_LAST_IDX = 0x0e84,/* 16 bit Status BMU Last Index */
STAT_LIST_ADDR_LO= 0x0e88,/* 32 bit Status List Start Addr (low) */
STAT_LIST_ADDR_HI= 0x0e8c,/* 32 bit Status List Start Addr (high) */
STAT_TXA1_RIDX = 0x0e90,/* 16 bit Status TxA1 Report Index Reg */
STAT_TXS1_RIDX = 0x0e92,/* 16 bit Status TxS1 Report Index Reg */
STAT_TXA2_RIDX = 0x0e94,/* 16 bit Status TxA2 Report Index Reg */
STAT_TXS2_RIDX = 0x0e96,/* 16 bit Status TxS2 Report Index Reg */
STAT_TX_IDX_TH = 0x0e98,/* 16 bit Status Tx Index Threshold Reg */
STAT_PUT_IDX = 0x0e9c,/* 16 bit Status Put Index Reg */
/* FIFO Control/Status Registers (Yukon-2 only)*/
STAT_FIFO_WP = 0x0ea0,/* 8 bit Status FIFO Write Pointer Reg */
STAT_FIFO_RP = 0x0ea4,/* 8 bit Status FIFO Read Pointer Reg */
STAT_FIFO_RSP = 0x0ea6,/* 8 bit Status FIFO Read Shadow Ptr */
STAT_FIFO_LEVEL = 0x0ea8,/* 8 bit Status FIFO Level Reg */
STAT_FIFO_SHLVL = 0x0eaa,/* 8 bit Status FIFO Shadow Level Reg */
STAT_FIFO_WM = 0x0eac,/* 8 bit Status FIFO Watermark Reg */
STAT_FIFO_ISR_WM= 0x0ead,/* 8 bit Status FIFO ISR Watermark Reg */
/* Level and ISR Timer Registers (Yukon-2 only)*/
STAT_LEV_TIMER_INI= 0x0eb0,/* 32 bit Level Timer Init. Value Reg */
STAT_LEV_TIMER_CNT= 0x0eb4,/* 32 bit Level Timer Counter Reg */
STAT_LEV_TIMER_CTRL= 0x0eb8,/* 8 bit Level Timer Control Reg */
STAT_LEV_TIMER_TEST= 0x0eb9,/* 8 bit Level Timer Test Reg */
STAT_TX_TIMER_INI = 0x0ec0,/* 32 bit Tx Timer Init. Value Reg */
STAT_TX_TIMER_CNT = 0x0ec4,/* 32 bit Tx Timer Counter Reg */
STAT_TX_TIMER_CTRL = 0x0ec8,/* 8 bit Tx Timer Control Reg */
STAT_TX_TIMER_TEST = 0x0ec9,/* 8 bit Tx Timer Test Reg */
STAT_ISR_TIMER_INI = 0x0ed0,/* 32 bit ISR Timer Init. Value Reg */
STAT_ISR_TIMER_CNT = 0x0ed4,/* 32 bit ISR Timer Counter Reg */
STAT_ISR_TIMER_CTRL= 0x0ed8,/* 8 bit ISR Timer Control Reg */
STAT_ISR_TIMER_TEST= 0x0ed9,/* 8 bit ISR Timer Test Reg */
};
enum {
LINKLED_OFF = 0x01,
LINKLED_ON = 0x02,
LINKLED_LINKSYNC_OFF = 0x04,
LINKLED_LINKSYNC_ON = 0x08,
LINKLED_BLINK_OFF = 0x10,
LINKLED_BLINK_ON = 0x20,
};
/* GMAC and GPHY Control Registers (YUKON only) */
enum {
GMAC_CTRL = 0x0f00,/* 32 bit GMAC Control Reg */
GPHY_CTRL = 0x0f04,/* 32 bit GPHY Control Reg */
GMAC_IRQ_SRC = 0x0f08,/* 8 bit GMAC Interrupt Source Reg */
GMAC_IRQ_MSK = 0x0f0c,/* 8 bit GMAC Interrupt Mask Reg */
GMAC_LINK_CTRL = 0x0f10,/* 16 bit Link Control Reg */
/* Wake-up Frame Pattern Match Control Registers (YUKON only) */
WOL_CTRL_STAT = 0x0f20,/* 16 bit WOL Control/Status Reg */
WOL_MATCH_CTL = 0x0f22,/* 8 bit WOL Match Control Reg */
WOL_MATCH_RES = 0x0f23,/* 8 bit WOL Match Result Reg */
WOL_MAC_ADDR = 0x0f24,/* 32 bit WOL MAC Address */
WOL_PATT_RPTR = 0x0f2c,/* 8 bit WOL Pattern Read Pointer */
/* WOL Pattern Length Registers (YUKON only) */
WOL_PATT_LEN_LO = 0x0f30,/* 32 bit WOL Pattern Length 3..0 */
WOL_PATT_LEN_HI = 0x0f34,/* 24 bit WOL Pattern Length 6..4 */
/* WOL Pattern Counter Registers (YUKON only) */
WOL_PATT_CNT_0 = 0x0f38,/* 32 bit WOL Pattern Counter 3..0 */
WOL_PATT_CNT_4 = 0x0f3c,/* 24 bit WOL Pattern Counter 6..4 */
};
#define WOL_REGS(port, x) (x + (port)*0x80)
enum {
WOL_PATT_RAM_1 = 0x1000,/* WOL Pattern RAM Link 1 */
WOL_PATT_RAM_2 = 0x1400,/* WOL Pattern RAM Link 2 */
};
#define WOL_PATT_RAM_BASE(port) (WOL_PATT_RAM_1 + (port)*0x400)
enum {
BASE_GMAC_1 = 0x2800,/* GMAC 1 registers */
BASE_GMAC_2 = 0x3800,/* GMAC 2 registers */
};
/*
* Marvel-PHY Registers, indirect addressed over GMAC
*/
enum {
PHY_MARV_CTRL = 0x00,/* 16 bit r/w PHY Control Register */
PHY_MARV_STAT = 0x01,/* 16 bit r/o PHY Status Register */
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