From 638772c7553f6893f7b346bfee4d46851af59afc Mon Sep 17 00:00:00 2001 From: Lennert Buytenhek Date: Wed, 11 Feb 2009 17:25:24 +0800 Subject: fb: add support of LCD display controller on pxa168/910 (base layer) This driver is originally written by Lennert, modified by Green to be feature complete, and ported by Jun Nie and Kevin Liu for pxa168/910 processors. The patch adds support for the on-chip LCD display controller, it currently supports the base (graphics) layer only. Signed-off-by: Lennert Buytenhek Signed-off-by: Green Wan Cc: Peter Liao Signed-off-by: Jun Nie Signed-off-by: Kevin Liu Acked-by: Krzysztof Helt Signed-off-by: Eric Miao --- include/video/pxa168fb.h | 127 +++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 127 insertions(+) create mode 100644 include/video/pxa168fb.h (limited to 'include') diff --git a/include/video/pxa168fb.h b/include/video/pxa168fb.h new file mode 100644 index 000000000000..b5cc72fe0461 --- /dev/null +++ b/include/video/pxa168fb.h @@ -0,0 +1,127 @@ +/* + * linux/arch/arm/mach-mmp/include/mach/pxa168fb.h + * + * Copyright (C) 2009 Marvell International Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __ASM_MACH_PXA168FB_H +#define __ASM_MACH_PXA168FB_H + +#include +#include + +/* Dumb interface */ +#define PIN_MODE_DUMB_24 0 +#define PIN_MODE_DUMB_18_SPI 1 +#define PIN_MODE_DUMB_18_GPIO 2 +#define PIN_MODE_DUMB_16_SPI 3 +#define PIN_MODE_DUMB_16_GPIO 4 +#define PIN_MODE_DUMB_12_SPI_GPIO 5 +#define PIN_MODE_SMART_18_SPI 6 +#define PIN_MODE_SMART_16_SPI 7 +#define PIN_MODE_SMART_8_SPI_GPIO 8 + +/* Dumb interface pin allocation */ +#define DUMB_MODE_RGB565 0 +#define DUMB_MODE_RGB565_UPPER 1 +#define DUMB_MODE_RGB666 2 +#define DUMB_MODE_RGB666_UPPER 3 +#define DUMB_MODE_RGB444 4 +#define DUMB_MODE_RGB444_UPPER 5 +#define DUMB_MODE_RGB888 6 + +/* default fb buffer size WVGA-32bits */ +#define DEFAULT_FB_SIZE (800 * 480 * 4) + +/* + * Buffer pixel format + * bit0 is for rb swap. + * bit12 is for Y UorV swap + */ +#define PIX_FMT_RGB565 0 +#define PIX_FMT_BGR565 1 +#define PIX_FMT_RGB1555 2 +#define PIX_FMT_BGR1555 3 +#define PIX_FMT_RGB888PACK 4 +#define PIX_FMT_BGR888PACK 5 +#define PIX_FMT_RGB888UNPACK 6 +#define PIX_FMT_BGR888UNPACK 7 +#define PIX_FMT_RGBA888 8 +#define PIX_FMT_BGRA888 9 +#define PIX_FMT_YUV422PACK 10 +#define PIX_FMT_YVU422PACK 11 +#define PIX_FMT_YUV422PLANAR 12 +#define PIX_FMT_YVU422PLANAR 13 +#define PIX_FMT_YUV420PLANAR 14 +#define PIX_FMT_YVU420PLANAR 15 +#define PIX_FMT_PSEUDOCOLOR 20 +#define PIX_FMT_UYVY422PACK (0x1000|PIX_FMT_YUV422PACK) + +/* + * PXA LCD controller private state. + */ +struct pxa168fb_info { + struct device *dev; + struct clk *clk; + struct fb_info *info; + + void __iomem *reg_base; + dma_addr_t fb_start_dma; + u32 pseudo_palette[16]; + + int pix_fmt; + unsigned is_blanked:1; + unsigned panel_rbswap:1; + unsigned active:1; +}; + +/* + * PXA fb machine information + */ +struct pxa168fb_mach_info { + char id[16]; + + int num_modes; + struct fb_videomode *modes; + + /* + * Pix_fmt + */ + unsigned pix_fmt; + + /* + * I/O pin allocation. + */ + unsigned io_pin_allocation_mode:4; + + /* + * Dumb panel -- assignment of R/G/B component info to the 24 + * available external data lanes. + */ + unsigned dumb_mode:4; + unsigned panel_rgb_reverse_lanes:1; + + /* + * Dumb panel -- GPIO output data. + */ + unsigned gpio_output_mask:8; + unsigned gpio_output_data:8; + + /* + * Dumb panel -- configurable output signal polarity. + */ + unsigned invert_composite_blank:1; + unsigned invert_pix_val_ena:1; + unsigned invert_pixclock:1; + unsigned invert_vsync:1; + unsigned invert_hsync:1; + unsigned panel_rbswap:1; + unsigned active:1; + unsigned enable_lcd:1; +}; + +#endif /* __ASM_MACH_PXA168FB_H */ -- cgit v1.2.2