#ifndef __BNX2X_INIT_VALUES_H__
#define __BNX2X_INIT_VALUES_H__
/* This array contains the list of operations needed to initialize the chip.
*
* For each block in the chip there are three init stages:
* common - HW used by both ports,
* port1 and port2 - initialization for a specific Ethernet port.
* When a port is opened or closed, the management CPU tells the driver
* whether to init/disable common HW in addition to the port HW.
* This way the first port going up will first initializes the common HW,
* and the last port going down also resets the common HW
*
* For each init stage/block there is a list of actions needed in a format:
* {operation, register, data}
* where:
* OP_WR - write a value to the chip.
* OP_RD - read a register (usually a clear on read register).
* OP_SW - string write, write a section of consecutive addresses to the chip.
* OP_SI - copy a string using indirect writes.
* OP_ZR - clear a range of memory.
* OP_ZP - unzip and copy using DMAE.
* OP_WB - string copy using DMAE.
*
* The #defines mark the stages.
*
*/
static const struct raw_op init_ops[] = {
#define PRS_COMMON_START 0
{OP_WR, PRS_REG_INC_VALUE, 0xf},
{OP_WR, PRS_REG_EVENT_ID_1, 0x45},
{OP_WR, PRS_REG_EVENT_ID_2, 0x84},
{OP_WR, PRS_REG_EVENT_ID_3, 0x6},
{OP_WR, PRS_REG_NO_MATCH_EVENT_ID, 0x4},
{OP_WR, PRS_REG_CM_HDR_TYPE_0, 0x0},
{OP_WR, PRS_REG_CM_HDR_TYPE_1, 0x12170000},
{OP_WR, PRS_REG_CM_HDR_TYPE_2, 0x22170000},
{OP_WR, PRS_REG_CM_HDR_TYPE_3, 0x32170000},
{OP_ZR, PRS_REG_CM_HDR_TYPE_4, 0x5},
{OP_WR, PRS_REG_CM_HDR_LOOPBACK_TYPE_1, 0x12150000},
{OP_WR, PRS_REG_CM_HDR_LOOPBACK_TYPE_2, 0x22150000},
{OP_WR, PRS_REG_CM_HDR_LOOPBACK_TYPE_3, 0x32150000},
{OP_ZR, PRS_REG_CM_HDR_LOOPBACK_TYPE_4, 0x4},
{OP_WR, PRS_REG_CM_NO_MATCH_HDR, 0x2100000},
{OP_WR, PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_0, 0x100000},
{OP_WR, PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_1, 0x10100000},
{OP_WR, PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_2, 0x20100000},
{OP_WR, PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_3, 0x30100000},
{OP_ZR, PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_4, 0x4},
{OP_WR, PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_0, 0x100000},
{OP_WR, PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_1, 0x12140000},
{OP_WR, PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_2, 0x22140000},
{OP_WR, PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_3, 0x32140000},
{OP_ZR, PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_4, 0x4},
{OP_RD, PRS_REG_NUM_OF_PACKETS, 0x0},
{OP_RD, PRS_REG_NUM_OF_CFC_FLUSH_MESSAGES, 0x0},
{OP_RD, PRS_REG_NUM_OF_TRANSPARENT_FLUSH_MESSAGES, 0x0},
{OP_RD, PRS_REG_NUM_OF_DEAD_CYCLES, 0x0},
{OP_WR_E1H, PRS_REG_FCOE_TYPE, 0x8906},
{OP_WR, PRS_REG_FLUSH_REGIONS_TYPE_0, 0xff},
{OP_WR, PRS_REG_FLUSH_REGIONS_TYPE_1, 0xff},
{OP_WR, PRS_REG_FLUSH_REGIONS_TYPE_2, 0xff},
{OP_WR, PRS_REG_FLUSH_REGIONS_TYPE_3, 0xff},
{OP_WR, PRS_REG_FLUSH_REGIONS_TYPE_4, 0xff},
{OP_WR, PRS_REG_FLUSH_REGIONS_TYPE_5, 0xff},
{OP_WR, PRS_REG_FLUSH_REGIONS_TYPE_6, 0xff},
{OP_WR, PRS_REG_FLUSH_REGIONS_TYPE_7, 0xff},
{OP_WR, PRS_REG_PURE_REGIONS, 0x3e},
{OP_WR, PRS_REG_PACKET_REGIONS_TYPE_0, 0x0},
{OP_WR, PRS_REG_PACKET_REGIONS_TYPE_1, 0x3f},
{OP_WR, PRS_REG_PACKET_REGIONS_TYPE_2, 0x3f},
{OP_WR, PRS_REG_PACKET_REGIONS_TYPE_3, 0x3f},
{OP_WR, PRS_REG_PACKET_REGIONS_TYPE_4, 0x0},
{OP_WR, PRS_REG_PACKET_REGIONS_TYPE_5, 0x3f},
{OP_WR, PRS_REG_PACKET_REGIONS_TYPE_6, 0x3f},
{OP_WR, PRS_REG_PACKET_REGIONS_TYPE_7, 0x3f},
#define PRS_COMMON_END 47
#define SRCH_COMMON_START 47
{OP_WR_E1H, SRC_REG_E1HMF_ENABLE, 0x1},
#define SRCH_COMMON_END 48
#define TSDM_COMMON_START 48
{OP_WR_E1, TSDM_REG_CFC_RSP_START_ADDR, 0x411},
{OP_WR_E1H, TSDM_REG_CFC_RSP_START_ADDR, 0x211},
{OP_WR_E1, TSDM_REG_CMP_COUNTER_START_ADDR, 0x400},
{OP_WR_E1H, TSDM_REG_CMP_COUNTER_START_ADDR, 0x200},
{OP_WR_E1, TSDM_REG_Q_COUNTER_START_ADDR, 0x404},
{OP_WR_E1H, TSDM_REG_Q_COUNTER_START_ADDR, 0x204},
{OP_WR_E1, TSDM_REG_PCK_END_MSG_START_ADDR, 0x419},
{OP_WR_E1H, TSDM_REG_PCK_END_MSG_START_ADDR, 0x219},
{OP_WR, TSDM_REG_CMP_COUNTER_MAX0, 0xffff},
{OP_WR, TSDM_REG_CMP_COUNTER_MAX1, 0xffff},
{OP_WR, TSDM_REG_CMP_COUNTER_MAX2, 0xffff},
{OP_WR, TSDM_REG_CMP_COUNTER_MAX3, 0xffff},
{OP_ZR, TSDM_REG_AGG_INT_EVENT_0, 0x2},
{OP_WR, TSDM_REG_AGG_INT_EVENT_2, 0x34},
{OP_WR, TSDM_REG_AGG_INT_EVENT_3, 0x35},
{OP_ZR, TSDM_REG_AGG_INT_EVENT_4, 0x7c},
{OP_WR, TSDM_REG_ENABLE_IN1, 0x7ffffff},
{OP_WR, TSDM_REG_ENABLE_IN2, 0x3f},
{OP_WR, TSDM_REG_ENABLE_OUT1, 0x7ffffff},
{OP_WR, TSDM_REG_ENABLE_OUT2, 0xf},
{OP_RD, TSDM_REG_NUM_OF_Q0_CMD, 0x0},
{OP_RD, TSDM_REG_NUM_OF_Q1_CMD, 0x0},
{OP_RD, TSDM_REG_NUM_OF_Q3_CMD, 0x0},
{OP_RD, TSDM_REG_NUM_OF_Q4_CMD, 0x0},
{OP_RD, TSDM_REG_NUM_OF_Q5_CMD, 0x0},
{OP_RD, TSDM_REG_NUM_OF_Q6_CMD, 0x0},
{OP_RD, TSDM_REG_NUM_OF_Q7_CMD, 0x0},
{OP_RD, TSDM_REG_NUM_OF_Q8_CMD, 0x0},
{OP_RD, TSDM_REG_NUM_OF_Q9_CMD, 0x0},
{OP_RD, TSDM_REG_NUM_OF_Q10_CMD, 0x0},
{OP_RD, TSDM_REG_NUM_OF_Q11_CMD, 0x0},
{OP_RD, TSDM_REG_NUM_OF_PKT_END_MSG, 0x0},
{OP_RD, TSDM_REG_NUM_OF_PXP_ASYNC_REQ, 0x0},
{OP_RD, TSDM_REG_NUM_OF_ACK_AFTER_PLACE, 0x0},
{OP_WR_E1, TSDM_REG_INIT_CREDIT_PXP_CTRL, 0x1},
{OP_WR_ASIC, TSDM_REG_TIMER_TICK, 0x3e8},
{OP_WR_EMUL, TSDM_REG_TIMER_TICK, 0x1},
{OP_WR_FPGA, TSDM_REG_TIMER_TICK, 0xa},
#define TSDM_COMMON_END 86
#define TCM_COMMON_START 86
{OP_WR, TCM_REG_XX_MAX_LL_SZ, 0x20},
{OP_WR, TCM_REG_XX_OVFL_EVNT_ID, 0x32},
{OP_WR, TCM_REG_TQM_TCM_HDR_P, 0x2150020},
{OP_WR, TCM_REG_TQM_TCM_HDR_S, 0x2150020},
{OP_WR, TCM_REG_TM_TCM_HDR, 0x30},
{OP_WR, TCM_REG_ERR_TCM_HDR, 0x8100000},
{OP_WR, TCM_REG_ERR_EVNT_ID, 0x33},
{OP_WR, TCM_REG_EXPR_EVNT_ID, 0x30},
{OP_WR, TCM_REG_STOP_EVNT_ID, 0x31},
{OP_WR, TCM_REG_PRS_WEIGHT, 0x4},
{OP_WR, TCM_REG_PBF_WEIGHT, 0x5},
{OP_WR, TCM_REG_CP_WEIGHT, 0x0},
{OP_WR, TCM_REG_TSDM_WEIGHT, 0x4},
{OP_WR, TCM_REG_TCM_TQM_USE_Q, 0x1},
{OP_WR, TCM_REG_GR_ARB_TYPE, 0x1},
{OP_WR, TCM_REG_GR_LD0_PR, 0x1},
{OP_WR, TCM_REG_GR_LD1_PR, 0x2},
{OP_WR, TCM_REG_CFC_INIT_CRD, 0x1},
{OP_WR, TCM_REG_FIC0_INIT_CRD, 0x40},
{OP_WR, TCM_REG_FIC1_INIT_CRD, 0x40},
{OP_WR, TCM_REG_TQM_INIT_CRD, 0x20},
