From 781c7b129b1beb876905f7212927aa0ee1b022e5 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Fri, 7 May 2010 08:40:53 +0000 Subject: spi/pl022: add support for the PL023 derivate This adds support for a further ST variant of the PL022 called PL023. Some differences in the control registers due to being stripped down to SPI mode only, and a new clock feedback sample delay config setting is available. Signed-off-by: Linus Walleij Signed-off-by: Grant Likely --- include/linux/amba/pl022.h | 32 ++++++++++++++++++++++++++++++-- 1 file changed, 30 insertions(+), 2 deletions(-) (limited to 'include/linux/amba') diff --git a/include/linux/amba/pl022.h b/include/linux/amba/pl022.h index 612f39913340..abf26cc47a2b 100644 --- a/include/linux/amba/pl022.h +++ b/include/linux/amba/pl022.h @@ -182,8 +182,8 @@ enum ssp_microwire_wait_state { }; /** - * enum Microwire - whether Full/Half Duplex, only available - * in the ST Micro variant. + * enum ssp_duplex - whether Full/Half Duplex on microwire, only + * available in the ST Micro variant. * @SSP_MICROWIRE_CHANNEL_FULL_DUPLEX: SSPTXD becomes bi-directional, * SSPRXD not used * @SSP_MICROWIRE_CHANNEL_HALF_DUPLEX: SSPTXD is an output, SSPRXD is @@ -194,6 +194,31 @@ enum ssp_duplex { SSP_MICROWIRE_CHANNEL_HALF_DUPLEX }; +/** + * enum ssp_clkdelay - an optional clock delay on the feedback clock + * only available in the ST Micro PL023 variant. + * @SSP_FEEDBACK_CLK_DELAY_NONE: no delay, the data coming in from the + * slave is sampled directly + * @SSP_FEEDBACK_CLK_DELAY_1T: the incoming slave data is sampled with + * a delay of T-dt + * @SSP_FEEDBACK_CLK_DELAY_2T: dito with a delay if 2T-dt + * @SSP_FEEDBACK_CLK_DELAY_3T: dito with a delay if 3T-dt + * @SSP_FEEDBACK_CLK_DELAY_4T: dito with a delay if 4T-dt + * @SSP_FEEDBACK_CLK_DELAY_5T: dito with a delay if 5T-dt + * @SSP_FEEDBACK_CLK_DELAY_6T: dito with a delay if 6T-dt + * @SSP_FEEDBACK_CLK_DELAY_7T: dito with a delay if 7T-dt + */ +enum ssp_clkdelay { + SSP_FEEDBACK_CLK_DELAY_NONE, + SSP_FEEDBACK_CLK_DELAY_1T, + SSP_FEEDBACK_CLK_DELAY_2T, + SSP_FEEDBACK_CLK_DELAY_3T, + SSP_FEEDBACK_CLK_DELAY_4T, + SSP_FEEDBACK_CLK_DELAY_5T, + SSP_FEEDBACK_CLK_DELAY_6T, + SSP_FEEDBACK_CLK_DELAY_7T +}; + /** * CHIP select/deselect commands */ @@ -237,6 +262,8 @@ struct pl022_ssp_controller { * @ctrl_len: Microwire interface: Control length * @wait_state: Microwire interface: Wait state * @duplex: Microwire interface: Full/Half duplex + * @clkdelay: on the PL023 variant, the delay in feeback clock cycles + * before sampling the incoming line * @cs_control: function pointer to board-specific function to * assert/deassert I/O port to control HW generation of devices chip-select. * @dma_xfer_type: Type of DMA xfer (Mem-to-periph or Periph-to-Periph) @@ -260,6 +287,7 @@ struct pl022_config_chip { enum ssp_microwire_ctrl_len ctrl_len; enum ssp_microwire_wait_state wait_state; enum ssp_duplex duplex; + enum ssp_clkdelay clkdelay; void (*cs_control) (u32 control); }; -- cgit v1.2.2